KR101356171B1 - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A fringe field switching (FFS) liquid crystal display and a method of manufacturing the same of the present invention are to improve the transmittance of the liquid crystal display panel by forming a common electrode to have a slit electrode pattern over the entire pixel area. Providing a first substrate including a pixel portion; Forming a gate electrode and a gate line on the first substrate through a first mask process; Forming a first insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active pattern on the gate electrode with the first insulating layer interposed therebetween, and forming an n + amorphous silicon thin film pattern patterned on the active pattern in the same form as the active pattern; Forming a source electrode and a drain electrode electrically connected to the source region and the drain region of the active pattern using the second mask process, and defining a pixel region intersecting the gate line; Forming a; Forming a box-shaped pixel electrode directly connected to a portion of the drain electrode in the pixel region through a third mask process, and removing a portion of the n + amorphous silicon thin film pattern to form an ohmic contact layer; Forming a second insulating film on the first substrate on which the pixel electrode is formed; Forming a common electrode on the entire pixel portion of the first substrate on which the second insulating film is formed through a fourth mask process, and forming the common electrode to have a plurality of slits in the pixel region; And bonding the first substrate and the second substrate to each other.

In this case, the fringe field type liquid crystal display of the present invention and a method of manufacturing the same simplify a manufacturing process by overlapping a sub-color filter to serve as a black matrix, and at the same time overlap the common electrode on the data line with the pixel electrode. It is characterized in that to prevent color mixing defects due to the mixed color around the data line.

Slit, Common Electrode, Pixel Electrode, Sub-Color Filter, Black Matrix

Description

Fringe field type liquid crystal display device and manufacturing method therefor {FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a fringe field type liquid crystal display device and a manufacturing method thereof, and more particularly, to a fringe field type liquid crystal display device which can reduce the number of masks, simplify the manufacturing process, improve transmittance and prevent color mixing defects. And to a method for producing the same.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is because of the refractive anisotropy of the liquid crystal molecules, and liquid crystal molecules aligned horizontally with the substrate are oriented in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

Accordingly, there is an in-plane switching (IPS) type liquid crystal display device in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle to 170 degrees or more.

FIG. 2 is a plan view showing a portion of an array substrate of a transverse electric field type liquid crystal display device, wherein a fringe field formed between the pixel electrode and the common electrode penetrates the slit to drive liquid crystal molecules positioned on the pixel region and the common electrode. A portion of an array substrate of a fringe field switching (FFS) liquid crystal display is shown.

As shown in the figure, the array substrate 10 of the fringe field type liquid crystal display device has a gate line 16 and a data line 17 arranged vertically and horizontally on the transparent array substrate 10 to define a pixel area. And a thin film transistor, which is a switching element, is formed in an intersection region of the gate line 16 and the data line 17.

The thin film transistor includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor may include a gate insulating film (not shown) for insulation between the gate electrode 21 and the source / drain electrodes 22 and 23 and the source electrode by a gate voltage supplied to the gate electrode 21. An active pattern (not shown) for forming a conductive channel between the 22 and the drain electrode 23 is included.

A box-shaped common electrode 8 and a pixel electrode 18 are formed in the pixel region, wherein the pixel electrode 18 is formed together with the common electrode 8 to generate a fringe field. 18, a plurality of slits 18s are included.

In this case, the pixel electrode 18 is electrically connected to the drain electrode 23 through a contact hole 40 formed in a passivation layer (not shown), and the common electrode 8 is connected to the gate line 16. It is connected to the common line 8l arranged in parallel.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required ought.

3A through 3F are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate illustrated in FIG. 2.

As shown in FIG. 3A, a gate electrode 21 made of a conductive metal material, a common line 8l, and a gate line (not shown) are formed on the array substrate 10 using a photolithography process (first mask process). Form.

3B, an insulating film, an amorphous silicon thin film, and an n + amorphous silicon thin film are sequentially formed on the entire surface of the array substrate 10 on which the gate electrode 21, the common line 8l, and the gate line are formed. Deposit.

Thereafter, the insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film are selectively patterned by using a photolithography process (second mask process) to form the amorphous silicon in the state where the gate insulating film 15a is interposed on the gate electrode 21. An active pattern 24 made of a thin film is formed.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 3C, the transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (third mask process) to form the upper portion on the common line 8l. The common electrode 8 which is electrically connected to the common line 8l is formed.

As shown in FIG. 3D, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (a fourth mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In addition, a data line 17 defining a pixel region is formed along with the gate line through the fourth mask process.

In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed between the active pattern 24 and the source / drain electrodes 22 and 23 by removing a predetermined region through the fourth mask process. An ohmic contact layer 25 'for ohmic contact is formed.

Next, as shown in FIG. 3E, a protective film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22, the drain electrode 23, and the data line 17 are formed, and then a photolithography process. Through the fifth mask process, a portion of the passivation layer 15b is removed to form a contact hole 40 exposing a portion of the drain electrode 23.

Finally, as illustrated in FIG. 3F, the contact hole 40 is formed by depositing a transparent conductive metal material on the entire surface of the array substrate 10 and then selectively patterning the same by using a photolithography process (sixth mask process). The pixel electrode 18 is formed to be electrically connected to the drain electrode 23. In this case, the pixel electrode 18 includes a plurality of slits 18s in the pixel electrode 18 to generate a fringe field together with the common electrode 8 thereunder.

As described above, fabrication of an array substrate including a thin film transistor requires a total of six photolithography processes for patterning a gate electrode, an active pattern, a common electrode, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development process. There is a disadvantage of lowering the yield.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

In addition, the fringe field type liquid crystal display device has an advantage of having a wide viewing angle of about 160 degrees, but has a disadvantage in that aperture ratio and transmittance are reduced as the opaque common lines are arranged in the pixel area. In addition, in the aforementioned fringe field type liquid crystal display device, since the slit formed in the pixel electrode is formed only in a region corresponding to the common electrode, the fringe field is not formed in the region adjacent to the data line, thereby decreasing transmittance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same, which produce an array substrate by five mask processes.

Another object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same to prevent contamination of the back channel of the active pattern generated in the process of reducing the number of masks.

Another object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same to improve the transmittance of the liquid crystal display panel.

Another object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same, which simplify a mask process of a color filter substrate by overlapping a sub-color filter to serve as a black matrix.

Another object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same, which prevents color mixing defects caused by color mixing around the data line caused by the absence of a black matrix on the data line.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above object, the fringe field type liquid crystal display device of the present invention comprises: a first substrate including a pixel portion; A gate electrode and a gate line formed on the first substrate; A first insulating film formed on the first substrate on which the gate electrode and the gate line are formed; An active pattern formed on the gate electrode with the first insulating layer interposed therebetween; A source electrode and a drain electrode formed on the first substrate on which the first insulating film is formed, and electrically connected to the source region and the drain region of the active pattern; A data line formed on the first substrate on which the first insulating film is formed and defining a pixel region crossing the gate line; A box electrode formed in the pixel area and directly connected to a part of the drain electrode; A second insulating film formed on the first substrate on which the pixel electrode is formed; A common electrode formed on the entire pixel portion of the first substrate on which the second insulating film is formed, the common electrode having a plurality of slits in the pixel region; A second substrate joined to face the first substrate; And a color filter formed on the second substrate to be a sub-color filter, and adjacent sub-color filters overlap and serve as a black matrix.

A method of manufacturing a fringe field type liquid crystal display device according to the present invention comprises the steps of: providing a first substrate including a pixel portion; Forming a gate electrode and a gate line on the first substrate through a first mask process; Forming a first insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active pattern on the gate electrode with the first insulating layer interposed therebetween, and forming an n + amorphous silicon thin film pattern patterned on the active pattern in the same form as the active pattern; Forming a source electrode and a drain electrode electrically connected to the source region and the drain region of the active pattern using the second mask process, and defining a pixel region intersecting the gate line; Forming a; Forming a box-shaped pixel electrode directly connected to a portion of the drain electrode in the pixel region through a third mask process, and removing a portion of the n + amorphous silicon thin film pattern to form an ohmic contact layer; Forming a second insulating film on the first substrate on which the pixel electrode is formed; Forming a common electrode on the entire pixel portion of the first substrate on which the second insulating film is formed through a fourth mask process, and forming the common electrode to have a plurality of slits in the pixel region; And bonding the first substrate and the second substrate to each other.

As described above, the fringe field type liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of reducing the number of masks used in the manufacture of the thin film transistor to improve the yield and reduce the cost.

In addition, the fringe field type liquid crystal display device and the manufacturing method thereof according to the present invention can prevent the degradation of the characteristics of the thin film transistor by blocking the back channel of the active pattern from being contaminated.

In addition, the fringe field type liquid crystal display device and a method of manufacturing the same according to the present invention provide an effect of improving image quality by improving aperture ratio and transmittance and preventing color mixing defects.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the fringe field type liquid crystal display device and a method of manufacturing the same.

4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a first exemplary embodiment of the present invention, in which a fringe field formed between the pixel electrode and the common electrode penetrates the slit and passes through the pixel region and the pixel electrode. A portion of an array substrate of a fringe field type liquid crystal display device which realizes an image by driving liquid crystal molecules positioned on is shown.

For reference, in the drawings, for convenience of description, one pixel including a gate pad part, a data pad part, and a thin film transistor of the pixel part is illustrated. In an actual liquid crystal display device, N gate lines and M data lines cross each other. MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the drawing, in the array substrate 110 according to the first embodiment of the present invention, a gate line 116 and a data line 117 are arranged vertically and horizontally on the array substrate 110 to define a pixel area. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 116 and the data line 117, and a plurality of slits for driving a liquid crystal (not shown) by generating a fringe field in the pixel area. A common electrode 108 having a 108s and a pixel electrode 118 in the form of a box are formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

In this case, a part of the source electrode 122 extends in one direction to form a part of the data line 117, and a part of the drain electrode 123 extends toward the pixel area to directly contact the pixel electrode without a separate contact hole. 118 is electrically connected.

As described above, the common electrode 108 and the pixel electrode 118 having a plurality of slits 108s for generating a fringe field are formed in the pixel region, wherein the pixel electrode 118 is the pixel region. The common electrode 108 is formed in a box shape within the pixel portion, and is formed to have a plurality of slits 108s in each pixel region at the same time.

In this case, the liquid crystal display according to the first exemplary embodiment of the present invention shows a fringe field type liquid crystal display device which drives a liquid crystal molecule by inducing a fringe field, which is a parabolic transverse electric field, in the liquid crystal layer. have.

As described above, when the common electrode 108 is formed in a single pattern over the entire pixel portion, it is necessary to form a common line for electrically connecting the common electrodes as compared with the case where the common electrode is formed in each pixel region. There will be no. As a result, the number of masks required to fabricate the array substrate 110 can be reduced by one.

In addition, since the opaque common line is not required as described above, the common electrode 108 is also formed on the data line 117, so that the aperture ratio is improved, and the left and right ends of the pixel electrode 118 are connected to the data line 117. It is present in the outermost slit 108s of the periphery so that the transmittance around the data line 117 is maximized.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p is connected to the gate pad line 116p and the data pad line 117p through a gate pad electrode 126p and a data pad electrode 127p, respectively. You will be authorized.

For reference, reference numerals 140a and 140b indicate a first contact hole and a second contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the first contact hole 140a. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the second contact hole 140b.

The fringe field type liquid crystal display device according to the first embodiment of the present invention uses an active pattern using a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask). By forming the source / drain electrodes and the data line in one mask process and forming a pixel electrode to directly connect the drain electrode without a separate contact hole, an array substrate may be manufactured in a total of five mask processes.

In this case, the fringe field type liquid crystal display according to the first exemplary embodiment of the present invention removes the n + amorphous silicon thin film pattern formed in the channel region of the active pattern through a mask process for forming the pixel electrode. The back channel of the pattern may be blocked to prevent contamination of the thin film transistor.

When the active pattern, the source electrode and the drain electrode are formed in one mask process to reduce the number of masks, the conductive layer is deposited to form a pixel electrode when the n + amorphous silicon thin film formed in the channel region of the active pattern is removed. In order to prevent the back channel of the active pattern from being contaminated in the process of etching the conductive layer, this will be described in detail through a method of manufacturing a fringe field type liquid crystal display.

5A through 5E are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate illustrated in FIG. 4, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

6A to 6E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

As shown in FIGS. 5A and 6A, a gate electrode 121 and a gate line 116 are formed in a pixel portion of the array substrate 110 made of a transparent insulating material such as glass, and the array substrate 110 may be formed. A gate pad line 116p is formed in the gate pad portion.

In this case, the gate electrode 121, the gate line 116, and the gate pad line 116p are selectively deposited through a photolithography process (first mask process) after depositing a first conductive layer on the entire surface of the array substrate 110. It is formed by patterning.

Here, the first conductive layer may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum A low resistance opaque conductive material such as a molybdenum alloy can be used. The first conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIGS. 5B and 6B, the first insulating layer 115a and the amorphous layer are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the gate pad line 116p are formed. A silicon thin film, an n + amorphous silicon thin film and a second conductive film are formed.

Thereafter, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (second mask process) to form an active pattern including the amorphous silicon thin film in the pixel portion of the array substrate 110 ( 124 is formed, and a source electrode 122 and a drain electrode 123 formed of the second conductive layer are formed on the active pattern 124.

In this case, a data line 117 made of the second conductive layer is formed in the data line region of the array substrate 110 through the second mask process, and the second data pad portion of the array substrate 110 is formed. A data pad line 117p made of a conductive film is formed.

In this case, a first n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 is formed on the active pattern 124.

In addition, a lower portion of the data line 117 and the data pad line 117p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 117 and the data pad line 117p. The first amorphous silicon thin film pattern 124 ', the second n + amorphous silicon thin film pattern 125 ", the second amorphous silicon thin film pattern 124", and the third n + amorphous silicon thin film pattern 125' "are formed, respectively. .

Here, the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 according to the first embodiment of the present invention use a half-tone mask to perform one mask process (second mask process). It is possible to form at the same time through), with reference to the drawings will be described in detail the second mask process. However, the present invention is not limited thereto, and the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 may be formed by two mask processes.

7A to 7F are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention in the array substrate illustrated in FIGS. 5B and 6B.

As shown in FIG. 7A, the first insulating layer 115a, the amorphous silicon thin film 120, and the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the gate pad line 116p are formed. The n + amorphous silicon thin film 125 and the second conductive film 130 are formed.

The second conductive layer 130 may be formed of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a source electrode, a drain electrode, and a data line.

As shown in FIG. 7B, after the first photosensitive film 170 formed of the photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, the first half- according to the first embodiment of the present invention is formed. Light is selectively irradiated to the first photosensitive layer 170 through a tone mask 180.

In this case, the first half-tone mask 180 blocks the first transmission region I transmitting all of the irradiated light and the second transmission region II transmitting only a part of the light and blocking part of the light and all the irradiated light. The blocking region III is provided, and only the light passing through the first half-tone mask 180 is irradiated to the first photosensitive film 170.

Subsequently, after developing the first photoresist layer 170 exposed through the first half-tone mask 180, as shown in FIG. 7C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 170a to the fifth photoresist pattern 170e having a predetermined thickness remain in an area where all of the light is blocked or partially blocked by the light, and the first transmission area I through which all the light is transmitted The first photoresist film is completely removed to expose the surface of the second conductive film 130.

In this case, the first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III are formed thicker than the fifth photoresist pattern 170e formed through the second transmission region II. In addition, the first photoresist film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a photoresist.

Next, as shown in FIG. 7D, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second formed on the lower portion of the first photosensitive film pattern 170a to the fifth photosensitive film pattern 170e formed as described above are used as a mask. When the conductive film is selectively removed, an active pattern 124 formed of the amorphous silicon thin film is formed in the pixel portion of the array substrate 110, and the second conductive layer is formed in the data line portion of the array substrate 110. The formed data line 117 is formed.

In addition, a data pad line 117p formed of the second conductive layer is formed in the data pad part of the array substrate 110.

The first n + amorphous silicon thin film pattern 125 'formed of the n + amorphous silicon thin film and the second conductive film and patterned in the same manner as the active pattern 124 is formed on the active pattern 124, The conductive film pattern 130 'is formed.

In addition, a lower portion of the data line 117 and the data pad line 117p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 117 and the data pad line 117p. The first amorphous silicon thin film pattern 124 ', the second n + amorphous silicon thin film pattern 125 ", the second amorphous silicon thin film pattern 124", and the third n + amorphous silicon thin film pattern 125' "are formed, respectively. .

Subsequently, as shown in FIG. 7E, an ashing process of removing a portion of the first to fifth photoresist patterns may be performed to completely remove the fifth photoresist pattern of the second transmission region II. .

In this case, the first photoresist pattern to the fourth photoresist pattern correspond to the blocking region III by the sixth photoresist pattern 170a 'through the ninth photoresist pattern 170d' where the thickness of the fifth photoresist pattern is removed. Only the source electrode region and the drain electrode region and the upper portion of the data line 117 and the data pad line 117p remain.

Subsequently, as shown in FIG. 7F, the array substrate 110 is removed by removing a portion of the second conductive film pattern using the remaining sixth photoresist pattern 170a ′ to ninth photoresist pattern 170d ′ as a mask. A source electrode 122 and a drain electrode 123 formed of the second conductive film are formed in the pixel portion.

In this case, the first n + amorphous silicon thin film pattern 125 ′ formed of an n + amorphous silicon thin film remains on the active pattern 124, and is formed on the entire surface of the array substrate 110 to form a pixel electrode to be described later. When the third conductive layer is deposited, the channel region of the active pattern 124, specifically, the back channel, may be prevented from being contaminated by the deposition of the third conductive layer.

As described above, the first embodiment of the present invention uses a half-tone mask to form the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 through one mask process. do.

Next, as illustrated in FIGS. 5C and 6C, a third conductive layer is formed on the entire surface of the array substrate 110 on which the active patterns 124, the source / drain electrodes 122 and 123, and the data lines 117 are formed. do.

Thereafter, the third conductive film is selectively patterned using a photolithography process (third mask process) to form a pixel electrode 118 directly connected to the drain electrode 123 in the pixel portion of the array substrate 110. do.

In this case, the first n + amorphous silicon thin film pattern may be selectively removed through the third mask process to ohmic contact between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123. The ohmic contact layer 125n is formed.

As described above, according to the first exemplary embodiment of the present invention, the pixel electrode 118 and the ohmic contact layer 125n can be formed through a single mask process by using a half-tone mask in the third mask process. This will be described in detail with reference to the drawings. However, the present invention is not limited thereto, and the ohmic contact layer 125n may be formed during the process of forming the source electrode 122 and the drain electrode 123 in the second mask process.

8A through 8F are cross-sectional views illustrating a third mask process according to the first embodiment of the present invention in the array substrate illustrated in FIGS. 5C and 6C.

As shown in FIG. 8A, a third conductive layer 150 is formed on the entire surface of the array substrate 110 on which the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 are formed.

In this case, the third conductive layer includes a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a pixel electrode.

In this case, when the first n + amorphous silicon thin film pattern 125 ′ remains on the channel region of the active pattern 124 as described above, the back channel of the active pattern 124 is formed by deposition of the third conductive layer. It is possible to prevent contamination.

As shown in FIG. 8B, after forming the second photosensitive film 175 made of photosensitive material such as photoresist on the entire surface of the array substrate 110, the second half- according to the first embodiment of the present invention is formed. Light is selectively irradiated to the second photosensitive layer 175 through a tone mask 185.

In this case, the second half-tone mask 185 blocks the first transmission region I through which all of the irradiated light is transmitted and the second transmission region II through which only a part of the light is transmitted and partly blocks the light. The blocking region III is provided, and only the light passing through the second half-tone mask 185 is irradiated to the second photosensitive film 175.

Subsequently, after developing the second photoresist layer 175 exposed through the second half-tone mask 185, as shown in FIG. 8C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 175a and the second photoresist pattern 175b having a predetermined thickness remain in the region where all of the light is blocked or partially blocked by the light, and the first transmission region I through which all the light is transmitted The second photoresist film is completely removed to expose the surface of the third conductive film 150.

In this case, the first photoresist pattern 175a formed in the blocking region III is thicker than the second photoresist pattern 175b formed through the second transmission region II. In addition, the second photoresist layer is completely removed in a region where light is entirely transmitted through the first transmissive region I because the photoresist of the positive type is used. The present invention is not limited to this, A photoresist may be used.

Next, as shown in FIG. 8D, the second conductive film and the first n + amorphous silicon thin film formed below the first photosensitive film pattern 175a and the second photosensitive film pattern 175b formed as a mask are used as masks. When the pattern is selectively removed, an ohmic contact layer 125n formed of the n + amorphous silicon thin film and patterned in the same shape as the source / drain 122 and 123 is formed in the pixel portion of the array substrate 110. Will be.

In this case, the ohmic contact layer 125n serves to ohmic contact between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123.

Subsequently, as shown in FIG. 8E, an ashing process of removing a portion of the first photoresist pattern and the second photoresist pattern is performed to completely remove the second photoresist pattern of the second transmission region II.

In this case, the first photoresist layer pattern is a third photoresist layer pattern 175a 'from which the thickness of the second photoresist layer pattern is removed and remains only in the pixel electrode region corresponding to the blocking region III.

Subsequently, as shown in FIG. 8F, a portion of the third conductive film is removed by using the remaining third photoresist pattern 175a 'as a mask, and thus the pixel portion of the array substrate 110 is transferred to the third conductive film. The pixel electrode 118 thus formed is formed.

In this case, the pixel electrode 118 may be directly connected to a part of the drain electrode 123 without a separate contact hole, thereby eliminating a mask process required to form the contact hole.

Next, as shown in FIGS. 5D and 6D, after forming the second insulating film 115b over the array substrate 110 on which the pixel electrode 118 is formed, the photolithography process (fourth mask process) is performed. The first contact hole 140a and the second contact hole 140a expose a portion of the data pad line 117p and the gate pad line 116p to the data pad part and the gate pad part of the array substrate 110 by selectively removing the insulating film. The contact hole 140b is formed.

As illustrated in FIGS. 5E and 6E, a fourth conductive layer formed of a transparent conductive material is formed on the entire surface of the second insulating layer 115b in which the first contact hole 140a and the second contact hole 140b are formed. Thereafter, by selectively patterning using a photolithography process (a fifth mask process), a common electrode 108 having a plurality of slits 108s is formed in the pixel region.

In this case, by selectively patterning the fourth conductive layer using the fifth mask process, the data pad portion and the gate pad portion respectively pass through the first contact hole 140a and the second contact hole 140b. The data pad electrode 127p and the gate pad electrode 126p electrically connected to the line 117p and the gate pad line 116p are formed.

In this case, the fourth conductive layer is a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form the common electrode 108, the data pad electrode 127p, and the gate pad electrode 126p. It includes.

In addition, the common electrode 108 according to the first embodiment of the present invention is formed in a single pattern over the entire pixel portion, and a plurality of common electrodes 108 are disposed in the pixel region in which the pixel electrode 118 is formed. Slits 108s are formed.

In this case, since the common electrode 108 is formed in a single pattern over the entire pixel portion, the common electrode 108 is also formed on the gate line 116, the data line 117, and the thin film transistor, in which the plurality of slits 108s are not formed. It is characterized by that. For reference, the pixel portion refers to the area of the brand of the array substrate 110 in which all pixel regions are collected to display an image.

In particular, in the fringe field type liquid crystal display device according to the first embodiment of the present invention, since the common electrode 108 is formed on the data line 117, the aperture ratio of the liquid crystal display panel is improved, and the pixel electrode 118 Left and right ends are present in the outermost slit 108s around the data line 117 to maximize the transmittance around the data line 117.

In addition, the pixel electrode 118 is directly overlapped with the drain electrode 124 of the thin film transistor to form a contact hole for connecting the pixel electrode 118 and the drain electrode 123. Do not need to be formed in the pixel region, thereby increasing the aperture ratio of the pixel region.

The array substrate according to the first embodiment of the present invention manufactured as described above is configured to form a liquid crystal display device by being bonded to face the color filter substrate, which will be described in detail with reference to the accompanying drawings.

FIG. 9 is a schematic cross-sectional view of a fringe field type liquid crystal display device according to a first exemplary embodiment in which the array substrate and the color filter substrate illustrated in FIG. 4 are bonded to each other. FIG. A fringe field type liquid crystal display device in which black matrices are removed by acting as a matrix is shown.

As shown in the drawing, the array substrate 110 fabricated as described above is bonded to the color filter substrate 105 in a state where a constant cell gap is maintained by column spacers (not shown) formed on the color filter substrate 105. Thus, the liquid crystal display device is configured.

At this time, the color filter substrate 105 is formed on the transparent color filter substrate 105, a color filter consisting of red, green and blue sub-color filters (106a, 106b), the sub-color filter (106a, Some parts of 106b) overlap each other and act as a black matrix.

The black matrix is a component that is patterned in the boundary region of the pixels to block leakage of light generated from the backlight of the lower portion of the liquid crystal display and prevents color mixing of adjacent pixels. In the case of the first embodiment of the present invention, Since the overlapped regions of the sub-color filters 106a and 106b serve as the black matrix, the mask process for forming the black matrix can be omitted.

In this case, although not shown in the drawings, an overcoat layer may be further formed on the color filter, and the overcoat layer may be formed by overlapping portions of the sub-color filters 106a and 106b. It removes the step and serves to planarize the upper surface of the color filter.

For reference, reference numeral d denotes a distance between the data line 117 and the pixel electrode 118, and the pixel electrode 118 of the first embodiment of the present invention is spaced apart from the data line 117 by a predetermined distance. By being located between the outermost slits 108a, the aperture ratio and the transmittance can be improved as much as possible.

In the fringe field type liquid crystal display device according to the first embodiment configured as described above, black matrix does not exist on the data line 117, and thus variations occur during the bonding process of the color filter substrate 105 and the array substrate 110. In some cases, color mixing defects may occur due to color mixing around the data line 117.

Accordingly, the fringe field type liquid crystal display device according to the second embodiment of the present invention, in which the common electrode on the data line is overlapped with the pixel electrode to reduce the transmittance around the data line to prevent the color mixing defect, will be described in detail with reference to the drawings. Explain.

FIG. 10 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention, except for the configuration of the pixel electrode and the common electrode. Consists of the same components as the display device.

As shown in the figure, in the array substrate 210 according to the second embodiment of the present invention, a gate line 216 and a data line 217 arranged vertically and horizontally on the array substrate 210 to define a pixel area are provided. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 216 and the data line 217, and a plurality of slits for driving a liquid crystal (not shown) by generating a fringe field in the pixel area. A common electrode 208 having 208s and a pixel electrode 218 in the form of a box are formed.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 electrically connected to the pixel electrode 218. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

In this case, a part of the source electrode 222 extends in one direction to form a part of the data line 217, and a part of the drain electrode 223 extends toward the pixel area to directly contact the pixel electrode without a separate contact hole. 218 is electrically connected.

As in the first embodiment described above, a common electrode 208 and a pixel electrode 218 having a plurality of slits 208s for generating a fringe field are formed in the pixel region, wherein the pixel electrode 218 is formed. Is formed in a box shape in the pixel region, and the common electrode 208 is formed to have a single pattern over the entire pixel portion and to have a plurality of slits 208s in each pixel region. It is done.

In addition, when the common electrode 208 is formed in a single pattern over the entire pixel portion, it is necessary to form a common line for electrically connecting the common electrodes as compared with the case where the common electrode is formed in each pixel region. There will be no. As a result, the number of masks required to fabricate the array substrate 210 can be reduced by one.

In addition, since the opaque common line is not necessary as described above, the common electrode 208 is also formed on the data line 217, so that the aperture ratio is improved. In this case, the pixel electrode 218 of the second embodiment of the present invention The transmittance around the data line 217 may be improved by forming a portion closer to the data line 217 than the pixel electrode of the first embodiment and partially overlapping the common electrode 208 on the data line 217. It is possible to prevent the above-described color mixing defects by lowering.

The gate pad electrode 226p and the data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad The line 217p receives a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

For reference, reference numerals 240a and 240b denote first and second contact holes, respectively, wherein the data pad electrode 227p is electrically connected to the data pad line 217p through the first contact hole 240a. The gate pad electrode 226p is electrically connected to the gate pad line 216p through the second contact hole 240b.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device according to a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

11A through 11E are cross-sectional views sequentially illustrating a manufacturing process along lines Xa-Xa ', Xb-Xb, and Xc-Xc of the array substrate illustrated in FIG. 10, and a process of manufacturing an array substrate of a pixel portion is shown on the left side. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

12A to 12E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 10.

As shown in FIGS. 11A and 12A, a gate electrode 221 and a gate line 216 are formed in a pixel portion of the array substrate 210 made of a transparent insulating material such as glass, and the array substrate 210 may be formed. A gate pad line 216p is formed in the gate pad portion.

In this case, the gate electrode 221, the gate line 216, and the gate pad line 216p may be selectively deposited through a photolithography process (first mask process) after depositing a first conductive layer on the entire surface of the array substrate 210. It is formed by patterning.

Next, as shown in FIGS. 11B and 12B, the first insulating layer 215a and the amorphous layer are formed on the entire surface of the array substrate 210 on which the gate electrode 221, the gate line 216, and the gate pad line 216p are formed. A silicon thin film, an n + amorphous silicon thin film and a second conductive film are formed.

Thereafter, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (second mask process), thereby forming an active pattern formed of the amorphous silicon thin film in the pixel portion of the array substrate 210 ( 224 is formed, and a source electrode 222 and a drain electrode 223 formed of the second conductive layer are formed on the active pattern 224.

In this case, a data line 217 made of the second conductive layer is formed in the data line region of the array substrate 210 through the second mask process, and the second data pad portion of the array substrate 210 is formed. A data pad line 217p made of a conductive film is formed.

In this case, a first n + amorphous silicon thin film pattern 225 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 224 is formed on the active pattern 224.

In addition, the amorphous silicon thin film and the n + amorphous silicon thin film are formed under the data line 217 and the data pad line 217p, respectively, and are patterned in the same form as the data line 217 and the data pad line 217p. The first amorphous silicon thin film pattern 224 ', the second n + amorphous silicon thin film pattern 225 ", the second amorphous silicon thin film pattern 224", and the third n + amorphous silicon thin film pattern 225' "are formed, respectively. .

Here, the active pattern 224, the source / drain electrodes 222 and 223, and the data line 217 according to the second embodiment of the present invention are once used by using a half-tone mask as in the case of the first embodiment. It can be formed at the same time through the mask process (second mask process), but the present invention is not limited to this, the active pattern 224 and the source / drain electrodes 222 and 223 and the data line 217 It can also be formed by a mask process.

Next, as illustrated in FIGS. 11C and 12C, a third conductive layer is formed on the entire surface of the array substrate 210 on which the active patterns 224, the source / drain electrodes 222 and 223, and the data lines 217 are formed. do.

Thereafter, the third conductive layer is selectively patterned using a photolithography process (third mask process) to form a pixel electrode 218 directly connected to the drain electrode 223 in the pixel portion of the array substrate 210. do.

In this case, the first n + amorphous silicon thin film pattern may be selectively removed through the third mask process to ohmic contact between the source / drain region of the active pattern 224 and the source / drain electrodes 222 and 223. The ohmic contact layer 225n is formed.

As described above, the second embodiment of the present invention uses the half-tone mask in the third mask process as in the case of the first embodiment to mask the pixel electrode 218 and the ohmic contact layer 225n once. The present invention may be formed through a process, but the present invention is not limited thereto. The ohmic contact layer 225n may be formed during the process of forming the source electrode 222 and the drain electrode 223 in the second mask process. You may.

However, the pixel electrode 218 of the second embodiment of the present invention is formed closer to the adjacent data line 217 than the pixel electrode of the first embodiment.

Next, as shown in FIGS. 11D and 12D, after forming the second insulating film 215b on the entire surface of the array substrate 210 on which the pixel electrode 218 is formed, the photolithography process (fourth mask process) is performed. Selectively removing the first contact hole 240a and the second contact hole 240a to expose a portion of the data pad line 217p and the gate pad line 216p, respectively, by selectively removing the data through the data pad portion and the gate pad portion of the array substrate 210. The contact hole 240b is formed.

11E and 12E, a fourth conductive film made of a transparent conductive material is formed on the entire surface of the second insulating film 215b in which the first contact hole 240a and the second contact hole 240b are formed. Thereafter, by selectively patterning using a photolithography process (a fifth mask process), a common electrode 208 having a plurality of slits 208s is formed in the pixel region.

In this case, by selectively patterning the fourth conductive layer by using the fifth mask process, the data pad part and the gate pad part respectively pass through the first contact hole 240a and the second contact hole 240b. A data pad electrode 227p and a gate pad electrode 226p electrically connected to the line 217p and the gate pad line 216p are formed.

In this case, the common electrode 208 according to the second embodiment of the present invention is formed in a single pattern over the entire pixel portion as in the first embodiment, and the pixel electrode 218 is formed within the pixel region. A plurality of slits 208s are formed in the common electrode 208.

However, in the fringe field type liquid crystal display device according to the second embodiment of the present invention, the pixel electrode 218 is formed closer to the adjacent data line 217, while the pixel electrode 218 is formed on the data line 217. By partially overlapping the common electrode 208, the transmittance around the data line 217 may be lowered to prevent the above-described color mixing failure.

That is, the outermost slit 208s of the common electrode 208 according to the second embodiment of the present invention is formed on the pixel electrode 218 in a form spaced apart from the data line 217 by a predetermined interval. In this case, the pixel electrode 218 may be formed to have a distance of about 3 μm from the data line 217.

The array substrate according to the second embodiment of the present invention manufactured as described above is configured to form a liquid crystal display device by being bonded to face the color filter substrate, which will be described in detail with reference to the accompanying drawings.

FIG. 13 is a schematic cross-sectional view of a fringe field type liquid crystal display device according to a second exemplary embodiment in which the array substrate and the color filter substrate illustrated in FIG. 10 are bonded to each other. The adjacent sub-color filters are overlapped with each other. A fringe field type liquid crystal display device in which black matrices are removed by acting as a matrix is shown.

As shown in the drawing, the array substrate 210 fabricated as described above is bonded to the color filter substrate 205 in a state where a constant cell gap is maintained by a column spacer (not shown) formed on the color filter substrate 205. Thus, the liquid crystal display device is configured.

At this time, the color filter substrate 205 is formed on the transparent color filter substrate 205, a color filter consisting of red, green and blue sub-color filters (206a, 206b), the sub-color filter (206a, Portions of 206b) overlap each other and serve as a black matrix.

In this case, reference numeral d 'denotes a distance between the data line 217 and the pixel electrode 218, and the pixel electrode 218 of the second embodiment of the present invention has the data line 217 as compared with the case of the first embodiment. It is formed to be closer to the () while overlapping the common electrode 208 on the data line 217 by W width to reduce the transmittance around the data line 217 to prevent the above-described color mixing failure Will be.

FIG. 14A is a graph schematically illustrating the transmittance of a pixel region in the fringe field type liquid crystal display according to the first embodiment of the present invention illustrated in FIG. 4, and FIG. 14B is a second embodiment of the present invention illustrated in FIG. 10. In the fringe field type liquid crystal display device according to an example, it is a graph schematically showing the transmittance of a pixel region.

14A and 14B illustrate the results obtained by simulation of the shape of the electric field lines of the fringe field formed by the pixel electrode and the common electrode according to the distance from the data line and the corresponding transmittance.

14A illustrates a case where the distance d between the pixel electrode and the data line is 5 μm, the widths of all the slits except the common electrode and the outermost slit are 4 μm, and the width of the outermost slit is 6 μm. The transmittance is shown.

In addition, in FIG. 14B, the distance d ′ between the pixel electrode and the data line is 3 μm, the width of the common electrode and all the slits is 4 μm, and the common electrode on the pixel electrode and the data line is about 1 μm. Transmittance when overlapping with width W

As shown in the figure, in the fringe field type liquid crystal display of the second embodiment, it can be seen that the transmittance B around the data line decreases sharply compared with the transmittance A of the first embodiment. As a result, even in the case of poor adhesion, color mixing defects around the data line 217 can be prevented.

In the fringe field type liquid crystal display device of the first and second embodiments of the present invention configured as described above, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern is described as an example, but the present invention is not limited thereto. The present invention is also applicable to a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as the active pattern.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view showing a portion of an array substrate of a fringe field type liquid crystal display device;

3A to 3F are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate shown in FIG. 2.

4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention;

5A to 5E are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate shown in FIG.

6A to 6E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A to 7F are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5B and 6B.

8A to 8F are cross-sectional views illustrating a third mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5C and 6C.

9 is a schematic cross-sectional view of a fringe field type liquid crystal display device according to a first embodiment of the present invention in which the array substrate and the color filter substrate shown in FIG. 4 are bonded to each other.

10 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention.

11A to 11E are cross-sectional views sequentially illustrating a manufacturing process along lines Xa-Xa ', Xb-Xb and Xc-Xc of the array substrate shown in FIG.

12A to 12E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 10.

FIG. 13 is a schematic cross-sectional view of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention in which the array substrate and the color filter substrate illustrated in FIG. 10 are bonded to each other.

FIG. 14A is a graph schematically illustrating the transmittance of a pixel region in the fringe field type liquid crystal display device according to the first embodiment of the present invention shown in FIG. 4.

FIG. 14B is a graph schematically illustrating transmittance of a pixel region in the fringe field type liquid crystal display device according to the second embodiment of the present invention shown in FIG. 10.

DESCRIPTION OF REFERENCE NUMERALS

108,208 Common electrode 108s, 208s Slit

110,210: array substrate 116,216: gate line

117,217 data line 118,218 pixel electrode

121,221 gate electrode 122,222 source electrode

123,223 Drain electrode 124,224 Active pattern

Claims (9)

Providing a first substrate including a pixel portion; Forming a gate electrode and a gate line on the first substrate through a first mask process; Forming a first insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active pattern on the gate electrode with the first insulating layer interposed therebetween, and forming an n + amorphous silicon thin film pattern patterned on the active pattern in the same form as the active pattern; Forming a source electrode and a drain electrode electrically connected to the source region and the drain region of the active pattern using the second mask process, and defining a pixel region intersecting the gate line; Forming a; Forming a box-shaped pixel electrode directly connected to a portion of the drain electrode in the pixel region through a third mask process, and removing a portion of the n + amorphous silicon thin film pattern to form an ohmic contact layer; Forming a second insulating film on the first substrate on which the pixel electrode is formed; Forming a common electrode on the entire pixel portion of the first substrate on which the second insulating film is formed through a fourth mask process, and forming the common electrode to have a plurality of slits in the pixel region; And A method of manufacturing a fringe field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate. The method of claim 1, wherein the pixel electrode partially overlaps the common electrode on the data line. The method of claim 1, wherein a color filter including a sub-color filter is formed on the second substrate, and adjacent sub-color filters overlap and serve as a black matrix. . The method of claim 1, wherein the outermost slit of the common electrode is spaced apart from the data line by a predetermined distance and is formed on the pixel electrode. The method of claim 1, wherein the pixel electrode is formed to have a distance of 3 μm from the data line. A first substrate including a pixel portion; A gate electrode and a gate line formed on the first substrate; A first insulating film formed on the first substrate on which the gate electrode and the gate line are formed; An active pattern formed on the gate electrode with the first insulating layer interposed therebetween; A source electrode and a drain electrode formed on the first substrate on which the first insulating film is formed, and electrically connected to the source region and the drain region of the active pattern; A data line formed on the first substrate on which the first insulating film is formed and defining a pixel region crossing the gate line; A box electrode formed in the pixel area and directly connected to a part of the drain electrode; A second insulating film formed on the first substrate on which the pixel electrode is formed; A common electrode formed on the entire pixel portion of the first substrate on which the second insulating film is formed, the common electrode having a plurality of slits in the pixel region; A second substrate joined to face the first substrate; And A fringe field type liquid crystal display device, wherein the sub-color filter is formed on the second substrate, and adjacent sub-color filters include a color filter overlapping and serving as a black matrix. 7. The fringe field type liquid crystal display of claim 6, wherein the outermost slit of the common electrode is positioned on the pixel electrode spaced apart from the data line by a predetermined distance. 8. The fringe field type liquid crystal display device according to claim 7, wherein the pixel electrode is positioned to be spaced apart from the data line by 3 mu m. The fringe field type liquid crystal display device according to claim 6, wherein the slit width of the common electrode and the distance between the slits are the same.

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