KR20090044467A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The liquid crystal display of the present invention and a method of manufacturing the same are formed by forming an opaque light shielding pattern below the data line and / or the gate line to serve as a black matrix of the upper color filter substrate. Providing a first substrate to prevent light leakage due to misalignment at the time of adhesion while minimizing the margin of the upper black matrix to improve the aperture ratio. Forming a light shielding pattern on the first substrate through a first mask process; Forming an active pattern, a source / drain electrode, and a data line on the light blocking pattern with the first insulating layer interposed using the first mask process; A gate line is formed on the active pattern of the first substrate while the second insulating layer is interposed through a second mask process, and the gate line crosses the data line to define a pixel region in the pixel portion of the first substrate. Forming a; Forming a third insulating film on the first substrate; Forming a contact hole exposing a portion of the drain electrode by removing a portion of the third insulating layer through a third mask process; Forming a pixel electrode electrically connected to the drain electrode through the contact hole using a fourth mask process; And bonding the first substrate and the second substrate to each other.

The liquid crystal display and the manufacturing method thereof according to the present invention configured as described above use a half-gate mask to simultaneously form a source / drain electrode, an active pattern, and the light shielding pattern, thereby performing a top gate array substrate in a four mask process. It characterized in that the production.

Data line, gate line, shading pattern, 4 mask, active pattern

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to reduce the number of masks to simplify the manufacturing process, improve the yield and at the same time minimize the margin of the black matrix of the upper color filter substrate to improve the aperture ratio The present invention relates to a liquid crystal display device and a manufacturing method thereof.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 using a photolithography process (first mask process).

Next, as shown in FIG. 2B, the first insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed. The active pattern 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same shape as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 2C, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (third mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process, thereby forming an ohmic − between the active pattern 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25 'is formed.

Next, as shown in FIG. 2D, a second insulating film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process (fourth mask). The contact hole 40 exposing a part of the drain electrode 23 is formed by removing a part of the second insulating layer 15b through the process).

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned by using a photolithography process (a fifth mask process) through the contact hole 40. The pixel electrode 18 electrically connected to the drain electrode 23 is formed.

As described above, manufacturing of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active pattern, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. It has the disadvantage of dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

The array substrate manufactured as described above is bonded to the color filter substrate 5 in a state where a constant cell gap is maintained by a column spacer (not shown) formed on the color filter substrate 5 as shown in FIG. 3. The liquid crystal display device is constructed.

In this case, as described above, the color filter substrate 5 is a color filter composed of a plurality of sub-color filters 7 for implementing red, green, and blue colors on the transparent color filter substrate 5 and the sub-color. A black matrix 6 is formed between the filters 7 and blocks light passing through the liquid crystal layer 90, and a transparent common electrode 8 applying a voltage to the liquid crystal layer 90.

The black matrix 6 is patterned at the boundary area of the pixels to block leakage of light generated from the backlight of the lower part of the liquid crystal display, and to prevent color mixing of adjacent pixels. In order to improve light leakage due to misalignment generated when the array substrate 10 is bonded, the array substrate 10 has a predetermined margin d.

In particular, when the color filter substrate 5 and the array substrate 10 are bonded together, light leakage may occur around the data line 17 due to misalignment. In order to prevent this, the margin d of the black matrix is stored in the data matrix. It is formed to have a width wider than the width of the line (17). Such a margin (d) of the black matrix is a factor for lowering the aperture ratio of the liquid crystal display device, and its improvement is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can realize a high brightness by enlarging the aperture region and at the same time improve light defects caused by misalignment.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device in which the high-aperture rate liquid crystal display device is manufactured by four mask processes.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display of the present invention comprises a light shielding pattern formed on the first substrate; An active pattern and an amorphous silicon thin film pattern formed on the light blocking pattern with a first insulating film interposed therebetween; A source electrode and a drain electrode formed on the active pattern and electrically connected to a source region and a drain region of the active pattern; a data line formed on the amorphous silicon thin film pattern with an n + amorphous silicon thin film pattern interposed therebetween; A gate electrode formed on the active pattern with a second insulating layer interposed therebetween; A gate line formed on the amorphous silicon thin film pattern with the second insulating layer interposed therebetween and defining a pixel area crossing the data line; A third insulating film formed on the first substrate; A pixel electrode formed in the pixel region and electrically connected to the drain electrode through a contact hole formed in the third insulating layer; And a second substrate bonded to and opposed to the first substrate.

In addition, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate; Forming a light shielding pattern on the first substrate through a first mask process; Forming an active pattern, a source / drain electrode, and a data line on the light blocking pattern with the first insulating layer interposed using the first mask process; A gate line is formed on the active pattern of the first substrate while the second insulating layer is interposed through a second mask process, and the gate line crosses the data line to define a pixel region in the pixel portion of the first substrate. Forming a; Forming a third insulating film on the first substrate; Forming a contact hole exposing a portion of the drain electrode by removing a portion of the third insulating layer through a third mask process; Forming a pixel electrode electrically connected to the drain electrode through the contact hole using a fourth mask process; And bonding the first substrate and the second substrate to each other.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the liquid crystal display and the method of manufacturing the same according to the present invention provide the effect of improving the aperture ratio by minimizing the margin of the black matrix.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention. FIG. 4 includes a thin film transistor including a gate pad part, a data pad part, and a pixel part for convenience of description. The pixel is shown.

That is, in an actual liquid crystal display device, N gate lines and M data lines cross each other, and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged vertically and horizontally on the array substrate 110 to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor is electrically connected to the pixel electrode 118 through the gate electrode 121 connected to the gate line 116, the source electrode 122 connected to the data line 117, and the first contact hole 140a. The drain electrode 123 is connected. In addition, the thin film transistor includes an active pattern 124 that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

In this case, the thin film transistor according to the first embodiment of the present invention is characterized in that the gate electrode 121 is a top gate method positioned on the source electrode 122, the drain electrode 123, and the active pattern 124. It is done.

In addition, the array substrate 110 according to the first embodiment of the present invention has a light shielding pattern made of an opaque conductive material such as chromium under the active pattern 124, the data line 117, and the data pad line 117p. 130 ', 130 ", and 130'" are formed, and the light blocking patterns 130 ', 130 ", and 130'" are formed in the thin film transistor region, the data line 117 region, and the data pad line ( 117p) serves to block the transmission of light to the area. For reference, reference numerals 124 'and 124 "denote a first amorphous silicon thin film pattern and a second amorphous silicon thin film pattern made of an amorphous silicon thin film.

In this case, a common line 108l is arranged in a direction substantially parallel to the gate line 116 in the pixel area, and a part of the common line 108l is interposed between a third insulating film (not shown). In addition, a storage capacitor Cst is formed by overlapping a portion of the pixel electrode 118 thereon. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. In general, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is input and is leaked. Disappear. Therefore, in order to maintain the applied voltage, the storage capacitor Cst needs to be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stability of gray scale display and reduction of flicker and afterimage in addition to signal retention.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140b and 140c indicate a second contact hole and a third contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the second contact hole 140b. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c.

Here, the liquid crystal display according to the first exemplary embodiment of the present invention uses a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask to include a diffraction mask) and an active pattern and a source / The drain electrode and the data line are formed in one mask process, and the light shielding pattern of the present invention is formed under the active pattern and the data line by using the mask process. Thus, an array substrate can be manufactured in a total of four mask processes. .

In this case, in the liquid crystal display according to the first exemplary embodiment of the present invention, a light blocking pattern is disposed on a lower layer to form the light blocking pattern, an active pattern, and a source / drain electrode in one mask process, and the active pattern and the source are sequentially formed on the upper layer. The top gate method in which the drain electrode and the first insulating film are formed and the gate electrode is formed thereon is described, which will be described in detail through the following manufacturing method of the liquid crystal display.

5A through 5D are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate illustrated in FIG. 4, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

6A to 6D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

As shown in FIGS. 5A and 6A, a first conductive film, a first insulating film 115, an amorphous silicon thin film, an n + amorphous silicon thin film, and a second conductive film are formed on an array substrate 110 made of a transparent insulating material such as glass. Deposit.

Thereafter, the first conductive film, the first insulating film 115, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (a first mask process). An active pattern 124 formed of the amorphous silicon thin film is formed in the pixel portion, and a source electrode 122 and a drain electrode 123 formed of the second conductive layer are formed on the active pattern 124.

In this case, a data line 117 made of the second conductive layer is formed in the data line region of the array substrate 110 through the first mask process, and the second data pad portion of the array substrate 110 is formed. A data pad line 117p made of a conductive film is formed.

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active pattern 124 and ohmic-contacting between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123. 125n is formed.

In addition, the first light shielding pattern 130 formed of the first conductive film and patterned substantially in the same shape as the active pattern 124 with the first insulating film 115 interposed under the active pattern 124. ') Is formed.

Further, a fourth n + amorphous layer formed of the n + amorphous silicon thin film under the data line 117 and the data pad line 117p and patterned in substantially the same shape as the data line 117 and the data pad line 117p. A silicon thin film pattern 125 ″ ″ and a fifth n + amorphous silicon thin film pattern 125 ″ ″ ″ are formed. The first conductive film, the first insulating film 115, and the amorphous silicon thin film are formed under the fourth n + amorphous silicon thin film pattern 125 ″ ″ and the fifth n + amorphous silicon thin film pattern 125 ″ ″ ″, respectively. A second light shielding pattern 130 "patterned to have a width substantially equal to or wider than that of the fourth n + amorphous silicon thin film pattern 125" "and the fifth n + amorphous silicon thin film pattern 125 '" ", respectively. And the first amorphous silicon thin film pattern 124 ', the third light blocking pattern 130' ", and the second amorphous silicon thin film pattern 124" are formed.

The active pattern 124, the source / drain electrodes 122 and 123, the data line 117, and the first to third light blocking patterns 130 ′ to 130 ″ according to the first embodiment of the present invention By using the half-tone mask, it is possible to simultaneously form through one mask process (first mask process), and the first mask process will be described in detail with reference to the following drawings, but the present invention is not limited thereto. The active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 may be formed by two mask processes.

7A to 7G are cross-sectional views illustrating in detail the first mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5A and 6A.

As shown in FIG. 7A, the first conductive layer 130, the first insulating layer 115, the amorphous silicon thin film 120, the n + amorphous silicon thin film 125 and the second are sequentially disposed on the entire surface of the array substrate 110. The conductive film 150 is formed.

In this case, the first conductive layer 130 may be made of an opaque conductive material such as chromium (Cr) to form the first to third light blocking patterns, and the second conductive layer 150 may be a source electrode. Aluminum (Al), aluminum alloy (Tungsten; W), copper (Cu), chromium, molybdenum (Mo) and molybdenum alloy ( It can be made of a low resistance opaque conductive material, such as molally).

As shown in FIG. 7B, after forming the photoresist film 170 made of a photoresist such as a photoresist on the entire surface of the array substrate 110, the half-tone mask according to the first embodiment of the present invention ( Light is selectively irradiated to the photosensitive film 170 through 180.

In this case, the half-tone mask 180 includes a first transmission region I transmitting all of the irradiated light, a second transmission region II transmitting only a part of the light, and blocking a portion of the light, and blocking all the irradiated light. The region III is provided, and only the light passing through the first half-tone mask 180 is irradiated to the photosensitive film 170.

Subsequently, after developing the photoresist film 170 exposed through the half-tone mask 180, light passes through the blocking region III and the second transmission region II, as shown in FIG. 7C. The first photoresist pattern 170a to the fifth photoresist pattern 170e having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the second conductive layer 150 is exposed.

In this case, the first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III are formed thicker than the fifth photoresist pattern 170e formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. May be used.

Next, as shown in FIG. 7D, the first conductive film and the first insulating film 115 formed under the first photosensitive film pattern 170a to the fifth photosensitive film pattern 170e formed as above as a mask are used as masks. ), When the amorphous silicon thin film, the n + amorphous silicon thin film and the second conductive film are selectively removed, an active pattern 124 made of the amorphous silicon thin film is formed in the pixel portion of the array substrate 110.

The first light blocking pattern 130 ′ and the second light blocking pattern 130 ′ formed of the first conductive layer with the first insulating layer 115 interposed in the lower portion of the active pattern 124, the data line region, and the data pad line region. The light blocking pattern 130 ″ and the third light blocking pattern 130 ″ ″ are formed.

At this time, the first n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and the second conductive layer and patterned substantially in the same shape as the active pattern 124 on the active pattern 124, respectively. The second conductive film pattern 150 ′ is formed.

In addition, the second light blocking pattern 130 ″ and the third light blocking pattern 130 ″ ″ are formed of the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film, respectively, and the second light blocking pattern 130 is substantially formed. The first amorphous silicon thin film pattern 124 'and the second n + amorphous silicon thin film pattern 125 ", the data line pattern 150 " The second amorphous silicon thin film pattern 124 ", the third n + amorphous silicon thin film pattern 125 '", and the data pad line pattern 150' "are formed, respectively.

Subsequently, as shown in FIG. 7E, an ashing process of removing a portion of the first to fifth photoresist patterns may be performed to completely remove the fifth photoresist pattern of the second transmission region II. do.

In this case, the first photoresist pattern to the fourth photoresist pattern correspond to the blocking region III by the sixth photoresist pattern 170a 'through the ninth photoresist pattern 170d' where the thickness of the fifth photoresist pattern is removed. Only the source / drain electrode region, the data line region and the data pad line region remain.

Here, in the case of the first embodiment of the present invention, the sixth photoresist pattern 170a 'to ninth photoresist pattern 170d' is not only thicker than the first to fourth photoresist patterns through the ashing process. Although the width thereof is reduced, the present invention is not limited thereto, and the sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' may include the first photoresist pattern and the fourth photoresist pattern. It may be patterned to have substantially the same width as.

Subsequently, as shown in FIGS. 7F and 7G, the array is removed by removing a portion of the second conductive film pattern using the remaining sixth photoresist pattern 170a ′ through the ninth photoresist pattern 170d ′ as a mask. The source electrode 122 and the drain electrode 123 formed of the second conductive layer are formed in the pixel portion of the substrate 110.

In addition, a portion of the data line pattern and the data pad line pattern is removed by using the remaining sixth photoresist pattern 170a 'to ninth photoresist pattern 170d' as a mask, thereby removing the data line region of the array substrate 110. And a data line 117 and a data pad line 117p each formed of the second conductive layer in the data pad line region.

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active pattern 124 and ohmic-contacting between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123. 125n is formed.

Further, a fourth n + amorphous layer formed of the n + amorphous silicon thin film under the data line 117 and the data pad line 117p and patterned in substantially the same shape as the data line 117 and the data pad line 117p. The silicon thin film pattern 125 ″ ″ and the fifth n + amorphous silicon thin film pattern 125 ″ ″ ″ are formed.

As described above, according to the first embodiment of the present invention, the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, and the first to third light blocking patterns 130 ′ are formed by using a half-tone mask. 130 '") can be formed through a single mask process.

In this case, the first to third light blocking patterns 130 'to 130' ″ of the first embodiment of the present invention are formed under the active pattern 124, the data line 117, and the data pad line 117p. For example, the present invention is not limited thereto, and the light shielding pattern of the present invention is not only the active pattern 124, the data line 117, and the data pad line 117p but also the gate line and the gate pad line. It may also be formed at the bottom.

Next, as shown in FIGS. 5B and 6B, the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, and the first to third light blocking patterns 130 ′ to 130 ′ are illustrated. The gate electrode 121, the gate line 116, and the common line 108l are formed in the pixel portion of the array substrate 110 having the " " formed thereon, and the array substrate 110 is formed. Gate pad line 116p is formed with the second insulating film 115a interposed therebetween.

In this case, the gate electrode 121, the gate line 116, the common line 108l, and the gate pad line 116p may form a third conductive layer on the active pattern 124, source / drain electrodes 122 and 123, and data. The line 117 and the first to third light blocking patterns 130 'to 130' are deposited on the entire surface of the array substrate 110, and then selectively patterned through a photolithography process (second mask process). .

Here, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy may be used as the third conductive film. The third conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

In this case, the liquid crystal display of the present invention has a top gate method in which the gate electrode 121 is positioned on the array substrate 110 on which the active pattern 124 and the source / drain electrodes 122 and 123 are formed. It features.

Next, as illustrated in FIGS. 5C and 6C, a third surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the common line 108l, and the gate pad line 116p is formed is formed. After the insulating film 115b is formed, the first contact hole 140a exposing a part of the drain electrode 123 of the array substrate 110 is formed by selectively removing the insulating film 115b through a photolithography process (third mask process). do.

In addition, a portion of the data pad line 117p and the gate pad line 116p may be removed from each of the data pad portion and the gate pad portion by removing a partial region of the third insulating layer 115b through the third mask process. The second contact hole 140b and the third contact hole 140c are formed to be exposed.

5D and 6D, a fourth conductive film made of a transparent conductive material is formed on the entire surface of the third insulating film 115b in which the first contact holes 140a to 3rd contact holes 140c are formed. After that, the pixel electrode 118 is electrically connected to the drain electrode 123 through the first contact hole 140a in the pixel region by selectively patterning the photolithography process (fourth mask process). Form.

In this case, by selectively patterning the fourth conductive layer by using the fourth mask process, the data pads are formed through the second contact hole 140b and the third contact hole 140c in the data pad part and the gate pad part, respectively. The data pad electrode 127p and the gate pad electrode 126p electrically connected to the line 117p and the gate pad line 116p are formed.

In this case, the fourth conductive layer may be formed of indium tin oxide (ITO) or indium zinc oxide to form the pixel electrode 118, the data pad electrode 127p, and the gate pad electrode 126p. It includes a transparent conductive material having excellent transmittance such as Indium Zinc Oxide (IZO).

The array substrate according to the first embodiment of the present invention manufactured as described above is configured to form a liquid crystal display device by being bonded to face the color filter substrate, which will be described in detail with reference to the accompanying drawings.

FIG. 8 is a schematic cross-sectional view of a liquid crystal display according to a first exemplary embodiment in which the array substrate and the color filter substrate illustrated in FIG. 5D are bonded to each other, and the light blocking pattern of the lower array substrate is black on the upper color filter substrate. The liquid crystal display device which acts as a matrix is shown.

As shown in the drawing, the array substrate 110 fabricated as described above is bonded to the color filter substrate 105 in a state where a constant cell gap is maintained by column spacers (not shown) formed on the color filter substrate 105. Thus, the liquid crystal display device is configured.

In this case, the color filter substrate 105 is a color filter composed of a plurality of sub-color filters 107 for implementing red, green and blue colors on the transparent color filter substrate 105 and the sub-color filter 107. It is composed of a black matrix 106 that separates and blocks light passing through the liquid crystal layer 190, and a transparent common electrode 108 that applies a voltage to the liquid crystal layer 190.

The black matrix 106 may be patterned on the boundary region of the pixels to block leakage of light generated from the backlight of the lower portion of the liquid crystal display and to prevent color mixing of adjacent pixels.

In this case, although not shown in the drawings, an overcoat layer may be further formed on the color filter, and the overcoat layer may include a portion of the sub-color filters 106 and the black matrix 106. It serves to planarize the upper surface of the color filter by removing the step that occurs as the overlap.

In this case, in the first exemplary embodiment of the present invention, the first light blocking pattern made of an opaque conductive material under the active pattern 124, the data line 117, and the data pad line (not shown) of the lower array substrate 110 is formed. 130 '), the second light blocking pattern 130 ", and the third light blocking pattern (not shown) form a role of the black matrix 106 to block leakage of light generated from the backlight of the lower part of the liquid crystal display as described above. As a result, the black matrix 106 of the color filter substrate 105 can reduce the margin d 'by the w width, thereby providing an effect of substantially improving the aperture ratio.

That is, even when misalignment occurs when the color filter substrate 105 and the array substrate 110 are bonded together, the active pattern 124, the data line 117, and the data of the array substrate 110 on which the black matrix 106 is positioned. The first light blocking pattern 130 ′, the second light blocking pattern 130 ″, and the third light blocking pattern made of an opaque conductive material are formed under the pad line, thereby preventing the leakage of light generated from the lower backlight. .

For reference, reference numeral d denotes a margin of the black matrix in the above-described conventional liquid crystal display device.

As described above, in the liquid crystal display of the first embodiment, the first light blocking pattern 130 ′, the second light blocking pattern 130 ″, and the first light blocking pattern 130 and the data pad line are disposed under the active pattern 124, the data line 117, and the data pad line. Although the case where the third light shielding pattern is formed is described by way of example, the present invention is not limited thereto, and the present invention is not limited thereto. Also applicable to the case, it will be described in detail through the following second embodiment of the present invention.

FIG. 9 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention, except that a light blocking pattern is formed under the gate line and the gate pad line, respectively. It is composed of the same components as the array substrate of the display device.

As shown in the figure, a gate line 216 and a data line 217 are formed on the array substrate 210 of the second embodiment to be arranged vertically and horizontally on the array substrate 210 to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed.

The thin film transistor is electrically connected to the pixel electrode 218 through a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a first contact hole 240a. The drain electrode 223 is connected. In addition, the thin film transistor includes an active pattern 224 that forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

In this case, the thin film transistor according to the second embodiment of the present invention is characterized in that the gate electrode 221 is a top gate method positioned on the source electrode 222, the drain electrode 223, and the active pattern 224. It is done.

In addition, the array substrate 210 according to the second embodiment of the present invention is the active pattern 224, the data line 217, the gate line 216, the data pad line 217p and the gate pad line 216p. A light shielding pattern 230 is formed at an lower portion of an opaque conductive material such as chromium. The light shielding pattern 230 includes the thin film transistor region, the data line 117 region, and the gate line 116 region. In this case, light is transmitted to the data pad line 117p region and the gate pad line 216p region. For reference, reference numeral 224 ′ denotes an amorphous silicon thin film pattern formed of an amorphous silicon thin film on the light blocking pattern 230.

In this case, a common line 208l is arranged in a direction substantially parallel to the gate line 216 in the pixel area, and a part of the common line 208l is interposed between a third insulating film (not shown). The storage capacitor Cst is formed by overlapping with a portion of the pixel electrode 218 thereon.

The gate pad electrode 226p and the data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad A line 217p is a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

For reference, reference numerals 240b and 240c represent second and third contact holes, respectively, wherein the data pad electrode 227p is electrically connected to the data pad line 217p through the second contact hole 240b. The gate pad electrode 226p is electrically connected to the gate pad line 216p through the third contact hole 240c.

Here, the liquid crystal display according to the second exemplary embodiment of the present invention not only has the active pattern 224, the data line 217, and the data pad line 217p but also the gate line 216 and the gate pad line 216p. As the light shielding pattern 230 made of an opaque conductive material exists, the black matrix margin of the upper color filter substrate may be further reduced as compared with the liquid crystal display of the first embodiment, and as a result, the aperture ratio may be further improved. .

10A is a plan view schematically illustrating a black matrix structure of an upper color filter substrate in a general liquid crystal display, and FIG. 10B is an upper color in the liquid crystal display according to the second embodiment of the present invention shown in FIG. 9. It is a top view which shows schematically the black matrix structure of a filter substrate.

As shown in FIG. 10A, a general liquid crystal display device is provided in order to block leakage of lower backlight light from the upper color filter substrate 5 to the thin film transistor region, the gate line region and the data line region of the lower array substrate. The black matrix 6 is formed.

In this case, the black matrix 6 is formed to have a predetermined margin to prevent light leakage caused by misalignment generated when the color filter substrate 5 and the array substrate are bonded together. As a result, in the case of a general liquid crystal display device, the aperture ratio decreases due to the margin of the black matrix.

As shown in FIG. 10B, in the liquid crystal display according to the second exemplary embodiment of the present invention, a light blocking pattern made of an opaque conductive material is formed in a thin film transistor region, a gate line region, and a data line region of a lower array substrate. The black matrix 206 of the color filter substrate 205 may be formed to have a minimum width for distinguishing red, green, and blue sub-color filters. As a result, the aperture ratio is improved by the reduced margin width of the black matrix.

In the first and second embodiments, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern is described as an example, but the present invention is not limited thereto, and the present invention is not limited thereto. The same applies to the polysilicon thin film transistors used.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a cross-sectional view schematically illustrating a general liquid crystal display device in which the array substrate and the color filter substrate illustrated in FIG. 2E are bonded to each other.

4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

5A to 5D are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate shown in FIG.

6A to 6D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A to 7G are cross-sectional views illustrating in detail the first mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5A and 6A.

FIG. 8 is a schematic cross-sectional view of a liquid crystal display according to a first exemplary embodiment of the present invention in which the array substrate and the color filter substrate illustrated in FIG. 5D are bonded to each other.

9 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 10A is a plan view schematically illustrating a black matrix structure of an upper color filter substrate in a general liquid crystal display device; FIG.

FIG. 10B is a plan view schematically illustrating a black matrix structure of an upper color filter substrate in the liquid crystal display according to the second exemplary embodiment of the present invention shown in FIG. 9.

** Explanation of symbols for main parts of drawings **

110,210: array substrate 116,216: gate line

117,217 data line 118,218 pixel electrode

121,221 gate electrode 122,222 source electrode

123,223 Drain electrode 124,224 Active pattern

130 '~ 130' ", 230: Shading pattern

Claims (15)

Providing a first substrate; Forming a light shielding pattern on the first substrate through a first mask process; Forming an active pattern, a source / drain electrode, and a data line on the light blocking pattern with the first insulating layer interposed using the first mask process; A gate line is formed on the active pattern of the first substrate while the second insulating layer is interposed through a second mask process, and the gate line crosses the data line to define a pixel region in the pixel portion of the first substrate. Forming a; Forming a third insulating film on the first substrate; Forming a contact hole exposing a portion of the drain electrode by removing a portion of the third insulating layer through a third mask process; Forming a pixel electrode electrically connected to the drain electrode through the contact hole using a fourth mask process; And And attaching the first substrate and the second substrate to each other. The method of claim 1, further comprising forming an ohmic contact layer on the active pattern by ohmic contacting the source / drain region and the source / drain electrode of the active pattern using the first mask process. A method of manufacturing a liquid crystal display device, characterized in that. The method of claim 1, wherein the forming of the light blocking pattern comprises forming a first light blocking pattern under the active pattern in substantially the same shape as the active pattern. The method of claim 3, wherein the forming of the light blocking pattern comprises forming a second light blocking pattern under the data line to have a width substantially wider than that of the data line. Way. 5. The liquid crystal display of claim 4, wherein the forming of the light blocking pattern comprises forming a third light blocking pattern under the gate line to have a width substantially wider than that of the gate line. Way. The method of claim 1, further comprising forming a common line in the pixel region using the second mask process with the second insulating layer interposed therebetween. The method of claim 1, wherein a portion of the common line overlaps a portion of the pixel electrode with the third insulating layer interposed therebetween to form a storage capacitor. The method of claim 1, further comprising forming a black matrix on the second substrate corresponding to the light blocking pattern to have a narrower width than the light blocking pattern. A light blocking pattern formed on the first substrate; An active pattern and an amorphous silicon thin film pattern formed on the light blocking pattern with a first insulating film interposed therebetween; A source electrode and a drain electrode formed on the active pattern and electrically connected to a source region and a drain region of the active pattern; a data line formed on the amorphous silicon thin film pattern with an n + amorphous silicon thin film pattern interposed therebetween; A gate electrode formed on the active pattern with a second insulating layer interposed therebetween; A gate line formed on the amorphous silicon thin film pattern with the second insulating layer interposed therebetween and defining a pixel area crossing the data line; A third insulating film formed on the first substrate; A pixel electrode formed in the pixel region and electrically connected to the drain electrode through a contact hole formed in the third insulating layer; And And a second substrate bonded to and opposed to the first substrate. 10. The liquid crystal display of claim 9, further comprising an ohmic contact layer formed on the active pattern and ohmic contacting the source / drain region of the active pattern and the source / drain electrode. The liquid crystal display of claim 9, wherein the light blocking pattern comprises a first light blocking pattern patterned under the active pattern to be substantially the same as the active pattern. The liquid crystal display of claim 11, wherein the light blocking pattern includes a second light blocking pattern patterned to have a width substantially lower than that of the data line under the data line. The liquid crystal display of claim 12, wherein the light blocking pattern includes a third light blocking pattern patterned to have a width substantially lower than that of the gate line under the gate line. The liquid crystal display of claim 9, further comprising a common line formed in the pixel region and overlapping a portion of the pixel electrode with the third insulating layer interposed therebetween to form a storage capacitor. 10. The liquid crystal display of claim 9, further comprising a black matrix formed on the second substrate corresponding to the light blocking pattern and patterned to have a narrower width than the light blocking pattern.

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