KR101408257B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

 The liquid crystal display device and its manufacturing method of the present invention maximize productivity by a three-mask process using a top gate structure and form a black matrix on a lower array substrate, Providing a first substrate for preventing light leakage due to misalignment while minimizing a margin of a black matrix to improve an aperture ratio; Forming an engraved pattern by etching a portion of the first substrate through a first mask process and then forming a black matrix within the engraved pattern of the first substrate so as not to have a step with respect to the surface of the first substrate; ; Forming a first insulating film on the first substrate on which the black matrix is formed; Forming a pixel electrode on a first substrate on which the first insulating film is formed through a second mask process and forming a source / drain electrode and a data line on a black matrix of the first substrate on which the first insulating film is formed; An active pattern is formed on the black matrix of the first substrate on which the pixel electrodes, the source / drain electrodes, and the data lines are formed through a third mask process, and the second insulating layer is formed on the black matrix of the first substrate on which the active pattern is formed. Forming a gate electrode in the interposed state; Forming a gate line located above the black matrix through the third mask process and intersecting the data line to define a pixel region; And bonding the first substrate and the second substrate together, wherein the black matrix is formed to be positioned below the thin film transistor region, the data line, and the gate line.

A top gate, a lift-off, a black matrix, a source electrode, a drain electrode,

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device capable of improving the aperture ratio by reducing the number of masks, simplifying the manufacturing process and improving the yield and minimizing the margin of the black matrix, And a manufacturing method thereof.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal display panel, 5 and the array substrate 10 are bonded together through a cemented key (not shown) formed on the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required ought.

2A to 2E are cross-sectional views sequentially showing the steps of manufacturing an array substrate in the liquid crystal display device shown in Fig.

2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 by using a photolithography process (first mask process).

Next, as shown in FIG. 2B, a first insulating film 15a, an amorphous silicon thin film and an n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed The amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form an active pattern 24 made of the amorphous silicon thin film on the gate electrode 21.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active pattern 24 is formed on the active pattern 24.

2C, a conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a third mask process) The electrode 22 and the drain electrode 23 are formed. At this time, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed by the third mask process, and the ohmic-and-amorphous silicon thin film pattern is formed between the active pattern 24 and the source / drain electrodes 22, Thereby forming an ohmic contact layer 25 '.

2d, a second insulating layer 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process A part of the second insulating film 15b is removed through the contact hole 40 to expose a part of the drain electrode 23.

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (fifth mask process) The pixel electrode 18 electrically connected to the drain electrode 23 is formed.

As described above, the fabrication of the array substrate including the thin film transistor requires five photolithography processes in total for patterning the gate electrode, the active pattern, the source / drain electrode, the contact hole, and the pixel electrode.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a photosensitive process application, exposure, and development process. As a result, a large number of photolithography processes reduce production yield, and the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

At this time, a technology has been developed in which an active pattern and a source / drain electrode are formed by a single mask process using a diffraction mask, so that an array substrate can be manufactured by a total of four mask processes.

However, the liquid crystal display of the above structure has a problem in that since the active pattern and the source / drain electrodes are patterned through two etching processes by using the diffraction mask, the data lines, that is, the source electrode and the drain electrode, The active pattern remains.

The active pattern is made of a pure amorphous silicon thin film. At this time, the active pattern under the data line is exposed to the lower backlight except the gate line, that is, the portion covered by the gate electrode and the gate line, A photocurrent is generated. At this time, due to the minute flickering of the backlight, the amorphous silicon thin film reacts finely and is repeatedly activated and deactivated, thereby causing a change in the photocurrent. Such a photocurrent component is coupled together with a signal flowing to neighboring pixel electrodes to distort the movement of the liquid crystal located on the pixel electrodes. As a result, wavy noise is generated on the screen of the liquid crystal display device in which a thin line of a wave pattern appears.

In addition, the active pattern located below the data line protrudes to both sides of the data line by a predetermined distance, so that the aperture ratio of the liquid crystal display device decreases as the aperture region of the pixel portion is eroded by the protruding distance.

Meanwhile, the array substrate fabricated as described above is bonded to the upper color filter substrate in a state where a certain cell gap is maintained by the column spacer, thereby forming a liquid crystal display device.

At this time, as described above, the color filter substrate is divided into a color filter composed of a plurality of sub-color filters for realizing red, green and blue colors on a transparent color filter substrate and a color filter for separating the sub- And a transparent common electrode for applying a voltage to the liquid crystal layer.

Here, the black matrix is patterned in the boundary region of the pixels to block leakage of light generated from the backlight in the lower portion of the liquid crystal display device and to prevent color mixing of adjacent pixels, and the color filter substrate and the array substrate A predetermined margin is provided in order to improve the light leakage phenomenon due to the misalignment that occurs when the light leakage occurs. Such a margin of the black matrix is a cause of lowering the aperture ratio of the liquid crystal display device, and it is required to be improved.

An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same which are capable of manufacturing an array substrate of a top gate structure by three mask processes.

It is another object of the present invention to provide a liquid crystal display device capable of enlarging an opening area to realize a high brightness and at the same time to improve a deficiency of a light leakage caused by misalignment of alignment and a manufacturing method thereof.

It is still another object of the present invention to provide a liquid crystal display device capable of realizing high image quality due to no occurrence of a noisy noise and a method of manufacturing the same.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a first substrate having an engraved pattern formed by etching a part of a region; A black matrix formed within the engraved pattern of the first substrate so as not to have a step with respect to the surface of the first substrate, the black matrix comprising a first conductive film; A first insulating layer formed on the first substrate on which the black matrix is formed; A source / drain electrode formed on the black matrix of the first substrate on which the first insulating film is formed and formed of the second conductive film and formed on the first substrate on which the first insulating film is formed, A data line; An active pattern formed on the black matrix of the first substrate on which the pixel electrodes, the source / drain electrodes and the data lines are formed; A gate electrode formed on the black matrix of the first substrate on which the active pattern is formed, a gate electrode formed of a fourth conductive film in a state in which the second insulating film is interposed, and a gate line crossing the data line to define a pixel region; And a second substrate bonded to the first substrate so as to be opposite to the first substrate, wherein the black matrix is located under the thin film transistor region, the data line, and the gate line.

In addition, a method of manufacturing a liquid crystal display of the present invention includes: providing a first substrate; Forming an engraved pattern by etching a portion of the first substrate through a first mask process and then forming a black matrix within the engraved pattern of the first substrate so as not to have a step with respect to the surface of the first substrate; ; Forming a first insulating film on the first substrate on which the black matrix is formed; Forming a pixel electrode on a first substrate on which the first insulating film is formed through a second mask process and forming a source / drain electrode and a data line on a black matrix of the first substrate on which the first insulating film is formed; An active pattern is formed on the black matrix of the first substrate on which the pixel electrodes, the source / drain electrodes, and the data lines are formed through a third mask process, and the second insulating layer is formed on the black matrix of the first substrate on which the active pattern is formed. Forming a gate electrode in the interposed state; Forming a gate line located above the black matrix through the third mask process and intersecting the data line to define a pixel region; And bonding the first substrate and the second substrate together, wherein the black matrix is formed to be positioned below the thin film transistor region, the data line, and the gate line.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention reduce the number of masks used in the manufacture of thin film transistors, thereby reducing the manufacturing process and cost. Particularly, in the liquid crystal display device and the manufacturing method thereof according to the present invention, the productivity is maximized by fabricating the array substrate by three mask processes.

Further, in the liquid crystal display device and the manufacturing method thereof according to the present invention, a black matrix is formed on the lower array substrate, thereby preventing a defective light source due to misalignment when the array substrate and the color filter substrate are attached. As a result, the yield is improved.

Further, the liquid crystal display device and the manufacturing method thereof according to the present invention provide an effect of increasing the aperture ratio as the margin of the black matrix is minimized.

In addition, the liquid crystal display device and the method of manufacturing the same according to the present invention can provide a high-quality liquid crystal display device without wave noise and light leakage.

Hereinafter, preferred embodiments of a liquid crystal display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a plan view schematically showing a part of an array substrate of a liquid crystal display according to an embodiment of the present invention. In FIG. 3, one pixel including a gate pad portion, a data pad portion, Respectively.

In an actual liquid crystal display device, N number of gate lines and M number of data lines intersect to form MxN pixels, but one pixel is shown in the figure for simplicity.

As shown in the drawing, a gate line 116 and a data line 117 are formed on an array substrate 110 on the array substrate 110 in the vertical and horizontal directions to define pixel regions have. A thin film transistor, which is a switching element, is formed in the intersection region of the gate line 116 and the data line 117. A common electrode of the color filter substrate (not shown) is connected to the thin film transistor And a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118 . The thin film transistor includes an active pattern (not shown) which forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121 .

The thin film transistor according to an embodiment of the present invention is characterized in that the gate electrode 121 has a top gate structure in which the source electrode 122, the drain electrode 123, and the active pattern 124 are located. do.

In addition, the array substrate 110 according to the embodiment of the present invention includes gate lines, that is, the gate electrodes 121 and the gate lines 116 and the data lines, that is, the source electrodes 122 and the drain electrodes 123, And a black matrix 106 made of an opaque conductive material such as chromium is formed under the line 117. The black matrix 106 is formed of a transparent conductive material such that light is transmitted through the thin film transistor, And the like.

At this time, a portion of the gate line 116 located at the front end overlaps with a portion of the pixel electrode 118 above the first insulating film (not shown) to form a storage capacitor. The storage capacitor serves to keep the voltage applied to the liquid crystal capacitor constant until a next signal is received. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. Generally, the voltage applied to the liquid crystal capacitor can not be maintained until the next signal is received, And disappear. Therefore, to maintain the applied voltage, a storage capacitor must be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

A gate pad line 116p and a data pad line 117p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110, The scan signal and the data signal received from the driver circuit portion (not shown) of the scan driver 116 and the data line 117, respectively.

Here, the liquid crystal display device according to the embodiment of the present invention may be applied to a data line and a pixel electrode by using a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask) And the active pattern and the gate wiring are formed by a single mask process, whereby the array substrate can be manufactured by a total of three mask processes.

In this case, in order to form the active pattern and the gate wiring by a single mask process, the liquid crystal display according to an embodiment of the present invention includes a black matrix on the lowermost layer, a source / drain electrode and an active pattern, An insulating film, that is, a top gate type in which a gate insulating film is formed and a gate electrode is formed in the uppermost layer is applied.

In addition, the black matrix according to an embodiment of the present invention has a step by etching a part of an array substrate made of an insulating material such as glass and then forming it in the etched array substrate using a lift off process This will be described in detail through the following manufacturing method of the liquid crystal display device.

4A to 4C are cross-sectional views sequentially showing a manufacturing process according to lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc of the array substrate shown in FIG. 3. In the left side, And the array substrate of the data pad portion and the gate pad portion is sequentially formed on the right side.

5A to 5C are plan views sequentially showing manufacturing steps of the array substrate shown in Fig.

As shown in FIGS. 4A and 5A, in an etched portion of an array substrate 110 made of a transparent insulating material such as glass, a black matrix 106 according to an embodiment of the present invention made of an opaque metal material such as chromium ).

At this time, the black matrix 106 is formed in the etched array substrate 110 by etching a part of the area of the array substrate 110 made of insulating material such as glass and then performing a lift-off process, , Which will be described in detail with reference to the drawings.

6A to 6D are cross-sectional views illustrating the first mask process according to the embodiment of the present invention in the array substrate shown in Figs. 4A and 5A.

As shown in FIG. 6A, a predetermined first mask pattern 170 is formed on an array substrate 110 made of an insulating material such as glass.

The first mask pattern 170 may be formed of a predetermined photoresist. In order to form a black matrix on the lower array substrate 110, the first mask pattern 170 may include a thin film transistor region in which the black matrix is to be formed, And the light irradiated to the region is patterned so as to be transmitted therethrough. This is because a positive type photoresist is used, and the present invention is not limited thereto, and a negative type photoresist may be used.

6B, a portion of the array substrate 110 is etched using hydrofluoric acid (HF) using the first mask pattern 170 as a mask to form a predetermined Thereby forming the engraved pattern H.

At this time, the engraved pattern H is formed in a region where the black matrix is to be formed, the gate line and the data line to be formed according to the embodiment of the present invention, and is formed by isotropic etching by hydrofluoric acid (HF) 1, the array substrate 110 is over-etched to the bottom of the mask pattern 170.

Next, as shown in FIG. 6C, the first conductive layer 190 is deposited on the entire surface of the array substrate 110 including the engraved pattern H in a state where the first mask pattern 170 remains, do.

At this time, the first conductive layer 190 may be formed of an opaque metal material such as chromium to form a black matrix according to an embodiment of the present invention.

Thereafter, as shown in FIG. 6D, the first mask pattern is removed through a lift-off process to form a black matrix 106 according to an embodiment of the present invention in the engraved pattern, The first conductive layer formed on the first mask pattern is removed together with the first mask pattern.

The lift-off process may include depositing a conductive metal material such as the first conductive film to a predetermined thickness on a photosensitive material such as the first mask pattern, depositing the conductive metal material in a solution such as a stripper, And removing the photosensitive material together with the metal material. At this time, the metal material formed in the engraved pattern is not removed and the black matrix 106 is formed.

As described above, in the embodiment of the present invention, the black matrix 106 is formed in a predetermined engraved pattern by etching a part of the area of the array substrate 110 and then using a lift-off process, The surface of the substrate 110 does not have a step.

In addition, since the black matrix 106 is formed on the lower array substrate 110, it is not necessary to consider the margin of the black matrix 106, so that the aperture area of the pixel is increased. As a result, do.

In addition, even when misalignment occurs when the color filter substrate and the array substrate 110 are misaligned, the thin film transistor region of the array substrate 110 and the gate wiring and the data wiring are opaque. The black matrix 106 is formed to prevent leakage of light generated from the lower backlight.

Next, as shown in FIGS. 4B and 5B, the first insulating layer 115a, the second conductive layer, the third conductive layer, and the n + amorphous silicon thin film 115 are formed on the entire surface of the array substrate 110 on which the black matrix 106 is formed. / RTI >

Thereafter, the second conductive film, the third conductive film, and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form the second conductive film in the pixel region of the array substrate 110 The source electrode 122 and the drain electrode 123 and the data line 117 are formed in the pixel portion of the array substrate 110 while the pixel electrode 118 is formed.

In addition, a data pad line 117p made of the third conductive film is formed on the data pad portion of the array substrate 110 using the second mask process.

A data line 117 including the source electrode 122 and a data pad 117b including the source electrode 122 are formed under the data line 117 and the data pad line 117p including the source electrode 122, The first conductive film pattern 130 'and the second conductive film pattern 130 "patterned in the same manner as the line 117 p are formed.

The data line 117 including the source electrode 122, the drain electrode 123 and the data pad line 117p are connected to a data line (not shown) formed of the n + amorphous silicon thin film and including the source electrode 122, The first ohmic-contact pattern 125na and the second ohmic-contact pattern 125nb patterned in the same pattern as the drain electrode 117, the drain electrode 123, and the data pad line 117p are formed.

Here, the source / drain electrodes 122 and 123, the data lines 117 and the pixel electrodes 118 according to the embodiment of the present invention are formed by performing a single mask process (second mask process) by using a half- The second mask process will be described in detail with reference to the drawings.

FIGS. 7A to 7G are cross-sectional views illustrating the second mask process according to the embodiment of the present invention in the array substrate shown in FIGS. 4B and 5B.

7A, the first insulating layer 115a, the second conductive layer 130, the third conductive layer 140, and the n + amorphous silicon thin film 115 are formed on the entire surface of the array substrate 110 on which the black matrix 106 is formed. (125).

The second conductive layer 130 may be a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) ≪ / RTI >

The third conductive layer 140 may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu) Resistant opaque conductive material such as chromium, molybdenum (Mo), and molybdenum alloy (Mo ally).

7B, a second photoresist layer 270 made of a photosensitive material such as a photoresist is formed on the entire surface of the array substrate 110, and then a half-tone mask 180 according to an embodiment of the present invention The second photoresist layer 270 is selectively irradiated with light.

At this time, the half-tone mask 180 is provided with a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 180 is irradiated onto the second photoresist layer 270.

7C, after the second photoresist layer 270 exposed through the half-tone mask 180 is developed, the second photoresist layer 270 is exposed through the blocking region III and the second transmissive region II, The first photoresist pattern 270a to the fourth photoresist pattern 270d having a predetermined thickness remain in a region where the light is blocked or only partially blocked. In the first transmissive region I where all the light is transmitted, The surface of the n + amorphous silicon thin film 125 is exposed.

At this time, the first to third photosensitive film patterns 270a to 270c formed in the blocking region III are formed thicker than the fourth photosensitive film pattern 270d formed through the second transmitting region II. In addition, the second photoresist layer is completely removed in a region where light is entirely transmitted through the first transmissive region I because the photoresist of the positive type is used. The present invention is not limited to this, A photoresist may be used.

7D, using the first to fourth photosensitive film patterns 270a to 270d formed as described above as a mask, the second conductive film, the third conductive film, and the n < + > A data line 117 including a source electrode 122 made of the third conductive film, and a drain electrode pattern (not shown) including a drain electrode are formed in the pixel portion of the array substrate 110 by selectively removing the amorphous silicon thin film, 140 'are formed.

A data pad line 117p of the third conductive layer is formed on the data pad of the array substrate 110. A pixel electrode of the pixel electrode of the array substrate 110, (118) is formed.

At this time, the second conductive layer is formed under the data line 117 including the source electrode 122, the drain electrode pattern 140 'and the data pad line 117p, and the source electrode 122, The first conductive film pattern 130 'patterned in the same pattern as the data line 117 and the drain electrode pattern 140' and the data pad line 117p and the pixel electrode 118 and the second conductive film pattern 130 ") Is formed.

The n + amorphous silicon thin film is formed on the data line 117 including the source electrode 122, the drain electrode pattern 140 ', and the data pad line 117p and includes the source electrode 122, A first n + amorphous silicon thin film pattern 125 'and a second n + amorphous silicon thin film pattern 125' patterned in the same pattern as the data line 117, the drain electrode pattern 140 'and the data pad line 117p, an n + amorphous silicon thin film pattern 125 "is formed.

Thereafter, as shown in FIG. 7E, an ahing process for removing a portion of the first to fourth photoresist patterns is performed to completely remove the fourth photoresist pattern of the second transmissive area II .

At this time, the first to third photosensitive film patterns correspond to the blocking region III by the fifth to seventh photosensitive film patterns 170a 'to 170c' that are removed by the thickness of the fourth photosensitive film pattern And only the upper portion of the data line 117 including the source electrode 122, the drain electrode region, and the upper portion of the data pad line 117p.

Thereafter, as shown in FIGS. 7F and 7G, using the remaining fifth photoresist pattern 170a 'to the seventh photoresist pattern 170c' as a mask, the first n + amorphous silicon thin film pattern and the drain electrode pattern A drain electrode 123 made of the third conductive film is formed in the pixel portion of the array substrate 110 and a pixel electrode 118 in the pixel region is exposed.

At this time, a second ohmic contact pattern 125nb formed of the n + amorphous silicon thin film and patterned substantially in the same pattern as the drain electrode 123 is formed on the drain electrode 123.

4C and 5C, an active pattern (not shown) is formed in the pixel portion of the array substrate 110 on which the source / drain electrodes 122 and 123, the data lines 117 and the pixel electrodes 118 are formed And a gate electrode 121 and a gate line 116 are formed in a state where a second insulating layer 115b is interposed therebetween and a gate pad line 116p ).

At this time, the active pattern 124 and the gate electrode 121, the gate line 116 and the gate pad line 116p are electrically connected to the source / drain electrodes 122 and 123, the data line 117 and the pixel electrode 118 The amorphous silicon thin film, the second insulating film 115b, and the fourth conductive film are deposited on the entire surface of the array substrate 110 on which the first insulating layer 115 and the second insulating layer 115b are formed, and then patterned selectively through a photolithography process (third mask process).

At this time, the second n + amorphous silicon thin film pattern on the data pad line 116p is removed through the third mask process, and the first and second ohmic contact patterns are partially removed to remove the active pattern 124 Contact layer 125n for ohmic-contact between the source / drain region of the source / drain electrodes 122 and 123 and the source / drain region of the source / drain electrodes 122 and 123.

Here, as the fourth conductive film, a low resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy may be used. The fourth conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

In the thin film transistor according to the embodiment of the present invention, the top gate structure in which the gate electrode 121 is positioned above the array substrate 110 on which the source / drain electrodes 122 and 123 and the active pattern 124 are formed, Hereinafter, the third mask process will be described in detail with reference to the drawings.

8A to 8C are cross-sectional views showing the third mask process according to the embodiment of the present invention in the array substrate shown in Figs. 4C and 5C.

8A, the amorphous silicon thin film 120 and the second insulating film 120 are formed on the entire surface of the array substrate 110 on which the source / drain electrodes 122 and 123, the data line 117, and the pixel electrode 118 are formed. The first conductive film 115b and the fourth conductive film 150 are formed.

The fourth conductive layer 150 may be formed of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, and molybdenum alloy to form a gate electrode, a gate line, and a gate pad line . The fourth conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

Then, a predetermined second mask pattern 370 is formed on the array substrate 110, as shown in FIG. 8B.

At this time, the second mask pattern 370 may be formed of a predetermined photoresist. In order to form an active pattern and a gate wiring on the lower array substrate 110, the second mask pattern 370 is irradiated with a gate electrode region, a gate line region, And patterned so as to block the incident light. This is because a positive type photoresist is used, and the present invention is not limited thereto, and a negative type photoresist may be used.

Thereafter, as shown in FIG. 8C, the amorphous silicon thin film, the second insulating film 115b, the fourth conductive film, and a part of the n + amorphous silicon thin film are selectively removed using the second mask pattern 370 as a mask An active pattern 124 made of the amorphous silicon thin film is formed on a pixel portion of the array substrate 110 and a gate electrode made of the fourth conductive film is formed in a state where the second insulating film 115b is interposed therebetween 121 are formed.

A gate line 116 which overlaps with a part of the pixel electrode 118 and constitutes a storage capacitor with the second insulating film 115b interposed therebetween is formed in a pixel portion of the array substrate 110, A gate pad line 116p made of the fourth conductive film is formed on the gate pad portion of the substrate 110. [

At this time, the amorphous silicon thin film is formed under the gate line 116 and the gate pad line 116p with the second insulating layer 115b interposed therebetween, and the gate line 116 and the gate pad line The first amorphous silicon thin film pattern 120 'and the second amorphous silicon thin film pattern 120' patterned in the same pattern as the first amorphous silicon thin film pattern 116 'and the second amorphous silicon thin film pattern 120'

Also, the second n + amorphous silicon thin film pattern on the data pad line 116p is removed through the third mask process, and the first and second ohmic contact patterns are partially removed to form the active pattern 124 And an ohmic contact layer 125n for ohmic contact between the source / drain region of the source / drain electrodes 122 and 123 and the source /

The array substrate of the present invention having the above-described structure according to the present invention is adhered to the color filter substrate by a sealant formed on the outer periphery of the image display area. In this case, the color filter substrate is provided with color A filter is formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

In addition, although the amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern is described as an example of the present invention, the present invention is not limited thereto, and the present invention can be applied to a polycrystalline silicon thin film It is also applied to a silicon thin film transistor.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are sectional views sequentially showing a manufacturing process of an array substrate in the liquid crystal display device shown in Fig.

3 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to an embodiment of the present invention.

4A to 4C are cross-sectional views sequentially showing a manufacturing process according to lines IIIa-IIIa ', IIIb-IIIb and IIIc-IIIc of the array substrate shown in FIG. 3;

5A to 5C are plan views sequentially showing the manufacturing steps of the array substrate shown in Fig.

6A to 6D are cross-sectional views illustrating the first mask process according to the embodiment of the present invention, in the array substrate shown in Figs. 4A and 5A.

FIGS. 7A to 7G are cross-sectional views specifically showing a second mask process according to an embodiment of the present invention, in the array substrate shown in FIGS. 4B and 5B. FIG.

FIGS. 8A to 8C are cross-sectional views specifically showing a third mask process according to the embodiment of the present invention, in the array substrate shown in FIGS. 4C and 5C. FIG.

DESCRIPTION OF REFERENCE NUMERALS

106: black matrix 110: array substrate

116: gate line 117: data line

118: pixel electrode 121: gate electrode

122: source electrode 123: drain electrode

124: Active pattern

Claims (15)

Providing a first substrate; Forming an engraved pattern by etching a portion of the first substrate through a first mask process and then forming a black matrix within the engraved pattern of the first substrate so as not to have a step with respect to the surface of the first substrate; ; Forming a first insulating film on the first substrate on which the black matrix is formed; Forming a pixel electrode on a first substrate on which the first insulating film is formed through a second mask process and forming a source / drain electrode and a data line on a black matrix of the first substrate on which the first insulating film is formed; An active pattern is formed on the black matrix of the first substrate on which the pixel electrodes, the source / drain electrodes, and the data lines are formed through a third mask process, and the second insulating layer is formed on the black matrix of the first substrate on which the active pattern is formed. Forming a gate electrode in the interposed state; Forming a gate line located above the black matrix through the third mask process and intersecting the data line to define a pixel region; And And bonding the first substrate and the second substrate, Wherein the black matrix is formed so as to be located below the thin film transistor region, the data line, and the gate line. The method of claim 1, wherein the first mask process Forming a first mask pattern on the first substrate; Etching a portion of the first substrate using the first mask pattern as a mask to form a depressed pattern in the gate wiring, the data wiring, and the thin film transistor region; Forming a first conductive layer on the entire surface of the first substrate on which the engraved pattern is formed; And And selectively removing the first mask pattern and the first conductive layer to form a black matrix made of the first conductive layer only in the depressed pattern. The method of claim 2, wherein the first substrate is etched using fluorine. 3. The method of claim 2, wherein the first mask pattern and the first conductive layer are selectively removed using a lift-off process. The method of claim 1, wherein the second mask process Forming a second conductive film, a third conductive film, and an n + amorphous silicon thin film on a first substrate on which the first insulating film is formed; A mask having a first transmissive region through which all of the irradiated light is transmitted and a second transmissive region through which only a part of light is blocked and a part of which is blocked and a blocking region which blocks all the irradiated light are applied to form a first substrate on which the n + amorphous silicon thin film is formed, Forming a first photoresist pattern to a fourth photoresist pattern; The second conductive film, the third conductive film, and the n + amorphous silicon thin film are selectively removed using the first photoresist pattern to the fourth photoresist pattern as masks to form the third conductive film on the black matrix of the first substrate. Forming a source electrode, a data line and a drain electrode pattern, and forming a pixel electrode made of the second conductive film under the drain electrode pattern; Removing the fourth photoresist pattern through an ashing process and removing a portion of the first photoresist pattern to a third photoresist pattern to form a fifth photoresist pattern to a seventh photoresist pattern; And The drain electrode pattern and the n + amorphous silicon thin film are selectively removed using the fifth photoresist pattern to the seventh photoresist pattern as masks to form a drain electrode made of the third conductive film on the black matrix of the first substrate, And exposing the pixel electrode in the pixel region. The method of claim 5, further comprising: forming a first ohmic-contact pattern and a second ohmic-contact pattern made of the n + amorphous silicon thin film on the data line and the drain electrode including the source electrode through the second mask process The method further comprising the step of: 7. The method of claim 6, wherein the third masking step Forming an amorphous silicon thin film, a second insulating film, and a fourth conductive film on the first substrate on which the pixel electrode, the source / drain electrode, and the data line are formed; And The amorphous silicon thin film, the second insulating film, and the fourth conductive film are selectively removed to form an active pattern on the black matrix, and on the black matrix of the first substrate on which the active pattern is formed, And forming a gate electrode on the gate insulating film. 8. The method of claim 7, further comprising selectively removing the first and second ohmic-contact patterns through the third mask process to form ohmic-contact regions between the source / drain regions of the active pattern and the source / Wherein the step of forming the liquid crystal layer further comprises the step of forming a layer. A first substrate having an engraved pattern formed by etching a part of the region; A black matrix formed within the engraved pattern of the first substrate so as not to have a step with respect to the surface of the first substrate, the black matrix comprising a first conductive film; A first insulating layer formed on the first substrate on which the black matrix is formed; A source / drain electrode formed on the black matrix of the first substrate on which the first insulating film is formed and formed of the second conductive film and formed on the first substrate on which the first insulating film is formed, A data line; An active pattern formed on the black matrix of the first substrate on which the pixel electrodes, the source / drain electrodes and the data lines are formed; A gate electrode formed on the black matrix of the first substrate on which the active pattern is formed, a gate electrode formed of a fourth conductive film in a state in which the second insulating film is interposed, and a gate line crossing the data line to define a pixel region; And And a second substrate which is adhered to and opposite to the first substrate, Wherein the black matrix is located under the thin film transistor region, the data line, and the gate line. delete The liquid crystal display device according to claim 9, further comprising a conductive film pattern formed below the data line including the source electrode, the conductive film pattern comprising the second conductive film. The semiconductor device according to claim 9, further comprising an ohmic contact layer formed between the active pattern and the source / drain electrode and ohmic-contacting the source / drain region and the source / drain electrode of the active pattern. Liquid crystal display device. The liquid crystal display of claim 9, wherein the first conductive layer is made of chromium. The liquid crystal display of claim 9, wherein the second conductive layer is made of a transparent conductive material of indium-tin-oxide and indium-zinc-oxide. The liquid crystal display device of claim 9, wherein the third conductive film and the fourth conductive film are made of a low-resistance opaque conductive material of aluminum, an aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy.

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