KR101483024B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The liquid crystal display device and the method of manufacturing the same of the present invention can form an opaque light shielding pattern in the lower part of the data line and / or the gate line to serve as a black matrix of the upper color filter substrate, The method comprising: providing a first substrate to prevent leakage of light due to misalignment during bonding, and to improve the aperture ratio by minimizing a margin of an upper black matrix; Forming a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern with an opaque conductive material on the first substrate through a first mask process; Forming an active pattern and a source / drain electrode on the first light-shielding pattern including the first insulating layer using the first mask process; Forming a data line on the second light-shielding pattern including the first insulating layer, the amorphous silicon thin-film pattern, and the n + amorphous silicon thin-film pattern using the first mask process; Forming a gate electrode on the active pattern of the first substrate in which the second insulating film is interposed through a second mask process; The second insulating film, the amorphous silicon thin film pattern, and the n < + > amorphous silicon thin film pattern are interposed between the data line and the third light- Forming a gate line defining a gate line; Forming a third insulating film on the first substrate on which the gate electrode and the gate line are formed; Removing a part of the third insulating film through a third mask process to form a contact hole exposing a part of the drain electrode; Forming a pixel electrode electrically connected to the drain electrode through the contact hole using a fourth mask process; And bonding the first substrate and the second substrate together.

In the liquid crystal display device and the method of manufacturing the same, the active matrix pattern and the light-shielding pattern are simultaneously formed by using the half-tone mask, the top gate type array substrate Is produced.

Data line, gate line, shielding pattern, 4 mask, active pattern

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

More specifically, the present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a method of manufacturing a liquid crystal display device and a method of manufacturing the same, which can improve the aperture ratio by reducing the number of masks, simplifying the manufacturing process and improving the yield and minimizing the margin of the black matrix of the upper color filter substrate And a method of manufacturing the liquid crystal display device.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required ought.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal display panel, 5 and the array substrate 10 are bonded together through a cemented key (not shown) formed on the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required ought.

2A to 2E are cross-sectional views sequentially showing the steps of manufacturing an array substrate in the liquid crystal display device shown in Fig.

2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 by using a photolithography process (first mask process).

Next, as shown in FIG. 2B, a first insulating film 15a, an amorphous silicon thin film and an n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed The amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form an active pattern 24 made of the amorphous silicon thin film on the gate electrode 21.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active pattern 24 is formed on the active pattern 24.

2C, a conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a third mask process) The electrode 22 and the drain electrode 23 are formed. At this time, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed by the third mask process, and the ohmic-and-amorphous silicon thin film pattern is formed between the active pattern 24 and the source / drain electrodes 22, Thereby forming an ohmic contact layer 25 '.

2d, a second insulating layer 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process A part of the second insulating film 15b is removed through the contact hole 40 to expose a part of the drain electrode 23.

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (fifth mask process) The pixel electrode 18 electrically connected to the drain electrode 23 is formed.

As described above, the fabrication of the array substrate including the thin film transistor requires five photolithography processes in total for patterning the gate electrode, the active pattern, the source / drain electrode, the contact hole, and the pixel electrode.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as a photoresist application, an exposure, and a development process. There is a drawback that it drops.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

The array substrate fabricated in this manner is adhered to the color filter substrate 5 in a state where a certain cell gap is maintained by a column spacer (not shown) formed on the color filter substrate 5 as shown in FIG. 3 Thereby constituting a liquid crystal display device.

At this time, as described above, the color filter substrate 5 is provided with a color filter composed of a plurality of sub-color filters 7 implementing red, green and blue hues on the transparent color filter substrate 5, And a transparent common electrode 8 for applying a voltage to the liquid crystal layer 90. The black matrix 6 separates the light emitted from the liquid crystal layer 90 and filters out the light passing through the liquid crystal layer 90.

The black matrix 6 is patterned in the boundary region of the pixels to prevent leakage of light generated from the backlight in the lower portion of the liquid crystal display device and to prevent color mixture of adjacent pixels. And has a predetermined margin d in order to improve the light leakage phenomenon due to misalignment occurring when the array substrate 10 is attached.

In particular, light leakage phenomenon may occur around the data line 17 due to misalignment when the color filter substrate 5 and the array substrate 10 are attached together. In order to prevent this, the margin d of the black matrix Is formed to have a width wider than the width of the line (17). Such a margin (d) of the black matrix is a factor that lowers the aperture ratio of the liquid crystal display device and is required to be improved.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of enlarging an aperture area to realize a high brightness and at the same time to improve a light leakage caused by misalignment and a manufacturing method thereof.

It is another object of the present invention to provide a method of manufacturing a liquid crystal display device in which the high aperture ratio liquid crystal display device is manufactured by four mask processes.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above object, a liquid crystal display device of the present invention includes a first light-shielding pattern formed of a conductive material opaque to a thin-film transistor region, a data line region, and a gate line region of a first substrate, pattern; An active pattern formed on the first light-shielding pattern on which the first insulating film is disposed; A source electrode and a drain electrode formed on the active pattern and electrically connected to the source region and the drain region of the active pattern; A data line formed on the second light-shielding pattern including the first insulating film, the amorphous silicon thin film pattern, and the n + amorphous silicon thin film pattern; A gate electrode formed on the active pattern with a second insulating film interposed therebetween; A gate line formed on the third light-shielding pattern interposed between the first insulating layer, the second insulating layer, the amorphous silicon thin-film pattern, and the n + amorphous silicon thin-film pattern and intersecting the data line to define a pixel region; A third insulating film formed on the first substrate on which the gate electrode and the gate line are formed; A pixel electrode formed in the pixel region and electrically connected to the drain electrode through a contact hole formed in the third insulating film; And a second substrate which is adhered to and opposed to the first substrate.

In addition, a method of manufacturing a liquid crystal display of the present invention includes: providing a first substrate; Forming a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern with an opaque conductive material on the first substrate through a first mask process; Forming an active pattern and a source / drain electrode on the first light-shielding pattern including the first insulating layer using the first mask process; Forming a data line on the second light-shielding pattern including the first insulating layer, the amorphous silicon thin-film pattern, and the n + amorphous silicon thin-film pattern using the first mask process; Forming a gate electrode on the active pattern of the first substrate in which the second insulating film is interposed through a second mask process; The second insulating film, the amorphous silicon thin film pattern, and the n < + > amorphous silicon thin film pattern are interposed between the data line and the third light- Forming a gate line defining a gate line; Forming a third insulating film on the first substrate on which the gate electrode and the gate line are formed; Removing a part of the third insulating film through a third mask process to form a contact hole exposing a part of the drain electrode; Forming a pixel electrode electrically connected to the drain electrode through the contact hole using a fourth mask process; And bonding the first substrate and the second substrate together.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention reduce the number of masks used in the manufacture of thin film transistors, thereby reducing the manufacturing process and cost.

Further, the liquid crystal display device and the manufacturing method thereof according to the present invention provide an effect of increasing the aperture ratio as the margin of the black matrix is minimized.

Hereinafter, preferred embodiments of a liquid crystal display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view schematically showing a part of an array substrate of a liquid crystal display according to the first embodiment of the present invention. In FIG. 4, for convenience of explanation, one gate pad portion, a data pad portion, Pixel.

That is, in an actual liquid crystal display device, N number of gate lines and M number of data lines intersect to form MxN pixels, but one pixel is shown in the drawing for simplicity of explanation.

As shown in the drawing, a gate line 116 and a data line 117 are vertically and horizontally arranged on the array substrate 110 on the array substrate 110 of the first embodiment to define pixel regions. A thin film transistor, which is a switching element, is formed in the intersection region of the gate line 116 and the data line 117. A common electrode of the color filter substrate (not shown) is connected to the thin film transistor And a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor is electrically connected to the pixel electrode 118 through a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a first contact hole 140a. And a drain electrode 123 connected thereto. The thin film transistor includes an active pattern 124 which forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

The thin film transistor according to the first embodiment of the present invention is characterized in that the gate electrode 121 is a top gate type in which the source electrode 122 and the drain electrode 123 are located above the active pattern 124 .

The array substrate 110 according to the first embodiment of the present invention includes a light shielding pattern made of an opaque conductive material such as chromium at a lower portion of the active pattern 124, the data line 117 and the data pad line 117p 130 ', 130', 130 '') are formed on the substrate 110. The light shielding patterns 130 ', 130 ", and 130' 'are formed in the thin film transistor region, the data line 117, 117p of the light shielding layer. For reference, reference numerals 124 'and 124' denote a first amorphous silicon thin film pattern and a second amorphous silicon thin film pattern made of an amorphous silicon thin film.

In this case, common lines 1081 are arranged in the pixel region in a direction substantially parallel to the gate lines 116, and a part of the common lines 1081 are arranged in a direction in which a third insulating film (not shown) And a storage capacitor Cst is formed by overlapping a part of the pixel electrode 118 on the upper portion. The storage capacitor Cst serves to keep the voltage applied to the liquid crystal capacitor constant until the next signal is received. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. Generally, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is received, Disappear. Therefore, in order to maintain the applied voltage, the storage capacitor Cst must be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

A gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110, The scan signal and the data signal received from the driver circuit portion (not shown) of the scan driver 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend to the driving circuit portion and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively. The line 117p connects the scanning signal and the data signal from the driving circuit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, .

For reference, reference numerals 140b and 140c denote a second contact hole and a third contact hole, respectively. Here, the data pad electrode 127p is electrically connected to the data pad line 117p through the second contact hole 140b And the gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c

Here, the liquid crystal display device according to the first embodiment of the present invention uses an active pattern and a source / drain mask using a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask) The drain electrode and the data line are formed by a single mask process, and the light-shielding pattern of the present invention is formed under the active pattern and the data line by using the mask process, thereby making it possible to fabricate the array substrate by a total of four mask processes .

In this case, in order to form the light-shielding pattern, the active pattern, and the source / drain electrodes by a single mask process, the liquid crystal display according to the first embodiment of the present invention includes a light- / Drain electrode and a first insulating film are formed on the first insulating film and a gate electrode is formed on the first insulating film. This will be described in detail with reference to the following method of manufacturing a liquid crystal display device.

5A to 5D are cross-sectional views sequentially showing a manufacturing process according to line IVa-IVa ', line IVb-IVb and line IVc-IVc of the array substrate shown in FIG. 4. In the left side, And the array substrate of the data pad portion and the gate pad portion is sequentially formed on the right side.

6A to 6D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.

As shown in FIGS. 5A and 6A, a first conductive film, a first insulating film 115, an amorphous silicon thin film, an n + amorphous silicon thin film, and a second conductive film are formed on an array substrate 110 made of a transparent insulating material such as glass Lt; / RTI >

Thereafter, the first conductive film, the first insulating film 115, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (first mask process) An active pattern 124 made of the amorphous silicon thin film is formed on the pixel portion and a source electrode 122 and a drain electrode 123 made of the second conductive film are formed on the active pattern 124.

At this time, a data line 117 made of the second conductive film is formed in the data line region of the array substrate 110 through the first mask process, and a data line 117 made of the second conductive film is formed in the data pad portion of the array substrate 110, Thereby forming a data pad line 117p made of a conductive film.

At this time, on the active pattern 124, an ohmic contact layer (not shown) is formed of the n + amorphous silicon thin film and ohmic-contacted between the source / drain region of the active pattern 124 and the source / drain electrodes 122, (125n) is formed.

The first light-shielding pattern 130 (hereinafter, referred to as " first light-shielding pattern ") 130 formed of the first conductive layer and patterned substantially in the same pattern as the active pattern 124 is formed under the active pattern 124 with the first insulating layer 115 interposed therebetween. ') Is formed.

The fourth n + amorphous silicon layer, which is formed of the n + amorphous silicon thin film and is patterned substantially in the same pattern as the data line 117 and the data pad line 117p, is formed under the data line 117 and the data pad line 117p. A silicon thin film pattern 125 "and a fifth n + amorphous silicon thin film pattern 125" "are formed. The first conductive layer, the first insulating layer 115, and the amorphous silicon thin film are formed under the fourth n + amorphous silicon thin film pattern 125 "'and the fifth n + amorphous silicon thin film pattern 125' '' Shielding pattern 130 "which is patterned so as to have a width substantially equal to or wider than the fourth n + amorphous silicon thin film pattern 125" 'and the fifth n + amorphous silicon thin film pattern 125' ", The first amorphous silicon thin film pattern 124 ', the third light shielding pattern 130' ', and the second amorphous silicon thin film pattern 124' are formed.

Here, the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, and the first to third light-shielding patterns 130 'to 130' '' according to the first embodiment of the present invention The first mask process will be described in detail with reference to the accompanying drawings. However, the present invention is not limited thereto. And the active pattern 124 and the source / drain electrodes 122 and 123 and the data line 117 may be formed by two mask processes.

7A to 7G are cross-sectional views showing the first mask process according to the first embodiment of the present invention in the array substrate shown in Figs. 5A and 6A.

7A, the first conductive layer 130, the first insulating layer 115, the amorphous silicon thin film 120, the n + amorphous silicon thin film 125, and the second insulating layer 125 are sequentially formed on the array substrate 110, A conductive film 150 is formed.

Here, the first conductive layer 130 may be made of an opaque conductive material such as chromium (Cr) to form first to third light-shielding patterns, and the second conductive layer 150 may be formed of a conductive material, Aluminum alloy, tungsten (W), copper (Cu), chromium, molybdenum (Mo), and molybdenum alloy (Al) Mo ally, and the like.

7B, a photosensitive film 170 made of a photosensitive material such as a photoresist is formed on the entire surface of the array substrate 110, and then a half-tone mask (not shown) according to the first embodiment of the present invention And selectively irradiates the photoresist layer 170 with light.

At this time, the half-tone mask 180 is provided with a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the first half-tone mask 180 is irradiated onto the photoresist layer 170.

Then, after the photoresist layer 170 exposed through the half-tone mask 180 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 7C. A first photoresist pattern 170a to a fifth photoresist pattern 170e having a predetermined thickness are left in an area where all the light is blocked or partially blocked and the photoresist film is completely removed in the first light transmission area I The surface of the second conductive layer 150 is exposed.

The first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III are thicker than the fifth photoresist pattern 170e formed through the second transmissive region II. In addition, the photoresist layer is completely removed from the region through which the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, May be used.

Next, as shown in FIG. 7D, using the first photoresist pattern 170a to the fifth photoresist pattern 170e formed as described above as a mask, a first conductive film, a first insulating film 115 ), The amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed, the active pattern 124 of the amorphous silicon thin film is formed on the pixel portion of the array substrate 110.

The first light-shielding pattern 130 'and the second light-shielding pattern 130', which are the first conductive layer, are formed in the lower part of the active pattern 124, the data line area, and the data pad line area with the first insulating layer 115 interposed therebetween. The light shielding pattern 130 "and the third light shielding pattern 130" " are formed.

At this time, a first n + amorphous silicon thin film pattern 125 'formed of the n + amorphous silicon thin film and the second conductive film and patterned substantially in the same pattern as the active pattern 124 is formed on the active pattern 124, The second conductive film pattern 150 'is formed.

The amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are formed on the second light-shielding pattern 130 "and the third light-shielding pattern 130" The first n + amorphous silicon thin film pattern 125 '' and the data line pattern 150 '' and the third n + amorphous silicon thin film pattern 125 '', which are patterned in the same pattern as the third light- 2 amorphous silicon thin film pattern 124 '' and the third n + amorphous silicon thin film pattern 125 '' and the data pad line pattern 150 '', respectively.

Thereafter, as shown in FIG. 7E, an ahing process for removing a portion of the first to fifth photosensitive film patterns is performed to completely remove the fifth photosensitive film pattern of the second transmission region II do.

At this time, the first to fourth photosensitive film patterns correspond to the blocking region III with the sixth photosensitive film pattern 170a 'to the ninth photosensitive film pattern 170d' removed by the thickness of the fifth photosensitive film pattern Only the source / drain electrode region, the data line region, and the data pad line region remain.

Here, in the case of the first embodiment of the present invention, the sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' are not only thicker than the first photoresist pattern to the fourth photoresist pattern, The sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' are formed on the first photoresist pattern to the fourth photoresist pattern 170d ', respectively, And may be patterned to have substantially the same width.

7F and 7G, a part of the second conductive film pattern is removed using the remaining sixth photosensitive film pattern 170a 'to the ninth photosensitive film pattern 170d' as a mask, A source electrode 122 and a drain electrode 123, which are the second conductive film, are formed in a pixel portion of the substrate 110.

In addition, by partially removing the data line pattern and the data pad line pattern using the remaining sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' as masks, the data line area of the array substrate 110 And a data line 117 and a data pad line 117p made of the second conductive film are formed in the data pad line region, respectively.

At this time, on the active pattern 124, an ohmic contact layer (not shown) is formed of the n + amorphous silicon thin film and ohmic-contacted between the source / drain region of the active pattern 124 and the source / drain electrodes 122, (125n) is formed.

The fourth n + amorphous silicon layer, which is formed of the n + amorphous silicon thin film and is patterned substantially in the same pattern as the data line 117 and the data pad line 117p, is formed under the data line 117 and the data pad line 117p. A silicon thin film pattern 125 "and a fifth n + amorphous silicon thin film pattern 125" "are formed.

As described above, the first embodiment of the present invention uses the half-tone mask to form the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, and the first to third light-shielding patterns 130 ' To 130 "") can be formed through a single mask process.

In this case, the first to third light-shielding patterns 130 'to 130' '' of the first embodiment of the present invention are formed under the active pattern 124, the data line 117, and the data pad line 117p The present invention is not limited thereto. The light-shielding pattern of the present invention can be applied to the gate line and the gate pad line as well as the active pattern 124, the data line 117 and the data pad line 117p, Can also be formed on the bottom.

Next, as shown in FIGS. 5B and 6B, the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, and the first to third light-shielding patterns 130 'to 130' The gate line 121 and the gate line 116 and the common line 1081 are formed in the pixel portion of the array substrate 110 on which the second insulating film 115a is formed and the array substrate 110 The gate pad line 116p is formed with the second insulating layer 115a interposed therebetween.

At this time, the gate electrode 121, the gate line 116, the common line 1081 and the gate pad line 116p form a third conductive film on the active pattern 124, the source / drain electrodes 122 and 123, Is deposited on the entire surface of the array substrate 110 on which the line 117 and the first to third light shielding patterns 130 'to 130' '' are formed, and is selectively patterned through a photolithography process (second mask process) .

Here, as the third conductive film, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy may be used. The third conductive layer may be formed in a multi-layer structure in which two or more low resistance conductive materials are stacked.

The liquid crystal display of the present invention has a top gate structure in which the gate electrode 121 is positioned above the array substrate 110 on which the active pattern 124 and the source and drain electrodes 122 and 123 are formed .

Next, as shown in FIGS. 5C and 6C, on the front surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the common line 1081 and the gate pad line 116p are formed, A first contact hole 140a for exposing a part of the drain electrode 123 of the array substrate 110 is formed by selectively removing the insulating film 115b through a photolithography process (a third mask process) do.

In addition, a part of the third insulating film 115b may be removed through the third masking process so that a part of the data pad line 117p and the gate pad line 116p are formed in the data pad portion and the gate pad portion, A second contact hole 140b and a third contact hole 140c are formed.

5D and 6D, a fourth conductive film made of a transparent conductive material is formed on the entire surface of the third insulating film 115b on which the first to third contact holes 140a to 140c are formed A pixel electrode 118 electrically connected to the drain electrode 123 through the first contact hole 140a is formed in the pixel region by patterning selectively using a photolithography process (fourth mask process) .

At this time, the fourth conductive layer is selectively patterned using the fourth mask process to form data pad portions and gate pad portions, respectively, through the second contact holes 140b and the third contact holes 140c, A data pad electrode 127p and a gate pad electrode 126p electrically connected to the line 117p and the gate pad line 116p are formed.

The fourth conductive layer may be formed of indium tin oxide (ITO) or indium zinc oxide (ITO) to form the pixel electrode 118, the data pad electrode 127p, and the gate pad electrode 126p. And indium zinc oxide (IZO).

The array substrate according to the first embodiment of the present invention, which is fabricated as described above, is attached to the color filter substrate opposite to the color filter substrate, thereby forming a liquid crystal display device.

FIG. 8 is a cross-sectional view schematically showing a liquid crystal display according to a first embodiment of the present invention in which the array substrate and the color filter substrate shown in FIG. 5D are cemented together, And a liquid crystal display device serving as a matrix.

As shown in the drawing, the array substrate 110 manufactured as described above is adhered to the color filter substrate 105 in a state where a certain cell gap is maintained by a column spacer (not shown) formed on the color filter substrate 105, Thereby constituting a liquid crystal display device.

At this time, the color filter substrate 105 is provided with a color filter composed of a plurality of sub-color filters 107 implementing red, green and blue hues on the transparent color filter substrate 105, And a transparent common electrode 108 for applying a voltage to the liquid crystal layer 190. The liquid crystal layer 190 is formed of a transparent matrix material.

The black matrix 106 may be patterned in a boundary region of pixels to prevent leakage of light generated from the backlight in the lower portion of the liquid crystal display device and to prevent color mixing of neighboring pixels.

At this time, although not shown in the drawing, an over coat layer may be further formed on the color filter, and the overcoat layer may be formed by a part of the sub-color filters 106, The upper surface of the color filter is flattened by eliminating the step that occurs due to overlapping.

At this time, in the case of the first embodiment of the present invention, a first light-shielding pattern (not shown) made of an opaque conductive material is formed under the active pattern 124 of the lower array substrate 110, the data line 117 and the data pad line Shielding pattern (not shown) is formed between the first light-shielding pattern 130 ', the second light-shielding pattern 130' and the third light-shielding pattern 130 ', the black matrix 106 functions to block leakage of light generated from the backlight below the liquid- As a result, the black matrix 106 of the color filter substrate 105 can reduce the margin d 'by the width w, thereby providing an effect of substantially improving the aperture ratio.

That is, even if misalignment occurs when the color filter substrate 105 and the array substrate 110 are attached together, the active pattern 124 of the array substrate 110 on which the black matrix 106 is located, the data line 117, The first light-shielding pattern 130 ', the second light-shielding pattern 130', and the third light-shielding pattern, which are made of opaque conductive material, are formed under the pad line, thereby blocking leakage of light generated from the lower backlight .

For reference, reference numeral "d" denotes the margin of the black matrix in the conventional liquid crystal display device described above.

As described above, the liquid crystal display of the first embodiment has the first light-shielding pattern 130 'and the second light-shielding pattern 130 "and the second light-shielding pattern 130" below the active pattern 124, the data line 117, Shielding pattern is formed not only under the active pattern, the data line, and the data pad line but also under the gate line and the gate pad line. And will be described in detail through the following second embodiment of the present invention.

9 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to a second embodiment of the present invention. In the liquid crystal display device according to the first embodiment, except that a shielding pattern is also formed under the gate lines and gate pad lines, And is composed of the same components as the array substrate of the display device.

As shown in the drawing, a gate line 216 and a data line 217 are formed on the array substrate 210 on the array substrate 210 in the second embodiment. In addition, a thin film transistor, which is a switching device, is formed in an intersection region of the gate line 216 and the data line 217, and a common electrode of a color filter substrate (not shown) is connected to the thin film transistor A pixel electrode 218 for driving a liquid crystal (not shown) is formed.

The thin film transistor is electrically connected to the pixel electrode 218 through a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a first contact hole 240a. And the drain electrode 223 connected thereto. The thin film transistor includes an active pattern 224 that forms a conduction channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

The thin film transistor according to the second embodiment of the present invention is a top gate type in which the gate electrode 221 is located above the source electrode 222, the drain electrode 223 and the active pattern 224 .

The array substrate 210 according to the second embodiment of the present invention includes the active pattern 224, the data line 217, the gate line 216, the data pad line 217p, and the gate pad line 216p. And a light shielding pattern 230 made of an opaque conductive material such as chrome is formed on the lower portion of the gate line 116. The light shielding pattern 230 is formed on the thin film transistor region, The data pad line 117p region, and the gate pad line 216p region. Reference numeral 224 'denotes an amorphous silicon thin film pattern made of an amorphous silicon thin film on the light shielding pattern 230.

At this time, common lines 2081 are arranged in the pixel region in a direction substantially parallel to the gate lines 216, and a part of the common lines 2081 are arranged in a direction in which a third insulating film (not shown) And overlaps a part of the pixel electrode 218 on the upper part to form a storage capacitor Cst.

A gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210, The gate line 216 and the data line 217 transmit the scan signal and the data signal, respectively, to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend to the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, The line 217p is connected to the gate pad line 216p and the data pad line 217p through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, .

The data pad electrode 227p is electrically connected to the data pad line 217p through the second contact hole 240b and the second contact hole 240b is electrically connected to the data pad line 217p through the second contact hole 240b. And the gate pad electrode 226p is electrically connected to the gate pad line 216p through the third contact hole 240c

Here, the liquid crystal display according to the second embodiment of the present invention is not limited to the active pattern 224, the data line 217 and the data pad line 217p as well as the lower part of the gate line 216 and the gate pad line 216p The black matrix margin of the upper color filter substrate can be further reduced as compared with the liquid crystal display of the first embodiment as a result of the presence of the light shielding pattern 230 made of the opaque conductive material, .

10A is a plan view schematically showing a black matrix structure of an upper color filter substrate in a general liquid crystal display device, and FIG. 10B is a plan view of a liquid crystal display device according to a second embodiment of the present invention shown in FIG. Fig. 6 is a plan view schematically showing a black matrix structure of a filter substrate. Fig.

As shown in FIG. 10A, a typical liquid crystal display device includes a thin film transistor region, a gate line region, and a data line region of a lower array substrate on an upper color filter substrate 5, A black matrix 6 is formed.

At this time, the black matrix 6 is formed to have a predetermined margin to prevent light leakage due to misalignment occurring when the color filter substrate 5 and the array substrate are attached together. As a result, in the case of a general liquid crystal display device, the aperture ratio is reduced by the margin of the black matrix.

10B, in the liquid crystal display device according to the second embodiment of the present invention, the light shielding pattern made of the opaque conductive material is formed in the thin film transistor region, the gate line region, and the data line region of the lower array substrate, The black matrix 206 of the color filter substrate 205 may be formed to have only a minimum width for distinguishing red, green and blue sub-color filters. As a result, the aperture ratio is improved by the reduced margin of the black matrix.

Although the amorphous silicon thin film transistor using the amorphous silicon thin film as the active pattern has been described as an example of the first and second embodiments, the present invention is not limited thereto. The present invention can be applied to the case where the polycrystalline silicon thin film Is also applied to a polycrystalline silicon thin film transistor.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are sectional views sequentially showing a manufacturing process of an array substrate in the liquid crystal display device shown in Fig.

FIG. 3 is a cross-sectional view schematically showing a general liquid crystal display device in which the array substrate and the color filter substrate shown in FIG.

4 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to the first embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views sequentially showing a manufacturing process according to lines IVa-IVa ', IVb-IVb and IVc-IVc of the array substrate shown in FIG.

6A to 6D are plan views sequentially showing the manufacturing steps of the array substrate shown in Fig.

FIGS. 7A to 7G are cross-sectional views specifically showing a first mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5A and 6A. FIG.

8 is a cross-sectional view schematically showing a liquid crystal display according to a first embodiment of the present invention in which the array substrate and the color filter substrate shown in FIG.

9 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to a second embodiment of the present invention.

10A is a plan view schematically showing a black matrix structure of an upper color filter substrate in a general liquid crystal display device.

FIG. 10B is a plan view schematically showing a black matrix structure of an upper color filter substrate in a liquid crystal display device according to a second embodiment of the present invention shown in FIG. 9; FIG.

DESCRIPTION OF REFERENCE NUMERALS

110, 210: array substrate 116, 216: gate line

117, 217: Data lines 118, 218:

121, 221: gate electrodes 122, 222: source electrode

123, 223: drain electrode 124, 224: active pattern

130 'to 130' '', 230: Shading pattern

Claims (15)

Providing a first substrate; Forming a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern on the thin-film transistor region, the data line region and the gate line region of the first substrate through a first masking process with opaque conductive materials; Forming an active pattern and a source / drain electrode on the first light-shielding pattern including the first insulating layer using the first mask process; Forming a data line on the second light-shielding pattern including the first insulating layer, the amorphous silicon thin-film pattern, and the n + amorphous silicon thin-film pattern using the first mask process; Forming a gate electrode on the active pattern of the first substrate in which the second insulating film is interposed through a second mask process; The first insulating film, the amorphous silicon thin film pattern, the n < + > amorphous silicon thin film pattern, and the second insulating film are sequentially interposed between the third light-shielding pattern and the data line, Forming a gate line defining an area; Forming a common line in the pixel region above the first substrate in which only the second insulating film is interposed using the second mask process; Forming a third insulating film on the first substrate on which the gate electrode, the gate line, and the common line are formed; Removing a part of the third insulating film through a third mask process to form a contact hole exposing a part of the drain electrode; Forming a pixel electrode electrically connected to the drain electrode through the contact hole using a fourth mask process; And And bonding the first substrate and the second substrate to each other. The method of claim 1, further comprising: forming an n + amorphous silicon thin film on the active pattern using the first mask process, wherein an ohmic contact layer is formed between the source / drain region of the active pattern and the source / And forming a second electrode on the second electrode. The method of manufacturing a liquid crystal display device according to claim 1, wherein the first light-shielding pattern is formed under the active pattern so as to have the same shape as the active pattern. The method according to claim 3, wherein the second light-shielding pattern is formed under the data line so as to have a wider width than the data line. 5. The method of claim 4, wherein the third light-shielding pattern is formed under the gate line so as to have a width wider than the gate line. delete The manufacturing method of a liquid crystal display device according to claim 1, wherein a part of the common line overlaps with a part of the pixel electrode in which the third insulating film is interposed, thereby forming a storage capacitor. The method of claim 1, further comprising forming a black matrix on the second substrate corresponding to the first, second, and third light-shielding patterns so as to have a narrower width than the first, second, and third light- And forming a second electrode on the second electrode. A first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern provided on the thin-film transistor region, the data line region, and the gate line region of the first substrate, respectively, as opaque conductive materials; An active pattern provided on the first light-shielding pattern on which the first insulating film is disposed; A source electrode and a drain electrode provided on the active pattern and electrically connected to a source region and a drain region of the active pattern; A data line provided on the second light-shielding pattern having the first insulating film, the amorphous silicon thin film pattern and the n + amorphous silicon thin film pattern interposed therebetween; A gate electrode provided on the active pattern with a second insulating film interposed therebetween; And a gate line which is provided on the third light-shielding pattern in which the first insulating film, the amorphous silicon thin film pattern, the n + amorphous silicon thin film pattern, and the second insulating film are sequentially interposed and crosses the data line, ; A common line provided in a pixel region above the first substrate in which only the second insulating film exists; A third insulating layer provided on the first substrate having the gate electrode, the gate line, and the common line; A pixel electrode provided in the pixel region and electrically connected to the drain electrode through a contact hole provided in the third insulating film; And And a second substrate which is adhered to and adhered to the first substrate. 10. The semiconductor device according to claim 9, further comprising an ohmic contact layer provided on the active pattern as an n + amorphous silicon thin film and ohmic-contacting the source / drain region of the active pattern and the source / drain electrode. Liquid crystal display device. The liquid crystal display of claim 9, wherein the first light-shielding pattern is patterned in the same pattern as the active pattern under the active pattern. The liquid crystal display of claim 11, wherein the second light-shielding pattern is patterned to have a width wider than the data line below the data line. 13. The liquid crystal display of claim 12, wherein the third light-shielding pattern is patterned to have a width wider than the gate line under the gate line. 10. The liquid crystal display device according to claim 9, wherein the common line overlaps with a part of the pixel electrode in which the third insulating film is interposed, thereby constituting a storage capacitor. 10. The light-emitting device according to claim 9, further comprising: a black matrix provided on the second substrate corresponding to the first, second, and third light-shielding patterns and patterned to have a narrower width than the first, second, Wherein the liquid crystal display device further includes a liquid crystal display panel.

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