KR102574600B1 - Display device - Google Patents

Abstract

The present invention provides a display device capable of improving off current characteristics of a thin film transistor due to internal light reflection. A display device according to an exemplary embodiment includes a gate line, a common line, a data line, a thin film transistor, and a black matrix. The gate line and the common line are arranged side by side in one direction, and the data line is arranged crossing the gate line. The thin film transistor is disposed at the intersection of the gate line and the data line. The black matrix is disposed to overlap the gate line and the thin film transistor, but partially exposes the gate line.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of improving off-current characteristics of a thin film transistor due to internal light reflection.

A liquid crystal display device displays an image by adjusting light transmittance of a liquid crystal using an electric field. The liquid crystal display device is roughly classified into a vertical electric field type and a horizontal electric field type according to the direction of an electric field driving the liquid crystal.

In a vertical electric field liquid crystal display, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are disposed to face each other, and a vertical electric field formed between them drives liquid crystal in a twisted nematic (TN) mode. Such a vertical field type liquid crystal display device has an advantage of a large aperture ratio, but has a disadvantage of a narrow viewing angle of about 90 degrees.

A horizontal electric field type liquid crystal display drives liquid crystal in an in-plane switching (IPS) mode by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field type liquid crystal display device has a wide viewing angle. On the other hand, the horizontal field type liquid crystal display device has a disadvantage in that the aperture ratio is lower than that of the vertical field type liquid crystal display device.

FIG. 1 is a plan view showing a pixel structure of a conventional liquid crystal display device, and FIG. 2 is a cross-sectional view illustrating a pixel structure of the liquid crystal display device shown in FIG. 1 .

Referring to FIG. 1 , a conventional liquid crystal display includes gate lines GL and data lines DL crossing each other on a transparent lower substrate. Gate lines GL and data lines DL orthogonal to each other with a gate insulating layer interposed therebetween define a pixel area of a matrix arrangement. On one side of the pixel area, a gate line GL serving as a gate electrode, a semiconductor layer A positioned on a gate insulating film covering the gate line GL, a source electrode S branching from the data line DL, and a source A thin film transistor (T) including a drain electrode (D) disposed to face the electrode (S) at a predetermined interval is disposed. One side of the semiconductor layer (A) is in contact with the source electrode (S), and the other side is in contact with the drain electrode (D).

At least one insulating film for protecting a device is disposed on the thin film transistor T, and a pixel electrode PXL and a common electrode COM made of a transparent conductive material are disposed on the insulating film. The pixel electrode PXL contacts the drain electrode D through the pixel contact hole PH penetrating the insulating layer. In addition, the pixel electrode PXL has slits in which a plurality of line segments are arranged in parallel at regular intervals in the pixel area. The common electrode COM is disposed in a plate shape on the entire surface of the pixel area and is connected to a common line CL arranged in parallel with the gate line GL. The common electrode COM is connected to the common line CL through a common contact hole CH penetrating the insulating layers.

A horizontal electric field is formed between the pixel electrode PXL and the common electrode COM in the surface direction of the lower substrate, and the liquid crystal layer disposed on the lower substrate is driven by the horizontal electric field. An upper substrate facing the lower substrate is disposed on the liquid crystal layer. A black matrix BM partitioning a plurality of pixel areas disposed on the lower substrates is disposed on the upper substrate. The black matrix BM blocks metal wires such as the gate line GL, the data line DL, the common line CL, the source electrode S, and the drain electrode D to prevent external light from being reflected.

Referring to FIG. 2 , the black matrix BM includes a metal material called carbon black showing a black color. When light is incident from a light source located under the lower substrate SUB, some of the light is emitted to the upper substrate USUB and some of the light is reflected from the black matrix BM. Light reflected from the black matrix BM is reflected from the gate line GL formed on the lower substrate SUB and introduced into an adjacent thin film transistor. Therefore, when light is incident on the semiconductor layer of the thin film transistor, the off current characteristic of the thin film transistor is deteriorated.

The present invention provides a display device capable of improving off current characteristics of a thin film transistor due to internal light reflection.

To achieve the above object, a display device according to an exemplary embodiment includes a gate line, a common line, a data line, a thin film transistor, and a black matrix. The gate line and the common line are arranged side by side in one direction, and the data line is arranged crossing the gate line. The thin film transistor is disposed at the intersection of the gate line and the data line. The black matrix is disposed to overlap the gate line and the thin film transistor, but partially exposes the gate line.

For example, the exposed portion of the gate line exposed by the black matrix is adjacent to the thin film transistor.

For example, the width of the exposed portion of the gate line is 3 μm or more, but is less than or equal to the distance before the exposed portion of the gate line reaches the semiconductor layer of the thin film transistor.

In one example, the exposed portion of the gate line faces the common line.

For example, a light blocking pattern disposed between the gate line and the black matrix may be further included.

For example, the light blocking pattern overlaps the gate line and the black matrix.

Also, the display device according to an exemplary embodiment includes a gate line, a common line, a data line, a thin film transistor, a black matrix, and a light blocking pattern. The gate line and the common line are arranged side by side in one direction, and the data line is arranged crossing the gate line. The thin film transistor is disposed at the intersection of the gate line and the data line. The black matrix is disposed to overlap the gate line and the thin film transistor. The light blocking pattern is positioned between the gate line and the black matrix and overlaps the gate line and the black matrix.

For example, the corner of the light blocking pattern coincides with the corner of the gate line.

For example, the corner of the light blocking pattern is positioned outside the gate line.

For example, the width of the light blocking pattern covers at least one end of the gate line and is 3 μm or more in the direction of the semiconductor layer of the thin film transistor, and is less than or equal to the distance from one end of the black matrix to the semiconductor layer of the thin film transistor.

In the present invention, by forming an undercut through over-etching, a common electrode can be formed without an additional mask process. In particular, by patterning the common electrode in the pixel contact hole without a separate process, it is possible to prevent a decrease in yield and an increase in manufacturing cost due to an additional process.

In addition, according to the present invention, the black matrix is reduced to expose a portion of the gate line overlapping the black matrix. Accordingly, by blocking light incident on the black matrix from being reflected and reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

In addition, according to the present invention, a light blocking pattern is formed between the black matrix and the gate line to block light from a light source to the black matrix with the gate line, and to prevent light incident from the upper substrate from traveling to the black matrix using the light blocking pattern. block it Accordingly, by blocking light from reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

In addition, in the present invention, when the black matrix is formed to completely cover the gate line, the light blocking pattern LSP is formed between the black matrix and the gate line. Therefore, light from the light source is blocked from being reflected by the black matrix and proceeding to the gate line, and light incident from the upper substrate can be blocked by the black matrix. Accordingly, by blocking light from reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

1 is a plan view showing a pixel structure of a liquid crystal display according to the prior art;
2 is a cross-sectional view schematically illustrating a pixel structure of the liquid crystal display shown in FIG. 1;
3 is a plan view showing the structure of a display device according to a first embodiment of the present invention;
4 is a cross-sectional view of the display device according to the first embodiment of the present invention shown in FIG. 3 taken along the line II';
5 schematically illustrates a display device according to a first embodiment of the present invention;
6A to 6F are cut along the cut line II' in FIG. 3 and are views for explaining a method of manufacturing a display device according to the first embodiment of the present invention.
7 is a plan view showing the structure of a display device according to a second embodiment of the present invention;
8 is a cross-sectional view of the display device according to the second embodiment of the present invention shown in FIG. 7 taken along the line II-II';
9 is a diagram schematically illustrating a display device according to a second embodiment of the present invention;
10 is a plan view showing the structure of a display device according to a third embodiment of the present invention;
11 is a cross-sectional view of the display device according to the third embodiment of the present invention shown in FIG. 10 taken along the line III-III'.
12 schematically illustrates a display device according to a third embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

Hereinafter, technical features of the present invention will be described in detail through preferred embodiments. It should be noted that the features of the present invention are not limited to the following examples.

<First Embodiment>

Hereinafter, a display device according to a first embodiment of the present invention will be described with reference to FIGS. 3 to 5 . 3 is a plan view showing the structure of a display device according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view of the display device according to the first embodiment of the present invention shown in FIG. 3 taken along the line II'. 5 is a diagram schematically illustrating a display device according to a first embodiment of the present invention.

Referring to FIGS. 3 and 4 , the display device according to the first embodiment of the present invention includes a gate line GL, a data line DL, and a common line CL crossing each other on a lower substrate SUB. . The gate line GL and the common line CL are arranged parallel to each other and cross the data line DL with the gate insulating layer GI interposed therebetween. A pixel area is defined by the intersection of the gate line GL, the data line DL, and the common line CL.

On one side of the pixel area, for example, at the intersection of the gate line GL and the data line DL, the gate line GL acting as a gate electrode, the data line DL acting as a source electrode S, and the data line A drain electrode (D) disposed to face and spaced apart from (DL) by a predetermined distance is positioned. A semiconductor layer A is formed on the gate insulating layer GI covering the gate line GL to overlap the gate line GL. One side of the semiconductor layer A contacts the data line DL, and the other side contacts the drain electrode D. Accordingly, the gate line GL, the semiconductor layer A, the data line DL, and the drain electrode D constitute the thin film transistor T.

The structure of the thin film transistor is not limited to the structures shown in FIGS. 3 and 4, and may include various structures such as a top gate structure, a bottom gate structure, and a double gate structure. can

A first insulating film PAS1 for protecting the device and a second insulating film PAC for planarization are sequentially formed on the thin film transistor T. A common electrode COM formed of a transparent conductive material is positioned on the second insulating layer PAC. The common electrode COM is connected to the common line CL through a common contact hole CH penetrating the gate insulating layer GI, the first insulating layer PAS1, and the second insulating layer PAC. A third insulating layer PAS2 insulating the common electrode COM is formed on the common electrode COM. In the present invention, an undercut (UA) is formed by over-etching the common electrode (COM) under the third insulating layer (PAS2). Since the undercut UA occurs under the third insulating layer PAS2, one end of the third insulating layer PAS2 protrudes from one end of the common electrode COM.

A pixel electrode PXL formed of a transparent conductive material is disposed on the third insulating layer PAS2 . The pixel electrode PXL is connected to the drain electrode D through the pixel contact hole PH penetrating the first insulating layer PAS1 , the second insulating layer PAC and the third insulating layer PAS2 . The pixel electrode PXL has slits in which a plurality of line segments are arranged in parallel at regular intervals in the pixel area. However, the shape of the pixel electrode PXL is not limited thereto.

As shown in FIG. 4 , the pixel electrode PXL formed on the third insulating layer PAS2 does not contact the common electrode COM by the undercut UA. The common electrode COM is formed in a plate shape over the entire pixel area except for the pixel contact hole PH through which the pixel electrode PXL is connected to the drain electrode D.

A horizontal electric field is formed between the pixel electrode PXL and the common electrode COM in the direction of the surface of the lower substrate SUB, and the liquid crystal layer LC disposed on the lower substrate SUB is affected by the horizontal electric field. drive An upper substrate USUB facing the lower substrate SUB is disposed on the liquid crystal layer LC. A black matrix BM partitioning openings OP of a plurality of pixel areas disposed on lower substrates SUB is disposed on the upper substrate USUB. The black matrix BM is formed to overlap metal wires such as the gate line GL, the data line DL, the common line CL, and the drain electrode D, so that light incident from the outside can pass through the metal wires. is reflected on the screen to prevent it from being visible to the user.

As shown in FIG. 3 , in the first embodiment of the present invention, the black matrix BM is disposed to overlap the gate line GL, but is formed to expose a part of the gate line GL. Exposing a part of the gate line GL by the black matrix BM means that the gate line GL is not covered by the black matrix BM when viewing the lower substrate SUB from the upper substrate USUB. says what is shown In the following, an area in which a portion of the gate line GL is visible without being covered by the black matrix BM will be referred to as an 'exposed portion' and described.

The exposed portion EP of the gate line GL is formed to block light from the light source from reaching the black matrix BM, and is formed by exposing the gate line GL by reducing the area of the black matrix BM. do. The exposed portion EP of the gate line GL includes a corner facing the common line CL defining the same pixel area. That is, the exposed portion EP of the gate line GL is disposed adjacent to the opening OP where the pixel electrode PXL and the common electrode COM overlap. Accordingly, by reducing the area of the black matrix BM to form the exposed portion EP of the gate line GL, the opening OP of the pixel area may be enlarged.

The exposed portion EP of the gate line GL may have a certain width W1 to improve the off current characteristics of the thin film transistor T. The width W1 of the exposed portion EP of the gate line GL is 3 μm or more, and the distance until the exposed portion EP of the gate line GL reaches the semiconductor layer A of the thin film transistor T (d1) may consist of the following. Here, when the width W1 of the exposed portion EP of the gate line GL is 3 μm or more, light incident from the bottom is blocked from reaching the black matrix BM, so that the off current characteristic of the thin film transistor T is improved. degradation can be prevented. When the width W1 of the exposed portion EP of the gate line GL is equal to or less than the distance d1 before reaching the semiconductor layer A of the thin film transistor T, external light incident from the upper substrate USUB It is possible to prevent the off current characteristic from deteriorating by reaching the semiconductor layer (A) of the thin film transistor (T).

As described above, according to the present invention, the black matrix BM is reduced to expose a portion of the gate line GL overlapping the black matrix BM. Accordingly, the gate line GL blocks light from the light source from traveling to the black matrix BM.

Referring to FIG. 5 in more detail, light incident from a light source located under the lower substrate SUB travels in the direction of the upper substrate USUB. At this time, the area of the black matrix BM is reduced so that the gate line GL protrudes more than the black matrix BM, so that the propagation of light is blocked by the gate line GL of the lower substrate SUB. That is, the gate line GL blocks light from reaching the black matrix BM formed on the upper substrate USUB. Therefore, by blocking light incident on the black matrix BM from being reflected and reaching the semiconductor layer A of the thin film transistor T, deterioration of the off current characteristic of the thin film transistor can be prevented.

Hereinafter, a method of manufacturing the display device according to the first embodiment of the present invention will be described with reference to FIGS. 6A to 6F. 6A to 6F are cut along the cut line II′ in FIG. 3 and are views for explaining a method of manufacturing a display device according to the first embodiment of the present invention.

Referring to FIG. 6A , a gate metal material is coated on the lower substrate SUB and patterned through a mask process to form a gate line GL and a common line (not shown, see FIG. 3 ). Gate metal materials are copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta), and tungsten. It consists of a single layer or multiple layers of any one selected from the group consisting of (W) or an alloy thereof. Since the mask process can be performed by a known method, a detailed description thereof will be omitted. The gate line GL and the common line are formed parallel to each other.

Referring to FIG. 6B , a gate insulating layer GI is formed on the lower substrate SUB on which the gate line GL and the common line are formed to insulate them. The gate insulating film GI is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. Next, a semiconductor material is deposited on the lower substrate SUB on which the gate insulating film GI is formed, and a source electrode material is deposited on the semiconductor material. Here, the semiconductor material may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), or an oxide-based semiconductor, and the source electrode material may be copper (Cu), molybdenum (Mo), aluminum (Al), or chromium (Cr). ), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta), and tungsten (W). Subsequently, a semiconductor material and a source electrode material are patterned through a mask process to form a semiconductor layer (A) overlapping the gate line (GL), and a source electrode (S) contacting a part of the semiconductor layer (A), a semiconductor layer ( A drain electrode D and a data line DL contacting the other part of A) are formed. In the present invention, the semiconductor material and the source electrode material are patterned in one mask process using a halftone mask, so that the semiconductor material always exists under the source electrode material. Accordingly, a semiconductor layer (A) of a semiconductor material is positioned under the source electrode (S) and the drain electrode (D), and the data line (DL) is also formed in a two-layer structure of the source electrode material and the semiconductor material.

The source electrode (S) and the drain electrode (D) are separated from each other and formed to be spaced apart from each other. Thus, the thin film transistor T having the gate line GL, the semiconductor layer A, the source electrode S, and the drain electrode D is manufactured.

Referring to FIG. 6C , a first insulating layer PAS1 is formed by coating an insulating material on the lower substrate SUB on which the thin film transistor T is formed. The first insulating layer PAS1 is formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. In this step, the first insulating layer PAS1 remains unpatterned.

Subsequently, a photosensitive insulating material is coated on the lower substrate SUB on which the first insulating layer PAS1 is formed. In order to pattern the photosensitive insulating material through a mask process, a mask (not shown) is prepared, and light is selectively irradiated to the photosensitive insulating material through the prepared mask. The photosensitive insulating material may be a positive type photo resist material or a negative type photo resist material. For example, when the photosensitive insulating material is a positive photoresist material, when the photosensitive insulating material exposed through a mask is developed, the photosensitive insulating material irradiated with light is removed and the photosensitive insulating material not irradiated with light remains. The remaining photosensitive insulating material becomes the second insulating layer PAC. A portion of the first insulating layer PAS1 is exposed through the region where the photosensitive insulating material is removed.

Next, the first insulating layer PAS1 is patterned using the second insulating layer PAC as a mask to form a pixel contact hole PH and a common contact hole (not shown). A portion of the drain electrode D is exposed through the pixel contact hole PH, and a portion of the common line (not shown) is exposed through the common contact hole (not shown).

Referring to FIG. 6D , a transparent conductive material is deposited on the lower substrate SUB on which the second insulating film PAC is formed, and then the insulating material is sequentially deposited. Next, when an insulating material is patterned through a mask process, a third insulating layer PAS2 is formed by removing a region corresponding to the pixel contact hole PH. As the third insulating layer PAS2 is patterned, the transparent conductive material positioned below the third insulating layer PAS2 is exposed in an area corresponding to the pixel contact hole PH. Then, the transparent conductive material is etched to form the common electrode COM through which the pixel contact hole PH is exposed. At this time, the common electrode COM is over-etched to form the undercut UA. Since the undercut UA is formed below the third insulating layer PAS2, one end of the third insulating layer PAS2 protrudes from one end of the common electrode COM in the pixel contact hole PH. In the present invention, the common electrode COM is also patterned using the mask that patterns the third insulating layer PAS2, so that the number of masks can be reduced, thereby reducing manufacturing time and cost.

Next, referring to FIG. 6E , a transparent conductive material is coated on the lower substrate SUB on which the third insulating layer PAS2 is formed. A transparent conductive material is patterned through a mask process to form the pixel electrode PXL. The pixel electrode PXL is formed along the third insulating layer PAS2 and does not contact the common electrode COM on which the undercut UA is formed. The pixel electrode PXL contacts and is electrically connected to the drain electrode D.

Next, referring to FIG. 6F , a transparent upper substrate USUB is prepared, and a black material is applied and patterned on the upper substrate USUB to form a black matrix BM. When the black matrix BM is bonded to the lower substrate SUB, the gate line GL formed on the lower substrate SUB is partially exposed. Then, the display device according to the first embodiment of the present invention is completed by bonding the upper substrate USUB and the lower substrate SUB to form the liquid crystal layer LC.

In the present invention, by forming an undercut through over-etching, a common electrode can be formed without an additional mask process. In particular, by patterning the common electrode in the pixel contact hole without a separate process, it is possible to prevent a decrease in yield and an increase in manufacturing cost due to an additional process.

In addition, according to the present invention, the black matrix is reduced to expose a portion of the gate line overlapping the black matrix. Accordingly, by blocking light incident on the black matrix from being reflected and reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

<Second Embodiment>

Hereinafter, a display device according to a second embodiment of the present invention will be described with reference to FIGS. 7 to 9 . 7 is a plan view showing the structure of a display device according to a second embodiment of the present invention. FIG. 8 is a cross-sectional view of the display device according to the second embodiment of the present invention shown in FIG. 7 taken along the line II-II'. 9 is a diagram schematically illustrating a display device according to a second exemplary embodiment of the present invention.

Referring to FIGS. 7 and 8 , the display device according to the second embodiment of the present invention includes a gate line GL, a data line DL, and a common line CL crossing each other on a lower substrate SUB. . The gate line GL and the common line CL are arranged parallel to each other and cross the data line DL with the gate insulating layer GI interposed therebetween. A pixel area is defined by the intersection of the gate line GL, the data line DL, and the common line CL.

On one side of the pixel area, for example, at the intersection of the gate line GL and the data line DL, the gate line GL acting as a gate electrode, the data line DL acting as a source electrode S, and the data line A drain electrode (D) disposed to face and spaced apart from (DL) by a predetermined distance is positioned. A semiconductor layer A is formed on the gate insulating layer GI covering the gate line GL to overlap the gate line GL. One side of the semiconductor layer A contacts the data line DL, and the other side contacts the drain electrode D. Accordingly, the gate line GL, the semiconductor layer A, the data line DL, and the drain electrode D constitute the thin film transistor T.

A first insulating film PAS1 for protecting the device and a second insulating film PAC for planarization are sequentially formed on the thin film transistor T. A common electrode COM formed of a transparent conductive material is positioned on the second insulating layer PAC. The common electrode COM is connected to the common line CL through a common contact hole CH penetrating the gate insulating layer GI, the first insulating layer PAS1, and the second insulating layer PAC. A third insulating layer PAS2 insulating the common electrode COM is formed on the common electrode COM. In the present invention, an undercut (UA) is formed by over-etching the common electrode (COM) under the third insulating layer (PAS2). Since the undercut UA occurs under the third insulating layer PAS2, one end of the third insulating layer PAS2 protrudes from one end of the common electrode COM.

A pixel electrode PXL formed of a transparent conductive material is disposed on the third insulating layer PAS2 . The pixel electrode PXL is connected to the drain electrode D through the pixel contact hole PH penetrating the first insulating layer PAS1 , the second insulating layer PAC and the third insulating layer PAS2 . The pixel electrode PXL has slits in which a plurality of line segments are arranged in parallel at regular intervals in the pixel area. However, the shape of the pixel electrode PXL is not limited thereto. The common electrode COM is formed in a plate shape over the entire pixel area except for the pixel contact hole PH through which the pixel electrode PXL is connected to the drain electrode D.

A liquid crystal layer LC is disposed on the lower substrate SUB, and an upper substrate USUB facing the lower substrate SUB is disposed on the liquid crystal layer LC. A black matrix BM partitioning openings OP of a plurality of pixel areas disposed on lower substrate SUB is disposed on upper substrate USUB. The black matrix BM is formed to overlap metal wires such as the gate line GL, the data line DL, the common line CL, and the drain electrode D, so that light incident from the outside can pass through the metal wires. is reflected on the screen to prevent it from being visible to the user.

As shown in FIG. 7 , in the second embodiment of the present invention, the black matrix BM is disposed to overlap the gate line GL, but is formed to expose a part of the gate line GL. The exposed portion EP of the gate line GL is formed to block light from the light source from reaching the black matrix BM, and is formed by exposing the gate line GL by reducing the area of the black matrix BM. do. Accordingly, by reducing the area of the black matrix BM to form the exposed portion EP of the gate line GL, the opening OP of the pixel area may be enlarged.

In the second embodiment of the present invention, the light blocking pattern LSP is disposed between the black matrix BM and the gate line GL. The light blocking pattern LSP serves to block light incident in the direction of the upper substrate USUB, and is disposed to overlap the gate line GL. The light blocking pattern LSP may be made of the same material as the semiconductor material and is disposed on the gate insulating layer GI insulating the gate line GL. The light blocking pattern LSP is disposed to overlap the exposed portion EP of the gate line GL. One end of the light blocking pattern LSP is formed to coincide with one end of the exposed portion EP of the gate line GL. When the light-blocking pattern LSP exposes one end of the exposed portion EP of the gate line GL, light incident from the upper substrate USUB is reflected by the exposed portion EP of the gate line GL to form a thin film transistor ( T) may be incident on the semiconductor layer (A). Accordingly, it is preferable that one end of the light blocking pattern LSP at least coincide with one end of the exposed portion EP of the gate line GL. Therefore, the light blocking pattern LSP is disposed to face the common line CL, and the pixel The electrode PXL and the common electrode COM are disposed adjacent to the overlapping opening OP.

The light blocking pattern LSP may have a predetermined width W2 to improve the off current characteristics of the thin film transistor T. The width W2 of the light blocking pattern LSP is equal to or greater than the distance d2 from one end of the gate line GL to just before the light blocking pattern LSP overlaps the black matrix BM, and the light blocking pattern LSP is the thin film transistor. It may be made less than the distance (d3) before reaching the semiconductor layer (A) of (T). If the width W2 of the light blocking pattern LSP is equal to or greater than the distance d2 from one end of the gate line GL to just before the light blocking pattern LSP overlaps the black matrix BM, the light incident from the top is black. It is possible to prevent deterioration of the off-current characteristic of the thin film transistor T by blocking it from reaching the matrix BM. When the width W2 of the light blocking pattern LSP is equal to or less than the distance d3 before reaching the semiconductor layer A of the thin film transistor T, the light blocking pattern LSP is prevented from being connected to the semiconductor layer A. can do.

As described above, according to the present invention, the black matrix BM is reduced to expose a portion of the gate line GL overlapping the black matrix BM. In addition, a light blocking pattern LSP is formed between the black matrix BM and the gate line GL. Therefore, the light from the light source is blocked from traveling to the black matrix BM by the gate line GL, and the traveling of light incident from the upper substrate USUB to the black matrix BM is blocked by the light blocking pattern LSP. do.

Referring to FIG. 9 in more detail, light incident from a light source located under the lower substrate SUB travels in the direction of the upper substrate USUB, but the gate line GL protrudes more than the black matrix BM, so that the lower substrate ( The propagation of light is blocked by the gate line GL of the SUB. In addition, light incident from the upper substrate USUB proceeds in the direction of the lower substrate SUB, but the propagation of the light is blocked by the light blocking pattern LSP formed on the gate line GL. That is, the light blocking pattern LSP blocks light from reaching the gate line GL formed on the lower substrate SUB. Accordingly, it is possible to prevent light reflected from the gate line GL from being incident on the black matrix BM and reaching the semiconductor layer A of the thin film transistor T. Therefore, the second embodiment of the present invention blocks light incident on the gate line GL from being reflected and reaching the semiconductor layer A of the thin film transistor T, thereby reducing the off current characteristic of the thin film transistor T. can prevent it from happening.

<Third Embodiment>

Hereinafter, a display device according to a third embodiment of the present invention will be described with reference to FIGS. 10 to 12 . 10 is a plan view showing the structure of a display device according to a third embodiment of the present invention. FIG. 11 is a cross-sectional view of the display device according to the third embodiment of the present invention shown in FIG. 10 taken along the line III-III'. 12 is a diagram schematically illustrating a display device according to a third embodiment of the present invention.

Referring to FIGS. 10 and 11 , the display device according to the third exemplary embodiment of the present invention includes a gate line GL, a data line DL, and a common line CL crossing each other on a lower substrate SUB. . The gate line GL and the common line CL are arranged parallel to each other and cross the data line DL with the gate insulating layer GI interposed therebetween. A pixel area is defined by the intersection of the gate line GL, the data line DL, and the common line CL.

On one side of the pixel area, for example, at the intersection of the gate line GL and the data line DL, the gate line GL acting as a gate electrode, the data line DL acting as a source electrode S, and the data line A drain electrode (D) disposed to face and spaced apart from (DL) by a predetermined distance is positioned. A semiconductor layer A is formed on the gate insulating layer GI covering the gate line GL to overlap the gate line GL. One side of the semiconductor layer A contacts the data line DL, and the other side contacts the drain electrode D. Accordingly, the gate line GL, the semiconductor layer A, the data line DL, and the drain electrode D constitute the thin film transistor T.

A first insulating film (PAS) for protecting the device and a second insulating film (PAC) for planarization are sequentially formed on the thin film transistor (T). A common electrode COM formed of a transparent conductive material is positioned on the second insulating layer PAC. The common electrode COM is connected to the common line CL through a common contact hole CH penetrating the gate insulating layer GI, the first insulating layer PAS1, and the second insulating layer PAC. A third insulating layer PAS2 insulating the common electrode COM is formed on the common electrode COM. In the present invention, an undercut (UA) is formed by over-etching the common electrode (COM) under the third insulating layer (PAS2). Since the undercut UA occurs under the third insulating layer PAS2, one end of the third insulating layer PAS2 protrudes from one end of the common electrode COM.

A pixel electrode PXL formed of a transparent conductive material is disposed on the third insulating layer PAS2 . The pixel electrode PXL is connected to the drain electrode D through the pixel contact hole PH penetrating the first insulating layer PAS1 , the second insulating layer PAC and the third insulating layer PAS2 . The pixel electrode PXL has slits in which a plurality of line segments are arranged in parallel at regular intervals in the pixel area. However, the shape of the pixel electrode PXL is not limited thereto. The common electrode COM is formed in a plate shape over the entire pixel area except for the pixel contact hole PH through which the pixel electrode PXL is connected to the drain electrode D.

A liquid crystal layer LC is disposed on the lower substrate SUB, and an upper substrate USUB facing the lower substrate SUB is disposed on the liquid crystal layer LC. A black matrix BM partitioning openings OP of a plurality of pixel areas disposed on lower substrate SUB is disposed on upper substrate USUB. The black matrix BM is formed to overlap metal wires such as the gate line GL, the data line DL, the common line CL, and the drain electrode D, so that light incident from the outside can pass through the metal wires. is reflected on the screen to prevent it from being visible to the user.

As shown in FIG. 10 , in the third embodiment of the present invention, the black matrix BM is disposed to overlap the gate line GL, but is disposed to completely cover the gate line GL. In the third embodiment of the present invention, a light blocking pattern LSP is disposed between the black matrix BM and the gate line GL. The light blocking pattern LSP serves to block light reflected from the black matrix BM, and is disposed to overlap the gate line GL. The light blocking pattern LSP may be made of the same material as the semiconductor material and is disposed on the gate insulating layer GI insulating the gate line GL.

The light blocking pattern LSP is disposed to cover at least one end of the gate line GL. Here, one end of the gate line GL refers to one end adjacent to the opening OP of the pixel area. For example, a corner of the light blocking pattern LSP and a corner of the gate line GL may at least coincide with each other. Also, as an example, the corner of the light blocking pattern LSP may be positioned outside the corner of the gate line GL. When the light blocking pattern LSP is disposed to cover one end of the gate line GL, the lower substrate SUB ), it is possible to prevent the incident light from being reflected from the black matrix BM and re-reflected from the gate line GL to be incident to the semiconductor layer A of the thin film transistor T.

The light-blocking pattern LSP may have a predetermined width W3 to improve the off-current characteristics of the thin film transistor T. The width W3 of the light blocking pattern LSP is 3 μm or more from one end of the gate line GL, and the distance from one end of the black matrix BM to the semiconductor layer A of the thin film transistor T ( d4) may consist of the following. When the width W3 of the light-blocking pattern LSP is 3 μm or more from one end of the gate line GL, the light incident from the bottom is blocked from being reflected by the black matrix BM and reaching the gate line GL, thereby blocking the thin film. Deterioration of the off current characteristic of the transistor T can be prevented. When the width W3 of the light blocking pattern LSP is equal to or less than the distance d4 from one end of the black matrix BM to the semiconductor layer A of the thin film transistor T, the light blocking pattern LSP is formed in the pixel area. It is possible to prevent connection with the semiconductor layer (A) without reducing the opening (OP) of the.

As described above, when the black matrix BM is formed to completely cover the gate line GL, the light blocking pattern LSP is formed between the black matrix BM and the gate line GL. Therefore, light from the light source is blocked from being reflected by the black matrix BM and proceeding to the gate line GL, and light incident from the upper substrate USUB can be blocked by the black matrix BM.

Referring to FIG. 12 in more detail, light incident from a light source located under the lower substrate SUB travels in the direction of the upper substrate USUB. Some light is reflected from the black matrix BM and travels to the gate line GL, but is blocked by the light blocking pattern LSP. That is, light reflected from the black matrix BM formed on the upper substrate USUB is blocked from reaching the gate line GL by the light blocking pattern LSP. In addition, light incident from the upper substrate USUB is blocked by the black matrix BM, and is blocked from reaching the gate line GL formed on the lower substrate SUB. Therefore, by blocking light incident on the black matrix BM from being reflected and reaching the semiconductor layer A of the thin film transistor T, deterioration of the off current characteristic of the thin film transistor can be prevented.

As described above, the present invention can form a common electrode without an additional mask process by forming an undercut through over-etching. In particular, by patterning the common electrode in the pixel contact hole without a separate process, it is possible to prevent a decrease in yield and an increase in manufacturing cost due to an additional process.

In addition, according to the present invention, the black matrix is reduced to expose a portion of the gate line overlapping the black matrix. Accordingly, by blocking light incident on the black matrix from being reflected and reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

In addition, according to the present invention, a light blocking pattern is formed between the black matrix and the gate line to block light from a light source to the black matrix with the gate line, and to prevent light incident from the upper substrate from traveling to the black matrix using the light blocking pattern. block it Accordingly, by blocking light from reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

In addition, in the present invention, when the black matrix is formed to completely cover the gate line, the light blocking pattern LSP is formed between the black matrix and the gate line. Therefore, light from the light source is blocked from being reflected by the black matrix and proceeding to the gate line, and light incident from the upper substrate can be blocked by the black matrix. Accordingly, by blocking light from reaching the semiconductor layer of the thin film transistor, deterioration of the off current characteristic of the thin film transistor can be prevented.

Through the above description, those skilled in the art will be able to make various changes and modifications without departing from the spirit of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

A: semiconductor layer DL: data line
D: drain electrode GL: gate line
CL: common line PXL: pixel electrode
COM: common electrode EP: exposed part

Claims (13)

a gate line arranged in one direction at a lower end of the pixel area;
a common line arranged parallel to the gate line at an upper portion of the pixel area;
a data line crossing the gate line;
a thin film transistor disposed at an intersection of the gate line and the data line; and
A black matrix overlapping the gate line and the thin film transistor,
The black matrix covers the common line and the data line, exposes an exposed portion corresponding to one side of the gate line, and covers the rest of the gate line except for the exposed portion. According to claim 1,
The exposed portion of the gate line exposed by the black matrix is adjacent to the thin film transistor. According to claim 2,
The display device of claim 1 , wherein a width of the exposed portion of the gate line is greater than or equal to 3 μm and less than or equal to a distance before the exposed portion of the gate line reaches the semiconductor layer of the thin film transistor. According to claim 3,
The exposed portion of the gate line faces the common line. According to claim 1,
The display device further comprises a light blocking pattern disposed between the gate line and the black matrix. According to claim 5,
The light blocking pattern overlaps the gate line. According to claim 6,
The light blocking pattern overlaps the black matrix. a gate line arranged in one direction at a lower end of the pixel area;
a common line arranged parallel to the gate line at an upper portion of the pixel area;
a data line crossing the gate line;
a thin film transistor disposed at an intersection of the gate line and the data line;
a black matrix overlapping the gate line and the thin film transistor; and
A light blocking pattern disposed between the gate line and the black matrix and overlapping the gate line and the black matrix;
The black matrix covers the gate line, the common line, and the data line. According to claim 8,
An edge of the light blocking pattern coincides with an edge of the gate line. According to claim 8,
A corner of the light-shielding pattern is located outside the gate line. According to claim 8,
The width of the light blocking pattern covers at least one end of the gate line and is 3 μm or more in the direction of the semiconductor layer of the thin film transistor, and is less than or equal to a distance from one end of the black matrix to the semiconductor layer of the thin film transistor. . According to claim 1,
first and second insulating films sequentially disposed on the thin film transistor;
a common electrode disposed on the second insulating layer and connected to the common line;
a third insulating layer disposed on the common electrode;
Further comprising a pixel electrode disposed on the third insulating film and connected to the thin film transistor;
The common electrode under the third insulating film has an undercut in which one end of the third insulating film protrudes from one end of the common electrode;
The display device of claim 1 , wherein the pixel electrode does not contact the common electrode by the undercut. According to claim 5,
The width of the light-shielding pattern is greater than or equal to a distance from one end of the gate line to one end of the black matrix, and less than or equal to a distance from one end of the gate line to one end of the semiconductor layer of the thin film transistor.

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