KR102506159B1 - Display device - Google Patents

Abstract

A display device according to an exemplary embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, a plurality of thin film transistors each disposed on the plurality of sub-pixels and including an active layer, a gate electrode and a source electrode on the active layer, and a substrate. and a plurality of light blocking layers disposed between the plurality of thin film transistors and overlapping the plurality of thin film transistors, and a plurality of buffer layers disposed between the plurality of light blocking layers and the plurality of thin film transistors, wherein the entire lower surface of the plurality of buffer layers includes a plurality of in contact with the light-shielding layer of Accordingly, the light blocking layer, the buffer layer, and the active layer of the thin film transistor can be formed in one mask process, thereby reducing the number of mask processes and manufacturing cost.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of simplifying the structure of the display device, thereby simplifying the manufacturing process of the display device and reducing manufacturing costs.

Recently, as we entered the information age, the display field that visually expresses electrical information signals has developed rapidly. is being developed. Examples of such a display device include a liquid crystal display device (LCD) and an organic light emitting display device (OLED).

Such display devices include a substrate including a plurality of thin film transistors and display elements for driving. At this time, the display element may vary depending on the type of display device. For example, a liquid crystal display device includes a lower substrate on which various wires, thin film transistors and pixel electrodes are disposed, an upper substrate on which color filters and black matrices are disposed, and an upper substrate. and a liquid crystal layer disposed between the lower substrate. Also, the common electrode may be disposed on either the lower substrate or the upper substrate according to the driving method of the liquid crystal display.

In the manufacturing process of such a display device, a mask process for forming and patterning a conductive material, an insulating material, etc., is performed several times in order to form thin film transistors, pixel electrodes, wires, and the like on a substrate. At this time, when the number of masks used increases, there is a problem in that manufacturing cost and manufacturing time increase.

An object of the present invention is to provide a display device capable of reducing the number of mask processes and reducing manufacturing cost and time by forming a light blocking layer, a buffer layer, and an active layer of a thin film transistor in one mask process.

Another problem to be solved by the present invention is to provide a display device capable of reducing the number of mask processes and reducing manufacturing cost and time by forming a common electrode and an overcoat layer in one mask process.

Another problem to be solved by the present invention is to integrally form a plurality of light blocking layers disposed below the thin film transistors of each of a plurality of sub-pixels, thereby minimizing the parasitic capacitance of the light blocking layers and minimizing the change in characteristics of the thin film transistors. It is to provide a display device with

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an exemplary embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, a plurality of sub-pixels, and an active layer, a gate electrode and a source electrode on the active layer. A plurality of thin film transistors including a plurality of light blocking layers disposed between the substrate and the plurality of thin film transistors, overlapping the plurality of thin film transistors, and a plurality of buffer layers disposed between the plurality of light blocking layers and the plurality of thin film transistors; , Whole lower surfaces of the plurality of buffer layers are in contact with the plurality of light-shielding layers. Therefore, since the plurality of buffer layers are disposed only on the plurality of light blocking layers, when etching the plurality of light blocking layers, the plurality of buffer layers and even the active layer can be etched together, thereby reducing manufacturing cost and time.

A display device according to another embodiment of the present invention includes a plurality of thin film transistors disposed on a substrate and including an active layer, a gate electrode and a source electrode on the active layer, a light blocking wire disposed between the substrate and the plurality of thin film transistors, A buffer layer disposed between the light blocking wiring and the plurality of thin film transistors and a plurality of gate wirings electrically connected to gate electrodes of the plurality of thin film transistors and extending in a first direction, wherein the light blocking wiring extends in the first direction. Therefore, since only one light-blocking wire is disposed in a plurality of sub-pixels, parasitic capacitance of the light-shielding wire can be minimized and a change in characteristics of the thin film transistor can be minimized.

Other embodiment specifics are included in the detailed description and drawings.

Since the light blocking layer, the buffer layer, and the active layer of the thin film transistor are formed in one mask process, the number of mask processes and manufacturing cost can be reduced.

Since the common electrode and the overcoating layer are formed in one mask process, the number of mask processes can be reduced and the manufacturing process can be simplified.

Since the present invention minimizes the parasitic capacitance of the light blocking layer and minimizes the change in characteristics of the thin film transistor, image quality can be improved.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is an enlarged view of area A of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line III-III' of FIG. 2 .
4A to 4J are schematic process diagrams for explaining a method of manufacturing a display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention.
6 is a plan view of a display device according to another exemplary embodiment of the present invention.
FIG. 7 is a cross-sectional view taken along line VII-VII' of FIG. 6 .

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the illustrated details. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists', etc. mentioned in the present invention is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

In addition, although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, the present invention will be described with reference to the drawings.

1 is a plan view of a display device according to an exemplary embodiment of the present invention. In FIG. 1 , only the substrate 110 and the plurality of sub-pixels SP among various components of the display device 100 are illustrated for convenience of description.

The substrate 110 is configured to support various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of a plastic material such as glass or polyimide.

The substrate 110 includes a display area AA and a non-display area NA.

The display area AA is an area where a plurality of sub-pixels SP are disposed to display an image. A sub-pixel SP including a light emitting area for displaying an image and a circuit for driving the sub-pixel SP may be disposed in the display area AA.

The non-display area NA is an area in which an image is not displayed, and is an area in which various wires, driving circuits, etc. for driving the sub-pixels SP and driving circuits disposed in the display area AA are disposed. Various ICs such as gate driver ICs and data driver ICs may be disposed in the non-display area NA.

A plurality of sub-pixels SP are disposed on the substrate 110 . The plurality of sub-pixels SP is a minimum unit constituting the display area AA, and each of the plurality of sub-pixels SP includes a light emitting area. In this case, a display element for emitting light in a light emitting area may be disposed in each of the plurality of sub pixels SP. The display element may be defined differently depending on the type of the display device 100, and may be, for example, a liquid crystal display element or an organic light emitting element, but is not limited thereto. Hereinafter, the display device 100 according to an exemplary embodiment of the present invention will be described assuming that it is a liquid crystal display device.

Hereinafter, the sub-pixel SP of the display device 100 will be described in detail with reference to FIGS. 2 and 3 .

FIG. 2 is an enlarged view of area A of FIG. 1 . FIG. 3 is a cross-sectional view taken along line III-III' of FIG. 2 . 2 and 3 , the display device 100 according to an exemplary embodiment of the present invention includes a substrate 110, a light blocking layer 111, a buffer layer 112, a gate insulating layer 113, an interlayer insulating layer ( 114), first passivation layer 115, second passivation layer 117, overcoating layer 116, gate line GL, data line DL, thin film transistor 120, common electrode 131, auxiliary A common electrode 132 and a pixel electrode 140 are included. However, in FIG. 2 , for convenience of description, illustration of the common electrode 131 is omitted, and only the common electrode opening 131OP is shown.

A light blocking layer 111 is disposed on the substrate 110 . The light blocking layer 111 may block light incident from a lower portion of the thin film transistor 120 to the active layer 121 of the thin film transistor 120 . When light is irradiated to the active layer 121 of the thin film transistor 120 , leakage current may occur and reliability of the thin film transistor 120 may be reduced. Accordingly, the light blocking layer 111 may be disposed under the active layer 121 of the thin film transistor 120 to block light incident on the thin film transistor 120 to minimize leakage current.

Meanwhile, the light blocking layer 111 may be made of an opaque conductive material. The light blocking layer 111 may be made of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but Not limited.

A buffer layer 112 is disposed on the light blocking layer 111 . The buffer layer 112 may minimize penetration of moisture or impurities from the substrate 110 . The buffer layer 112 may include, for example, a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A thin film transistor 120 is disposed on the buffer layer 112 . The thin film transistor 120 may be used as a driving element of the display device 100 . The thin film transistor 120 includes an active layer 121 , a gate electrode 122 , a source electrode 123 and a drain electrode 124 . In the display device 100 according to an exemplary embodiment of the present invention, the thin film transistor 120 includes an active layer 121, a gate electrode 122 on the active layer 121, and a source electrode 123 on the gate electrode 122. ) and the drain electrode 124 are disposed, and the gate electrode 122 is the thin film transistor 120 having a top gate structure disposed on the active layer 121 .

The active layer 121 includes a channel region 121C, a source region 121S, and a drain region 121D. The channel region 121C is a region overlapping the gate electrode 122, and when a voltage is applied to the gate electrode 122, a channel is formed to electrically connect the source region 121S and the drain region 121D. . The source region 121S and the drain region 121D are regions electrically connected to the source electrode 123 and the drain electrode 124, respectively.

The active layer 121 may be made of an oxide semiconductor. In this case, the source region 121S and the drain region 121D may be regions in which an oxide semiconductor is a conductor. However, it is not limited thereto, and the active layer 121 may be formed of, for example, amorphous silicon, polycrystalline silicon, or an organic semiconductor.

Meanwhile, the area of the upper surface of the buffer layer 112 may be greater than or equal to the area of the lower surface of the active layer 121 . If the area of the lower surface of the active layer 121 is greater than the area of the upper surface of the buffer layer 112, the active layer 121 extends to the outside of the buffer layer 112 to form a barrier between the side surface of the light blocking layer 111 and the substrate 110. It may touch the upper surface. Accordingly, it is difficult to properly block light incident on the active layer 121 , which may lead to a reliability problem of the thin film transistor 120 . Accordingly, the entire lower surface of the active layer 121 may be disposed to contact only the upper surface of the buffer layer 112 .

Also, the area of the upper surface of the light blocking layer 111 may be greater than or equal to the area of the lower surface of the buffer layer 112 . If the area of the upper surface of the light blocking layer 111 is smaller than the area of the lower surface of the buffer layer 112, the light blocking layer 111 may not overlap the entire active layer 121 disposed on the buffer layer 112. Accordingly, the light blocking layer 111 cannot properly block light incident on the active layer 121 , and leakage current of the thin film transistor 120 may increase. Accordingly, the area of the upper surface of the light blocking layer 111 may be greater than or equal to the area of the lower surface of the buffer layer 112 .

Meanwhile, a gate insulating layer 113 is disposed on the active layer 121 . The gate insulating layer 113 is a layer for insulating the gate electrode 122 and the active layer 121 and may be made of an insulating material. The gate insulating layer 113 may be formed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

The gate electrode 122 is disposed to overlap the channel region 121C of the active layer 121 on the active layer 121 and the gate insulating layer 113 . The gate electrode 122 may be made of a conductive material. The gate electrode 122 may be made of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but Not limited.

The gate line GL transfers the gate voltage to the sub-pixel SP. Specifically, the gate line GL transfers the gate voltage to the gate electrode 122 of the thin film transistor 120 of the sub-pixel SP. And the gate electrode 122 extends from the gate line GL. The gate electrode 122 and the gate line GL may be made of the same conductive material. The gate line GL may be formed of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. Not limited.

An interlayer insulating layer 114 is disposed on the gate electrode 122 . The interlayer insulating layer 114 is a layer for insulating the gate electrode 122, the source electrode 123, and the drain electrode 124, and may be made of an insulating material. The interlayer insulating layer 114 may be formed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode 123 and a drain electrode 124 are disposed on the interlayer insulating layer 114 . The source electrode 123 is electrically connected to the source region 121S of the active layer 121 through a contact hole formed in the interlayer insulating layer 114 . The drain electrode 124 is electrically connected to the drain region 121D of the active layer 121 through a contact hole formed in the interlayer insulating layer 114 . The source electrode 123 and the drain electrode 124 may be made of a conductive material. The source electrode 123 and the drain electrode 124 may be formed of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

The data line DL transfers the data voltage to the sub-pixel SP. Specifically, the data line DL transfers the data voltage to the source electrode 123 of the thin film transistor 120 of the sub-pixel SP. Also, the source electrode 123 is electrically connected to the data line DL. The source electrode 123 and the data line DL may be made of the same conductive material. The data line DL may be made of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. Not limited.

A first passivation layer 115 is disposed on the thin film transistor 120 . The first passivation layer 115 is an insulating layer for protecting a structure under the first passivation layer 115 . The first passivation layer 115 may be made of the same material as the gate insulating layer 113 . The first passivation layer 115 may include, for example, a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

An overcoat layer 116 is disposed on the first passivation layer 115 . The overcoating layer 116 flattens the top of the substrate 110 . The overcoating layer 116 may be formed to have a contact hole exposing the source electrode 123 or the drain electrode 124 . The overcoating layer 116 may be made of an organic material that has a low dielectric constant and can be dry etched.

In this case, the overcoating layer 116 may be made of an organic material that does not include a photosensitive material among organic materials. If the overcoating layer 116 is made of an organic material including a photosensitive material, a contact hole must be formed in the overcoating layer 116 through a separate mask process, and thus the manufacturing process may increase. Thus, the overcoating layer 116 may be made of an organic material that does not contain a photosensitive material. The overcoating layer 116 may include, for example, polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated It may be composed of at least one of unsaturated polyesters resin, poly-phenylenethers resin, poly-phenylenesulfides resin, and benzocyclobutene. , but not limited thereto.

A common electrode 131 is disposed on the overcoating layer 116 . The common electrode 131 is disposed on the entire surface of the plurality of sub-pixels SP of the substrate 110 and includes a common electrode opening 131OP. Accordingly, the common electrode 131 is disposed in an area excluding the area where the common electrode opening 131OP is disposed in the display area AA. In FIG. 2 , for convenience of description, hatching of the common electrode 131 is omitted and only the common electrode opening 131OP is shown.

The common electrode opening 131OP is an area in which the common electrode 131 is opened in an area where the pixel electrode 140 and the drain electrode 124 contact each other. The common electrode 131 may be made of a transparent conductive material. The common electrode 131 may be formed of, for example, tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITO). ; ITZO), etc., but is not limited thereto.

An auxiliary common electrode 132 is disposed on the common electrode 131 . The auxiliary common electrode 132 may be made of a metal material to reduce sheet resistance of the common electrode 131 . Specifically, when the common electrode 131 is formed of a material having a higher resistivity than metal, such as indium tin oxide (ITO) or indium zinc oxide (IZO), the auxiliary common electrode made of a metal material. By disposing 132, sheet resistance of the common electrode 131 can be reduced. The auxiliary common electrode 132 may be made of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. Not limited to this.

Meanwhile, the auxiliary common electrode 132 may be disposed to overlap the data line DL. In detail, since the auxiliary common electrode 132 is made of an opaque conductive material, an aperture ratio may decrease depending on the arrangement of the auxiliary common electrode 132 . However, by disposing the auxiliary common electrode 132 so as to overlap the data line DL, a decrease in aperture ratio due to the arrangement of the auxiliary common electrode 132 may be minimized.

A second passivation layer 117 is disposed on the common electrode 131 and the auxiliary common electrode 132 . The second passivation layer 117 is an insulating layer for protecting a structure under the second passivation layer 117 . The second passivation layer 117 may be made of the same material as the gate insulating layer 113 . The second passivation layer 117 may include, for example, a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A pixel electrode 140 is disposed on the second passivation layer 117 . The pixel electrode 140 is electrically connected to the drain electrode 124 of the thin film transistor 120 . However, depending on the type of the thin film transistor 120, the pixel electrode 140 may be electrically connected to the source electrode 123 of the thin film transistor 120, but is not limited thereto.

The pixel electrode 140 may be made of a transparent conductive material. The pixel electrode 140 may be, for example, tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITO). ; ITZO), etc., but is not limited thereto.

A portion of the pixel electrode 140 may be spaced apart from each other in an area overlapping the common electrode 131 . For example, one portion of the pixel electrode 140 may have a shape in which a plurality of line segments are spaced apart from each other. The pixel electrode 140 overlaps the common electrode 131 with the second passivation layer 117 therebetween. The pixel electrode 140 and the common electrode 131 form an electric field, and the light transmittance may be adjusted by rotating liquid crystal molecules using the electric field.

In the display device 100 according to an exemplary embodiment of the present invention, the light blocking layer 111 , the buffer layer 112 , and the active layer 121 may be formed through a single mask process. Specifically, the upper surface of the light blocking layer 111 and the lower surface of the buffer layer 112 have the same area, and the entire lower surface of the buffer layer 112 may come into contact with the upper surface of the light blocking layer 111 . In addition, the active layer 121 is disposed on the buffer layer 112 , and the entire lower surface of the active layer 121 may be in contact with the upper surface of the buffer layer 112 . If the buffer layer 112 is disposed on the entire upper surface of the substrate 110 including the light blocking layer 111, the light blocking layer 111 and the active layer 121 on the buffer layer 112 must be formed by different mask processes. Therefore, the number of mask processes can be increased. However, since the buffer layer 112 is disposed only on the upper surface of the light blocking layer 111 in the display device 100 according to an exemplary embodiment of the present invention, the light blocking layer 111 must be formed first and then the active layer 121 must be formed. The light blocking layer 111, the buffer layer 112, and the active layer 121 may be formed in one mask process without need. However, even if the buffer layer 112 is not disposed on the entire upper surface of the substrate 110, on the upper surface of the substrate 110 on which the buffer layer 112 is not disposed, an interlayer insulating layer (which may be made of the same material as the buffer layer 112) 114) is disposed instead, so that penetration of impurities or the like from the substrate 110 can be minimized. Accordingly, the light blocking layer 111, the buffer layer 112, and the active layer 121 may be formed in one mask process, thereby reducing the number of mask processes and manufacturing cost.

Meanwhile, in the display device 100 according to an exemplary embodiment of the present invention, contact holes of the auxiliary common electrode 132 , the common electrode 131 , and the overcoating layer 116 may be formed through one mask process. Specifically, the entire lower surface of the common electrode 131 may contact only the upper surface of the overcoating layer 116 , and the entire lower surface of the auxiliary common electrode 132 may contact only the upper surface of the common electrode 131 . At this time, a contact hole exposing the drain electrode 124 of the thin film transistor 120 is disposed in the overcoating layer 116 disposed below the common electrode 131 . If the overcoating layer 116 is made of a photosensitive organic material, such as photosensitive photo acryl or photosensitive polyimide, the overcoating layer 116 itself is exposed and developed without photoresist through a separate mask process to contact hole can be formed. Therefore, it is necessary to first form a contact hole in the overcoating layer 116 through one mask process, and then form the common electrode 131 and the auxiliary common electrode 132 on the overcoating layer 116 in which the contact hole is formed through another mask process. Therefore, the number of mask processes can be increased. However, in the display device 100 according to an embodiment of the present invention, since the overcoating layer 116 is made of an organic material that does not contain a photosensitive material, contact holes can be formed in the overcoating layer 116 using a photoresist pattern. there is. Therefore, since contact holes may be formed in the overcoating layer 116 using a photoresist pattern for etching the common electrode 131 and the auxiliary common electrode 132, the overcoating layer 116, the common electrode 131 and By forming the auxiliary common electrode 132 through one mask process, the number of mask processes and manufacturing cost can be reduced.

Hereinafter, a manufacturing method of the display device 100 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4A to 4J .

4A to 4J are schematic process diagrams for explaining a method of manufacturing a display device according to an exemplary embodiment of the present invention. Specifically, FIGS. 4A to 4J are schematic process diagrams for explaining a manufacturing method of the display device 100 of FIGS. 1 to 3 .

Referring to FIGS. 4A to 4E , a light blocking layer 111 , a buffer layer 112 , and an active layer 121 are formed through a first mask process.

Referring to FIG. 4A, a light blocking layer material 111m, a buffer layer material 112m, and an active layer material 121m are sequentially formed on a substrate 110, and the active layer material 121m, the buffer layer material 112m, and A first photoresist pattern PR1 for etching the light blocking layer material 111m is formed.

The first photoresist pattern PR1 may be formed to have a level difference by applying a photoresist on the active layer material 121m and then exposing and developing the photolithography process using a mask.

The first photoresist pattern PR1 may be formed differently according to the type of photoresist. Specifically, in the positive photoresist, the photoresist remains in an area where light is blocked by the mask, and the photoresist can be removed in an area where light is transmitted. Conversely, in the negative photoresist, the photoresist may be removed from a region where light is blocked by the mask, and the photoresist may remain in a region through which light is transmitted. In the method of manufacturing the display device 100 according to an exemplary embodiment, the photoresist may be a positive photoresist or a negative photoresist, but is not limited thereto.

Subsequently, referring to FIG. 4B , the active layer material 121m and the buffer layer material 112m may be etched collectively. Specifically, only the active layer material 121m and the buffer layer material 112m overlapping the first photoresist pattern PR1 are left, and the active layer material 121m and the buffer layer material do not overlap the first photoresist pattern PR1. (112m) may be etched to form the active layer 121 and the buffer layer 112.

At this time, the etching process may be divided into wet etching and dry etching. Wet etching is a chemical etching method using chemicals, and the etching speed is fast, and dry etching is an etching method using a reactive gas or gas. For example, the conductive layer used for the gate electrode 122, the source electrode 123, and the drain electrode 124 of the thin film transistor 120 can be patterned mainly using wet etching, and the insulating layer, the protective layer and An inorganic layer such as the active layer 121 may be patterned mainly through dry etching, but is not limited thereto.

Meanwhile, the active layer material 121m and the buffer layer material 112m may be dry etched using equipment such as RIE (Reactive Ion Etching) or ICP (Inductive Couple Plasma) using plasma. In addition, wet etching may be simultaneously performed using an inorganic acid-based solution such as BOE (Buffered Oxide Etchant), HF, and H ₂ SO ₄ . Accordingly, the active layer material 121m and the buffer layer material 112m may be etched collectively, or may be dry-etched or wet-etched, but is not limited thereto.

However, when the active layer material 121m and the buffer layer material 112m are simultaneously etched by a wet etching method with a solution such as BOE, the etching rate for the active layer material 121m is higher than the etching rate for the buffer layer material 112m. It can be fast. Accordingly, even if the active layer material 121m and the buffer layer material 112m are etched to the same size, the active layer material 121m is not overetched more than the first photoresist pattern PR1 or the buffer layer material 112m is not partially etched. may not be Therefore, even if the active layer material 121m and the buffer layer material 112m are simultaneously etched, the width of the active layer 121 and the width of the buffer layer 112 may not be the same.

Then, as the active layer material 121m and the buffer layer material 112m are etched, the exposed light blocking layer material 111m may be etched to form the light blocking layer 111 . Specifically, the light blocking layer 111 is formed by leaving only the light blocking layer material 111m overlapping the first photoresist pattern PR1 and etching the light blocking layer material 111m that does not overlap the first photoresist pattern PR1. can form

The light blocking layer material 111m made of a conductive material may be etched using a wet etching method. Since wet etching has a high etching rate, the light blocking layer material 111m may be over-etched more than the first photoresist pattern PR1. Therefore, the widths of the buffer layer 112 and the light blocking layer 111 may not be the same, and the width of the buffer layer 112 may be slightly larger.

Subsequently, referring to FIG. 4C , the first photoresist pattern PR1 may be ashed, and an end of the buffer layer 112 protruding outward of the light blocking layer 111 may be etched. In addition, the active layer 121 may be etched in a smaller size using the second photoresist pattern PR2 reduced by ashing.

Specifically, as described in FIG. 4B, the active layer material 121m, the buffer layer material 112m, and the light blocking layer material 111m are etched by the same first photoresist pattern PR1, and the etching ratio of each material In some cases, over-etching may occur, but the sizes of the active layer 121, the buffer layer 112, and the light-blocking layer 111 do not differ greatly. Therefore, the area of the lower surface of the active layer 121 and the area of the upper surface of the light blocking layer 111 are not significantly different. Accordingly, only the active layer 121 may be etched again so that the active layer 121 may have a smaller area than the light blocking layer 111 so that light blocking by the active layer 121 and the light blocking layer 111 is effectively performed. there is.

First, a second photoresist pattern PR2 that is smaller than the first photoresist pattern PR1 may be formed by ashing the first photoresist pattern PR1 using a dry etching method.

When the first photoresist pattern PR1 is ashed, a part of the buffer layer 112 that can be etched by dry etching may also be etched. Specifically, the ends of the buffer layer 112 protruding outward from the light blocking layer 111 may be etched together so that the side surfaces of the light blocking layer 111 and the buffer layer 112 are disposed on the same plane.

Subsequently, after the formation of the second photoresist pattern PR2 and the etching of the ends of the buffer layer 112 are completed, a portion of the active layer 121 that does not overlap the second photoresist pattern PR2 is etched to form the active layer 121. ) can be reduced.

Finally, after the active layer 121 is completely etched, the second photoresist pattern PR2 remaining on the active layer 121 may be removed through a strip process.

Accordingly, the light blocking layer 111 , the buffer layer 112 , and the active layer 121 may be formed through the first mask process. In addition, a halftone mask may be used to form the upper surface of the light blocking layer 111 and the lower surface of the buffer layer 112 to have the same area, and the area of the upper surface of the buffer layer 112 to be larger than the area of the lower surface of the active layer 121 . However, the light blocking layer 111 may be formed to be larger than the buffer layer 112 according to the design of the first photoresist pattern PR1 without being limited to those shown in FIGS. 4A to 4C, and the active layer 121 And the buffer layer 112 may be formed in the same size.

Referring to FIG. 4D , a gate insulating layer 113 and a gate electrode 122 are formed through a second mask process.

Referring to FIG. 4D , a gate insulating layer 113 and a gate electrode 122 may be sequentially formed on the active layer 121 . Specifically, a gate insulating material and a gate electrode 122 material are sequentially formed on the active layer 121 .

At this time, a conductorization process of the active layer 121 may be performed. Specifically, the active layer 121 overlapping the gate insulating layer 113 and the gate electrode 122 may serve as a channel region 121C maintaining a semiconductor state, and the active layer not overlapping the gate electrode 122. ( 121 ) The source region 121S and the drain region 121D of the active layer 121 may be formed by performing a conductorization process on partial regions on both sides.

Referring to FIG. 4E , an interlayer insulating layer 114 is formed through a third mask process, and a source electrode 123 and a drain electrode 124 are formed through a fourth mask process.

Referring to FIG. 4E , an interlayer insulating layer 114 is formed on the entire surface of the substrate 110 . Specifically, the interlayer insulating layer 114 is formed on a portion of the substrate 110 where the light blocking layer 111 is not formed, the source region 121S and drain region 121D of the active layer 121, and the gate electrode 122. is formed to cover

Then, a contact hole may be formed in the interlayer insulating layer 114 through a third mask process to open the source region 121S and the drain region 121D of the active layer 121 .

Next, a conductive material constituting the source electrode 123 and the drain electrode 124 is formed on the interlayer insulating layer 114, and the conductive material is formed to fill the contact hole formed in the interlayer insulating layer 114 to form an active layer. It may contact the source region 121S and the drain region 121D of (121). In addition, the source electrode 123 and the drain electrode 124 may be formed by etching the conductive material through a fourth mask process.

Accordingly, the light blocking layer 111 and the thin film transistor 120 may be formed on the substrate 110 by performing the first through fourth mask processes.

Referring to FIGS. 4F to 4I , a contact hole of the overcoating layer 116, a common electrode 131, and an auxiliary common electrode 132 are formed through a fifth mask process.

First, referring to FIG. 4F, a first passivation layer 115, an overcoat layer material 116m, a common electrode material 131m, and an auxiliary common electrode material 132m are sequentially formed on the thin film transistor 120, and 3 Photoresist pattern PR3 is formed.

Referring to FIG. 4G , the common electrode 131 and the common electrode opening 131OP may be formed by etching the auxiliary common electrode material 132m and the common electrode material 131m at once. Specifically, the auxiliary common electrode material 132m that does not overlap the third photoresist pattern PR3 while leaving only the auxiliary common electrode material 132m overlapping the third photoresist pattern PR3 and the common electrode material 131m. In addition, the common electrode 131 and the common electrode opening 131OP may be formed by etching the common electrode material 131m.

In this case, the auxiliary common electrode material 132m and the common electrode 131 made of a conductive material may be etched using a wet etching method.

Referring to FIG. 4H , while ashing the third photoresist pattern PR3, the overcoating layer material 116m is etched in an area overlapping the drain electrode 124 of the thin film transistor 120 to form an overcoating layer in which a contact hole is formed. (116) can be formed.

Specifically, the third photoresist pattern PR3 may be reduced to a size for forming the auxiliary common electrode 132 . A fourth photoresist pattern PR4 reduced to a size for forming the auxiliary common electrode 132 may be formed by ashing the third photoresist pattern PR3 using a dry etching method.

At this time, the overcoating layer material 116m, which can be etched by dry etching, can also be etched at the same time. Specifically, the third photoresist pattern PR3 does not overlap, and the overcoating layer material 116m exposed by the common electrode opening 131OP is etched to overlap the drain electrode 124 of the thin film transistor 120. A contact hole may be formed in the region.

However, the overcoating layer material 116m may be over-etched compared to the common electrode opening 131OP. Accordingly, the diameter of the common electrode opening 131OP may be smaller than that of the contact hole formed in the overcoating layer 116 .

Next, referring to FIG. 4I , an auxiliary common electrode 132 may be formed, and an end of the common electrode 131 protruding beyond the contact hole of the overcoating layer 116 may be etched.

Specifically, by leaving only the auxiliary common electrode material 132m overlapping the fourth photoresist pattern PR4 and etching the auxiliary common electrode material 132m that does not overlap the fourth photoresist pattern PR4, the auxiliary common electrode ( 132) can be formed.

At this time, the end of the common electrode 131 protruding to the inside of the contact hole formed in the overcoating layer 116 is also etched, so that the side surface of the common electrode 131 and the side surface of the overcoating layer 116 are disposed on the same plane. It can be. That is, the common electrode opening 131OP and the contact hole of the overcoating layer 116 may have the same diameter. Therefore, the common electrode opening 131OP can be expanded while forming the contact holes of the common electrode 131, the auxiliary common electrode 132, and the overcoating layer 116, and the common electrode opening 131OP has an initial diameter and The diameter after the process is complete may be different.

Accordingly, the common electrode 131 , the auxiliary common electrode 132 , and the overcoating layer 116 may be formed through the fifth mask process. In this case, since contact holes of the same size are formed in the common electrode 131 and the overcoating layer 116 and only the auxiliary common electrode 132 is etched in different sizes, a halftone mask can be used in the fifth mask process. However, when the auxiliary common electrode 132 is omitted and only the common electrode 131 is disposed, the halftone mask may not be used.

Subsequently, the second passivation layer 117 is formed through a sixth mask process, and the pixel electrode 140 is formed through a seventh mask process.

Referring to FIG. 4J , a second passivation layer 117 is formed on the entire surface of the substrate 110 . In this case, the first passivation layer 115 and the second passivation layer 117 may come into contact with each other in the contact hole formed in the common electrode opening 131OP and the overcoating layer 116 .

Then, the first passivation layer 115 and the second passivation layer 117 are etched in the common electrode opening 131OP and the contact hole of the overcoating layer 116, so that the first passivation layer 115 and the second passivation layer ( 117, a contact hole may be formed, and the drain electrode 124 of the thin film transistor 120 may be exposed.

Therefore, contact holes are formed in all of the first passivation layer 115, the overcoating layer 116, the common electrode 131, and the second passivation layer 117 formed on the drain electrode 124 of the thin film transistor 120. The drain electrode 124 of the thin film transistor 120 may be exposed.

Next, after a contact hole exposing the drain electrode 124 of the thin film transistor 120 is formed, a material for the pixel electrode 140 is formed on the substrate 110 . The material of the pixel electrode 140 is in contact with the drain electrode 124 of the thin film transistor 120 within the common electrode opening 131OP and the contact hole of the overcoating layer 116, and is in contact with the second passivation layer 117 in other areas. can be encountered

In addition, the pixel electrode 140 may be formed by etching the material of the pixel electrode 140 through a seventh mask process. The pixel electrode 140 is electrically connected to the drain electrode 124 of the thin film transistor 120 and overlaps the common electrode 131 . However, the pixel electrode 140 may be insulated from the common electrode 131 through the second passivation layer 117 .

In the display device 100 and the manufacturing method of the display device 100 according to an exemplary embodiment of the present invention, the active layer 121, the buffer layer 112, and the light blocking layer 111 of the thin film transistor 120 are formed in one mask process. By forming it, the process can be simplified. Specifically, a light blocking layer material 111m, a buffer layer material 112m, and an active layer material 121m are sequentially formed on the substrate 110 . Subsequently, a first photoresist pattern PR1 having a step is formed on the active layer material 121m, and a light blocking layer material 111m and a buffer layer material 112m that do not overlap the first photoresist pattern PR1 are formed. The light blocking layer 111 and the buffer layer 112 may be formed by etching the active layer material 121m. Then, the first photoresist pattern PR1 is ashed to form a reduced second photoresist pattern PR2, and the active layer 121 is etched once more along the second photoresist pattern PR2 to form the active layer. (121) The area of the lower surface may be smaller than the area of the upper surface of the light blocking layer 111. Therefore, the active layer 121, the buffer layer 112, and the light blocking layer 111 may be formed through one mask process.

Also, in the display device 100 and the manufacturing method of the display device 100 according to an exemplary embodiment of the present invention, the contact hole of the auxiliary common electrode 132, the common electrode 131, and the overcoating layer 116 is used as a mask. By forming it in a process, the process can be simplified. Specifically, the overcoating layer 116 , the common electrode material 131m and the auxiliary common electrode material 132m are formed on the thin film transistor 120 . Then, a third photoresist pattern PR3 having a step difference is formed on the auxiliary common electrode material 132m, and the auxiliary common electrode material 132m and the common electrode material (not overlapping the third photoresist pattern PR3) 131m) may be etched to form the common electrode opening 131OP. Subsequently, the third photoresist pattern PR3 may be ashed to form a reduced fourth photoresist pattern PR4 and at the same time a contact hole may be formed in the overcoating layer 116 . Subsequently, the auxiliary common electrode material 132m may be etched once more along the fourth photoresist pattern PR4 to form the auxiliary common electrode 132 . Accordingly, the contact hole of the overcoating layer 116, the common electrode 131, and the auxiliary common electrode 132 may be formed through one mask process. Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the active layer 121, the buffer layer 112, and the light blocking layer 111 are formed through one mask process, and the overcoating layer 116 and the common electrode ( 131) and the auxiliary common electrode 132 can be formed in one mask process, thereby reducing the number of mask processes and manufacturing cost.

5 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention. Since the display device 500 of FIG. 5 is different from the display device 100 of FIGS. 1 to 3 only in the thin film transistor 520 and substantially the same in other configurations, redundant description will be omitted.

Referring to FIG. 5 , the pixel electrode 140 may be directly connected to the drain region 121D of the active layer 121 without being electrically connected to the drain electrode 124 of the thin film transistor 520 . That is, the thin film transistor 520 includes only the active layer 121, the gate electrode 122 and the source electrode 123, and the data voltage applied from the data line DL is applied to the source electrode 123 of the thin film transistor 520. ) and the active layer 121, and can be transferred directly to the pixel electrode 140.

In the display device 500 according to another exemplary embodiment of the present invention, the drain electrode 124 may not be disposed on the thin film transistor 520, and the pixel electrode 140 may directly contact the active layer 121. Specifically, the data voltage from the data line DL may be transferred to the pixel electrode 140 through the source electrode 123 , the active layer 121 , and the drain electrode 124 of the thin film transistor 520 . Therefore, in the display device 500 according to another embodiment of the present invention, the drain electrode 124 is removed, and the pixel electrode 140 is disposed to contact the active layer 121 instead, thereby simplifying the structure. There is an effect that the aperture ratio can be improved.

6 is a plan view of a display device according to another exemplary embodiment of the present invention. FIG. 7 is a cross-sectional view taken along line VII-VII' of FIG. 6 . Since the display device 600 of FIGS. 6 and 7 is different from the display device 500 of FIG. 5 only in the light blocking layer 611 and substantially the same in other configurations, redundant description will be omitted.

Referring to FIG. 6 , a plurality of light blocking layers 611 disposed between the substrate 110 and the plurality of thin film transistors 520 may be integrally formed. Therefore, the light blocking layer 611 disposed under the thin film transistor 520 of one sub-pixel SP and the light blocking layer 611 disposed under the thin film transistor 520 of the adjacent sub-pixel SP are mutually related to each other. It may be the same light blocking layer 611 . In this case, the light blocking layer 611 may be formed in the shape of a wire and may also be referred to as a light blocking wire. However, although the light blocking layer 611 is formed in the shape of a wire, a separate voltage may not be applied and may be floating.

Meanwhile, the display device 600 according to another embodiment of the present invention may use an inversion driving method to minimize deterioration of liquid crystal and improve image quality. The inversion driving method is a method of driving by inverting the polarity of a voltage applied to each pixel electrode 140 , that is, a data voltage for each frame.

The inversion driving method includes a column inversion method, a dot inversion method, and the like. In the column inversion method, the polarity of data voltages applied to the pixel electrodes 140 of one column line is the same, and the polarity of the data voltages applied to the pixel electrodes 140 of another column line adjacent to one column line is way to reverse it. In the dot inversion method, the polarity of the data voltage applied to each pixel electrode 140 is reversed even within one column line, and the data voltage applied to the pixel electrode 140 of another column line adjacent to one column line is reversed. The polarity is also reversed. That is, in the dot inversion method, a plurality of pixels to which data voltages of the same polarity are applied may form a mosaic pattern.

Therefore, polarities of data voltages applied to pixel electrodes 140 adjacent to each other in a row direction or a column direction of the display device 600 according to another exemplary embodiment of the present invention may be different. For example, among the plurality of sub-pixels SP, a first sub-pixel SP1 and a second sub-pixel SP2 may be adjacent to each other in a row direction or a column direction, and the first sub-pixel SP1 may be adjacent to each other during one frame. The polarities of the data voltages applied to and the second sub-pixel SP2 may be different. During the next frame, polarities of data voltages applied to the first sub-pixel SP1 and the second sub-pixel SP2 may be reversed.

Meanwhile, the light blocking layer 611 disposed in the plurality of sub-pixels SP is floated without a separate voltage applied thereto. Therefore, a coupling electric field may be generated in the light blocking layer 611 by the data voltage applied to the pixel electrode 140 via the data line DL and the thin film transistor 520 . Accordingly, a coupling electric field due to a configuration different from that of the floating light blocking layer 611 may occur, resulting in parasitic capacitance, resulting in poor crosstalk and deterioration in image quality.

In this case, data voltages of different polarities may be applied to second sub-pixels SP2 adjacent to the first sub-pixel SP1 , and the light blocking layer 611 of the first sub-pixel SP1 and the second sub-pixel SP2 may be applied. Coupling electric fields of different polarities may also be formed in the light blocking layer 611 of (SP2). Accordingly, the light blocking layer 611 of the first sub-pixel SP1 and the light blocking layer 611 of the second sub-pixel SP2 may have different polarities.

Therefore, in the display device 600 according to another exemplary embodiment of the present invention, light blocking layers 611 having different polarities are integrally formed in adjacent sub-pixels SP, so that the light blocking layer 611 has a different configuration. It is possible to minimize parasitic capacitance due to the coupling electric field between the terminals. For example, among the plurality of sub-pixels SP, data voltages of different polarities may be applied to first and second sub-pixels SP1 and SP2 adjacent in a row direction or a column direction. In addition, a coupling electric field may be generated by a data voltage or the like in each of the light-blocking layer 611 of the first sub-pixel SP1 and the light-blocking layer 611 of the second sub-pixel SP2 to generate parasitic capacitance. In this case, coupling electric fields of different polarities may be generated between the light blocking layer 611 of the first sub-pixel SP1 and the light blocking layer 611 of the second sub-pixel SP2 due to data voltages of different polarities. The light blocking layer 611 of the first sub-pixel SP1 and the light blocking layer 611 of the second sub-pixel SP2 may have different polarities. Therefore, when the light blocking layer 611 of the first sub-pixel SP1 and the light blocking layer 611 of the second sub-pixel SP2 are integrally formed, the coupling electric field in each light blocking layer 611 cancels out. It can be. For example, when the light blocking layer 611 of the first sub-pixel SP1 has a positive polarity and the light blocking layer 611 of the second sub-pixel SP2 has a negative polarity, the two light blocking layers 611 ) integrally formed, the electric field of each light blocking layer 611 can be canceled, and parasitic capacitance can also be minimized.

Accordingly, in the display device 600 according to another embodiment of the present invention, one light blocking layer 611 may be disposed in a plurality of sub-pixels SP to which data voltages of different polarities are applied. Even if a separate voltage is not applied to the light blocking layer 611, the light blocking layers 611 of the plurality of sub-pixels (SP) to which data voltages of different polarities are applied are respectively connected, and the light blocking layer 611 and the data voltage It is possible to cancel coupling electric fields of different polarities generated by the like. In addition, as the electric field of the light blocking layer 611 is minimized, parasitic capacitance may also be reduced, defects such as crosstalk may be reduced, and image quality of the display device 600 may be improved.

A display device according to various embodiments of the present disclosure can be described as follows.

A display device according to an exemplary embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, a plurality of thin film transistors each disposed on the plurality of sub-pixels and including an active layer, a gate electrode and a source electrode on the active layer, and a substrate. and a plurality of light blocking layers disposed between the plurality of thin film transistors and overlapping the plurality of thin film transistors, and a plurality of buffer layers disposed between the plurality of light blocking layers and the plurality of thin film transistors, wherein the entire lower surface of the plurality of buffer layers includes a plurality of in contact with the light-shielding layer of

According to another feature of the present invention, the area of the upper surface of the light blocking layer may be greater than or equal to the area of the lower surface of the buffer layer.

According to another feature of the present invention, the area of the upper surface of the buffer layer may be greater than or equal to the area of the lower surface of the active layer.

According to another feature of the present invention, a plurality of light blocking layers disposed in sub-pixels sharing the gate line among the plurality of sub-pixels may be integrally formed, further including a plurality of gate wires electrically connected to the gate electrode. .

According to another feature of the present invention, the light blocking layer may extend in the same direction as the plurality of gate wires.

According to another feature of the present invention, an overcoating layer disposed on the plurality of thin film transistors and a common electrode disposed on the overcoating layer may be further included, and an entire lower surface of the common electrode may be in contact with the overcoating layer.

According to another feature of the present invention, a pixel electrode disposed on the common electrode and electrically connected to the thin film transistor may be further included, and the common electrode may be opened at a contact point between the pixel electrode and the thin film transistor.

According to another feature of the present invention, a first sub-pixel and a second sub-pixel among a plurality of sub-pixels are adjacent to each other in a row direction or a column direction, and a voltage applied to the first sub-pixel and the second sub-pixel during one frame The polarity of may be different.

A display device according to another embodiment of the present invention includes a plurality of thin film transistors disposed on a substrate and including an active layer, a gate electrode and a source electrode on the active layer, a light blocking wire disposed between the substrate and the plurality of thin film transistors, A buffer layer disposed between the light blocking wiring and the plurality of thin film transistors and a plurality of gate wirings electrically connected to gate electrodes of the plurality of thin film transistors and extending in a first direction, wherein the light blocking wiring extends in the first direction.

According to another feature of the present invention, the light blocking wiring may overlap a plurality of thin film transistors.

According to another feature of the present invention, the entire lower surface of the buffer layer may be in contact with the upper surface of the light blocking wiring, and the entire lower surface of the plurality of active layers may be in contact with the buffer layer.

According to another feature of the present invention, an overcoating layer disposed on the plurality of thin film transistors and a common electrode disposed on the overcoating layer may be further included, and the entire upper surface of the overcoating layer may contact the entire lower surface of the common electrode.

According to another feature of the present invention, a pixel electrode disposed on the common electrode and connected to the plurality of thin film transistors may be further included, and the common electrode may be opened at a contact point where the plurality of thin film transistors and the pixel electrode are electrically connected. there is.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100, 500, 600: display device
110: substrate
111, 611: light blocking layer
112: buffer layer
113: gate insulating layer
114: interlayer insulating layer
115: first passivation layer
116: overcoating layer
117: second passivation layer
120, 520: thin film transistor
121: active layer
121C: channel area
121D: drain area
121S: source area
122: gate electrode
123: source electrode
124: drain electrode
131: common electrode
131OP: common electrode opening
132: auxiliary common electrode
140: pixel electrode
111m: light-shielding layer material
112m: buffer layer material
121m: active layer material
116m: Overcoating layer material
131m: common electrode material
132m: auxiliary common electrode material
AA: display area
NA: non-display area
SP: sub pixel
SP1: first sub-pixel
SP2: second sub-pixel
DL: data wiring
GL: Gate wiring
PR1: first photoresist pattern
PR2: second photoresist pattern
PR3: third photoresist pattern
PR4: fourth photoresist pattern

Claims (13)

a substrate on which a plurality of sub-pixels are defined;
a plurality of thin film transistors disposed in each of the plurality of sub-pixels and including an active layer, a gate electrode and a source electrode on the active layer;
a plurality of light blocking layers disposed between the substrate and the plurality of thin film transistors and overlapping the plurality of thin film transistors;
a plurality of buffer layers disposed between the plurality of light blocking layers and the plurality of thin film transistors;
an overcoating layer disposed on the plurality of thin film transistors;
a common electrode disposed on the overcoating layer; and
a pixel electrode disposed on the common electrode;
Entire lower surfaces of the plurality of buffer layers are in contact with the plurality of light blocking layers,
The pixel electrode directly contacts the active layer. According to claim 1,
The area of the upper surface of the light blocking layer is greater than or equal to the area of the lower surface of the buffer layer. According to claim 2,
The area of the upper surface of the buffer layer is greater than or equal to the area of the lower surface of the active layer. According to claim 1,
Further comprising a plurality of gate wires electrically connected to the gate electrode,
The plurality of light-blocking layers disposed in sub-pixels sharing the gate line among the plurality of sub-pixels are integrally formed. According to claim 4,
The light blocking layer extends in the same direction as the plurality of gate wires. According to claim 1,
The entire lower surface of the common electrode is in contact with the overcoating layer,
An auxiliary common electrode disposed on the common electrode,
The auxiliary common electrode is disposed to overlap a data line that transmits a data voltage to the plurality of sub-pixels. According to claim 6,
The common electrode is open at a contact point between the pixel electrode and the thin film transistor. According to claim 5,
Among the plurality of sub-pixels, a first sub-pixel and a second sub-pixel are adjacent to each other in a row direction or a column direction;
Polarities of voltages applied to the first sub-pixel and the second sub-pixel during one frame are different. a substrate on which a plurality of sub-pixels are disposed;
a plurality of thin film transistors including an active layer disposed in each of the plurality of sub-pixels, and a gate electrode and a source electrode on the active layer;
a light blocking wiring disposed between the substrate and the plurality of thin film transistors;
a buffer layer disposed between the light blocking wiring and the plurality of thin film transistors; and
a plurality of gate wires electrically connected to the gate electrodes of the plurality of thin film transistors and extending in a first direction;
The light-blocking wire extends in the first direction and is disposed on the substrate between a thin film transistor of a first sub-pixel among the plurality of sub-pixels and a thin-film transistor between a second sub-pixel adjacent to the first sub-pixel. becomes,
Polarities of data voltages applied to the first sub-pixel and the second sub-pixel are different from each other. According to claim 9,
The light blocking wiring overlaps the plurality of thin film transistors. According to claim 9,
The entire lower surface of the buffer layer is in contact with the upper surface of the light-shielding wiring,
The display device, wherein entire lower surfaces of the plurality of active layers are in contact with the buffer layer. According to claim 9,
an overcoating layer disposed on the plurality of thin film transistors;
a common electrode disposed on the overcoating layer; and
Further comprising an auxiliary common electrode disposed on the common electrode,
The entire upper surface of the overcoating layer contacts the entire lower surface of the common electrode. According to claim 12,
Further comprising pixel electrodes disposed on the common electrode and connected to the plurality of thin film transistors,
The common electrode is open at a contact point where the plurality of thin film transistors and the pixel electrode are electrically connected.

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