KR101206286B1 - Method of fabricating liquid crystal display device - Google Patents

Abstract

In the method of manufacturing the liquid crystal display of the present invention, when the active pattern and the source / drain electrodes are formed by using diffraction exposure, wave noise is prevented by removing the protrusions of the active pattern when the source / drain electrodes are patterned together. In order to simplify the manufacturing process and reduce the manufacturing cost by improving the image quality while reducing the number of masks, providing a first substrate and a second substrate bonded to face the first substrate; Forming a gate electrode and a gate line on the first substrate; Forming a first insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on the first substrate; Forming first and second photoresist patterns having a first thickness and a third photoresist pattern having a second thickness on the first substrate; Patterning the conductive layer using the first, second, and third photosensitive layer patterns as a mask to form a second conductive layer pattern having a width smaller than that of the first, second, and third photosensitive layer patterns; The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the first, second and third photoresist pattern as a mask, and the amorphous silicon thin film pattern and n + amorphous silicon having the same shape as the first, second and third photoresist pattern Forming a thin film pattern; Removing the third photoresist pattern and simultaneously removing the first and second photoresist patterns by the thickness of the third photoresist pattern to form fourth and fifth photoresist patterns having a third thickness; Patterning the conductive layer pattern using the fourth and fifth photoresist layer patterns as a mask to form a source / drain electrode and a data line formed of the conductive layer, and simultaneously form an amorphous silicon thin film pattern and an n + amorphous silicon thin film pattern under the conductive layer pattern. Patterning a side surface of the same shape as that of the source / drain electrode; Patterning the n + amorphous silicon thin film pattern on the channel region using the fourth and fifth photoresist patterns as a mask to form an active pattern formed of the amorphous silicon thin film on the gate electrode; Forming a second insulating film on the first substrate and selectively removing the second insulating film to form a first contact hole exposing the drain electrode; Forming a pixel electrode electrically connected to the drain electrode through the first contact hole; And forming a liquid crystal layer between the first substrate and the second substrate.

Diffraction exposure, active pattern, source electrode, drain electrode, number of masks

Description

Manufacturing method of liquid crystal display device {METHOD OF FABRICATING LIQUID CRYSTAL DISPLAY DEVICE}

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are sectional views sequentially showing a manufacturing process of an array substrate in the liquid crystal display device shown in Fig.

3 is a plan view illustrating a portion of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

4A to 4D are cross-sectional views sequentially illustrating a manufacturing process along line IIIa-IIIa 'of the array substrate shown in FIG. 3.

5A to 5F are cross-sectional views specifically showing a second mask process of this embodiment shown in FIG. 4B.

6 is a cross-sectional view illustrating a thin film transistor structure manufactured by a general four mask process.

DESCRIPTION OF REFERENCE NUMERALS

110: array substrate 116n-1, 116n: gate line

117m, 117m + 1: data line 118: pixel electrode

121: gate electrode 122: source electrode

123: drain electrode 124 ": active pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device in which the number of masks is reduced to simplify the manufacturing process, improve yield, and improve image quality.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

In this case, a thin film transistor (TFT) is generally used as a switching element of the liquid crystal display, and an amorphous silicon thin film is used as a channel layer of the thin film transistor.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of mask processes in terms of productivity is required. It is required.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 defining a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. , 10 is formed through a bonding key (not shown) formed on the color filter substrate 5 or the array substrate 10.

2A to 2E are cross-sectional views sequentially showing the steps of manufacturing an array substrate in the liquid crystal display device shown in Fig.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the substrate 10 by using a photolithography process (first mask process).

Next, as shown in FIG. 2B, the first insulating film 15A, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the substrate 10 on which the gate electrode 21 is formed. An active pattern 24 made of an amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same form as the active pattern 24 is formed on the active pattern 24.

2C, a source electrode is formed on the active pattern 24 by depositing a conductive metal material on the entire surface of the substrate 10 and then selectively patterning the same by using a photolithography process (third mask process). And the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process, thereby making an ohmic between the active pattern 24 and the source / drain electrodes 22 and 23. -Form an ohmic contact layer 25 '.

Next, as shown in FIG. 2D, after depositing the second insulating film 15B on the entire surface of the substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, a photolithography process (fourth mask process) A portion of the second insulating layer 15B is removed to form a contact hole 40 exposing a portion of the drain electrode 23.

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the substrate 10 and then selectively patterned using a photolithography process (fifth mask process) to drain through the contact hole 40. The pixel electrode 18 electrically connected to the electrode 23 is formed.

As described above, the fabrication of the array substrate including the thin film transistor requires five photolithography processes in total for patterning the gate electrode, the active pattern, the source / drain electrode, the contact hole, and the pixel electrode.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development. As a result, many photolithography processes have many problems, such as lowering the production yield and increasing the probability of defects in the formed thin film transistors.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device having a reduced number of masks used for manufacturing a thin film transistor and a method of manufacturing the same.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which solves wave noise defects and improves device reliability and image quality.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above object, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate and a second substrate bonded to the first substrate; Forming a gate electrode and a gate line on the first substrate; Forming a first insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on the first substrate; Forming first and second photoresist patterns having a first thickness and a third photoresist pattern having a second thickness on the first substrate; Patterning the conductive layer using the first, second, and third photosensitive layer patterns as a mask to form a second conductive layer pattern having a width smaller than that of the first, second, and third photosensitive layer patterns; The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the first, second and third photoresist pattern as a mask, and the amorphous silicon thin film pattern and n + amorphous silicon having the same shape as the first, second and third photoresist pattern Forming a thin film pattern; Removing the third photoresist pattern and simultaneously removing the first and second photoresist patterns by the thickness of the third photoresist pattern to form fourth and fifth photoresist patterns having a third thickness; Patterning the conductive layer pattern using the fourth and fifth photoresist layer patterns as a mask to form a source / drain electrode and a data line formed of the conductive layer, and simultaneously form an amorphous silicon thin film pattern and an n + amorphous silicon thin film pattern under the conductive layer pattern. Patterning a side surface of the same shape as that of the source / drain electrode; Patterning the n + amorphous silicon thin film pattern on the channel region using the fourth and fifth photoresist patterns as a mask to form an active pattern formed of the amorphous silicon thin film on the gate electrode; Forming a second insulating film on the first substrate and selectively removing the second insulating film to form a first contact hole exposing the drain electrode; Forming a pixel electrode electrically connected to the drain electrode through the first contact hole; And forming a liquid crystal layer between the first substrate and the second substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the manufacturing method of the liquid crystal display device according to the present invention.

FIG. 3 is a plan view showing a portion of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention. In the actual array substrate, N gate lines and M data lines cross each other to provide MxN pixels, but the description will be simplified. The m-by-n pixel is shown in the figure.

As shown in the drawing, an n-th gate line 116n and an m-th data line 117m are formed on the array substrate 110 to be arranged vertically and horizontally on the substrate 110 to define an mxn-th pixel region. A thin film transistor, which is a switching element, is formed in an intersection area of the nth gate line 116n and the mth data line 117m, and is connected to the thin film transistor in the pixel area so as to have a common color filter substrate (not shown). A pixel electrode 118 for driving a liquid crystal (not shown) is formed together with the electrode.

The thin film transistor includes a gate electrode 121 constituting a part of the n-th gate line 116n, a source electrode 122 connected to the m-th data line 117m, and a drain electrode connected to the pixel electrode 118. 123). In addition, the thin film transistor may include a first insulating film (not shown) for insulating the gate electrode 121 and the source / drain electrodes 122 and 123 and a gate electrode supplied to the gate electrode 121. An active pattern (not shown) for forming a conductive channel between the 122 and the drain electrode 123 is included.

In this case, a part of the source electrode 122 is connected to the m-th data line 117m to form a part of the m-th data line 117m, and a part of the drain electrode 123 extends toward the pixel region. And electrically connected to the pixel electrode 118 through the contact hole 140 formed in the second insulating layer (not shown).

In this case, a portion of the n−1 th gate line 116n−1, which is a front gate line, overlaps with a portion of the pixel electrode 118 therebetween with the first insulating layer therebetween to form a storage capacitor Cst. . The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. In general, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is input and is leaked. Disappear. Therefore, in order to maintain the applied voltage, the storage capacitor Cst needs to be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

The array substrate 110 according to the present embodiment configured as described above may be manufactured through a total of four mask processes by forming active patterns and source / drain electrodes 122 and 123 using diffraction exposure, and the source / drain electrodes 122 may be manufactured. , 123) It is possible to prevent the wave noise by removing the protrusions of the active pattern at the time of patterning, which will be described in detail through the following manufacturing process of the liquid crystal display.

4A to 4D are cross-sectional views sequentially illustrating a manufacturing process along line IIIa-IIIa 'of the array substrate illustrated in FIG. 3.

As shown in FIG. 4A, the gate electrode 121 and the gate line 116n-1 are formed on the substrate 110 made of a transparent insulating material such as glass. In this case, the gate line 116n-1 means the gate line of the front end of the corresponding pixel, that is, the n-1th gate line 116n-1, and the gate line of the corresponding pixel, that is, the nth gate line 116n. Also formed in the same manner as the n-th gate line 116n-1.

In this case, the gate electrode 121 and the n-th gate line 116n-1 are formed by depositing a first conductive layer on the entire surface of the substrate 110 and patterning the same through a photolithography process (first mask process). .

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), or the like. The same low resistance opaque conductive material can be used. In addition, the gate electrode 121 and the n−1 th gate line 116n− 1 may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIG. 4B, the first insulating film 115A, the amorphous silicon thin film, and the like are sequentially formed on the entire surface of the substrate 110 on which the gate electrode 121 and the n−1 th gate line 116n-1 are formed. After depositing the n + amorphous silicon thin film and the second conductive film, the patterned upper portion of the gate electrode 121 by selectively patterning the amorphous silicon thin film, the n + amorphous silicon thin film and the second conductive film using a photolithography process (second mask process). An active pattern 124 ″ made of the amorphous silicon thin film is formed on the substrate, and a source electrode 122 and a drain electrode 123 made of the second conductive film are formed.

The n + amorphous silicon thin film is formed on the active pattern 124 ″, and is patterned in the same form as the source / drain electrodes 122 and 123 to form a predetermined region of the active pattern 124 ″ below the source / drain. An ohmic contact layer 125 " for ohmic-contacting the electrodes 122 and 123 is formed. A portion of the source electrode 122 substantially crosses the n-th gate line to define a corresponding pixel region. The m-th data line 117m is formed.

As described above, the active pattern 124 "and the source / drain electrodes 122 and 123 are simultaneously formed in one mask process (second mask process) using diffraction exposure. 2 The mask process will be described in detail.

5A to 5F are cross-sectional views illustrating in detail a process of simultaneously forming an active pattern and a source / drain electrode in FIG. 4B, which sequentially illustrate the second mask process of this embodiment.

As shown in FIG. 5A, the first insulating layer 115A, the amorphous silicon thin film 124, and the like are sequentially formed on the entire surface of the substrate 110 on which the gate electrode 121 and the n-th gate line 116n-1 are formed. The n + amorphous silicon thin film 125 and the second conductive film 130 are deposited.

In this case, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy may be used as the second conductive layer 130.

Thereafter, the photoresist film 170 made of a photoresist such as photoresist is formed on the entire surface of the substrate 110, and then light is selectively irradiated onto the photoresist film 170 through the diffraction mask 180 of the present embodiment.

In this case, the diffraction mask 180 used in the present embodiment is applied with a transmission region I and a slit pattern that transmit all of the irradiated light so that only a part of the light is transmitted and a portion of the slit region II and all of the irradiated light are blocked. A blocking region III is provided to block the light, and only the light passing through the diffraction mask 180 is irradiated to the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the diffraction mask 180 is developed, as shown in FIG. 5B, light is blocked or partially blocked through the blocking region III and the slit region II. The photoresist patterns 170A to 170C having a predetermined thickness remain in the exposed region, and the photoresist layer is completely removed in the transmission region I through which all the light is transmitted, thereby exposing the surface of the second conductive layer 130.

In this case, the first photoresist pattern 170A and the second photoresist pattern 170B formed through the blocking region III are formed thicker than the third photoresist pattern 170C formed in the slit region II. In addition, the photoresist film is completely removed in the region where all the light is transmitted through the transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist may be used.

Next, as shown in FIG. 5C, when the second conductive film formed below the photosensitive film patterns 170A to 170C is formed as a mask, the second conductive film is formed on the substrate 110. The second conductive film pattern 130 ′ is formed.

In the present embodiment, wet etching is used as an etching of the second conductive layer, wherein the second conductive layer pattern 130 ′ is reduced in width than the photoresist patterns 170A to 170C thereon. It will be patterned.

Subsequently, as shown in FIG. 5D, if the amorphous silicon thin film and the n + amorphous silicon thin film under the second conductive film pattern 130 ′ are selectively removed using the photoresist pattern 170A to 170C as a mask, An amorphous silicon thin film pattern 124 ′ consisting of the amorphous silicon thin film and an n + amorphous silicon thin film 124 ′ and an n + amorphous silicon thin film pattern 125 ′ are formed in a predetermined region on the gate electrode 121.

In this case, dry etching is used to etch the amorphous silicon thin film and the n + amorphous silicon thin film, and the amorphous silicon thin film pattern 124 'and the n + amorphous silicon thin film pattern 125' are formed on the upper photoresist pattern ( 170A ~ 170C) to be patterned in the same form. As a result, the amorphous silicon thin film pattern 124 ′ and the n + amorphous silicon thin film pattern 125 ′ have protrusions P partially protruding from the side of the second conductive film pattern 130 ′.

When the ashing process is performed to remove a portion of the photoresist patterns 170A to 170C, as shown in FIG. 5E, a slit to which an upper portion of the amorphous silicon thin film pattern 124 ′ is applied, i. The third photoresist pattern of the region II is completely removed to expose the surface of the second conductive layer pattern 130 ′.

In this case, the first photoresist pattern and the second photoresist pattern correspond to the blocking region III by the fourth photoresist pattern 170A 'and the fifth photoresist pattern 170B', which have the thickness of the third photoresist pattern removed. It remains only in a predetermined area.

Subsequently, as shown in FIG. 5F, a predetermined region (ie, a channel) of the amorphous silicon thin film pattern 124 ′ is formed by using the remaining fourth photoresist pattern 170A ′ and the fifth photoresist pattern 170B ′ as a mask. When the second conductive layer pattern is selectively etched, the source electrode 122 and the drain electrode 123 formed of the second conductive layer are formed on the gate electrode 121. In this case, a part of the source electrode 122 extends in one direction to form a part of the m-th data line 117m.

Dry etching is used as an etching of the second conductive film pattern, and when the second conductive film pattern is etched, the protrusions of the amorphous silicon thin film pattern under the second conductive film pattern and the n + amorphous silicon thin film pattern are also etched together. .

In this embodiment, an etching gas capable of simultaneously etching the second conductive film pattern, the amorphous silicon thin film pattern, and the n + amorphous silicon thin film pattern is used. For example, molybdenum or molybdenum alloy may be used as the second conductive film. In the case of using, a mixture of Cl ₂ and O ₂ may be used as an etching gas. The Cl ₂ and O ₂ can be used by mixing in a ratio of 1: 0.5 to 4, and during etching, the chamber pressure is maintained at 100 to 1000 mT (Torr) and the plasma power is 0.1 to 0.5 W (watt) / cm ² . can do.

Thereafter, the n + amorphous silicon thin film pattern on the channel region is selectively etched using the fourth photoresist pattern 170A 'and the fifth photoresist pattern 170B' as masks, thereby forming the amorphous layer on the gate electrode 121. An active pattern 124 "formed of a silicon thin film pattern is formed. The active pattern 124" has the same side surface as the source / drain electrodes 122 and 123 thereon, and the source / drain described above. When the electrodes 122 and 123 are patterned, even when the protrusions of the amorphous silicon thin film pattern and the n + amorphous silicon thin film pattern are partially etched, the n + amorphous silicon thin film pattern is completely removed.

At this time, the n + amorphous silicon thin film pattern formed on the active pattern 124 "is patterned to form an ohmic contact layer 125 for ohmic contact between the active pattern 124" and the source / drain electrodes 122 and 123. ").

In general, when the active pattern and the source / drain electrodes are simultaneously patterned by using diffraction exposure, as shown in FIG. 6, the side surface of the active pattern 224 ′ under the source / drain electrodes 222 and 223 is formed on the source. It is patterned to protrude relative to the / drain electrodes 222 and 223, and wave noise is generated due to the protruding protrusion P ', which causes deterioration in image quality. For reference, reference numeral 217 denotes a data line and reference numerals 221 and 225 ″ denote a gate electrode and an ohmic contact layer.

However, as shown in FIG. 4B, in the present embodiment, when etching the second conductive film constituting the source / drain electrodes 122 and 123, an etching gas capable of etching the second conductive film and the amorphous silicon thin film together. By using it, it is possible to remove the protrusion of the active pattern 124 ".

As illustrated in FIG. 4C, after the second insulating film 115B is deposited on the entire surface of the substrate 110 on which the source electrode 122 and the drain electrode 123 are formed, a photolithography process (third mask process) is performed. The contact hole 140 exposing a portion of the drain electrode 123 is formed by removing a portion of the second insulating layer 115B through the opening.

Thereafter, as illustrated in FIG. 4D, a transparent conductive material is deposited on the entire surface of the substrate 110 and then selectively patterned using a photolithography process (a fourth mask process) to form a drain electrode through the contact hole 140. The pixel electrode 118 electrically connected to the 123 is formed.

In this case, the transparent conductive material includes a conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A portion of the corresponding pixel electrode 118 is formed to overlap with a portion of the n−1 th gate line 116n−1 so that the n−1 th gate line is disposed with the first insulating layer 115A therebetween. Together with 116n-1, a storage capacitor Cst (see FIG. 3) is formed.

The array substrate 110 configured as described above is bonded to face the color filter substrate (not shown) by a sealant (not shown) formed outside the image display area to form a liquid crystal display panel. The bonding of the color filter substrate is performed through a bonding key (not shown) formed on the array substrate 110 and the color filter substrate.

In the present embodiment, an amorphous silicon thin film transistor using an amorphous silicon thin film as the channel layer is described as an example, but the present invention is not limited thereto, and the present invention is also applied to a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as the channel layer. do.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

As described above, the manufacturing method of the liquid crystal display according to the present invention reduces the number of masks used in the manufacturing of the thin film transistor by simultaneously patterning the active pattern and the source / drain electrodes using diffraction exposure, thereby reducing the manufacturing process and cost. To provide.

In addition, the manufacturing method of the liquid crystal display according to the present invention can prevent wave noise by removing side protrusions of the active pattern when patterning the source / drain electrodes. As a result, the image quality is improved and the yield is improved by removing defects.

Claims (14)

Providing a first substrate and a second substrate joined against the first substrate; Forming a gate electrode and a gate line on the first substrate; Forming a first insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on the first substrate; Forming first and second photoresist patterns having a first thickness and a third photoresist pattern having a second thickness on the first substrate; Patterning the conductive layer using the first, second, and third photosensitive layer patterns as a mask to form a second conductive layer pattern having a width smaller than that of the first, second, and third photosensitive layer patterns; The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the first, second and third photoresist pattern as a mask, and the amorphous silicon thin film pattern and n + amorphous silicon having the same shape as the first, second and third photoresist pattern Forming a thin film pattern; Removing the third photoresist pattern and simultaneously removing the first and second photoresist patterns by the thickness of the third photoresist pattern to form fourth and fifth photoresist patterns having a third thickness; Patterning the conductive layer pattern using the fourth and fifth photoresist layer patterns as a mask to form a source / drain electrode and a data line formed of the conductive layer, and simultaneously form an amorphous silicon thin film pattern and an n + amorphous silicon thin film pattern under the conductive layer pattern. Patterning a side surface of the same shape as that of the source / drain electrode; Patterning the n + amorphous silicon thin film pattern on the channel region using the fourth and fifth photoresist patterns as a mask to form an active pattern formed of the amorphous silicon thin film on the gate electrode; Forming a second insulating film on the first substrate and selectively removing the second insulating film to form a first contact hole exposing the drain electrode; Forming a pixel electrode electrically connected to the drain electrode through the first contact hole; And Forming a liquid crystal layer between the first substrate and the second substrate. The liquid crystal of claim 1, wherein the third photoresist layer pattern is formed in a first region above the gate electrode, and the first and second photoresist layer patterns are formed in second regions on the left and right sides of the first region. Method for manufacturing a display device. The method of claim 2, wherein the conductive layer is patterned by wet etching using the first, second, and third photosensitive layer patterns as a mask. The method of claim 3, wherein the amorphous silicon thin film and the n + amorphous silicon thin film are patterned by dry etching using the first, second, and third photosensitive film patterns as a mask. The method of claim 4, wherein the amorphous silicon thin film pattern and the n + amorphous silicon thin film pattern are patterned to have protrusions protruding from side surfaces thereof, as compared with an upper conductive film pattern. The method of claim 5, wherein the fourth and fifth photoresist patterns are narrower than the first and second photoresist patterns. The method of claim 6, wherein the conductive layer pattern is patterned by dry etching using the fourth and fifth photoresist layer patterns as a mask. The method of claim 7, wherein protrusions of the amorphous silicon thin film pattern and the n + amorphous silicon thin film pattern under the conductive film pattern are also removed when the conductive film pattern is patterned. 10. The method of claim 8, wherein the conductive film is made of molybdenum or molybdenum alloy. The method of claim 9, wherein the dry etching is a gas in which Cl ₂ and O ₂ is mixed as an etching gas, wherein the Cl ₂ and O ₂ is used in a ratio of 1: 0.5 to 4 Method of manufacturing a liquid crystal display device. The method of claim 1, wherein the forming of the first and second photoresist patterns and the third photoresist patterns are performed. Forming a photoresist film on the conductive film; Irradiating light on the photosensitive film through a diffraction mask having a first transmission region for transmitting all the light, a second transmission region for selectively transmitting the light, and a blocking region for blocking the light; And Developing a photoresist film irradiated with light through the diffraction mask to form a photoresist pattern on the conductive layer, and to form a third photoresist pattern having a second thickness in the first region above the gate electrode and to the left and right of the first region And forming first and second photoresist patterns having a first thickness in the second region. 12. The liquid crystal display of claim 11, wherein when a positive type photosensitive film is used, the second transmission region of the diffraction mask is applied to a channel region of an active pattern, and the blocking region is applied to a source / drain region. Manufacturing method. The method of claim 11, wherein the diffraction mask has a diffraction pattern formed in a second transmission region selectively transmitting light to form a third photoresist pattern of a second thickness thinner than the first thickness on the channel region of the active pattern. Method of manufacturing a liquid crystal display device, characterized in that. delete

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