KR20100069432A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a method of manufacturing the same are provided to reduce the number of masks, thereby reducing manufacturing processes and costs. CONSTITUTION: A gate electrode(121), a gate line(116), a pixel electrode(118), and a common electrode(108) are formed in a pixel unit of the first substrate(110) through the first mask process. An ohmic contact layer(125n) is formed on a source area and a drain area of an active pattern. Source/drain electrodes(122,123) are formed in the pixel unit through the second mask process. A data line(117) is formed. A data pad electrode(127p) and a gate pad electrode(126p) are formed in a data pad unit and a gate pad unit of the first substrate respectively.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same, which can reduce the number of masks, simplify the manufacturing process, reduce manufacturing costs and improve productivity. .

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, is a method of driving the liquid crystal of the pixel portion by using a thin film transistor (TFT) as a switching element.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. The bonding of the 5 and the array substrate 10 is made through a bonding key (not shown) formed on the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of an opaque conductive film is formed on the array substrate 10 using a photolithography process (first mask process).

Next, as shown in FIG. 2B, the first insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed. The active pattern 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, an n + amorphous silicon thin film pattern 25 patterned in the same shape as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 2C, an opaque conductive film is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (third mask process) to form an upper portion of the active pattern 24. The source electrode 22 and the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process, thereby forming an ohmic − between the active pattern 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25 'is formed.

Next, as shown in FIG. 2D, a second insulating film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process (fourth mask). The contact hole 40 exposing a part of the drain electrode 23 is formed by removing a part of the second insulating layer 15b through the process).

Lastly, as shown in FIG. 2E, a transparent conductive film is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (fifth mask process) to drain electrodes through the contact holes 40. A pixel electrode 18 electrically connected to the 23 is formed.

As described above, fabrication of an array substrate including a thin film transistor requires at least five photolithography processes for patterning a gate electrode, an active pattern, a source / drain electrode, a contact hole, and a pixel electrode.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. There is a downside to dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

At this time, by forming the active pattern and the source / drain electrodes in a single mask process using a half-tone mask, a technique for manufacturing an array substrate through a total of four mask processes has been developed.

However, the liquid crystal display of the above structure is patterned to the data line, that is, the source electrode, the drain electrode, and the lower periphery of the data line by simultaneously patterning the active pattern and the source / drain electrodes through two etching processes using a half-tone mask. The protruding active pattern remains.

The active pattern is formed of a pure amorphous silicon thin film, wherein the active pattern under the data line is exposed to the backlight light below the gate line, ie, except for the portion covered by the gate electrode and the gate line, thereby being exposed by the backlight light. Photocurrent is generated. At this time, due to the minute flickering of the backlight light, the amorphous silicon thin film reacts finely, and the activation and deactivation states are repeated, thereby causing a change in the photocurrent. The photocurrent component is coupled with a signal flowing to a neighboring pixel electrode to distort the movement of the liquid crystal located in the pixel electrode. As a result, wavy noise in which wavy thin lines appear on the screen of the liquid crystal display is generated.

In addition, since the active pattern disposed below the data line protrudes a predetermined distance to both sides of the data line, the opening ratio of the liquid crystal display device is reduced as the opening area of the pixel portion is eroded by the protruding distance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a liquid crystal display device in which an array substrate of a liquid crystal display device is manufactured by two mask processes.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which prevent wave noise by forming an active pattern in an island shape.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display of the present invention comprises a first substrate; A gate electrode, a gate line, a pixel electrode, and a common electrode formed on the first substrate; An active pattern formed on the gate electrode through a gate insulating layer and divided into a source region, a drain region, and a channel region; An ohmic contact layer formed on the source region and the drain region of the active pattern; A first hole exposing a portion of the first substrate and a first contact hole and a second contact hole exposing a source region and a drain region of the active pattern, respectively, formed on the first substrate on which the active pattern is formed; Protective film; Source / drain electrodes electrically connected to the source / drain regions of the active pattern; A data line crossing the gate line to define a pixel area; And a second substrate bonded to and opposed to the first substrate.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method including: providing a first substrate divided into a pixel unit, a data pad unit, and a gate pad unit; Forming a gate electrode, a gate line, a pixel electrode, and a common electrode on the pixel portion of the first substrate through a first mask process, and forming a gate pad line on the gate pad portion of the first substrate; An active pattern divided into a source region, a drain region, and a channel region is formed on the gate electrode with the gate insulating layer interposed using the first mask process, and an ohmic contact is formed on the source region and the drain region of the active pattern. Forming a layer; Forming a protective film on the first substrate; A source / drain electrode electrically connected to the source / drain regions of the active pattern is formed in the pixel portion of the first substrate through a second mask process, and a data line is defined to cross the gate line to define the pixel region. Making; Forming a data pad electrode and a gate pad electrode on the data pad portion and the gate pad portion of the first substrate using the second mask process; And bonding the first substrate and the second substrate to each other.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost. In particular, a process reduction effect of about 35% can be achieved compared to the existing four mask process.

In addition, in the liquid crystal display and the method of manufacturing the same according to the present invention, since the active pattern does not remain under the data line as the active pattern is formed in the island form, there is a problem of wave noise and aperture ratio loss in the existing four mask process. Will be able to solve.

In addition, the liquid crystal display and the method of manufacturing the same according to the present invention do not have an active pattern and a gate insulating layer between the common line and the pixel line, thereby increasing the storage capacitance, thereby providing an effect of improving the aperture ratio.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention, and for convenience of description, illustrates one pixel including a gate pad part, a data pad part, and a thin film transistor of a pixel part. .

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

In this case, the liquid crystal display of the in-plane switching (IPS) method in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle to 170 degrees or more is described as an example. It is not limited.

As shown in the figure, a gate line 116 and a data line 117 are formed in the array substrate 110 according to the exemplary embodiment of the present invention, which are arranged horizontally and horizontally on the array substrate 110 to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117, and a common electrode 108 for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel region. ) And pixel electrodes 118 are alternately arranged.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. .

For reference, reference numeral 125n denotes an ohmic contact layer for ohmic contact between the source / drain region of the active pattern and the source / drain electrodes 122 and 123. In this case, the source electrode 122 and the drain electrode 123 are electrically connected to the source region and the drain region of the active pattern through the first contact hole 140a and the second contact hole 140b formed in the passivation layer (not shown). You will be connected to

In this case, an insulating material constituting the protective layer is deposited between the ohmic contact layer 125n to prevent the back channel of the thin film transistor from being exposed after patterning the source / drain electrodes 122 and 123.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to extend the pixel electrode 118 through the pixel line 118L. 118) electrically.

As described above, the common electrode 108 and the pixel electrode 118 for generating a transverse electric field are alternately arranged in the pixel region.

In this case, a common line 108L is formed below the pixel area in a direction substantially parallel to the gate line 116, and one side of the plurality of common electrodes 108 is formed on the common line ( 108L).

In addition, the plurality of pixel electrodes 118 are connected to the pixel electrode lines 118l arranged in a direction substantially parallel to the gate line 116, and connect the connection electrodes 118a of the pixel lines 118L. Electrically connected to the drain electrode 123 through.

The common electrode 108, the pixel electrode 118, the common line 108L and the pixel electrode line 118l may be formed of a gate wiring, that is, a first conductive layer constituting the gate electrode 121 and the gate line 116. The connection electrode 118a and the pixel line 118L may be formed of a third conductive layer constituting the data line, that is, the source electrode 122, the drain electrode 123, and the data line 117.

In this case, a source electrode pattern (not shown) and a drain formed of a second conductive film are disposed below the source electrode 122, the drain electrode 123, the data line 117, and the pixel line 118L. An electrode pattern (not shown), a data line pattern (not shown), and a pixel line pattern (not shown) are formed.

In this case, a portion of the pixel line 118L overlaps a portion of the common line 108L below the passivation layer to form a storage capacitor Cst. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. The storage capacitor Cst has effects such as stability of gray scale display and reduction of flicker and afterimage in addition to signal retention.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit portion, and are connected to the corresponding gate pad line 116p and the data pad line (not shown), respectively, and the gate pad line 116p and the data. The pad line receives a scan signal or a data signal from a driving circuit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line, respectively.

For reference, reference numeral 140c denotes a third contact hole formed in the passivation layer, wherein the gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c. .

Here, the liquid crystal display according to the embodiment of the present invention is a multi-exposure mask, that is, a blocking region consisting of a dark portion, a first transmission region for transmitting all light, a second transmission region of half-tone, and a half-tone and a slit portion are applied. The gate wiring, the active pattern, the common electrode, and the pixel electrode are formed in one mask process using a multi-tone mask of the third transmission region, and a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask) In this case, the array substrate can be manufactured by a total of two mask processes by forming a data wiring, a pad electrode, and a protective film in one mask process by using a diffraction mask) and a lift-off process. Next will be described in detail through the manufacturing method of the liquid crystal display device.

In this case, the data line and the pad electrode have a multi-layer structure of two or more layers of the second conductive film and the third conductive film, and the second conductive film constituting the upper layer of the multi-layer structure is corroded by ITO (Indium Tin Oxide) or MoTi. Since the conductive material has a strong resistance to the data line and the pad electrode, the number of processes can be minimized.

4A and 4B are cross-sectional views sequentially illustrating a manufacturing process along lines IIIa-IIIa ', IIIb-IIIb, and IIIc-IIIc of the array substrate illustrated in FIG. 3, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

5A and 5B are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

4A and 5A, after forming a first conductive film, a first insulating film, an amorphous silicon thin film, and an n + amorphous silicon thin film on the entire surface of the array substrate 110 made of a transparent insulating material such as glass, photolithography The gate electrode 121, the gate line 116, the common electrode 108, and the pixel which are formed of the first conductive layer in the pixel portion of the array substrate 110 are selectively patterned through a process (first mask process). An electrode 118, a common line 108L, and a pixel line 118l are formed, and an active pattern 124 made of the amorphous silicon thin film is formed on the gate electrode 121.

In addition, a gate pad line 116p formed of the first conductive layer is formed on the gate pad of the array substrate 110, and an ohmic contact layer made of the n + amorphous silicon thin film on the active pattern 124. 125n).

In this case, a gate insulating layer 115a formed of the first insulating layer and patterned substantially the same as the active pattern 124 is formed between the gate electrode 121 and the active pattern 124.

Here, the gate electrode 121, the gate line 116, the common electrode 108, the pixel electrode 118, the common line 108L, the pixel line 118l, and the gate pad line according to the embodiment of the present invention. 116p and the active pattern 124 and the gate insulating film 115a are simultaneously formed in one mask process (first mask process) using a multiple exposure mask. Hereinafter, the first mask process will be described in detail with reference to the accompanying drawings. .

6A to 6H are cross-sectional views illustrating a first mask process according to an exemplary embodiment of the present invention shown in FIGS. 4A and 5A.

As shown in FIG. 6A, the first conductive layer 130, the first insulating layer 115, the amorphous silicon thin film 120, and the n + amorphous silicon thin film are formed on the entire surface of the array substrate 110 made of a transparent insulating material such as glass. 125).

In this case, the first conductive layer 130 may include aluminum (Al), aluminum alloy (Al alloy), to form a gate electrode, a gate line, a common electrode, a pixel electrode, a common line, a pixel line, and a gate pad line. Low resistance opaque conductive materials such as tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and the like may be used. In addition, the first conductive film may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

6B, after forming the first photosensitive layer 170 made of a photosensitive material such as a photoresist on the entire surface of the array substrate 110, the multi-exposure mask 180 according to the embodiment of the present invention. Light is selectively irradiated to the first photoresist film 170 through.

In this case, the multiple exposure mask 180 has a first transmission region I for transmitting all of the irradiated light and a second transmission region II having half-tone portions and half-tones to transmit only a part of the light and block some of the light. A third transmission region III consisting of a portion and a slit portion and a blocking region IV for blocking all irradiated light are provided, and only light transmitted through the multiple exposure mask 180 is irradiated to the first photosensitive film 170. Will be.

Subsequently, after developing the first photoresist layer 170 exposed through the multiple exposure mask 180, as illustrated in FIG. 6C, the blocking region IV, the second transmission region II, and the third photoresist layer 3 are exposed. The first photoresist pattern 170a to the ninth photoresist pattern 170i having a predetermined thickness remain in the region where all light is partially blocked or partially blocked through the transmission region III, and the first transmission region through which all the light is transmitted ( In I), the first photoresist film is completely removed to expose the surface of the n + amorphous silicon thin film 125.

In this case, the first photoresist pattern 170a and the second photoresist pattern 170b formed in the blocking region IV may include a third photoresist pattern formed through the second transmission region II and the third transmission region III. 170c) to thicker than the ninth photosensitive film pattern 170i. In addition, the third photoresist pattern 170c formed through the third transmission region III may be smaller than the fourth photoresist pattern 170c to ninth photoresist pattern 170i formed through the second transmission region II. The first photoresist film is completely removed in a region formed thickly and in which all light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. Type photoresist may be used.

Next, as shown in FIG. 6D, the first conductive film, the first insulating film, and the amorphous silicon formed under the mask using the first photosensitive film pattern 170a to ninth photosensitive film pattern 170i formed as described above as a mask. When the thin film and the n + amorphous silicon thin film are selectively removed, a gate electrode 121, a gate line (not shown), a common line 108L, and a pixel formed of the first conductive layer may be formed in the pixel portion of the array substrate 110. An electrode 118 and a common electrode 108 are formed, and a gate pad line 116p formed of the first conductive layer is formed in the gate pad portion of the array substrate 110.

In this case, for example, the first insulating layer pattern including the first insulating layer, the amorphous silicon thin film, and the n + amorphous silicon thin film on the gate electrode 121 and patterned in substantially the same shape as the gate electrode 121, respectively. 115 ′, the first amorphous silicon thin film pattern 120 ′ and the first n + amorphous silicon thin film pattern 125 ′ are formed.

In addition, the first insulating film pattern 115 formed of the first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film on the common line 108L and patterned in substantially the same shape as the common line 108L, respectively. "), The second amorphous silicon thin film pattern 120" and the second n + amorphous silicon thin film pattern 125 "are formed.

In addition, the first insulating layer pattern 115 including the first insulating layer, the amorphous silicon thin film, and the n + amorphous silicon thin film formed on the pixel electrode 118 and patterned in substantially the same shape as the pixel electrode 118. '"), The third amorphous silicon thin film pattern 120'" and the third n + amorphous silicon thin film pattern 125 '"are formed.

In addition, the first insulating layer pattern 115 formed of the first insulating layer, the amorphous silicon thin film, and the n + amorphous silicon thin film on the common electrode 108 and patterned in substantially the same shape as the common electrode 108. ""), The fourth amorphous silicon thin film pattern 120 "" and the fourth n + amorphous silicon thin film pattern 125 "" are formed.

In addition, the first insulating layer pattern including the first insulating layer, the amorphous silicon thin film, and the n + amorphous silicon thin film on the gate pad line 116p and patterned in substantially the same shape as the gate pad line 116p, respectively. 115 '″ ″, the fifth amorphous silicon thin film pattern 120' ″ ″, and the fifth n + amorphous silicon thin film pattern 125 '″ ″ are formed.

Subsequently, when an ashing process of removing a part of the thickness of the first photoresist pattern 170a to ninth photoresist pattern 170i is performed, as illustrated in FIG. 6E, the second transmission region II is formed. The fourth to ninth photoresist patterns of the photoresist are completely removed.

In this case, the first photoresist pattern to the third photoresist pattern include the tenth photoresist pattern 170a 'to the twelfth photoresist pattern 170c' whose thickness is removed by the thickness of the fourth photoresist pattern to the ninth photoresist pattern. Only the source and drain regions corresponding to (IV) and the third transmission region (III) remain in the channel region between the source region and the drain region.

Thereafter, as shown in FIG. 6F, the first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film formed under the tenth photosensitive film pattern 170a 'to the twelfth photosensitive film pattern 170c' as a mask are formed. When selectively removed, the active pattern 124 made of the amorphous silicon thin film is formed on the pixel portion of the array substrate 110 and the common line 108L, the pixel electrode 118 and the common electrode 108 are formed. And the surface of the gate pad line 116p is exposed.

In this case, a gate insulating film 115a formed of the first insulating film and patterned substantially the same as the active pattern 124 is formed under the active pattern 124.

In addition, a sixth n + amorphous silicon thin film pattern 125 ″ ″ ″ formed of the n + amorphous silicon thin film and patterned in substantially the same shape as the active pattern 124 is formed on the active pattern 124.

Subsequently, when an ashing process is performed to remove a portion of the thicknesses of the tenth photoresist pattern 170a ′ to the twelfth photoresist pattern 170c ′, as shown in FIG. 6G, the third transmission region III may be formed. The twelfth photosensitive film pattern is completely removed.

In this case, the tenth photoresist pattern and the eleventh photoresist pattern correspond to the blocking region III by the thirteenth photoresist pattern 170a ″ and the fourteenth photoresist pattern 170b ″, in which the thickness of the twelfth photoresist pattern is removed. Only remains in the source and drain regions.

Thereafter, as shown in FIG. 6H, a partial region of the n + amorphous silicon thin film is selectively removed by using the remaining thirteenth photoresist pattern 170a ″ and the fourteenth photoresist pattern 170b ″ as a mask. An ohmic contact layer 125n formed of the n + amorphous silicon thin film and ohmic contact between the source / drain region and the source / drain electrode of the active pattern 124 is formed on the upper portion of the active pattern 124.

Next, as illustrated in FIGS. 4B and 5B, the gate electrode 121, the gate line 116, the common electrode 108, the pixel electrode 118, the common line 108L, and the pixel line 118l are formed. After forming the passivation layer 115b on the entire surface of the array substrate 110 on which the gate pad line 116p, the active pattern 124, and the gate insulating layer 115a are formed, the photolithography process according to the embodiment of the present invention (second step) By applying the mask process and the lift-off process, the source electrode 122, the drain electrode 123, the data line 117, and the pixel line 118L are formed in the pixel portion in one mask process, and the data pad portion and The data pad electrode 127p and the gate pad electrode 126p are formed in the gate pad portion, respectively.

In this case, the gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c formed in the passivation layer 115b, and the plurality of pixel electrodes 118 are connected to the gate pad line 118p. The drain electrode 123 is electrically connected to the drain electrode 123 through the connection electrode 118a of the pixel line 118L.

In this case, a second electrode is formed under the source electrode 122, the drain electrode 123, the data line 117, the pixel line 118L, the data pad electrode 127p, and the gate pad electrode 126p. The source electrode pattern 122 ', the drain electrode pattern 123', the data line pattern 117 ', the pixel line pattern 118L', the data pad line 117p, and the gate pad electrode pattern 126p 'made of a conductive film. ) Is formed.

In this case, the source electrode pattern 122 ′ is electrically connected to the source region of the active pattern 124 through the first contact hole 140 a formed in the passivation layer 115b, and the drain electrode pattern 123 ′. ) Is electrically connected to the drain region of the active pattern 124 through the second contact hole 140b formed in the passivation layer 115b.

In this case, the second mask process uses a half-tone mask and a lift-off process so that the source electrode 122, the drain electrode 123, the data line 117, and the pixel line 118L are processed through one mask process. In addition, the data pad electrode 127p, the gate pad electrode 126p, the data pad line 117p, and the passivation layer 115b can be formed. Hereinafter, the second mask process will be described in detail with reference to the accompanying drawings.

7A to 7G are cross-sectional views illustrating a second mask process according to an exemplary embodiment of the present invention shown in FIGS. 4B and 5B.

As shown in FIG. 7A, the gate electrode 121, the gate line 116, the common electrode 108, the pixel electrode 118, the common line 108L, the pixel line 118l, and the gate pad line ( A passivation layer 115b is formed on the entire surface of the array substrate 110 on which the active pattern 124 and the gate insulating layer 115a are formed.

As shown in FIG. 7B, the second photosensitive layer 270 made of photosensitive material such as photoresist is formed on the array substrate 110 on which the passivation layer 115b is formed. Light is selectively irradiated to the second photosensitive layer 270 through a tone mask 280.

In this case, the half-tone mask 280 blocks the first transmission region I through which all of the irradiated light is transmitted, the second transmission region II through which only a part of the light is transmitted and partly blocks and blocks all the irradiated light. The region III is provided, and only the light passing through the half-tone mask 280 is irradiated to the second photosensitive film 270.

Subsequently, after the second photoresist layer 270 exposed through the half-tone mask 280 is developed, light is passed through the blocking region III and the second transmission region II, as shown in FIG. 7C. The first photoresist pattern 270a to the seventh photoresist pattern 270g having a predetermined thickness remain in the blocked or partially blocked region, and the second photoresist is disposed in the first transmission region I through which all light is transmitted. It is completely removed to expose the surface of the protective film 115b.

In this case, the first photoresist pattern 270a to the fourth photoresist pattern 270d formed in the blocking region III may include the fifth photoresist pattern 270e and the seventh photoresist pattern 270g formed through the second transmission region II. It is thicker than). In addition, the second photoresist film is completely removed in the region where all the light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a resist.

Next, as shown in FIG. 7D, the first photoresist pattern 270a to the seventh photoresist pattern 270g formed as described above is used as a mask to selectively remove a partial region of the protective film 115b formed thereunder. In this case, the first hole H1 exposing a part of the surface of the array substrate 110 and the first contact hole exposing a part of the ohmic contact layer 125n may be exposed in the pixel portion of the array substrate 110. 140a and a second contact hole 140b are formed, and the second hole H2 and the gate pad exposing the surface of the array substrate 110 to the data pad portion and the gate pad portion of the array substrate 110. The third contact hole 140c exposing a part of the line 116p is formed.

Subsequently, when the ashing process of removing a part of the thickness of the first photoresist pattern 270a to the seventh photoresist pattern 270g is performed, as illustrated in FIG. 7E, a fifth portion of the second transmission region II is formed. The photoresist pattern to the seventh photoresist pattern are completely removed.

In this case, the first photoresist pattern to the fourth photoresist pattern include the eighth photoresist pattern 270a 'to the eleventh photoresist pattern 270d' from which the thickness of the fifth photoresist pattern to the seventh photoresist pattern is removed. It remains only in the area corresponding to (III). In this case, the first transmission region I and the second transmission region II, in which the eighth photoresist pattern 270a 'through the eleventh photoresist pattern 270d' remain, are subjected to a lift-off process to be described later. A source electrode, a drain electrode, a data line, a pixel line, a data pad electrode, and a gate pad electrode are formed in the region.

Thereafter, as illustrated in FIG. 7F, a second conductive layer 150 and a third conductive layer 160 are formed on the entire surface of the array substrate 110.

In this case, the second conductive layer 150 may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy, and the third conductive layer 160 may be made of indium tin. It may be made of a transparent conductive material having excellent transmittance, such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the third conductive layer 160 may be made of a molybdenum alloy such as MoTi.

In addition, by further forming a conductive layer made of a conductive material such as MoTi under the second conductive film 150, it is possible to improve the adhesion to the array substrate 110 made of glass.

As shown in FIG. 7G, the eighth to eleventh photoresist patterns are removed through a lift-off process, wherein portions other than the first transmission region I and the second transmission region II are removed. The second conductive film and the third conductive film remaining in the substrate are removed together with the eighth photosensitive film pattern to the eleventh photosensitive film pattern.

As described above, the source electrode 122, the drain electrode 123, the data line 117, and the pixel line 118L formed of the third conductive layer are formed in the pixel portion in one mask process, and the data pad portion and the gate pad are formed. The data pad electrode 127p and the gate pad electrode 126p made of the third conductive film are respectively formed in the portion.

In this case, the source electrode 122, the drain electrode 123, the data line 117, the pixel line 118L, the data pad electrode 127p, and the gate pad electrode 126p made of a third conductive layer, which is a transparent conductive material. A source electrode pattern 122 ', a drain electrode pattern 123', a data line pattern 117 ', a pixel line pattern 118L', and a data pad, each of which is formed of the second conductive layer, which is a low resistance opaque conductive material, respectively. A line 117p and a gate pad electrode pattern 126p 'are formed.

In this case, the source electrode pattern 122 ′ is electrically connected to the source region of the active pattern 124 through the first contact hole 140 a formed in the passivation layer 115b, and the drain electrode pattern 123 ′. ) Is electrically connected to the drain region of the active pattern 124 through the second contact hole 140b formed in the passivation layer 115b.

In addition, the gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c formed in the passivation layer 115b, and the data line pattern 117 'is connected to the gate pad electrode 126p. The protection layer 115b of the pixel portion is formed in the first hole, and the data pad line 117p is formed in the second hole from which the protection layer 115b of the data pad portion is removed.

Here, the source electrode pattern 122 ', the drain electrode pattern 123', the data line pattern 117 ', the pixel line pattern 118L', and the data pad line are formed of the second conductive layer as the low resistance opaque conductive material. The source electrode 122 and the drain electrode 123 formed of the third conductive layer 117p and the gate pad electrode pattern 126p 'substantially transmit signals. ), The data line 117, the pixel line 118L, the data pad electrode 127p and the gate pad electrode 126p are respectively the source electrode pattern 122 ′, the drain electrode pattern 123 ′, and the data line pattern. 117 ', the pixel line pattern 118L', the data pad line 117p, and the gate pad electrode pattern 126p '.

In this case, a portion of the pixel line 118L overlaps a portion of the common line 108L below the passivation layer 115b to form a storage capacitor. As such, since an active pattern and a gate insulating layer do not exist between the pixel line 118L and the common line 108L constituting the storage capacitor, the storage capacitance can be increased, thereby improving the aperture ratio.

As described above, in the exemplary embodiment of the present invention, the array substrate including the thin film transistor may be manufactured in two mask processes, thereby providing an effect of reducing the manufacturing process and cost. In particular, a process reduction effect of about 35% can be achieved compared to the existing four mask process.

In the two mask process according to the embodiment of the present invention, since the active pattern and the data wiring are formed through different mask processes and the active pattern is formed in an island form, the active pattern does not exist under the data wiring. It is possible to solve the aperture ratio loss problem and the light leakage problem in the 4 mask process.

In addition, since the active pattern and the gate insulating layer do not exist between the pixel line and the common line and are formed as a protective film, the capacitance of the storage capacitor can be increased, thereby increasing the aperture ratio compared to the existing structure.

The array substrate according to the exemplary embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor, the gate line, and the data line are attached to the color filter substrate. As a result, a black matrix to prevent light leakage and a color filter for realizing red, green, and blue colors are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

Here, as described above, the embodiment of the present invention describes an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern as an example, but the present invention is not limited thereto, and the present invention is polycrystalline with the active pattern. The same applies to polycrystalline silicon thin film transistors using silicon thin films.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

4A and 4B are cross-sectional views sequentially showing manufacturing processes taken along lines IIIa-IIIa ', IIIb-IIIb, and IIIc-IIIc of the array substrate shown in FIG.

5A and 5B are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

6A to 6H are cross-sectional views illustrating in detail a first mask process according to an exemplary embodiment of the present invention shown in FIGS. 4A and 5A.

7A to 7G are cross-sectional views illustrating in detail a second mask process according to the embodiment of the present invention shown in FIGS. 4B and 5B.

DESCRIPTION OF REFERENCE NUMERALS

108: common electrode 110: array substrate

116: gate line 116p: gate pad line

117: data line 117p: data pad line

118: pixel electrode 121: gate electrode

122 source electrode 123 drain electrode

126p: gate pad electrode 127p: data pad electrode

Claims (15)

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode, a gate line, a pixel electrode, and a common electrode on the pixel portion of the first substrate through a first mask process, and forming a gate pad line on the gate pad portion of the first substrate; An active pattern divided into a source region, a drain region, and a channel region is formed on the gate electrode with the gate insulating layer interposed using the first mask process, and an ohmic contact is formed on the source region and the drain region of the active pattern. Forming a layer; Forming a protective film on the first substrate; A source / drain electrode electrically connected to the source / drain regions of the active pattern is formed in the pixel portion of the first substrate through a second mask process, and a data line is defined to cross the gate line to define the pixel region. Making; Forming a data pad electrode and a gate pad electrode on the data pad portion and the gate pad portion of the first substrate using the second mask process; And And attaching the first substrate and the second substrate to each other. 2. The method of claim 1, further comprising forming a common line on the pixel portion of the first substrate by using the first mask process. The method of claim 1, wherein the first mask process Forming a first conductive film, a first insulating film, an amorphous silicon thin film, and an n + amorphous silicon thin film on the first substrate; To block all of the irradiated light and a second transmission region made of half-tone portions, a third transmission region made of half-tone portions and a slit portion, to transmit only a part of the light and to block a portion of the light to transmit all the irradiated light Forming a first through ninth photoresist pattern on the first substrate by applying a multiple exposure mask having a blocking region; The first conductive film, the first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film are selectively removed by using the first photoresist pattern through the ninth photoresist pattern, and the first conductive layer is formed on the pixel portion of the first substrate. Forming a gate electrode, a gate line, a pixel electrode, and a common electrode, and forming a gate pad line formed of the first conductive layer on a gate pad of the first substrate; Removing the fourth photoresist pattern to the ninth photoresist pattern through an ashing process and simultaneously removing a portion of the thickness of the first photoresist pattern to the third photoresist pattern to form the tenth photoresist pattern to the twelfth photoresist pattern; The first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film are selectively removed by using the tenth to twelve photosensitive film patterns as masks, and the first insulating film and the amorphous silicon thin film are respectively formed in the pixel portion of the first substrate. Forming a gate insulating film and an active pattern; Forming a thirteenth photoresist pattern and a fourteenth photoresist pattern by removing the twelfth photoresist pattern and a portion of the tenth photoresist pattern and the eleventh photoresist pattern through an ashing process; And Selectively removing a portion of the n + amorphous silicon thin film using the 13th photosensitive film pattern and the 14th photosensitive film pattern as a mask to form an ohmic contact layer formed of the n + amorphous silicon thin film on the source region and the drain region of the active pattern Method of manufacturing a liquid crystal display device comprising the step. The method of claim 2, further comprising forming a pixel line constituting a storage capacitor by overlapping a portion of the common line with the passivation layer interposed between the pixel portion of the first substrate by using the second mask process. Method of manufacturing a liquid crystal display device comprising the The method of claim 1, wherein the second mask process A first half-tone mask is provided on the first substrate by applying a half-tone mask having a first transmission region that transmits all of the irradiated light, a second transmission region that transmits only a portion of the light and blocks a portion of the light, and a blocking region that blocks all the irradiated light. Forming a photoresist pattern to a seventh photoresist pattern; The first hole and the ohmic contact layer exposing a part of the surface of the first substrate to the pixel portion of the first substrate by selectively removing the partial region of the passivation layer using the first to seventh photoresist pattern as a mask. Forming a first contact hole and a second contact hole to expose a portion of the second contact hole, and a portion of the second hole and the gate pad line exposing the surface of the first substrate to the data pad portion and the gate pad portion of the first substrate. Forming a third contact hole to expose; Forming the eighth photoresist pattern through the eleventh photoresist pattern by removing the fifth photoresist pattern and the seventh photoresist pattern through an ashing process and simultaneously removing a portion of the thickness of the first photoresist pattern and the fourth photoresist pattern; Forming a second conductive film and a third conductive film on the entire surface of the first substrate; And The pixel portion of the first substrate by removing the eighth to eleventh photoresist patterns together with the second and third conductive layers deposited on the eighth to eleventh photoresist patterns through a lift-off process. A source electrode, a drain electrode, and a data line formed of the third conductive film are formed on the substrate; and a data pad electrode and a gate pad electrode made of the third conductive film are formed on the data pad portion and the gate pad portion of the first substrate, respectively. Method of manufacturing a liquid crystal display device comprising the step of. 6. The method of claim 5, wherein the second conductive film is formed of a low resistance opaque conductive material. The method of claim 5, wherein the third conductive layer is formed of a transparent conductive material. 6. The source electrode pattern, the drain electrode pattern, and the data line pattern of claim 5, wherein the source electrode, the drain electrode, the data line and the data pad electrode and the gate pad electrode formed of the third conductive film are respectively formed under the second conductive film. And a data pad line and a gate pad electrode pattern are formed. The method of claim 8, wherein the data line pattern is formed in the first hole from which the passivation layer of the pixel portion is removed, and the data pad line is formed in the second hole from which the passivation layer of the data pad portion is removed. Method of manufacturing a liquid crystal display device. The method of claim 5, wherein the source electrode and the drain electrode are electrically connected to the source region and the drain region of the active pattern through the first contact hole and the second contact hole, respectively. . A first substrate; A gate electrode, a gate line, a pixel electrode, and a common electrode formed on the first substrate; An active pattern formed on the gate electrode through a gate insulating layer and divided into a source region, a drain region, and a channel region; An ohmic contact layer formed on the source region and the drain region of the active pattern; A first hole exposing a portion of the first substrate and a first contact hole and a second contact hole exposing a source region and a drain region of the active pattern, respectively, formed on the first substrate on which the active pattern is formed; Protective film; Source / drain electrodes electrically connected to the source / drain regions of the active pattern; A data line crossing the gate line to define a pixel area; And And a second substrate bonded to and opposed to the first substrate. The liquid crystal display of claim 11, wherein the source electrode, the drain electrode, and the data line are made of a conductive material such as indium tin oxide (ITO) or MoTi, which is highly resistant to corrosion. 12. The liquid crystal of claim 11, further comprising a source electrode pattern, a drain electrode pattern, and a data line pattern formed under the source electrode, the drain electrode, and the data line and made of a low resistance conductive material having high conductivity. Display. The liquid crystal display of claim 13, wherein the data line pattern is formed in the first hole. 12. The liquid crystal display of claim 11, further comprising a pixel line disposed in a direction parallel to the gate line and connected to the pixel electrode to electrically connect the drain electrode and the pixel electrode.

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