KR101643267B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A liquid crystal display device and a manufacturing method thereof according to the present invention are characterized in that a gate wiring, an active pattern, a common electrode and a pixel electrode are formed using a multiple exposure mask (first mask), and a half-tone mask And forming a data line, a pad electrode, and a protective film by using the process. The present invention reduces the number of masks, thereby simplifying the manufacturing process and reducing manufacturing cost.

Particularly, in the liquid crystal display device and the method of manufacturing the same according to the present invention, when patterning a gate wiring composed of multiple layers of a transparent conductive film and an opaque conductive film by using the over-etching property of the conductive film according to wet etching, The transmissivity of the pixel region can be improved by forming the common electrode and the pixel electrode of the pattern.

Liquid crystal display, multiple exposure mask, half-tone mask, lift-off

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can simplify a manufacturing process by reducing the number of masks, .

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using a thin film transistor (TFT) as a switching element.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constructed as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal display panel, (Not shown) formed on the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required ought.

2A to 2E are cross-sectional views sequentially showing the steps of manufacturing an array substrate in the liquid crystal display device shown in Fig.

As shown in Fig. 2A, a gate electrode 21 made of an opaque conductive film is formed on the array substrate 10 by using a photolithography process (first mask process).

Next, as shown in FIG. 2B, a first insulating film 15a, an amorphous silicon thin film and an n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed The amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form an active pattern 24 made of the amorphous silicon thin film on the gate electrode 21.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active pattern 24 is formed on the active pattern 24.

Then, as shown in FIG. 2C, an opaque conductive film is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a third mask process) The source electrode 22 and the drain electrode 23 are formed. At this time, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed by the third mask process, and the ohmic-and-amorphous silicon thin film pattern is formed between the active pattern 24 and the source / drain electrodes 22, Thereby forming an ohmic contact layer 25 '.

2d, a second insulating layer 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process A part of the second insulating film 15b is removed through the contact hole 40 to expose a part of the drain electrode 23.

Finally, as shown in FIG. 2E, a transparent conductive film is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (fifth mask process) A pixel electrode 18 electrically connected to the pixel electrode 23 is formed.

As described above, the fabrication of the array substrate including the thin film transistor requires at least five photolithography processes for patterning the gate electrode, the active pattern, the source / drain electrode, the contact hole, and the pixel electrode.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as a photoresist application, an exposure, and a development process. There is a disadvantage that it falls.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

At this time, a technology has been developed in which an active pattern and a source / drain electrode are formed by a single mask process using a half-tone mask, thereby manufacturing an array substrate by a total of four mask processes.

However, the liquid crystal display device of the above structure is fabricated by patterning the active pattern and the source / drain electrodes simultaneously through two etching processes using a half-tone mask, and thus the data lines, that is, the source electrode and the drain electrode, The protruded active pattern remains.

The active pattern is made of a pure amorphous silicon thin film. At this time, the active pattern under the data line is exposed to the lower backlight except the gate line, that is, the portion covered by the gate electrode and the gate line, A photocurrent is generated. At this time, due to the minute flickering of the backlight, the amorphous silicon thin film reacts finely and is repeatedly activated and deactivated, thereby causing a change in the photocurrent. Such a photocurrent component is coupled together with a signal flowing to neighboring pixel electrodes to distort the movement of the liquid crystal located on the pixel electrodes. As a result, wavy noise is generated on the screen of the liquid crystal display device in which a thin line of a wave pattern appears.

In addition, the active pattern located below the data line protrudes to both sides of the data line by a predetermined distance, so that the aperture ratio of the liquid crystal display device decreases as the aperture region of the pixel portion is eroded by the protruded distance.

An object of the present invention is to provide a method of manufacturing a liquid crystal display device in which an array substrate of a liquid crystal display device is manufactured by two mask processes.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same that prevent wave noise by forming an active pattern in an island shape.

It is still another object of the present invention to provide a liquid crystal display device and a method of manufacturing the same that improve the transmissivity of a pixel region by forming a common electrode and a pixel electrode of a fine pattern with a transparent conductive film.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to an aspect of the present invention, there is provided a liquid crystal display device including a gate electrode and a gate line made of a non-transparent conductive material on a first substrate, a gate electrode pattern made of a transparent conductive material below the gate line, And a second substrate on the first substrate, the ohmic contact layer on the source region and the drain region being exposed on a first substrate having a common electrode, a pixel electrode, and an active pattern formed on the pixel region of the first substrate, A protective film having a contact hole, a second contact hole, and a first hole exposing a part of the surface of the first substrate, the opaque conductive material having a first contact hole and a second contact hole, A source electrode pattern and a drain electrode pattern electrically connected to the ohmic-contact layer on the drain region, And a source electrode, a drain electrode, and a data line made of a transparent conductive material are formed over the source electrode pattern, the drain electrode pattern, and the data line pattern, And the like.
At this time, the liquid crystal display of the present invention includes an active pattern formed on the gate electrode with a gate insulating film interposed therebetween, the active pattern being divided into a source region, a drain region, and a channel region, and an active pattern formed on the source region and the drain region of the active pattern, - contact layer.

The method of manufacturing a liquid crystal display of the present invention includes the steps of forming a first conductive film pattern to a fifth conductive film pattern with a second conductive film on a first substrate by applying a multiple exposure mask (first mask process) Forming a gate line and a pixel electrode line by forming a common line with a gate electrode having a width smaller than that of each of the first conductive film pattern and the second conductive film pattern and forming a gate line and a pixel electrode line in the pixel region of the first substrate, A step of forming a common electrode and a pixel electrode as a conductive film, forming a gate insulating film and an active pattern made of a first insulating film and an amorphous silicon thin film in the pixel portion of the first substrate, Forming an ohmic contact layer with the n + amorphous silicon thin film on the first passivation layer; selectively etching a portion of the passivation layer through a half-tone mask (second mask process) Forming a first contact hole and a second contact hole for exposing a part of the ohmic-contact layer, removing the first contact hole and the second contact hole in a state where the photoresist pattern for the second mask used in the second mask process remains, Forming a third opaque conductive film and a transparent fourth conductive film on the first conductive film and the second conductive film by a lift-off process; And a fourth conductive film formed on the pixel portion of the first substrate to selectively electrically connect the ohmic-contact layer on the source / drain region through the first / second contact hole Forming a data line that intersects the source / drain electrodes and the gate line to define the pixel region; and attaching the first substrate and the second substrate to each other. And it may be configured.
The first mask process may include forming a photoresist pattern for the first mask on the first substrate, forming a second conductive film, a first insulating film, an amorphous silicon thin film, and an n + amorphous silicon thin film Forming a first conductive film pattern to a fifth conductive film pattern by using the second conductive film in a pixel portion and a gate pad portion of the first substrate; The first conductive film is selectively removed and a part of the second conductive film is removed to form a second conductive film on the pixel portion of the first substrate, Forming a gate line and a pixel electrode line in the pixel region of the first substrate, forming a common line between the gate electrode and the common electrode, Forming an amorphous silicon thin film on the first insulating film; selectively etching and removing the first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film using the photoresist pattern for the first mask as a mask; Forming a gate insulating film made of the first insulating film and the amorphous silicon film and an active pattern on the pixel portion of the first substrate, again ashing the photoresist pattern for the first mask, Selectively removing a part of the n + amorphous silicon thin film using the photoresist pattern for the first mask as a mask to form an ohmic contact layer with the n + amorphous silicon thin film on the source region and the drain region of the active pattern, .

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention reduce the number of masks used in the manufacture of thin film transistors, thereby reducing the manufacturing process and cost. In particular, the 10-step process can be omitted in comparison with the existing 4-mask process, and a process reduction effect of about 38% can be obtained.

In addition, since the active pattern is formed in an island shape, the active pattern is not present in the lower portion of the data line, thereby solving the problem of the ratio noise phenomenon and the aperture ratio loss in the conventional four mask process. .

In addition, since the active pattern and the gate insulating film do not exist between the common line and the pixel line, the storage capacitance can be increased and the aperture ratio can be improved. Particularly, by forming the common electrode and the pixel electrode of a fine pattern with the transparent conductive film, the transmittance of the pixel region can be improved and the image quality is improved.

Hereinafter, preferred embodiments of a liquid crystal display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a plan view schematically showing a part of an array substrate of a liquid crystal display according to the first embodiment of the present invention. For convenience of explanation, one pixel including a gate pad portion, a data pad portion, and a thin- Respectively.

In an actual liquid crystal display device, N number of gate lines and M number of data lines intersect to form MxN pixels, but one pixel is shown in the figure for simplicity.

In this case, although a liquid crystal display device of the in-plane switching (IPS) type in which the liquid crystal molecules are driven in the horizontal direction with respect to the substrate and the viewing angle is increased to 170 degrees or more is illustrated as an example, But is not limited thereto.

As shown in the figure, a gate line 116 and a data line 117 'are formed on the array substrate 110 on the array substrate 110 in the first embodiment of the present invention, . A thin film transistor, which is a switching element, is formed at an intersection of the gate line 116 and the data line 117 '. A finger (not shown) for driving a liquid crystal (not shown) generates a transverse electric field in the pixel region. ) And the pixel electrode 118 are alternately arranged.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 'connected to the data line 117' and a drain electrode 123 'electrically connected to the pixel electrode 118. ). The thin film transistor includes an active pattern (not shown) for forming a conductive channel between the source electrode 122 'and the drain electrode 123' by a gate voltage supplied to the gate electrode 121 .

Reference numeral 125n denotes an ohmic contact layer for ohmic contact between a source / drain region of the active pattern and the source / drain electrodes 122 'and 123'. At this time, the source electrode 122 'and the drain electrode 123' are respectively connected to the source and drain regions of the active pattern through a first contact hole 140a and a second contact hole 140b formed in a protective film (not shown) Region. ≪ / RTI >

At this time, the insulating material constituting the protective layer is deposited between the ohmic-contact layers 125n to prevent the back channel of the thin film transistor from being exposed after the patterning of the source / drain electrodes 122 'and 123' do.

A part of the source electrode 122 'extends in one direction to constitute a part of the data line 117', and a part of the drain electrode 123 'extends toward the pixel region to pass through the pixel line 118L' And is electrically connected to the pixel electrode 118.

A gate pad electrode 126p 'and a data pad electrode 127p', which are electrically connected to the gate line 116 and the data line 117 ', respectively, are formed in the edge region of the array substrate 110, And transmits a scan signal and a data signal applied from an external driving circuit (not shown) to the gate line 116 and the data line 117 ', respectively.

That is, the gate line 116 and the data line 117 'extend to the driving circuit portion and are connected to a corresponding gate pad line 116p and a data pad line (not shown) The data pad lines are respectively supplied with a scanning signal from a driving circuit or a data signal through a gate pad electrode 126p 'and a data pad electrode 127p', which are electrically connected to the gate pad line 116p and a data pad line, respectively .

Reference numeral 140c denotes a third contact hole formed in the passivation layer. The gate pad electrode 126p 'is electrically connected to the gate pad line 116p through the third contact hole 140c do.

As described above, in the pixel region, the common electrode 108 and the pixel electrode 118 for generating a transverse electric field are alternately arranged.

At this time, a common line 108L arranged in a direction substantially parallel to the gate line 116 is formed in the lower part of the pixel region, and the common electrode 108 is formed such that one side thereof is connected to the common line 108L.

The plurality of pixel electrodes 118 are connected to the pixel electrode line 1181 arranged in a direction substantially parallel to the gate line 116 and the connection electrode 118a of the pixel line 118L ' And is electrically connected to the drain electrode 123 '.

The common line 108L and the pixel electrode line 1181 are formed of an opaque second conductive film constituting a gate wiring 121 or a gate line 116, The line 118L 'may be formed of a transparent fourth conductive film constituting the data line, that is, the source electrode 122' and the drain electrode 123 'and the data line 117'.

At this time, under the gate electrode 121, the gate line 116, the common line 108L, the pixel electrode line 1181 and the gate pad line 116p made of the opaque second conductive film, A gate line pattern (not shown), a common line pattern (not shown), a pixel electrode line pattern (not shown), and a gate pad line pattern (not shown).

Further, under the source electrode 122 ', the drain electrode 123', the data line 117 ', the pixel line 118L' and the data pad electrode 127p ', which are made of the transparent fourth conductive film, A source electrode pattern (not shown), a drain electrode pattern (not shown), a data line pattern (not shown), a pixel line pattern (not shown), and a data pad electrode pattern (not shown) have.

At this time, a part of the pixel line 118L 'is overlapped with a part of the common line 108L under the protective film to form a storage capacitor Cst. The storage capacitor Cst serves to keep the voltage applied to the liquid crystal capacitor constant until the next signal is received. The storage capacitor Cst has effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

Here, the liquid crystal display according to the first embodiment of the present invention includes a plurality of exposure masks, that is, a blocking region made up of a dark portion, a first transmitting region transmitting all light, a second transmitting region having half- A gate wiring, an active pattern, a common electrode, and a pixel electrode are formed by a single mask process using a multi-tone mask of a third transmission region to which a further half-tone mask or a diffraction mask The data line and the pad electrode and the protective film are formed by a single mask process using a lift-off process and a protective film, so that an array substrate can be manufactured by a total of two mask processes .

In this case, in the first embodiment of the present invention, the gate wiring is composed of a multilayer structure of a transparent first conductive film and a non-transparent second conductive film, and the common electrode and the pixel electrode are opaque to the transparent conductive film The upper transparent conductive film is removed using the over-etching property of the conductive film according to the wet etching when patterning the gate wiring composed of multiple layers of the film, and the transparent conductive film on the lower side is over-etched to form a fine pattern made of a transparent conductive film .

In addition, the data line and the pad electrode may have a multi-layered structure of an opaque third conductive film and a transparent fourth conductive film, and the fourth conductive film constituting the upper layer of the multi-layered structure may be formed of ITO (Indium Tin Oxide) Transparent conductive material or a conductive material having a high resistance to corrosion such as MoTi and protects the data line and the pad electrode, thereby minimizing the number of processes. This can be achieved in detail through the following manufacturing method of a liquid crystal display device Explain.

4A and 4B are cross-sectional views sequentially showing a manufacturing process according to lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc of the array substrate shown in FIG. 3. In the left side, And the array substrate of the data pad portion and the gate pad portion is sequentially formed on the right side.

5A and 5B are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.

As shown in FIGS. 4A and 5A, a first conductive film, a second conductive film, a first insulating film, an amorphous silicon thin film and an n + amorphous silicon thin film are formed on an entire surface of an array substrate 110 made of a transparent insulating material such as glass The gate line 121, the gate line 116, and the common line (not shown) made of the second conductive film are formed in the pixel portion of the array substrate 110 by selectively patterning through a photolithography process (first mask process) A common electrode 108 and a pixel electrode 118 are formed in the pixel region of the array substrate 110 and the gate electrode 121 and the pixel electrode line 1181, An active pattern 124 made of the amorphous silicon thin film is formed on the gate insulating film 115a.

A gate pad line 116p made of the second conductive film is formed on the gate pad portion of the array substrate 110 and an ohmic contact layer made of the n + amorphous silicon thin film is formed on the active pattern 124 125n.

At this time, a transparent first conductive film is formed under the gate electrode 121, the gate line 116, the common line 108L, the pixel electrode line 1181, and the gate pad line 116p made of the opaque second conductive film A gate line pattern (not shown), a common line pattern 130 ', a pixel electrode line pattern (not shown), and a gate pad line pattern 130' 'are formed.

Here, the gate electrode 121, the gate line 116, the common electrode 108, the pixel electrode 118, the common line 108L, the pixel electrode line 1181, and the gate electrode 121 according to the first embodiment of the present invention, The pad line 116p, the active pattern 124, and the gate insulating film 115a are simultaneously formed by using a single mask process (first mask process) using a multiple exposure mask and an over-etching property of the conductive film according to the wet etching , The first mask process will be described in detail with reference to the drawings.

6A to 6I are cross-sectional views illustrating a first mask process according to the first embodiment of the present invention shown in FIGS. 4A and 5A.

6A, a first conductive layer 130, a second conductive layer 135, a first insulating layer 115, and an amorphous silicon thin film (not shown) are formed on an entire surface of an array substrate 110 made of a transparent insulating material such as glass 120 and an n + amorphous silicon thin film 125 are formed.

Here, the first conductive layer 130 may have a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a common electrode and a pixel electrode. A transparent conductive material can be used.

The second conductive layer 135 may be formed of aluminum (Al), aluminum alloy (Al), tungsten (W), or the like to form a gate electrode, a gate line, ), Copper (Cu), chromium (Cr), molybdenum (Mo) and the like can be used. Also, the second conductive layer may be formed in a multi-layered structure in which two or more low resistance conductive materials are stacked.

6B, a first photoresist layer 170 made of a photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, and then a multiple exposure mask (not shown) according to the first embodiment of the present invention 180 to selectively irradiate the first photoresist layer 170 with light.

At this time, the multiple exposure mask 180 includes a first transmissive region I for transmitting all the irradiated light and a second transmissive region II consisting of a half-tone portion for transmitting only a part of light and blocking a part thereof, And a shielding region IV for shielding all the irradiated light are provided on the first photoresist layer 170 and only the light transmitted through the multiple exposure mask 180 is irradiated to the first photoresist layer 170 .

After the exposure of the first photoresist layer 170 exposed through the multiple exposure mask 180, as shown in FIG. 6C, the blocking regions IV and the second transmissive regions II and third The first to ninth photoresist patterns 170a to 170i having a predetermined thickness remain in a region where light is entirely blocked or partially blocked through the transmissive region III, I), the first photoresist layer is completely removed and the surface of the n + amorphous silicon thin layer 125 is exposed.

At this time, the first photoresist pattern 170a and the second photoresist pattern 170b formed in the blocking region IV are formed in the third photoresist pattern (not shown) formed through the second transmissive region II and the third transmissive region III 170c to the ninth photosensitive film pattern 170i. The third photoresist pattern 170c formed through the third transmissive area III may be formed so as to cover the fourth photoresist pattern 170c through the ninth photoresist pattern 170i formed through the second transmissive area II. And the first photoresist layer is completely removed in a region where light is completely transmitted through the first transmissive region I. This is because the positive photoresist is used and the present invention is not limited thereto, Type photo register may be used.

6D, using the first photoresist pattern 170a to the ninth photoresist pattern 170i formed as described above as a mask, a first insulating film, an amorphous silicon thin film, and an n + amorphous silicon film The first amorphous silicon thin film pattern 120 'to the fourth amorphous silicon thin film pattern 120' '' formed of the amorphous silicon thin film are sequentially formed in the pixel portion of the array substrate 110 And a fifth amorphous silicon thin film pattern 120 '' 'formed of the amorphous silicon thin film is formed on the gate pad portion of the array substrate 110.

At this time, the first amorphous silicon thin film pattern 120 ', the second amorphous silicon thin film pattern 120', the third amorphous silicon thin film pattern 120 '', the fourth amorphous silicon thin film pattern 120 '', A first insulating film pattern 115 ', a second insulating film pattern 115' ', a third insulating film pattern 115' '', and a fourth insulating film pattern 115 '' 'formed of the first insulating film are formed under the amorphous silicon thin film pattern 120' The insulating film pattern 115 "and the fifth insulating film pattern 115" "" are formed.

Also, the first amorphous silicon thin film pattern 120 ', the second amorphous silicon thin film pattern 120', the third amorphous silicon thin film pattern 120 '', the fourth amorphous silicon thin film pattern 120 '', A first n + amorphous silicon thin film pattern 125 ', a second n + amorphous silicon thin film pattern 125', and a third n + amorphous silicon thin film pattern 125 '' formed of the n + amorphous silicon thin film are formed on the amorphous silicon thin film pattern 120 ' A fourth n + amorphous silicon thin film pattern 125 "and a fifth n + amorphous silicon thin film pattern 125" "are formed.

Subsequently, as shown in FIG. 6E, when the second conductive film formed under the first photosensitive film pattern 170a through the ninth photosensitive film pattern 170i is selectively removed, The second insulating film pattern 115 '' 'is formed under the pattern 115', the second insulating film pattern 115 '', the third insulating film pattern 115 '', the fourth insulating film pattern 115 '' ' The first conductive film pattern 140 ', the second conductive film pattern 140' ', the third conductive film pattern 140' '', the fourth conductive film pattern 140 '' ', and the fifth conductive film 140' Pattern 140 ""

At this time, the first conductive film pattern 140 ', the second conductive film pattern 140' ', the third conductive film pattern 140' '', the fourth conductive film pattern 140 '' ' The first insulating film pattern 115 '', the second insulating film pattern 115 '', the third insulating film pattern 115 '' ', and the fourth insulating film pattern 140' '' The width of the fifth insulating film pattern 115 '' 'and the fifth insulating film pattern 115' '' 'can be reduced by about 1.0 to 2.0 μm.

The seventh photosensitive film pattern 170g and the eighth photosensitive film pattern 170h are formed to have a width of 3 to 5 mu m so as to pattern fine common electrodes and pixel electrodes of 2 mu m or less in the pixel region of the array substrate 110. [ And the third conductive film pattern 140 '' and the fourth conductive film pattern 140 '' 'under the second conductive film have a width of about 1 to 4 μm due to the over etching of the second conductive film.

Subsequently, as shown in FIG. 6F, using the first photoresist pattern 170a to the ninth photoresist pattern 170i as a mask, selectively removing the first conductive film formed therebelow, The conductive film is etched to form a gate electrode 121, a gate line (not shown), a common line 108L, and a pixel electrode line (not shown) made of the second conductive film in the pixel portion of the array substrate 110 A common electrode 108 and a pixel electrode 118 are formed in the pixel region of the array substrate 110 and the pixel electrode 118 is formed of the first conductive film and the gate pad portion of the array substrate 110 is formed of the second conductive film The gate pad line 116p is formed.

At this time, a gate electrode pattern made of the transparent first conductive film is formed under the gate electrode 121, the gate line, the common line 108L, the pixel electrode line, and the gate pad line 116p made of the opaque second conductive film (Not shown), a common line pattern 130 ", a pixel electrode line pattern (not shown), and a gate pad line pattern 130 '', respectively.

The first conductive layer may be etched by wet etching. When the first conductive layer is partially etched, a third conductive layer pattern having a width of about 1 to 4 탆 and a fourth conductive layer The film pattern is removed, and the common electrode 108 and the pixel electrode 118, which are formed only of the first conductive film, are formed in the pixel region of the array substrate 110.

At this time, the common electrode 108 and the pixel electrode 118 can have a fine line width of 2 탆 or less irrespective of the resolution of the photolithography process used in the photolithography process.

6G, when the ashing process for removing a part of the thicknesses of the first to ninth photosensitive film patterns 170a to 170i is performed, the second transmissive region II, The ninth photosensitive film pattern to the ninth photosensitive film pattern are completely removed.

In this case, the first to third photoresist patterns to the ninth photoresist pattern may be removed by the tenth photoresist pattern 170a 'to the ninth photoresist pattern 170c' Only the source region and the drain region corresponding to the third transmission region IV and the channel region between the source region and the drain region.

Thereafter, using the remaining tenth photosensitive film pattern 170a 'to the twelfth photosensitive film pattern 170c' as a mask, the first insulating film, the amorphous silicon film, and the n + amorphous silicon film are selectively removed, The active pattern 124 made of the amorphous silicon thin film is formed in the pixel portion of the array substrate 110 and the surface of the common line 108L and the gate pad line 116p is exposed.

At this time, even if the third conductive film pattern and the fourth conductive film pattern are left unremoved on the common electrode 108 and the pixel electrode 118, they are completely removed through the ashing process and the etching process, The surface of the pixel electrode 108 and the pixel electrode 118 are exposed.

A gate insulating layer 115a formed of the first insulating layer and patterned substantially in the same pattern as the active pattern 124 is formed under the active pattern 124. [

In addition, a sixth n + amorphous silicon thin film pattern 125 "" is formed on the active pattern 124 and is patterned to have substantially the same shape as the active pattern 124, which is formed of the n + amorphous silicon thin film .

6H, when the ashing process for removing a part of the thickness of the tenth photoresist pattern 170a 'to the twelfth photoresist pattern 170c' is performed, The 12th photosensitive film pattern is completely removed.

At this time, the tenth photoresist pattern and the 11th photoresist pattern correspond to the blocking area III with the thirteenth photoresist pattern 170a "and the fourteenth photoresist pattern 170b" Only the source region and the drain region are formed.

Thereafter, as shown in FIG. 6I, using the remaining thirteenth photosensitive film pattern 170a "and the fourteenth photosensitive film pattern 170b" as masks, a part of the n + amorphous silicon thin film is selectively removed, An ohmic contact layer 125n which is made of the n + amorphous silicon thin film and ohmic-contacts between the source / drain region of the active pattern 124 and the source / drain electrode is formed on the active layer 124.

Next, as shown in FIGS. 4B and 5B, the gate electrode 121, the gate line 116, the common electrode 108, the pixel electrode 118, the common line 108L, the pixel electrode line 1181 A protective film 115b is formed on the entire surface of the array substrate 110 on which the gate pad line 116p, the active pattern 124 and the gate insulating film 115a are formed. Thereafter, the photolithography process according to the first embodiment of the present invention The drain electrode 123 ', the data line 117' and the pixel line 118L 'are formed in the pixel portion by a single mask process by applying a lift-off process (a second mask process) And a data pad electrode 127p 'and a gate pad electrode 126p' are formed in the data pad portion and the gate pad portion, respectively.

Here, the gate pad electrode 126p 'is electrically connected to the gate pad line 116p through a third contact hole 140c formed in the passivation layer 115b, and the plurality of pixel electrodes 118 And is electrically connected to the drain electrode 123 'through the connection electrode 118a of the pixel line 118L'.

At this time, the source electrode 122 ', the drain electrode 123', the data line 117 ', the pixel line 118L', the data pad electrode 127p ', and the gate pad electrode A drain electrode pattern 123, a data line pattern 117, a pixel line pattern 118L, a data pad line 117p, and a gate pad 117b, which are opaque third conductive films, An electrode pattern 126p is formed.

At this time, the source electrode pattern 122 is electrically connected to the source region of the active pattern 124 through the first contact hole 140a formed in the protective layer 115b, and the drain electrode pattern 123 Is electrically connected to the drain region of the active pattern 124 through the second contact hole 140b formed in the protective film 115b.

Here, the second mask process may be performed by using a half-tone mask and a lift-off process so that the source electrode 122 ', the drain electrode 123', the data line 117 ' A data pad electrode 127p 'and a data pad line 117p' and a passivation layer 115b may be formed on the first mask layer 118L ', the data pad electrode 127p', the gate pad electrode 126p ' Will be described in detail.

FIGS. 7A to 7G are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention shown in FIGS. 4B and 5B.

7A, the gate electrode 121, the gate line (not shown), the common electrode 108, the pixel electrode 118, the common line 108L, the pixel electrode line (not shown) A protective film 115b is formed on the entire surface of the array substrate 110 where the line 116p, the active pattern 124 and the gate insulating film 115a are formed.

7B, a second photoresist layer 270 made of a photosensitive material, such as photoresist, is formed on the array substrate 110 on which the passivation layer 115b is formed. Then, as shown in FIG. 7B, And selectively irradiates the second photoresist layer 270 with light through the half-tone mask 280.

At this time, the half-tone mask 280 is provided with a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 280 is irradiated onto the second photoresist layer 270.

7C, after the second photoresist layer 270 exposed through the half-tone mask 280 is developed, light is transmitted through the blocking region III and the second transmissive region II, A first photoresist pattern 270a to a seventh photoresist pattern 270g having a predetermined thickness are left in a region where all of the light is blocked or only partially blocked, The surface of the protective film 115b is exposed.

The first photoresist pattern 270a to the fourth photoresist pattern 270d formed in the blocking region III may include a fifth photoresist pattern 270e and a seventh photoresist pattern 270d formed through the second transmissive area II, 270g). In addition, the second photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, A resist may be used.

7D, using the first photoresist pattern 270a to the seventh photoresist pattern 270g formed as described above as a mask, a portion of the passivation layer 115b formed under the photoresist pattern 270a is selectively removed A first hole H1 exposing a part of the surface of the array substrate 110 and a first contact hole 125 exposing a part of the ohmic-contact layer 125n are formed in a pixel portion of the array substrate 110 A second hole H2 for exposing the surface of the array substrate 110 is formed on a data pad portion and a gate pad portion of the array substrate 110, A third contact hole 140c exposing a part of the line 116p is formed.

7E, when the ashing process for removing a part of the thicknesses of the first to seventh photosensitive film patterns 270a to 270g is performed, The photoresist pattern to the seventh photoresist pattern are completely removed.

The first through fourth photoresist patterns 270a 'through 270d' may have a thickness ranging from the fifth photoresist pattern to the seventh photoresist pattern 270a ' (III). ≪ / RTI > At this time, the first transmissive region I and the second transmissive region II in which the eighth photoresist pattern 270a 'to the eleventh photoresist pattern 270d' are not left are subjected to a lift-off process A source electrode, a drain electrode, a data line, a pixel line, a data pad electrode, and a gate pad electrode.

Then, as shown in FIG. 7F, a third conductive layer 150 and a fourth conductive layer 160 are formed on the entire surface of the array substrate 110.

The third conductive layer 150 may be formed of a low resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, chromium, molybdenum, or a molybdenum alloy, -Tin-oxide, or indium-zinc-oxide. ≪ / RTI > In addition, the fourth conductive layer 160 may be made of a molybdenum alloy such as MoTi.

In addition, a conductive layer made of a conductive material such as MoTi may be further formed under the third conductive layer 150 to improve adhesion to the array substrate 110 made of glass.

As shown in FIG. 7G, the eighth photoresist pattern to the eleventh photoresist pattern are removed through a lift-off process. At this time, the first and second photoresist patterns I and II The second conductive film and the third conductive film remaining on the second conductive film pattern are removed together with the eighth photosensitive film pattern to the eleventh photosensitive film pattern.

As described above, the source electrode 122 ', the drain electrode 123', the data line 117 'and the pixel line 118L' of the fourth conductive film are formed in the pixel portion in the single mask process, A data pad electrode 127p 'and a gate pad electrode 126p', which are the fourth conductive films, are formed on the gate and gate pads, respectively.

At this time, the source electrode 122 ', the drain electrode 123', the data line 117 ', the pixel line 118L' and the data pad electrode 127p ', which are the fourth conductive films which are transparent conductive materials, A source electrode pattern 122, a drain electrode pattern 123, a data line pattern 117, and a pixel line pattern 118L, which are low conductive and opaque conductive materials, are formed under the pad electrode 126p ' The data pad line 117p and the gate pad electrode pattern 126p are formed.

The source electrode pattern 122 is electrically connected to a source region of the active pattern 124 through a first contact hole 140a formed in the protective layer 115b and the drain electrode pattern 123 is electrically connected to the source region of the active pattern 124. [ And is electrically connected to the drain region of the active pattern 124 through the second contact hole 140b formed in the protective film 115b.

The gate pad electrode 126p 'is electrically connected to the gate pad line 116p via a third contact hole 140c formed in the passivation layer 115b, and the data line pattern 117 is electrically connected to the gate pad line 116p. The protective layer 115b of the pixel portion is formed in the removed first hole and the data pad line 117p 'is formed in the second hole from which the protective layer 115b of the data pad portion is removed.

Here, the source electrode pattern 122, the drain electrode pattern 123, the data line pattern 117, the pixel line pattern 118L, and the data pad line 117p, which are made of the third conductive film, which is a low resistance opaque conductive material, And the gate pad electrode pattern 126p serve as signal wirings for substantially transmitting signals. The source electrode 122 'and the drain electrode 123', which are the fourth conductive films, , The data line 117 ', the pixel line 118L', the data pad electrode 127p 'and the gate pad electrode 126p' are electrically connected to the source electrode pattern 122, the drain electrode pattern 123, The data line line 117, the pixel line pattern 118L, the data pad line 117p, and the gate pad electrode pattern 126p.

At this time, a part of the pixel line pattern 118L is overlapped with a part of the common line 108L below the protective film 115b to form a storage capacitor. As described above, since the active pattern and the gate insulating film do not exist between the pixel line pattern 118L and the common line 108L constituting the storage capacitor, the storage capacitance can be increased and the aperture ratio can be improved.

As described above, according to the first embodiment of the present invention, an array substrate including thin film transistors can be manufactured by two mask processes, thereby providing a manufacturing process and a cost reduction effect. In particular, the 10-step process can be omitted in comparison with the existing 4-mask process, and a process reduction effect of about 38% can be obtained.

In the two-mask process according to the first embodiment of the present invention, the active pattern and the data line are formed through different mask processes, and the active pattern is formed in the island shape, so that there is no active pattern under the data line The problem of the aperture ratio loss and the light leakage problem in the conventional four-mask process can be solved.

In addition, since the active pattern and the gate insulating film are not present between the pixel line and the common line and are formed as a protective film, the capacity of the storage capacitor can be increased and the aperture ratio of the conventional structure can be increased. Particularly, by forming the common electrode and the pixel electrode of a fine pattern with the transparent conductive film, the transmittance of the pixel region can be improved and the image quality is improved.

8 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to a second embodiment of the present invention. When the common electrode, the pixel electrode and the data line according to the second embodiment of the present invention have a bent structure The liquid crystal molecules are arranged in two directions to form a 2-domain, which further improves the viewing angle compared to the mono-domain. However, the present invention is not limited to the transverse electric field type liquid crystal display device having the two-domain structure, and the present invention is applicable to a transverse electric field type liquid crystal display device having a multi-domain structure of two or more domains. For reference, the IPS structure forming the multi-domain of the 2-domain or more is referred to as an S-IPS (super-IPS) structure.

When the common electrode, the pixel electrode, and the data line are formed in a bending structure and the driving direction of the liquid crystal molecules is symmetrical, the abnormal light due to the birefringence characteristic of the liquid crystal is canceled out The color shift phenomenon can be minimized.

As shown in the figure, a gate line 216 and a data line 217 'are formed on an array substrate 210 of the second embodiment of the present invention, which are vertically and horizontally arranged on the array substrate 210 to define pixel regions. . In addition, a thin film transistor, which is a switching device, is formed in the intersection region of the gate line 216 and the data line 217 ', and a finger-shaped transistor (not shown) for driving a liquid crystal The common electrode 208 and the pixel electrode 218 are alternately arranged with a bent structure.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 'connected to the data line 217' and a drain electrode 223 'electrically connected to the pixel electrode 218' ). The thin film transistor includes an active pattern (not shown) which forms a conduction channel between the source electrode 222 'and the drain electrode 223' by a gate voltage supplied to the gate electrode 221.

Reference numeral 225n denotes an ohmic contact layer for ohmic-contacting the source / drain region of the active pattern with the source / drain electrodes 222 'and 223'. At this time, the source electrode 222 'and the drain electrode 223' are connected to the source and drain regions of the active pattern through a first contact hole 240a and a second contact hole 240b formed in a protective film (not shown) Region. ≪ / RTI >

At this time, the insulating material constituting the protective film is deposited between the ohmic-contact layers 225n, thereby preventing the back channel of the TFT after the patterning of the source / drain electrodes 222 'and 223' do.

A part of the source electrode 222 'extends in one direction to form a part of the data line 217', and a part of the drain electrode 223 'extends toward the pixel region and is connected to the pixel line 218L' And is electrically connected to the pixel electrode 218.

A gate pad electrode 226p 'and a data pad electrode 227p', which are electrically connected to the gate line 216 and the data line 217 ', respectively, are formed in the edge region of the array substrate 210, And transmits a scan signal and a data signal applied from an external driving circuit (not shown) to the gate line 216 and the data line 217 ', respectively.

That is, the gate line 216 and the data line 217 'extend to the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line (not shown) The data pad lines are respectively supplied with a scanning signal from a driving circuit or a data signal through a gate pad electrode 226p 'and a data pad electrode 227p' electrically connected to the gate pad line 216p and a data pad line .

Reference numeral 240c denotes a third contact hole formed in the passivation layer. The gate pad electrode 226p 'is electrically connected to the gate pad line 216p through the third contact hole 240c do.

As described above, in the pixel region, the common electrode 208 and the pixel electrode 218 for generating a transverse electric field are alternately arranged.

At this time, a common line 208L arranged in a direction substantially parallel to the gate line 216 is formed in the lower portion of the pixel region, and the plurality of common electrodes 208 are connected to the common line 208L.

The plurality of pixel electrodes 218 are connected to a pixel electrode line 2181 arranged in a direction substantially parallel to the gate line 216 and connected to the connection electrode 218a of the pixel line 218L ' To the drain electrode 223 '.

The common line 208L and the pixel electrode line 2181 are formed of an opaque second conductive film constituting a gate wiring, that is, a gate electrode 221 and a gate line 216, The pixel line 218L 'may be formed of a transparent fourth conductive film constituting the data line, that is, the source electrode 222', the drain electrode 223 'and the data line 217'.

At this time, under the gate electrode 221, the gate line 216, the common line 208L, the pixel electrode line 2181 and the gate pad line 216p made of the opaque second conductive film, A gate line pattern (not shown), a common line pattern (not shown), a pixel electrode line pattern (not shown), and a gate pad line pattern (not shown).

In addition, under the source electrode 222 ', the drain electrode 223', the data line 217 ', the pixel line 218L' and the data pad electrode 227p 'of the transparent fourth conductive film, A source electrode pattern (not shown), a drain electrode pattern (not shown), a data line pattern (not shown), a pixel line pattern (not shown), and a data pad electrode pattern (not shown) have.

At this time, a part of the pixel line 218L 'is overlapped with a part of the common line 208L under the protective layer, forming a storage capacitor Cst.

The array substrate according to the first and second embodiments of the present invention is adhered to the color filter substrate by a sealant formed on the outer periphery of the image display area, A black matrix for preventing light from leaking into gate lines and data lines, and a color filter for realizing red, green and blue colors.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

As described above, the amorphous silicon thin film transistor using the amorphous silicon thin film as the active pattern is described as an example of the first and second embodiments of the present invention, but the present invention is not limited thereto. The invention is also applied to a polycrystalline silicon thin film transistor using the polycrystalline silicon thin film as the active pattern.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are sectional views sequentially showing a manufacturing process of an array substrate in the liquid crystal display device shown in Fig.

3 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to a first embodiment of the present invention.

FIGS. 4A and 4B are cross-sectional views sequentially showing manufacturing processes according to lines IIIa-IIIa ', IIIb-IIIb and IIIc-IIIc of the array substrate shown in FIG.

5A and 5B are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG. 3;

6A to 6I are cross-sectional views illustrating a first mask process according to a first embodiment of the present invention shown in FIGS. 4A and 5A.

FIGS. 7A to 7G are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention shown in FIGS. 4B and 5B;

8 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to a second embodiment of the present invention.

DESCRIPTION OF REFERENCE NUMERALS

108, 208: common electrode 110, 210:

116, 216: gate lines 116p, 216p: gate pad line

117, 217: Data lines 117p, 217p: Data pad lines

118, 218: pixel electrodes 121, 221: gate electrode

122, 222: source electrode 123, 223: drain electrode

126p and 226p: gate pad electrodes 127p and 227p: data pad electrode

Claims (17)

Forming a transparent first conductive film, an opaque second conductive film, a first insulating film, an amorphous silicon thin film and an n + amorphous silicon thin film on a first substrate; Forming a photoresist pattern for a first mask on the first substrate by applying a multiple exposure mask (first mask process); Selectively removing the second conductive film, the first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film using the photoresist pattern for the first mask as a mask, Forming a first conductive film pattern to a fifth conductive film pattern with a second conductive film; Selectively removing the first conductive film and removing a part of the second conductive film using the photoresist pattern for the first mask as a mask to form a second conductive film on the pixel portion of the first substrate, Pattern and the second conductive film pattern, a gate line and a pixel electrode line are formed, and a gate electrode and a pixel electrode line are formed in the pixel region of the first substrate, Forming an electrode; Ashing the photoresist pattern for the first mask; Selectively removing the first insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film using the ashed photoresist pattern for the first mask to form the first insulating film and the amorphous silicon thin film on the pixel portion of the first substrate, Forming a gate insulating film and an active pattern; Ashing the photoresist pattern for the ashed first mask; Selectively removing a portion of the n + amorphous silicon thin film using the photoresist pattern for the first mask as the mask to form an ohmic contact layer with the n + amorphous silicon thin film on the source region and the drain region of the active pattern, ; Forming a protective film on the first substrate on which the ohmic-contact layer is formed; Forming a first contact hole and a second contact hole exposing a part of the ohmic contact layer by selectively removing a part of the protective film through a half-tone mask (second mask process); Forming an opaque third conductive film and a transparent fourth conductive film on the first substrate in a state where a photoresist pattern for a second mask used in the second mask process remains; The third conductive film and the fourth conductive film formed on the photoresist pattern for the second mask and the photoresist pattern for the second mask are selectively removed through a lift-off process to form the fourth conductive film on the pixel portion of the first substrate, Source / drain electrodes electrically connected to the ohmic-contact layer on the source / drain region through the first / second contact holes, and source / drain electrodes which cross the gate line and define the pixel region Forming a data line; And And bonding the first substrate and the second substrate to each other. The method of claim 1, further comprising: selectively removing the first conductive film and a part of the second conductive film using the photoresist pattern for the first mask as a mask, And forming a gate pad line having a width smaller than that of the fifth conductive film pattern by a film. The lithographic apparatus of claim 1, wherein the first mask process comprises a first transmission region for transmitting all the irradiated light and a second transmission region consisting of a half-tone portion for transmitting only a part of light and blocking a part of light, And a third transparent region formed on the first transparent mask and a blocking region for blocking all the irradiated light. The method according to claim 1, wherein the first conductive film pattern to the fifth conductive film pattern are formed by over-etching the second conductive film using wet etching so that each of the first conductive film pattern to the fifth conductive film pattern has a width And the liquid crystal display device is manufactured. The method according to claim 2, wherein a gate electrode pattern made of the first conductive film is formed under the gate electrode, the gate line, the common line, the pixel electrode line, and the gate pad line, , A common line pattern, a pixel electrode line pattern, and a gate pad line pattern are formed. The method according to claim 1, wherein the etching of the first conductive layer is performed using a wet etching, and the second conductive layer is partially etched when the first conductive layer is etched, And the common electrode and the surface of the pixel electrode are exposed. The method according to claim 1, further comprising the step of forming a pixel line constituting a storage capacitor by overlapping a part of the common line with the protective film in the pixel portion of the first substrate using the second mask process The method comprising the steps of: 3. The method of claim 2, wherein the second mask process Applying a half-tone mask having a first transmitting region for transmitting all the irradiated light and a second transmitting region for transmitting only a part of light and blocking a part of the light and a blocking region for blocking all the irradiated light, Forming a photoresist pattern to a seventh photoresist pattern; The first contact hole exposing a part of the ohmic-contact layer to the pixel portion of the first substrate by selectively removing a part of the protective film using the first photoresist pattern to the seventh photoresist pattern as a mask, Forming a second contact hole and a third contact hole exposing a portion of the gate pad line in the gate pad portion of the first substrate; Forming an eighth photosensitive film pattern to an eleventh photosensitive film pattern by removing the fifth photosensitive film pattern to the seventh photosensitive film pattern through an ashing process and removing a part of the thickness of the first photosensitive film pattern to the fourth photosensitive film pattern; Forming the third conductive film and the fourth conductive film on the entire surface of the first substrate in a state where the eighth photosensitive film pattern to the eleventh photosensitive film pattern remain; And The third conductive film and the fourth conductive film deposited on the eighth photosensitive film pattern to the eleventh photosensitive film pattern and the eighth photosensitive film pattern to the eleventh photosensitive film pattern are selectively removed through the lift- And forming the source electrode and the drain electrode and the data line electrically connected to the ohmic-contact layer through the first contact hole and the second contact hole as the fourth conductive film in the pixel portion of one substrate, Forming a data pad electrode as the fourth conductive film in the data pad portion of the first substrate and the gate pad portion and a gate pad electrode connected to the gate pad line through the third contact hole, A method of manufacturing a display device. delete delete The semiconductor device according to claim 8, wherein a source electrode pattern made of the third conductive film, a drain electrode pattern made of the second conductive film, and a source electrode pattern made of the third conductive film are formed under the source electrode, the drain electrode, And forming a data line pattern, a data pad line and a gate pad electrode pattern, respectively. 12. The method of claim 11, further comprising: selectively removing a portion of the passivation layer using the first photoresist pattern to the seventh photoresist pattern as a mask to expose a portion of the surface of the first substrate to the pixel portion of the first substrate A second hole is formed in the data pad portion of the first substrate to expose the first substrate surface, Wherein the data line pattern is formed in the first hole from which the protective film of the pixel portion is removed, and the data pad line is formed in the second hole from which the protective film of the data pad portion is removed. The liquid crystal display device according to claim 8, wherein the source electrode and the drain electrode are formed to be electrically connected to the source region and the drain region of the active pattern through the first contact hole and the second contact hole, respectively Gt; A gate electrode and a gate line made of an opaque conductive material on the first substrate; A gate electrode pattern and a gate line pattern made of a transparent conductive material under the gate electrode and the gate line; A common electrode and a pixel electrode made of the transparent conductive material in a pixel region of the first substrate; An active pattern provided on the gate electrode through a gate insulating layer, the active pattern being divided into a source region, a drain region, and a channel region; An ohmic contact layer on the source region and the drain region of the active pattern; A protective layer having a first contact hole exposing the ohmic contact layer, a second contact hole and a first hole exposing a part of the surface of the first substrate, on the first substrate provided with the active pattern; A source electrode pattern and a drain electrode pattern formed of an opaque conductive material and electrically connected to the ohmic contact layer on the source region and the ohmic contact layer through the first contact hole and the second contact hole, A data line pattern that intersects the gate line and defines the pixel region, and is located in the first hole; A source electrode and a drain electrode and a data line made of a transparent conductive material on the source electrode pattern, the drain electrode pattern, and the data line pattern; And And a second substrate which is adhered to and adhered to the first substrate. 15. The liquid crystal display of claim 14, wherein the source electrode, the drain electrode, and the data line are made of ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) having high resistance to corrosion. 15. The liquid crystal display of claim 14, wherein the gate electrode and the gate line have a smaller width than the gate electrode pattern and the gate line pattern, respectively. 15. The liquid crystal display of claim 14, further comprising a pixel line disposed in a direction parallel to the gate line and connected to the pixel electrode to electrically connect the drain electrode and the pixel electrode.

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