KR101898624B1 - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A Fringe Field Switching (FFS) liquid crystal display device and a method of manufacturing the same of the present invention are characterized in that in a fringe field type liquid crystal display device in which a common electrode is overlaid on a data line to realize high transmission, The gate wiring and the pixel electrode are simultaneously patterned using a mask, the data wiring and the common electrode are simultaneously patterned, and the common electrode is formed over the data line by a lift-off process so that the number of masks is reduced Thereby simplifying the manufacturing process and minimizing an increase in the driving voltage.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a fringe field type liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same. More particularly, the present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

Hereinafter, a general liquid crystal display device will be described in detail with reference to the drawings.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.

As shown in the drawing, a typical liquid crystal display device includes a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and blocking light transmitted through the liquid crystal layer 30 and a transparent common And an electrode (8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17, A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal panel, and the color filter substrate 5 (Not shown) formed on the color filter substrate 5 or the array substrate 10 are bonded to each other.

In this case, there is a twisted nematic (TN) method in which a nematic liquid crystal molecule is driven in a direction perpendicular to a substrate by a driving method generally used in the liquid crystal display device. However, the twisted nematic liquid crystal display Has a disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules, because liquid crystal molecules aligned horizontally with the substrate are oriented in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal panel.

There is an in-plane switching (IPS) type liquid crystal display device in which liquid crystal molecules are driven in a horizontal direction with respect to a substrate to improve a viewing angle to 170 degrees or more.

FIG. 2 is a cross-sectional view schematically showing a part of an array substrate of a transverse electric field type liquid crystal display device in which a fringe field formed between a pixel electrode and a common electrode passes through a slit to drive liquid crystal molecules positioned on a pixel region and a common electrode And shows a part of an array substrate of a fringe field switching (FFS) liquid crystal display device implementing an image.

In the fringe field type liquid crystal display device, a common electrode is formed in a lower part while liquid crystal molecules are oriented horizontally, and a pixel electrode is formed in an upper part, so that an electric field occurs in horizontal and vertical directions, And is tilted and driven.

As shown in the figure, on the array substrate 10 of a general fringe field type liquid crystal display device, gate lines (not shown) arranged vertically and horizontally on the transparent array substrate 10 to define pixel regions and data lines A thin film transistor, which is a switching element, is formed in an intersection region between the gate line and the data line.

The thin film transistor includes a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line, and a drain electrode 23 connected to the pixel electrode 18. The thin film transistor has a gate insulating film 15a for insulation between the gate electrode 21 and the source and drain electrodes 22 and 23 and a source electrode And an active layer 24 forming a conductive channel between the drain electrode 22 and the drain electrode 23.

At this time, the source / drain region of the active layer 24 forms an ohmic contact with the source / drain electrodes 22 and 23 through an ohmic contact layer 25n.

A common electrode 8 and a pixel electrode 18 are formed in the pixel region and the common electrode 8 is formed in the common electrode 8 to generate a fringe field together with the pixel electrode 18 having a rectangular shape. 8 includes a plurality of slits 8s.

At this time, the pixel electrode 18 is electrically connected to the drain electrode 23 through a contact hole formed in the first protective layer 15b.

Reference numeral 15c denotes a second protective film.

The fringe field type liquid crystal display having the above structure has a wide viewing angle as compared with the conventional twisted nematic method. However, in the fabrication of the array substrate including the thin film transistor, a number of mask processes And a photolithography process), a method of reducing the number of masks in terms of productivity is required.

That is, a high-resolution fringe field type liquid crystal display device is not suitable for reducing the number of masks because one layer is added in a laminated structure as compared with a general transverse electric field type liquid crystal display device. Particularly, in the case of a high-transmittance structure in which a common electrode is formed on the data line in an overlapped manner, the gap between the common electrode, the data line and the pixel electrode must be uniformly maintained in the entire region, so that the parasitic capacitance Therefore, it is difficult to reduce the number of masks without loss of transmittance.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems described above, and it is an object of the present invention to provide a fringe field type liquid crystal display device in which a common electrode is overlaid on a data line, Apparatus and a method of manufacturing the same.

Other objects and features of the present invention will be described in the following description of the invention and the claims.

According to another aspect of the present invention, there is provided a method of manufacturing a fringe field type liquid crystal display device, comprising: forming a pixel electrode made of a first conductive film in a pixel portion of a first substrate through a first mask process; Forming a gate insulating layer on the entire surface of the first substrate on which the gate electrode, the gate line, and the pixel electrode are formed, forming a gate insulating layer on the first substrate through the second mask process, Forming a first contact hole exposing the pixel electrode while forming an active layer in the pixel portion, forming a common electrode made of a third conductive film in the pixel portion of the first substrate through a third mask process Forming a source electrode, a drain electrode, and a data line made of a fourth conductive film; forming a source electrode, a drain electrode, Forming a fifth contact hole exposing a part of the common electrode by selectively patterning the passivation layer through a fourth mask process, and forming a second contact hole exposing a part of the common electrode, Forming a trench along the data line on the data line by removing a part of the thickness of the passivation film; forming a fifth conductive film on the entire surface of the first substrate in a state where the photoresist pattern used in the fourth mask process remains Wherein the fifth conductive film is formed in the trench by selectively removing the fifth conductive film formed on the photoresist pattern and the photoresist pattern through a lift-off process, and electrically connected to the common electrode through the fifth contact hole A step of forming a common electrode pattern to be connected and a step of bonding the first substrate and the second substrate . ≪ / RTI >
The fringe field type liquid crystal display device of the present invention includes a pixel electrode of a first substrate and a gate electrode and a gate line of a second conductive film and a pixel electrode of a first conductive film, And a first contact hole formed on the entire surface of the first substrate including the pixel electrode and exposing a part of the pixel electrode, the pixel electrode of the first substrate including the gate insulating film A source electrode, a drain electrode, and a data line, which are included in a pixel portion of the first substrate including the active layer, the common electrode being a third conductive film and the fourth conductive film, the source electrode, Drain electrodes, the data lines, and the common electrode, and a fifth contact layer is provided on the entire surface of the first substrate, A trench in which a part of the thickness of the protective film is removed along the data line in a protective film over the data line, a fifth conductive film in the trench, A common electrode pattern electrically connected to the common electrode, and a second substrate bonded to and facing the first substrate.

In this case, a gate pad line made of the second conductive film is formed in the gate pad portion of the first substrate through the first mask process.

At this time, a gate electrode pattern and a gate line pattern composed of the first conductive film are formed through the gate electrode and the gate line through the first mask process, and a gate pad pattern made of the first conductive film Thereby forming a line pattern.

And a second contact hole exposing the gate pad line is formed in the gate pad portion of the first substrate through the second mask process.

Forming a data pad line of the fourth conductive film on the data pad portion of the first substrate through the third mask process and forming a gate pad electrode pattern made of the third conductive film on the gate pad portion of the first substrate, Is formed.

In this case, the source electrode pattern, the drain electrode pattern and the data line pattern made of the third conductive film are formed on the source electrode, the drain electrode and the data line through the third mask process, 3 conductive film on the data pad line pattern.

The third contact hole and the fourth contact hole exposing the data pad line and the gate pad electrode pattern are formed by selectively patterning the passivation layer through the fourth mask process and the fifth contact hole exposing the common electrode, Is formed.

In this case, the common electrode pattern is electrically connected to the common electrode via the fifth contact hole.

The fifth conductive film formed on the photoresist pattern and the photoresist pattern is selectively removed through the lift-off process to electrically connect the data pad line and the gate pad electrode pattern through the third contact hole and the fourth contact hole, The data pad electrode and the gate pad electrode are formed.

The trench is formed not only on the data line but also on the gate line, and forms a lattice-shaped common electrode pattern on the data line and the gate line through the lift-off process.

The common electrode has a plurality of slits in each pixel region, and the common electrode between the slits is formed to have a finger shape.

Forming an n + amorphous silicon thin film pattern of an n + amorphous silicon thin film on the active layer through the second mask process; selectively patterning the n + amorphous silicon thin film pattern through the third mask process to form an ohmic contact layer; .

At this time, an interlayer film pattern made of a barrier metal of Mo, MoTi, Ti, or W is formed on the active layer through the second mask process, and the barrier metal is selectively patterned through the third mask process, And a step of forming a layer.

Another method of manufacturing a fringe field type liquid crystal display device of the present invention includes forming a pixel electrode made of a first conductive film in a pixel portion of a first substrate through a first mask process and forming a gate electrode made of a second conductive film, Forming a gate insulating film on the entire surface of the first substrate on which the gate electrode, the gate line, and the pixel electrode are formed; forming an active layer on a pixel portion of the first substrate through a second mask process; Forming an open hole for exposing a pixel region by removing a gate insulating film over the pixel electrode; forming a source electrode and a drain electrode, which are made of a third conductive film, in a pixel portion of the first substrate through a third mask process; Forming a data line on the first substrate, forming the source electrode, the drain electrode, Forming a common electrode made of a fourth conductive film on a pixel portion of the first substrate through a fourth mask process; forming a common electrode on the pixel portion of the first substrate by exposing the data pad portion and the gate pad portion of the first substrate; Removing the protective film formed on the data pad portion and the gate pad portion through etching at normal pressure in a state in which the data pad portion and the gate pad portion are exposed, And opening the gate pad portion.

In this case, a gate pad line made of the second conductive film is formed in the gate pad portion of the first substrate through the first mask process.

At this time, a gate electrode pattern and a gate line pattern composed of the first conductive film are formed through the gate electrode and the gate line through the first mask process, and a gate pad pattern made of the first conductive film Thereby forming a line pattern.

In this case, the data pad line of the third conductive layer is formed in the data pad portion of the first substrate through the third mask process.

And the common electrode is formed in a single pattern over the entire pixel portion.

In this case, the common electrode may have a plurality of slits in each pixel region, and the common electrode between the slits may have a finger shape.

As described above, in the fringe field type liquid crystal display device and the method of manufacturing the same according to the present invention, the gate wiring and the pixel electrode are simultaneously patterned using a half tone mask while the data wiring and the common electrode are simultaneously patterned , And a common electrode is formed to overlap the data line through a lift-off process. Thus, the array substrate can be manufactured by four mask processes. The gate line and the pixel electrode are simultaneously patterned using a half-tone mask, the data line is patterned using a half-tone mask, the gate insulating film of the pixel region is opened, and the atmospheric pressure etch etch, the array substrate can be manufactured by four mask processes.

As a result, the number of masks is reduced, thereby simplifying the manufacturing process and reducing the manufacturing cost.

In addition, as described above, the common electrode is formed to overlap the data line, and an active tail is not formed under the data line, thereby maximizing the transmittance.

Also, while the gate wiring and the pixel electrode are simultaneously patterned, the interval between the pixel electrode and the common electrode is minimized, thereby minimizing the driving voltage.

In addition, the step difference between the upper portion of the data line and the pixel region can be reduced by 40% or more compared to the conventional method, and the rubbing defect can be improved.

In addition, a direct connection between the gate wiring and the data wiring is possible, which is advantageous in that a narrow bezel due to shrinkage of the gate-in-panel (GIP) portion is facilitated.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.
2 is a cross-sectional view schematically showing a part of an array substrate of a transverse electric field type liquid crystal display device.
3 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention.
4 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention.
5A to 5D are plan views sequentially showing a manufacturing process of the array substrate shown in FIG. 3;
6A to 6D are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 4;
7A to 7F are cross-sectional views illustrating a first mask process according to the first embodiment of the present invention shown in FIG. 6A.
8A to 8F are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention shown in FIG. 6B.
9A to 9F are cross-sectional views illustrating a third mask process according to the first embodiment of the present invention shown in FIG. 6C.
10A to 10G are cross-sectional views illustrating a fourth mask process according to the first embodiment of the present invention shown in FIG. 6D.
11 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention.
12 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention.
FIGS. 13A to 13D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG. 11; FIG.
FIGS. 14A to 14E are sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 12; FIG.
15A to 15F are cross-sectional views illustrating a first mask process according to a second embodiment of the present invention shown in FIG. 14A.
16A to 16F are cross-sectional views illustrating a second mask process according to a second embodiment of the present invention shown in FIG. 14B.

Hereinafter, preferred embodiments of a fringe field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention, in which a fringe field formed between a pixel electrode and a common electrode passes through a slit, And Fig. 7 shows a part of an array substrate of a fringe field type liquid crystal display device which implements an image by driving liquid crystal molecules located on the fringe field type liquid crystal display device.

4 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to the first embodiment of the present invention. In FIG. 4, the A-A 'line, the BB line and the CC Sectional view taken along a line in FIG.

In this case, one pixel including a pixel portion, a data pad portion, and a gate pad portion is shown for convenience of explanation. In an actual liquid crystal display device, N gate lines and M data lines cross each other and MxN pixels However, in order to simplify the description, one pixel is shown in the drawing.

As shown in the drawings, the array substrate 110 according to the first embodiment of the present invention includes a gate line 116 and a data line 117, which are vertically and horizontally arranged on the array substrate 110, Is formed. In addition, a thin film transistor, which is a switching device, is formed in the intersection region of the gate line 116 and the data line 117. Inside the pixel region, a pixel electrode 118 for driving liquid crystal molecules by generating a fringe field, The common electrode 108 having the slits 108s of the common electrode 108 is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118 . The thin film transistor includes a gate insulating layer 115a for insulation between the gate electrode 121 and the source and drain electrodes 122 and 123 and a source electrode And an active layer 124 that forms a conduction channel between the drain electrode 122 and the drain electrode 123.

At this time, the source / drain regions of the active layer 124 form ohmic contacts with the source / drain electrodes 122 and 123 through the ohmic-contact layer 125n.

The gate electrode 121 and the gate line 116 are formed of a conductive material forming the pixel electrode 118 and are patterned in substantially the same manner as the gate electrode 121 and the gate line 116, A gate electrode pattern 121 'and a gate line pattern (not shown) are formed.

The source electrode 122 and the drain electrode 123 and the data line 117 are formed of a conductive material constituting the common electrode 108. The source electrode 122 and the drain electrode 123, A source electrode pattern 122 ', a drain electrode pattern 123' and a data line pattern 117 'patterned in substantially the same manner as the data line 117 are formed.

A part of the source electrode 122 and the source electrode pattern 122 'extend in one direction and are connected to the data line 117 and the data line pattern 117' A part of the drain electrode pattern 123 'extends toward the pixel region and is electrically connected to the pixel electrode 118 through the first contact hole 140a formed in the gate insulating layer 115a.

Although not shown in the figure, a barrier metal layer made of Mo, MoTi, Ti, or W is formed between the ohmic contact layer 125n and the source / drain electrode patterns 122 'and 123' . The barrier metal layer is disadvantageous in device characteristics when the ohmic-contact layer 125n made of the n + amorphous silicon thin film and the source / drain electrode patterns 122 'and 123' made of ITO are in contact with each other, ) May be formed in order to improve the device characteristics.

As described above, the common electrode 108 and the pixel electrode 118 are formed in the pixel region to generate a fringe field. At this time, the pixel electrode 118 may be formed in a rectangular shape within the pixel region, The common electrode 108 may be formed to have a plurality of slits 108s in the pixel region.

At this time, the plurality of slits 108s are filled with the protection film 115b and covered, and the common electrode 108 between the slits 108s may have a finger shape.

A common electrode pattern 108d electrically connected to the common electrode 108 is formed on the data line 117 through a fifth contact hole 140e, May be formed in a single pattern over the entire image display region to be displayed. At this time, the common electrode pattern 108d is formed to overlap not only the data line 117 but also the gate line 116, so that the common electrode pattern 108d can be formed in a lattice shape for each pixel region. However, The present invention is not limited to this.

At this time, the common electrode pattern 108d is formed so as to overlap the data line 117, and the active layer 124 and the data line 117 are formed through different mask processes, An active tail is not formed on the lower surface of the transparent substrate 117, so that the transmittance can be maximized.

A gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in an edge region of the array substrate 110, And transmits a scan signal and a data signal applied from a driving circuit unit (not shown) to the gate line 116 and the data line 117, respectively.

That is, the data line 117 and the gate line 116 extend to the driving circuit portion and are connected to the corresponding data pad line 117p and the gate pad line 116p, The line 116p connects the data signal and the scan signal from the driving circuit through the data pad electrode 127p and the gate pad electrode 126p electrically connected to the data pad line 117p and the gate pad line 116p, .

At this time, the data pad line 117p is electrically connected to the data pad electrode 127p through the third contact hole 140c. The gate pad line 116p is electrically connected to the gate pad electrode pattern 126p 'through the second contact hole 140c while the gate pad electrode pattern 126p' is electrically connected to the fourth contact hole 140d (Not shown) to the gate pad electrode 126p.

The data pad line 117p and the gate pad line 116p are electrically connected to the data pad line 117p and the gate pad line 116p by conductive materials constituting the pixel electrode 118, A data pad line pattern 117p 'and a gate pad line pattern 116p' patterned in the same pattern are formed.

In the fringe field type liquid crystal display device according to the first embodiment of the present invention, the gate lines (i.e., the gate electrodes 121 and the gate lines 116) are formed by using a half tone mask, The pixel electrode 118 is simultaneously patterned to form the active layer 124 using the half-tone mask, and the first contact hole 140a for the connection of the pixel electrode 118 is formed. It is also possible to pattern the data lines (i.e., the source electrode 122 and the drain electrode 123 and the data line 117) and the common electrode 108 simultaneously using a half-tone mask, and lift off And the common electrode pattern 108d is patterned on the data line 117. Thus, the array substrate 110 can be manufactured through four mask processes.

Hereinafter, a manufacturing method of the fringe field type liquid crystal display device according to the first embodiment of the present invention will be described in detail with reference to the drawings.

5A to 5D are plan views sequentially illustrating the manufacturing steps of the array substrate shown in FIG.

6A to 6D are cross-sectional views sequentially showing the steps of manufacturing the array substrate shown in FIG. 4. FIG. 6A to FIG. 6D show a process of fabricating an array substrate of the pixel portion on the left side and an array of data pad portions and gate pad portions, Thereby producing a substrate.

5A and 6A, a gate electrode 121, a gate line 116, and a pixel electrode 118 are formed on a pixel portion of an array substrate 110 made of a transparent insulating material such as glass, A gate pad line 116p is formed in the gate pad portion of the array substrate 110. [

The gate electrode 121, the gate line 116, the pixel electrode 118 and the gate pad line 116p are formed by depositing a first conductive film and a second conductive film on the entire surface of the array substrate 110 and then performing a photolithography process A first mask process).

At this time, the pixel electrode 118 is formed of the first conductive film, and the gate electrode 121, the gate line 116, and the gate pad line 116p are formed of the second conductive film.

The gate electrode 121, the gate line 116, and the gate pad line 116p are formed of the first conductive film. The gate electrode 121, the gate line 116, The gate electrode pattern 121 ', the gate line pattern (not shown), and the gate pad line pattern 116p' are formed in substantially the same pattern as the gate electrode patterns 116p and 116p.

As described above, the gate wiring (that is, the gate electrode 121 and the gate line 116) and the pixel electrode 118 can be simultaneously patterned through a single mask process by using a half-tone mask having a large area Hereinafter, the first mask process will be described in detail with reference to the drawings.

7A to 7F are cross-sectional views illustrating a first mask process according to the first embodiment of the present invention shown in FIG. 6A.

7A, the first conductive layer 131 and the second conductive layer 132 are sequentially deposited on the entire surface of the array substrate 110 made of a transparent insulating material such as glass.

The first conductive layer 131 may be formed of a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) .

The second conductive layer 132 may be formed of aluminum (Al), aluminum alloy (Al), tungsten (W), copper (Cu), chromium (Cr) A low resistance opaque conductive material such as molybdenum (Mo) and a molybdenum alloy or the like. In addition, the second conductive layer 132 may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

7B, a photoresist layer 160 made of a photosensitive material such as photoresist is formed on the array substrate 110 on which the second conductive layer 132 is formed. Then, Selectively irradiates light to the photoresist layer 160 through a half-tone mask 170 or a diffraction mask (hereinafter, referred to as a half-tone mask).

At this time, the half-tone mask 170 includes a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 170 is irradiated to the photoresist layer 160. As shown in FIG.

After the photoresist layer 160 exposed through the half-tone mask 170 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 7C. The first photosensitive film pattern 160a to the third photosensitive film pattern 160c having a predetermined thickness remain in the area where all the light is blocked or partially blocked and the photosensitive film is completely removed in the first transmission region I The surface of the second conductive layer 132 is exposed.

At this time, the first photoresist pattern 160a and the second photoresist pattern 160b formed in the blocking region III are thicker than the third photoresist pattern 160c formed through the second transmissive region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 7D, using the first photoresist pattern 160a to the third photoresist pattern 160c formed as described above as a mask, a first conductive film and a second conductive film The pixel electrode 118 made of the first conductive film is formed on the pixel portion of the array substrate 110. In addition,

A gate electrode 121 and a gate line (not shown) are formed in the pixel portion of the array substrate 110. The gate pad 121 of the array substrate 110 has a gate electrode 121 and a gate line A gate pad line 116p made of a film is formed.

At this time, a second conductive film pattern 132 'formed of the second conductive film and patterned in substantially the same shape as the pixel electrode 118 is formed on the pixel electrode 118.

The first conductive film is formed under the gate electrode 121, the gate line, and the gate pad line 116p, and is substantially the same as the gate electrode 121, the gate line, and the gate pad line 116p, A gate electrode pattern 121 ', a gate line pattern (not shown), and a gate pad line pattern 116 p' are formed.

As shown in FIG. 7E, when the ashing process for removing a part of the thickness of the first to third photosensitive film patterns 160a to 160c is performed, The photoresist pattern is completely removed.

At this time, the first photoresist pattern and the second photoresist pattern correspond to the blocking area III with the fourth photoresist pattern 160a 'and the fifth photoresist pattern 160b', which are removed by the thickness of the third photoresist pattern, Only in the region where it is located.

7F, using the fourth photoresist pattern 160a 'and the fifth photoresist pattern 160b' as a mask, the second conductive film pattern 160 formed on the pixel electrode 118 through etching is patterned using the fourth photoresist pattern 160a ' .

5B and 6B, on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the pixel electrode 118 and the gate pad line 116p are formed, The amorphous silicon thin film and the n + amorphous silicon thin film are formed.

Thereafter, the gate insulating film 115a, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form active portions of the amorphous silicon thin film in the pixel portion of the array substrate 110 Layer 124 is formed.

A first contact hole 140a exposing a part of the pixel electrode 118 is formed in the pixel portion of the array substrate 110 through the second mask process, A second contact hole 140b exposing a part of the gate pad line 116p is formed.

At this time, an n + amorphous silicon thin film pattern 125 'patterned in substantially the same shape as the active layer 124 is formed on the active layer 124.

In this case, the second mask process according to the first embodiment of the present invention can use a half-tone mask, which will be described in detail with reference to the following drawings.

8A to 8F are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention shown in FIG. 6B.

8A, the gate insulating layer 115a and the gate insulating layer 115 are sequentially formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the pixel electrode 118 and the gate pad line 116p are formed. The amorphous silicon thin film 120 and the n + amorphous silicon thin film 125 are deposited.

At this time, an interlayer made of a barrier metal such as Mo, MoTi, Ti, or W may be additionally deposited on the n + amorphous silicon thin film 125.

8B, a photosensitive film 160 made of a photosensitive material such as a photoresist is formed on the array substrate 110 on which the n + amorphous silicon thin film 125 is formed. Then, And selectively irradiates the photoresist layer 160 through the half-tone mask 170. [

At this time, the half-tone mask 170 includes a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 170 is irradiated to the photoresist layer 160. As shown in FIG.

Then, after the photoresist layer 160 exposed through the half-tone mask 170 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 8C. A first photoresist pattern 160a and a second photoresist pattern 160b having a predetermined thickness are left in an area where all the light is blocked or partially blocked and the photoresist layer is completely removed in the first transmissive area I The surface of the n + amorphous silicon thin film 125 is exposed.

At this time, the first photoresist pattern 160a formed in the blocking region III is thicker than the second photoresist pattern 160b formed through the second transmissive region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 8D, using the first photoresist pattern 160a and the second photoresist pattern 160b formed as described above as a mask, a gate insulating layer 115a formed under the photoresist pattern 160a and an amorphous silicon The pixel electrode of the array substrate 110 may be partially removed by selectively removing portions of the thin film and the n + amorphous silicon thin film (or the gate insulating film 115a, the amorphous silicon thin film, the n + amorphous silicon thin film, A first contact hole 140a exposing a part of the first contact hole 118 is formed.

A second contact hole 140b is formed in the gate pad portion of the array substrate 110 to expose a part of the gate pad line 116p.

As shown in FIG. 8E, when the ashing process for removing a part of the thickness of the first photoresist pattern 160a and the second photoresist pattern 160b is performed, The photoresist pattern is completely removed.

At this time, the first photoresist pattern is left only in a region corresponding to the blocking region III with the third photoresist pattern 160a 'removed by the thickness of the second photoresist pattern.

8F, using the third photoresist pattern 160a 'as a mask, the amorphous silicon thin film and the n + amorphous silicon thin film (or the amorphous silicon thin film and the n + amorphous silicon thin film, The active layer 124 made of the amorphous silicon thin film is formed in the pixel portion of the array substrate 110. In addition,

At this time, an n + amorphous silicon thin film pattern 125 'patterned in substantially the same shape as the active layer 124 is formed on the active layer 124.

When the interlayer film is deposited on the n + amorphous thin film, an interlayer film pattern patterned in substantially the same shape as the active layer 124 may be formed on the n + amorphous silicon thin film pattern 125 '.

5C and 6C, source / drain electrodes 122 and 123 are formed in a pixel portion of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern 125 'are formed. A data pad line 117p and a gate pad electrode pattern 126p 'are formed on a data pad portion and a gate pad portion of the array substrate 110, respectively, while a data line 117 and a common electrode 108 are formed do.

At this time, the drain electrode 123 is electrically connected to the pixel electrode 118 through the first contact hole 140a.

In addition, the gate pad electrode pattern 126p 'is electrically connected to the gate pad line 116p through the second contact hole 140b.

The source electrode 122, the drain electrode 123, the data line 117, the common electrode 108, the data pad line 117p and the gate pad electrode pattern 126p ' Is deposited on the entire surface of the array substrate 110, and then selectively patterned through a photolithography process (a third mask process).

The common electrode 108 and the gate pad electrode pattern 126 p 'are formed of the third conductive film and are electrically connected to the source electrode 122, the drain electrode 123, the data line 117, 117p are formed of the fourth conductive film.

The third conductive layer is formed under the source electrode 122, the drain electrode 123, the data line 117 and the data pad line 117p and is electrically connected to the source electrode 122 and the drain electrode 123 A source electrode pattern 122 ', a drain electrode pattern 123', a data line pattern 117 ', and a data pad line pattern 117' that are patterned in substantially the same pattern as the data line 117, the data line 117, (117p ') is formed.

In addition, the common electrode 108 may be formed to have a plurality of slits 108s in the pixel region, and the common electrode 108 between the slits 108s may have a finger shape.

The data line (that is, the source electrode 122 and the drain electrode 123 and the data line 117) and the common electrode 108 are simultaneously patterned through a single mask process by using a half-tone mask Hereinafter, the third mask process will be described in detail with reference to the drawings.

FIGS. 9A to 9F are cross-sectional views illustrating a third mask process according to the first embodiment of the present invention shown in FIG. 6C.

The third conductive layer 133 and the fourth conductive layer 134 are deposited on the entire surface of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern 125 'are formed, as shown in FIG. 9A do.

In this case, the third conductive layer 133 may be formed of a transparent conductive material having a high transmittance such as indium-tin-oxide or indium-zinc-oxide to form a common electrode and a gate pad electrode pattern.

The fourth conductive layer 134 may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form data lines and data pad lines. In addition, the fourth conductive layer 134 may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

9B, a photoresist layer 160 made of a photosensitive material such as a photoresist is formed on the array substrate 110 on which the fourth conductive layer 134 is formed. Then, And selectively irradiates the photoresist layer 160 through the half-tone mask 170. [

At this time, the half-tone mask 170 includes a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 170 is irradiated to the photoresist layer 160. As shown in FIG.

Then, after developing the exposed photoresist layer 160 through the half-tone mask 170, light is emitted through the blocking region III and the second transmissive region II, as shown in FIG. 9C. The first photosensitive film pattern 160a to the sixth photosensitive film pattern 160f having a predetermined thickness are left in the region where the light is blocked or partially blocked and the photosensitive film is completely removed in the first transmission region I, The surface of the fourth conductive film 134 is exposed.

The first photoresist pattern 160a to the fourth photoresist pattern 160d formed in the blocking region III may include a fifth photoresist pattern 160e and a sixth photoresist pattern 160f formed through the second transmissive area II. . Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 9D, using the first photoresist pattern 160a to the sixth photoresist pattern 160f formed as described above as a mask, a third conductive film and a part of the fourth conductive film The source and drain electrodes 122 and 123 and the data line 117 formed of the fourth conductive film and the data line 117 are formed in the pixel portion of the array substrate 110, A common electrode 108 is formed.

At this time, the common electrode 108 may be formed to have a plurality of slits 108s in the pixel region.

In addition, a data pad line 117p and a gate pad electrode pattern 126p 'are formed on the data pad portion and the gate pad portion of the array substrate 110, respectively, including the fourth conductive layer and the third conductive layer.

At this time, the drain electrode 123 is electrically connected to the pixel electrode 118 through the first contact hole 140a.

In addition, the gate pad electrode pattern 126p 'is electrically connected to the gate pad line 116p through the second contact hole 140b.

At this time, the third conductive film is formed under the source electrode 122, the drain electrode 123, the data line 117, and the data pad line 117p, and the source electrode 122 and the drain electrode 123 A source electrode pattern 122 ', a drain electrode pattern 123', a data line pattern 117 ', and a data pad line pattern 117' that are patterned in substantially the same pattern as the data line 117, the data line 117, (117p ') is formed. The fourth conductive layer is formed on the common electrode 108 and the gate pad electrode pattern 126 p 'and is formed substantially in the same shape as the common electrode 108 and the gate pad electrode pattern 126 p' The patterned fourth conductive film patterns 134 'and 134 "are formed.

Then, ashing process for removing a part of the thicknesses of the first to sixth photoresist patterns 160a to 160f is performed, as shown in FIG. 9E, The photoresist pattern and the sixth photoresist pattern are completely removed.

In this case, the first through fourth photoresist patterns 160a 'through 160d' are formed by removing the thicknesses of the fifth photoresist pattern and the sixth photoresist pattern, (III). ≪ / RTI >

9F, using the seventh photosensitive film pattern 160a 'to the tenth photosensitive film pattern 160d' as a mask, the common electrode 108 and the gate pad electrode pattern 126p ' The fourth conductive film patterns formed on the second conductive film pattern are removed.

The n + amorphous silicon thin film pattern (or the n + amorphous silicon thin film pattern and interlayer film pattern) formed at the lower portion thereof is selectively removed using the seventh photosensitive film pattern 160a 'to the tenth photosensitive film pattern 160d' An ohmic contact layer 125n made of the n + amorphous silicon thin film is formed on the active layer 124. [

At this time, if a layered structure is deposited on the n + amorphous silicon thin film, a barrier metal layer composed of the interlayer film may be formed on the ohmic-contact layer 125n. As described above, the barrier metal layer is disadvantageous in device characteristics when the ohmic-contact layer 125n made of the n + amorphous silicon thin film and the source / drain electrode patterns 122 'and 123' made of ITO are in contact with each other, Silicide may be formed to further improve device characteristics.

Thereafter, predetermined O ₂ ashing can proceed.

5D and 6D, a protective film 115b is deposited on the entire surface of the array substrate 110, and a protective film 115b is formed on the entire surface of the array substrate 110 by a half-tone mask (fourth mask process) and a lift- And the common electrode pattern 108d made of the fifth conductive film is formed on the data line 117. This will be described in detail with reference to the following drawings.

FIGS. 10A to 10G are cross-sectional views illustrating a fourth mask process according to the first embodiment of the present invention shown in FIG. 6D.

The source electrode 122, the drain electrode 123, the data line 117, the common electrode 108, the data pad line 117p, and the gate pad electrode pattern 126p 'are formed as shown in FIG. 10A A protective film 115b made of an inorganic insulating film or an organic insulating film is deposited on the entire surface of the array substrate 110. [

10B, a photosensitive film 160 made of a photosensitive material such as a photoresist is formed on the array substrate 110 on which the protective film 115b is formed, and then a half- And selectively irradiates light to the photoresist layer 160 through the tone mask 170.

At this time, the half-tone mask 170 includes a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 170 is irradiated to the photoresist layer 160. As shown in FIG.

Then, after the photoresist layer 160 exposed through the half-tone mask 170 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 10C. The first photoresist pattern 160a to the fourth photoresist pattern 160d having a predetermined thickness remain in the area where all the light is blocked or partially blocked and the photoresist film is completely removed in the first light transmission area I The surface of the protective film 115b is exposed.

At this time, the first to third photosensitive film patterns 160a to 160c formed in the blocking region III are formed thicker than the fourth photosensitive film pattern 160d formed through the second transmitting region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

10D, using the first to fourth photoresist patterns 160a to 160d formed as described above as a mask, a part of the protective film 115b formed under the photoresist film pattern is etched to form a A third contact hole 140c exposing a portion of the data pad line 117p and the gate pad electrode pattern 126p 'to the data pad portion and the gate pad portion of the array substrate 110, respectively, And a fourth contact hole 140d are formed.

At this time, a fifth contact hole exposing a part of the common electrode 108 may be formed in the pixel portion of the array substrate 110, though not shown in the figure.

Then, ashing process is performed to remove a part of the thicknesses of the first to fourth photoresist patterns 160a to 160d. As shown in FIG. 10E, The photoresist pattern is completely removed.

At this time, the first to third photosensitive film patterns correspond to the blocking region (III) with the fifth to the seventh photosensitive film patterns (160a ') to the seventh photosensitive film patterns (160c') removed by the thickness of the fourth photosensitive film pattern Only in the region where it is located. At this time, the first transmissive region I and the second transmissive region II substantially free from the fifth photoresist pattern 160a 'to the seventh photoresist pattern 160c' may be formed through a lift-off process A common electrode pattern, a data pad electrode, and a gate pad electrode.

A predetermined trench T may be formed on the data line 117 by removing a part of the thickness of the passivation layer 115b through a predetermined etching process. At this time, the trench T may be formed on the gate line. In this case, the common electrode pattern may have a lattice shape.

At this time, the protective layer 115b may be removed by a thickness substantially equal to the thickness of the common electrode pattern. However, the present invention is not limited thereto, and the etching process of the passivation layer 115b may not be performed, or a thickness different from the thickness of the common electrode pattern may be removed.

10F, a fifth conductive film 135 is formed on the entire surface of the array substrate 110 in a state where the fifth photosensitive film pattern 160a 'to the seventh photosensitive film pattern 160c' remain, .

The fifth conductive layer 135 may be formed of a transparent conductive material having a high transmittance such as indium-tin-oxide or indium-zinc-oxide to form a common electrode pattern, a data pad electrode, and a gate pad electrode .

Thereafter, a predetermined baking process may be performed.

As shown in FIG. 10G, the fifth photoresist pattern to the seventh photoresist pattern are removed through a lift-off process. At this time, the portions other than the first and second transmissive regions I and II The fifth conductive film remaining in the fifth conductive film pattern is removed together with the fifth conductive film pattern.

The fifth conductive layer is formed on the data line 117 (or the data line 117 and the gate line 116) of the array substrate 110 and the common electrode A common electrode pattern 108d electrically connected to the electrodes 108 is formed.

The data pad portion and the gate pad portion of the array substrate 110 are formed of the fifth conductive layer and are electrically connected to the data pad line 117p through the third contact hole 140c and the fourth contact hole 140d. A data pad electrode 127p and a gate pad electrode 126p electrically connected to the gate pad electrode pattern 126p 'are formed.

As described above, in the case of the first embodiment of the present invention, an array substrate including thin film transistors can be manufactured by four mask processes, thereby providing a manufacturing process and a cost saving effect.

In addition, since the active layer and the data line are formed through different mask processes, the active mask is not present in the 4-mask process according to the first embodiment of the present invention, The problem can be solved. In particular, by forming the common electrode pattern so as to overlap the data lines (or the data lines and gate lines) as described above, the transmittance can be maximized.

In addition, since there is no protective film between the common electrode and the pixel electrode, the transmissivity is improved by reducing the interval between the common electrode and the pixel electrode compared to the conventional structure, thereby providing a low power consumption effect. In particular, while the gate wiring and the pixel electrode are simultaneously patterned, the interval between the pixel electrode and the common electrode is minimized, so that the driving voltage can be minimized.

In addition, when the protective film over the data line is removed by a predetermined thickness, the step between the data line and the pixel region can be reduced by 40% or more compared to the conventional method, and the rubbing defect can be improved.

In addition, a direct connection between the gate wiring and the data wiring is possible, which is advantageous in that a narrow bezel due to shrinkage of the gate-in-panel (GIP) portion is facilitated.

In the array substrate according to the first embodiment of the present invention configured as described above, the color filter substrate is adhered to the color filter substrate in a state in which a certain cell gap is maintained by the column spacer. A color filter is formed.

At this time, the color filter substrate and the array substrate are bonded together through an align key formed on the color filter substrate or the array substrate.

In the meantime, the present invention is a method of patterning a gate wiring and a pixel electrode simultaneously using a half-tone mask, patterning an active layer using a half-tone mask and opening a gate insulating film of a pixel region, The array substrate can be fabricated by four mask processes by opening the pad portion through atmospheric etch, which will be described in detail through the following second embodiment of the present invention.

FIG. 11 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention, in which a fringe field formed between a pixel electrode and a common electrode passes through a slit, And Fig. 7 shows a part of an array substrate of a fringe field type liquid crystal display device which implements an image by driving liquid crystal molecules located on the fringe field type liquid crystal display device.

12 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention. In FIG. 12, the A-A 'line, the BB line and the CC Sectional view taken along a line in FIG.

In this case, one pixel including a pixel portion, a data pad portion, and a gate pad portion is shown for convenience of explanation. In an actual liquid crystal display device, N gate lines and M data lines cross each other and MxN pixels However, in order to simplify the description, one pixel is shown in the drawing.

As shown in the drawings, the array substrate 210 according to the second embodiment of the present invention includes a gate line 216 and a data line 217, which are vertically and horizontally arranged on the array substrate 210 to define a pixel region. Is formed. A thin film transistor, which is a switching device, is formed in the intersection region of the gate line 216 and the data line 217. In the pixel region, a pixel electrode 218 for driving the liquid crystal molecules by generating a fringe field, The common electrode 208 having the slits 208s of the common electrode 208 is formed.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 electrically connected to the pixel electrode 218 . The thin film transistor includes a gate insulating film 215a for insulation between the gate electrode 221 and the source and drain electrodes 222 and 223 and a source electrode 222 and a drain electrode 223 formed on the substrate.

At this time, the source / drain regions of the active layer 224 form ohmic contacts with the source / drain electrodes 222 and 223 through the ohmic-contact layer 225n.

The gate electrode 221 and the gate line 216 are formed of a conductive material that constitutes the pixel electrode 218 and are patterned in substantially the same manner as the gate electrode 221 and the gate line 216, A gate electrode pattern 221 'and a gate line pattern (not shown) are formed.

A part of the source electrode 222 extends in one direction and is connected to the data line 217. A part of the drain electrode 223 extends toward the pixel region and is electrically connected to the pixel electrode 218 directly Respectively.

As described above, the common electrode 208 and the pixel electrode 218 are formed in the pixel region to generate a fringe field. In this case, the pixel electrode 218 may be formed in a rectangular shape within the pixel region, The common electrode 208 may be formed to have a plurality of slits 208s in the pixel region.

At this time, the common electrode 208 is formed on the pixel electrode 218 with a protective film 215b interposed therebetween, and the common electrode 208 between the slits 208s may have a finger shape.

The common electrode 208 is formed on the data line 217, and the common electrode 208 can be formed in a single pattern over the entire image display region in which an image is displayed. At this time, the common electrode 208 may be formed to overlap not only the data line 217 but also the gate line 216.

The active layer 224 and the data line 217 are formed through a mask process different from the active layer 224 and the data line 217. In this case, The active tail is not formed in the lower portion of the first electrode 217, so that the transmittance can be maximized.

A gate pad line 216p and a data pad line 217p electrically connected to the gate line 216 and the data line 217 are formed in an edge region of the array substrate 210, And transmits a scan signal and a data signal applied from a driving circuit (not shown) to the gate line 216 and the data line 217, respectively.

That is, the data line 217 and the gate line 216 extend to the driving circuit portion and are connected to the corresponding data pad line 217p and the gate pad line 216p, And the data signal and the scanning signal are respectively supplied from the driving circuit section through the line 216p.

A gate pad line pattern 216p 'formed of a conductive material forming the pixel electrode 218 and patterned in substantially the same shape as the gate pad line 216p is formed under the gate pad line 216p. Respectively.

In the fringe field type liquid crystal display device according to the second embodiment of the present invention configured as described above, gate lines (i.e., the gate electrode 221 and the gate line 216) and the pixel electrode 218 The active layer 224 is formed using a half-tone mask and the gate insulating film 215a of the pixel region is opened for connection of the pixel electrode 218. [ Further, the data lines (that is, the source electrode 222, the drain electrode 223, and the data line 217), the protective film 215b, and the common electrode 208 are formed in order, The array substrate 210 can be manufactured through four mask processes by opening the pad portion.

Hereinafter, a manufacturing method of a fringe field type liquid crystal display device according to a second embodiment of the present invention will be described in detail with reference to the drawings.

Figs. 13A to 13D are plan views sequentially showing the manufacturing steps of the array substrate shown in Fig.

14A to 14E are cross-sectional views sequentially showing the manufacturing steps of the array substrate shown in Fig. 12, wherein the left side shows the process of manufacturing the array substrate of the pixel portion, and the right side shows the array of data pads and gate pads, Thereby producing a substrate.

13A and 14A, a gate electrode 221, a gate line 216, and a pixel electrode 218 are formed in a pixel portion of an array substrate 210 made of a transparent insulating material such as glass, And a gate pad line 216p is formed in the gate pad portion of the array substrate 210. [

The gate electrode 221, the gate line 216, the pixel electrode 218 and the gate pad line 216p are formed by depositing a first conductive film and a second conductive film on the entire surface of the array substrate 210 and then performing a photolithography process A first mask process).

At this time, the pixel electrode 218 is formed of the first conductive film, and the gate electrode 221, the gate line 216, and the gate pad line 216p are formed of the second conductive film.

The gate electrode 221, the gate line 216, and the gate pad line 216 p are formed of the first conductive film. The gate electrode 221, the gate line 216, A gate line pattern (not shown) and a gate pad line pattern 216 p 'are formed in substantially the same pattern as the gate electrode pattern 216'.

As described above, the gate wiring (that is, the gate electrode 221 and the gate line 216) and the pixel electrode 218 can be simultaneously patterned through a single mask process by using a half-tone mask having a large area Hereinafter, the first mask process will be described in detail with reference to the drawings.

15A to 15F are cross-sectional views illustrating a first mask process according to a second embodiment of the present invention shown in FIG. 14A.

As shown in FIG. 15A, a first conductive film 231 and a second conductive film 232 are sequentially deposited on an entire surface of an array substrate 210 made of a transparent insulating material such as glass.

The first conductive layer 231 may be formed of a transparent conductive material having a high transmittance such as indium-tin-oxide or indium-zinc-oxide to form a pixel electrode.

The second conductive layer 232 may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a gate wiring. The second conductive layer 232 may have a multi-layered structure in which two or more low-resistance conductive materials are stacked.

15B, a photosensitive film 260 made of a photosensitive material such as a photoresist is formed on the array substrate 210 on which the second conductive film 232 is formed. Then, And selectively irradiates light to the photoresist layer 260 through a half-tone mask 270 according to the pattern.

At this time, the half-tone mask 270 is provided with a first transmissive region I through which all the irradiated light is transmitted, a second transmissive region II through which only a part of light is partially blocked, And only the light that has passed through the half-tone mask 270 is irradiated to the photoresist layer 260.

Then, after the photoresist layer 260 exposed through the half-tone mask 270 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 15C. A first photoresist pattern 260a to a third photoresist pattern 260c having a predetermined thickness are left in an area where all the light is blocked or partially blocked and the photoresist layer is completely removed in the first light transmission area I The surface of the second conductive layer 232 is exposed.

At this time, the first photoresist pattern 260a and the second photoresist pattern 260b formed in the blocking region III are thicker than the third photoresist pattern 260c formed through the second transmissive region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 15D, using the first photosensitive film pattern 260a to the third photosensitive film pattern 260c formed as described above as a mask, a first conductive film and a second conductive film A pixel electrode 218 made of the first conductive film is formed on the pixel portion of the array substrate 210. [

A gate electrode 221 and a gate line (not shown) formed of the second conductive film are formed in a pixel portion of the array substrate 210. In the gate pad portion of the array substrate 210, A gate pad line 216p made of a film is formed.

At this time, a second conductive film pattern 232 'formed of the second conductive film and patterned in substantially the same shape as the pixel electrode 218 is formed on the pixel electrode 218.

The first conductive film is formed under the gate electrode 221 and the gate line and the gate pad line 216p and is substantially the same as the gate electrode 221 and the gate line and the gate pad line 216p A gate electrode pattern 221 ', a gate line pattern (not shown), and a gate pad line pattern 216 p' are patterned.

15E, when the ashing process for removing a part of the thicknesses of the first to third photoresist patterns 260a to 260c is performed, The photoresist pattern is completely removed.

At this time, the first photoresist pattern and the second photoresist pattern correspond to the blocking area III by the fourth photoresist pattern 260a 'and the fifth photoresist pattern 260b', which are removed by the thickness of the third photoresist pattern Only in the region where it is located.

15F, using the fourth photoresist pattern 260a 'and the fifth photoresist pattern 260b' as a mask, a second conductive film pattern (not shown) formed on the pixel electrode 218 through etching, .

Next, as shown in FIGS. 13B and 14B, on the entire surface of the array substrate 210 on which the gate electrode 221, the gate line 216, the pixel electrode 218 and the gate pad line 216p are formed, The amorphous silicon thin film and the n + amorphous silicon thin film are formed.

Thereafter, the gate insulating film 215a, the amorphous silicon thin film, and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form active portions of the amorphous silicon thin film in the pixel portion of the array substrate 210 To form a layer 224.

The gate insulating layer 215a on the pixel electrode 218 is entirely etched through the second mask process to form an open hole H for opening the pixel region, A pad portion open hole 240 is formed to expose a part of the gate pad line 216p.

At this time, an n + amorphous silicon thin film pattern 225 'patterned in substantially the same form as the active layer 224 is formed on the active layer 224.

In this case, the second mask process according to the second embodiment of the present invention can use a half-tone mask, which will be described in detail with reference to the following drawings.

FIGS. 16A to 16F are cross-sectional views illustrating a second mask process according to a second embodiment of the present invention shown in FIG. 14B.

The gate insulating film 215a and the gate insulating film 215b are sequentially formed on the entire surface of the array substrate 210 on which the gate electrode 221, the gate line 216, the pixel electrode 218 and the gate pad line 216p are formed, An amorphous silicon thin film 220 and an n + amorphous silicon thin film 225 are deposited.

Thereafter, as shown in FIG. 16B, a photosensitive film 260 made of a photosensitive material such as photoresist is formed on the array substrate 210 on which the n + amorphous silicon thin film 225 is formed, And selectively irradiates light to the photoresist layer 260 through a half-tone mask 270 according to the pattern.

At this time, the half-tone mask 270 is provided with a first transmissive region I through which all the irradiated light is transmitted, a second transmissive region II through which only a part of light is partially blocked, And only the light that has passed through the half-tone mask 270 is irradiated to the photoresist layer 260.

Then, after the photoresist layer 260 exposed through the half-tone mask 270 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 16C. A first photoresist pattern 260a and a second photoresist pattern 260b having a predetermined thickness are left in a region where all the light is blocked or partially blocked and the photoresist layer is completely removed in the first light transmission region I The surface of the n + amorphous silicon thin film 225 is exposed.

At this time, the first photoresist pattern 260a formed in the blocking region III is thicker than the second photoresist pattern 260b formed through the second transmissive region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 16D, using the first photoresist pattern 260a and the second photoresist pattern 260b formed as described above as a mask, a gate insulating layer 215a formed under the photoresist pattern and an amorphous silicon The openings H for exposing the pixel electrodes 218 to the outside are formed in the pixel portion of the array substrate 210 and the openings H for exposing the pixel electrodes 218 to the outside are formed, A pad portion open hole 240 for exposing a part of the gate pad line 216p is formed in a gate pad portion of the pad portion 210. [

16E, when the ashing process for removing a part of the thickness of the first and second photoresist patterns 260a and 260b is performed, the second photoresist pattern 260a and the second photoresist pattern 260b are removed. The photoresist pattern is completely removed.

At this time, the first photoresist pattern remains only in a region corresponding to the blocking region III with the third photoresist pattern 260a 'removed by the thickness of the second photoresist pattern.

Thereafter, as shown in FIG. 16F, using the third photoresist pattern 260a 'as a mask, a part of the amorphous silicon thin film and the n + amorphous silicon thin film formed therebelow are selectively removed through etching, An active layer 224 made of the amorphous silicon thin film is formed in the pixel portion of the array substrate 210. [

At this time, an n + amorphous silicon thin film pattern 225 'patterned in substantially the same form as the active layer 224 is formed on the active layer 224.

Next, as shown in FIGS. 13C and 15C, a source electrode 222 and a drain electrode (not shown) are formed in the pixel portion of the array substrate 210 on which the active layer 224 and the n + amorphous silicon thin film pattern 225 ' 223 and a data line 217 and a data pad line 217p is formed in a data pad portion of the array substrate 210. [

At this time, the drain electrode 223 is directly electrically connected to the pixel electrode 218.

The source electrode 222, the drain electrode 223, the data line 217 and the data pad line 217p are formed by depositing a third conductive film on the entire surface of the array substrate 210 and then performing a general photolithography process And then patterned selectively.

The third conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form data lines and data pad lines 217p. In addition, the third conductive film may be formed in a multi-layered structure in which two or more low resistance conductive materials are stacked.

Thereafter, predetermined O ₂ ashing can proceed.

13D and 14D, on the entire surface of the array substrate 210 on which the source electrode 222, the drain electrode 223, the data line 217 and the data pad line 217p are formed, A protective film 215b made of an organic insulating film is formed.

At this time, the protective layer 215b may be formed in a multi-layer structure of two or more layers.

A fourth conductive layer is deposited on the entire surface of the array substrate 210 and selectively patterned through a general photolithography process (fourth mask process) to form the fourth conductive layer in the pixel portion of the array substrate 210 The common electrode 208 is formed.

At this time, the common electrode 208 may be formed to have a plurality of slits 208s in the pixel region.

The common electrode 208 may be formed on the pixel electrode 218 with a protective film 215b interposed therebetween and the common electrode 208 between the slits 208s may have a finger shape.

The common electrode 208 is formed on the data line 217, and the common electrode 208 can be formed in a single pattern over the entire image display region in which an image is displayed. At this time, the common electrode 208 may be formed to overlap not only the data line 217 but also the gate line 216.

The active layer 224 and the data line 217 are formed through a mask process different from the active layer 224 and the data line 217. In this case, The active tail is not formed in the lower portion of the first electrode 217, so that the transmittance can be maximized.

As shown in FIG. 14E, the array substrate 210 according to the second embodiment of the present invention has a structure in which the color filter substrate 205 is adhered to the color filter substrate 205 in a state where a certain cell gap is maintained by the column spacer 250 At this time, the color filter substrate 205 is provided with a color filter (not shown) for realizing red, green and blue colors.

At this time, the color filter substrate 205 and the array substrate 210 are bonded to each other through an attachment key (not shown) formed on the color filter substrate 205 or the array substrate 210.

Next, the passivation layer 215b of the pad portion is removed through a predetermined etching process at normal pressure so that the data pad line 217p and the gate pad line 216p are exposed to the outside.

As described above, in the case of the second embodiment of the present invention, the array substrate including the thin film transistors can be manufactured by the four mask processes in the same manner as the first embodiment of the present invention, thereby providing a manufacturing process and a cost reduction effect do.

In the 4-mask process according to the second embodiment of the present invention, since the active layer and the data line are formed through different mask processes, there is no active tail, so that the problem of the aperture ratio loss and the light leakage The problem can be solved. In particular, by forming the common electrode pattern so as to overlap the data lines (or the data lines and gate lines) as described above, the transmittance can be maximized.

In addition, since the gate insulating film is removed between the common electrode and the pixel electrode and only the protective film is present, the transmittance is improved by reducing the interval between the common electrode and the pixel electrode compared to the conventional structure, thereby providing low power consumption. In particular, while the gate wiring and the pixel electrode are simultaneously patterned, the interval between the pixel electrode and the common electrode is minimized, so that the driving voltage can be minimized.

In addition, since the gate wiring and the data wiring can be directly connected, there is an advantage that the narrow bezel according to the reduction of the gate-in-panel part is facilitated.

Although the amorphous silicon thin film transistor using the amorphous silicon thin film as the active layer is described as an example of the fringe field type liquid crystal display of the first and second embodiments of the present invention, the present invention is not limited thereto. A polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as an active layer, and an oxide thin film transistor using an oxide.

In addition, the present invention can be applied not only to a liquid crystal display but also to an organic electroluminescent display device in which organic electroluminescent devices (Organic Light Emitting Diodes) are connected to other display devices manufactured using thin film transistors, for example, driving transistors .

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

108, 208: common electrode 108s, 208s: slit
110, 210: array substrate 116, 216: gate line
116p, 216p: gate pad line 117, 217: data line
117p and 217p: data pad lines 118 and 218: pixel electrodes
121, 221: gate electrodes 122, 222: source electrode
123, 223: drain electrode 124, 224: active layer
126p: gate pad electrode 127p: data pad electrode

Claims (19)

Forming a pixel electrode made of a first conductive film in a pixel portion of the first substrate through a first mask process and forming a gate electrode and a gate line made of a second conductive film;
Forming a gate insulating layer on the entire surface of the first substrate on which the gate electrode, the gate line, and the pixel electrode are formed;
Forming an active layer in a pixel portion of the first substrate through a second mask process and forming a first contact hole exposing the pixel electrode;
Forming a common electrode made of a third conductive film in a pixel portion of the first substrate through a third mask process and forming a source electrode and a drain electrode and a data line made of a fourth conductive film;
Forming a protective film on the entire surface of the first substrate on which the source electrode, the drain electrode, the data line, and the common electrode are formed;
Forming a fifth contact hole exposing a portion of the common electrode by selectively patterning the passivation layer through a fourth mask process; forming a trench along the data line above the data line by removing a thickness of the passivation layer; ;
Forming a fifth conductive layer on the entire surface of the first substrate in a state where the photoresist pattern used in the fourth mask process remains;
The fifth conductive film formed on the photoresist pattern and the photoresist pattern is selectively removed through a lift-off process to form the fifth conductive film in the trench, and the fifth conductive film is electrically connected to the common electrode through the fifth contact hole Forming a common electrode pattern; And
And bonding the first substrate and the second substrate to each other. The method of claim 1, wherein a gate pad line of the second conductive film is formed in a gate pad portion of the first substrate through the first mask process. The method as claimed in claim 2, wherein the gate electrode pattern and the gate line pattern are formed on the gate electrode and the gate line through the first mask process, And forming a gate pad line pattern made of a film. The method of claim 2, wherein the second contact hole exposes the gate pad line to the gate pad portion of the first substrate through the second mask process. The method of claim 2, further comprising: forming a data pad line of the fourth conductive film on the data pad portion of the first substrate through the third mask process, And forming a gate pad electrode pattern composed of the gate electrode pattern. The method of claim 5, further comprising forming a source electrode pattern, a drain electrode pattern, and a data line pattern including the third conductive film on the source electrode, the drain electrode, and the data line through the third mask process, And forming a data pad line pattern made of the third conductive film under the pad line. The method as claimed in claim 5, wherein the protective film is selectively patterned through the fourth mask process to form a third contact hole and a fourth contact hole exposing the data pad line and the gate pad electrode pattern, respectively, ≪ / RTI > delete The method of claim 7, further comprising: selectively removing the fifth conductive layer formed on the photoresist pattern and the photoresist pattern through the lift-off process to form the data pad line and the data pad line through the third contact hole and the fourth contact hole, Forming a data pad electrode and a gate pad electrode electrically connected to the gate pad electrode pattern. The liquid crystal display device according to claim 1, wherein the trench is formed not only on the data line but also on the gate line, and forms a lattice-shaped common electrode pattern on the data line and the gate line through the lift- A method of manufacturing a display device. The method of claim 1, wherein the common electrode has a plurality of slits in each pixel region, and the common electrode between the slits has a finger shape. A gate electrode and a gate line formed in the pixel portion of the first substrate, the gate electrode being composed of a pixel electrode and a second conductive film;
A gate insulating layer provided on the entire surface of the first substrate including the gate electrode, the gate line, and the pixel electrode, and including a first contact hole exposing a part of the pixel electrode;
An active layer provided in a pixel portion of the first substrate provided with the gate insulating film;
A source electrode and a drain electrode formed on the pixel portion of the first substrate having the active layer and including a common electrode and a fourth conductive film, and a data line;
And a fifth contact hole provided on the entire surface of the first substrate including the source electrode, the drain electrode, the data line, and the common electrode, and exposing a part of the common electrode;
A trench in which a part of the thickness of the protective film is removed along the data line in a protective film on the data line;
A common electrode pattern made of a fifth conductive film in the trench and electrically connected to the common electrode through the fifth contact hole; And
And a second substrate bonded to and facing the first substrate. 13. The liquid crystal display of claim 12, wherein the trench is provided on the data line and the gate line, and the common electrode pattern is provided in a lattice form on the data line and the gate line. Forming a pixel electrode made of a first conductive film in a pixel portion of the first substrate through a first mask process and forming a gate electrode and a gate line made of a second conductive film;
Forming a gate insulating layer on the entire surface of the first substrate on which the gate electrode, the gate line, and the pixel electrode are formed;
Forming an active layer in a pixel portion of the first substrate through a second mask process and removing an insulating film over the pixel electrode to form an open hole exposing a pixel region;
Forming a source electrode, a drain electrode, and a data line made of a third conductive film in a pixel portion of the first substrate through a third mask process;
Forming a protective film on the entire surface of the first substrate on which the source electrode, the drain electrode, and the data line are formed;
Forming a common electrode made of a fourth conductive film in a pixel portion of the first substrate through a fourth mask process;
Attaching the first substrate and the second substrate such that a data pad portion and a gate pad portion of the first substrate are exposed; And
And removing the protective film formed on the data pad portion and the gate pad portion by etching at normal pressure in a state in which the data pad portion and the gate pad portion are exposed to open the data pad portion and the gate pad portion A method of manufacturing a fringe field type liquid crystal display device. 15. The method of claim 14, wherein the gate pad line of the second conductive layer is formed in the gate pad portion of the first substrate through the first mask process. 16. The method of claim 15, further comprising: forming a gate electrode pattern and a gate line pattern made of the first conductive film through the gate electrode and the gate line through the first mask process; And forming a gate pad line pattern made of a film. 17. The method of claim 16, wherein the data pad line of the third conductive layer is formed in the data pad portion of the first substrate through the third mask process. 15. The method according to claim 14, wherein the common electrode is formed in a single pattern over the entire pixel portion. 19. The method of claim 18, wherein the common electrode has a plurality of slits in each pixel region, and the common electrode between the slits is formed to have a finger shape.

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