KR101964088B1 - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A Fringe Field Switching (FFS) liquid crystal display device and a manufacturing method thereof according to the present invention are characterized in that a gate wiring and a pixel electrode (or a common electrode) are simultaneously patterned by a single mask process, The data lines are simultaneously patterned to reduce the number of masks, thereby simplifying the fabrication process and reducing the fabrication cost.
Particularly, in the fringe field type liquid crystal display device and the method of manufacturing the same of the present invention, in the above-described four mask process, an etch stopper is deposited before the gate insulating film is deposited, The gap between the pixel electrode and the common electrode can be reduced by removing the gate insulating film, thereby reducing power consumption.

Description

Field of the Invention [0001] The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same. BACKGROUND OF THE INVENTION [0002]

Field of the Invention [0002] The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same, and more particularly, to a fringe field type liquid crystal display device capable of simultaneously realizing a high resolution and a high transmittance, and a method of manufacturing the same.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

With reference to the drawings will be described in detail a typical liquid crystal display device.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.

As shown in the drawing, a typical liquid crystal display device includes a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and blocking light transmitted through the liquid crystal layer 30 and a transparent common And an electrode (8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17, A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal panel, and the color filter substrate 5 (Not shown) formed on the color filter substrate 5 or the array substrate 10 are bonded to each other.

In this case, there is a twisted nematic (TN) method in which a nematic liquid crystal molecule is driven in a direction perpendicular to a substrate by a driving method generally used in the liquid crystal display device. However, the twisted nematic liquid crystal display Has a disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules, because liquid crystal molecules aligned horizontally with the substrate are oriented in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal panel.

There is an in-plane switching (IPS) type liquid crystal display device in which liquid crystal molecules are driven in a horizontal direction with respect to a substrate to improve a viewing angle to 170 degrees or more.

FIG. 2 is a cross-sectional view schematically showing a part of an array substrate of a transverse electric field type liquid crystal display device in which a fringe field formed between a pixel electrode and a common electrode passes through a slit to drive liquid crystal molecules positioned on a pixel region and a common electrode And shows a part of an array substrate of a fringe field switching (FFS) liquid crystal display device implementing an image.

As shown in the figure, a gate line (not shown) and a data line 17, which are vertically and horizontally arranged on the transparent array substrate 10 to define a pixel region, are formed on an array substrate 10 of a general fringe field type liquid crystal display device. And a thin film transistor, which is a switching element, is formed in an intersecting region of the gate line and the data line 17. [

The thin film transistor includes a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line, and a drain electrode 23 connected to the pixel electrode 18. The thin film transistor has a gate insulating film 15a for insulation between the gate electrode 21 and the source and drain electrodes 22 and 23 and a source electrode And an active layer 24 forming a conductive channel between the drain electrode 22 and the drain electrode 23.

At this time, the source / drain region of the active layer 24 forms an ohmic contact with the source / drain electrodes 22 and 23 through an ohmic contact layer 25n.

A common electrode 8 and a pixel electrode 18 are formed in the pixel region and the common electrode 8 is formed in the common electrode 8 to generate a fringe field together with the pixel electrode 18 having a rectangular shape. 8 includes a plurality of slits 8s.

Reference numeral 15b denotes a protective film.

The fringe field type liquid crystal display having the above structure has an advantage of improving the viewing angle and transmittance as compared with the conventional twisted nematic system. However, in the fabrication of the array substrate including the thin film transistor, (That is, a photolithography process), a method of reducing the number of masks in terms of productivity is required.

SUMMARY OF THE INVENTION The present invention provides a fringe field type liquid crystal display device in which an array substrate is manufactured by four mask processes and a manufacturing method thereof.

It is another object of the present invention to provide a fringe field type liquid crystal display device and a method of manufacturing the same that can reduce the power consumption by reducing the interval between the pixel electrode and the common electrode in the 4-mask process.

Other objects and features of the present invention will be described in the following description of the invention and the claims.

According to an aspect of the present invention, there is provided a method of manufacturing a fringe field type liquid crystal display device, comprising: providing a first substrate divided into a pixel portion and a pad portion; Forming a first electrode made of a first conductive film in a pixel portion of the first substrate through a first mask process and forming a gate electrode and a gate line and a common line made of a second conductive film; Sequentially forming an etch stopper and an insulating layer on the entire surface of the first substrate on which the first electrode, the gate electrode, the gate line, and the common line are formed, the etching stopper having an etch selectivity with respect to the dry etching; Forming an active layer in a pixel portion of the first substrate through a second mask process, forming a source electrode and a drain electrode of a third conductive film, and a data line crossing the gate line and defining a pixel region; Exposing an etch stopper of the pixel region by removing an insulating film over the first electrode through the second mask process; Forming a protective film on the entire surface of the first substrate on which the active layer, the source electrode, the drain electrode, and the data line are formed; Forming a first contact hole exposing the drain electrode by selectively removing the protective film through a third mask process; Forming a second electrode having a plurality of slits in a pixel region where the insulating film is removed through a fourth mask process, the fourth electrode being a fourth conductive film; And bonding the first substrate and the second substrate together.

In this case, a gate pad line made of the first conductive film is formed in the pad portion of the first substrate through the first mask process.

And a data pad line made of the third conductive film is formed on the pad portion of the first substrate through the second mask process.

The etch stopper is formed of a silicon oxide (SiO ₂ ) film having a thickness of 100 Å to 500 Å.

And the insulating film is formed of a silicon nitride film (SiNx).

A first gate insulating film formed of the insulating film between the gate electrode and the active layer and patterned to have substantially the same shape as the active layer is formed.

At this time, a second gate insulating film, a first amorphous silicon thin film pattern, and a second n + amorphous silicon thin film, which are composed of the nitride film, the amorphous silicon thin film and the n + amorphous silicon thin film and are patterned substantially in the same pattern as the data line, And a thin film pattern is formed.

The third gate insulating layer, the second amorphous silicon thin film pattern, and the third amorphous silicon thin film, which are formed of the nitride film, the amorphous silicon thin film and the n + amorphous silicon thin film and are patterned substantially in the same pattern as the data pad line, and an n + amorphous silicon thin film pattern is formed.

Wherein the first electrode forms a square pixel electrode, and the second electrode forms a rectangular common electrode.

At this time, the etch stopper and the protective layer are selectively removed using the third mask process, thereby forming a second contact hole exposing the pixel electrode.

At this time, the fourth mask process is used to form a connection electrode electrically connected to the drain electrode via the first contact hole and electrically connected to the pixel electrode through the second contact hole .

Wherein the first electrode forms a rectangular common electrode and the second electrode forms a rectangular pixel electrode.

In this case, the pixel electrode is electrically connected to the drain electrode through the first contact hole.

A fringe field type liquid crystal display device of the present invention includes: a gate electrode formed on a first substrate and including a first electrode and a second conductive film; a gate line and a common line; An etch stopper formed on the entire surface of the first substrate on which the first electrode, the gate electrode, the gate line, and the common line are formed; An active layer formed on the gate electrode through a first gate insulating film made of an insulating film having an etch selectivity to the etch stopper; A data line formed on the active layer and defining a pixel region intersecting the source electrode and the drain electrode of the third conductive film and the gate line; A protection layer formed on the entire surface of the first substrate on which the source electrode, the drain electrode, and the data line are formed; A second electrode formed of a fourth conductive film in a pixel region of the first substrate on which the protective film is formed and having a plurality of slits; And a second substrate which is adhered to and opposed to the first substrate, wherein the first gate insulating film is patterned to have substantially the same shape as the active layer, and the insulating film is removed between the first electrode and the second electrode .

At this time, the etch stopper is formed of a silicon oxide film having a thickness of 100 Å to 500 Å.

And the insulating film is formed of a silicon nitride film.

A second amorphous silicon thin film pattern and a second amorphous silicon thin film pattern formed of the nitride film, the amorphous silicon thin film and the n + amorphous silicon thin film and patterned in substantially the same pattern as the data line, Is formed.

Wherein the first electrode constitutes a square pixel electrode and the second electrode constitutes a rectangular common electrode.

In this case, a first contact hole exposing the drain electrode and a second contact hole exposing the pixel electrode may be additionally provided, by selectively removing the etch stopper and the protective layer.

The organic light emitting display further includes a connection electrode electrically connected to the drain electrode through the first contact hole and electrically connected to the pixel electrode through the second contact hole.

As described above, in the fringe field type liquid crystal display device and the method of manufacturing the same according to the present invention, the gate wiring and the pixel electrode (or the common electrode) are simultaneously patterned by a single mask process, and the active layer and the data The wiring is simultaneously patterned to reduce the number of masks, thereby simplifying the manufacturing process and reducing the manufacturing cost.

In the method of manufacturing a fringe field type liquid crystal display device according to the present invention, an etch stopper is deposited before the gate insulating film is deposited, and then the gate insulating film The interval between the pixel electrode and the common electrode is reduced, thereby providing an effect of reducing the power consumption.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.
2 is a cross-sectional view schematically showing a part of an array substrate of a transverse electric field type liquid crystal display device.
3 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention.
4 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention.
5 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention.
6A to 6D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.
7A to 7D are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 5;
8A to 8F are cross-sectional views illustrating a first mask process according to a second embodiment of the present invention shown in FIG. 7A.
9A to 9F are cross-sectional views illustrating a second mask process according to a second embodiment of the present invention shown in FIG. 7B.
10 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a third embodiment of the present invention.
11 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a third embodiment of the present invention.
FIGS. 12A to 12D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG. 10; FIG.
13A to 13D are sectional views sequentially showing a manufacturing process of the array substrate shown in Fig.

Hereinafter, preferred embodiments of a fringe field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention, in which a fringe field formed between a pixel electrode and a common electrode passes through a slit, And Fig. 7 shows a part of an array substrate of a fringe field type liquid crystal display device which implements an image by driving liquid crystal molecules located on the fringe field type liquid crystal display device.

In the fringe field type liquid crystal display device, a pixel electrode is formed in a lower part while a liquid crystal molecule is oriented horizontally, and a common electrode having a slit is formed in an upper part, so that an electric field is generated in horizontal and vertical directions, and is driven by a twist and a tilt.

3, the array substrate 110 according to the first embodiment of the present invention includes gate lines (not shown) arranged vertically and horizontally on the array substrate 110 to define pixel regions and data lines 117 Is formed. In addition, a thin film transistor, which is a switching element, is formed in the intersection region of the gate line and the data line 117. In the pixel region, a pixel electrode 118 for driving liquid crystal molecules by generating a fringe field and a plurality of slits A common electrode 108 having a plurality of electrodes 108s is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. The thin film transistor includes a gate insulating layer 115a for insulation between the gate electrode 121 and the source and drain electrodes 122 and 123 and a source electrode And an active layer 124 that forms a conduction channel between the drain electrode 122 and the drain electrode 123.

At this time, the source / drain regions of the active layer 124 form ohmic contacts with the source / drain electrodes 122 and 123 through the ohmic-contact layer 125n.

At this time, the gate electrode 121 and the gate line are formed with a gate electrode pattern (not shown) which is made of a conductive material constituting the pixel electrode 118 and is patterned substantially in the same shape as the gate electrode 121 and the gate line 121 'and a gate line pattern (not shown) are formed.

The amorphous silicon thin film pattern 120 'and the n + amorphous silicon thin film pattern 120', which are formed of the amorphous silicon thin film and the n + amorphous silicon thin film and are patterned substantially in the same pattern as the data line 117, (125 ') are formed.

A part of the source electrode 122 extends in one direction and is connected to the data line 117. A part of the drain electrode 123 extends toward the pixel region and the gate insulating layer 115a and the protective layer 115b The pixel electrode 118 is electrically connected to the pixel electrode 118 through the contact hole formed in the pixel electrode 118 and the connection electrode 190.

As described above, the common electrode 108 and the pixel electrode 118 are formed in the pixel region to generate a fringe field. At this time, the pixel electrode 118 may be formed in a rectangular shape within the pixel region, The common electrode 108 may be formed to have a plurality of slits 108s in the pixel region. However, the present invention is not limited to the structure of the common electrode 108 and the pixel electrode 118. The present invention can also be applied to a case where a common electrode is formed on the lower side and a pixel electrode having a plurality of slits on the lower side is formed It is possible.

The fringe field type liquid crystal display according to the first embodiment of the present invention configured as described above includes a half tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask, including a diffraction mask) (That is, the gate electrode 121 and the gate line) and the pixel electrode 118 are simultaneously patterned using the half-tone mask, and the active layer 124 and the data line The electrode 122, the drain electrode 123, and the data line 117) are simultaneously patterned, the array substrate 110 can be manufactured through four mask processes. The drain electrode 123 and the pixel electrode 118 are connected to each other through the contact hole formed in the gate insulating layer 115a and the protective layer 115b and the connection electrode 190, The common electrode 190 may be formed by patterning at the same time when the common electrode 108 is formed.

In the fringe field type liquid crystal display device according to the first embodiment of the present invention, the number of masks required to manufacture the array substrate 110 is reduced. However, in order to reduce the number of masks, the pixel electrodes 118 are formed on the same layer The gap between the pixel electrode 118 and the common electrode 108 is increased as compared with the conventional method, so that the driving voltage is increased. If the thickness of the passivation layer 115b is reduced to reduce the distance between the pixel electrode 118 and the common electrode 108, the capacitance between the data line 117 and the common electrode 108 increases The load of the data line 117 is increased, and a side effect of increasing the power consumption of the circuit part occurs.

Thus, in the fourth embodiment of the present invention, an etch stopper is deposited before the gate insulating film is deposited, and then the gate insulating film above the pixel electrode is removed during the patterning of the data line, And the power consumption can be reduced by reducing the interval between the common electrode and the common electrode, which will be described in detail with reference to the drawings.

4 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention.

5 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a second embodiment of the present invention. In FIG. 5, A-A 'line, BB line and CC Sectional view taken along a line in FIG.

In this case, one pixel including a pixel portion, a data pad portion, and a gate pad portion is shown for convenience of explanation. In an actual liquid crystal display device, N gate lines and M data lines cross each other and MxN pixels However, in order to simplify the description, one pixel is shown in the drawing.

As shown in the drawings, the array substrate 210 according to the second embodiment of the present invention includes a gate line 216 and a data line 217, which are vertically and horizontally arranged on the array substrate 210 to define a pixel region. Is formed. A thin film transistor, which is a switching device, is formed in the intersection region of the gate line 216 and the data line 217. In the pixel region, a pixel electrode 218 for driving the liquid crystal molecules by generating a fringe field, The common electrode 208 having the slits 208s of the common electrode 208 is formed.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 electrically connected to the pixel electrode 218 . The thin film transistor includes a first gate insulating layer 215a 'for insulation between the gate electrode 221 and the source / drain electrodes 222 and 223, and a gate electrode And an active layer 224 that forms a conduction channel between the source electrode 222 and the drain electrode 223.

At this time, the source / drain regions of the active layer 224 form ohmic contacts with the source / drain electrodes 222 and 223 through the ohmic-contact layer 225n. The first gate insulating layer 215a 'is made of a silicon nitride (SiNx) layer having a thickness of about 4000 Å, and is patterned to have substantially the same shape as the active layer 224 thereon.

The first gate insulating layer 215a 'is formed in an island shape between the gate electrode 221 and the active layer 224, and in particular, the second embodiment of the present invention includes the gate electrode 221 and the first An etch stopper 215 made of a silicon oxide (SiO ₂ ) film having a thickness of about 100 Å to 500 Å is formed on the entire surface of the array substrate 210 between the gate insulating films 215a '.

The gate electrode 221 and the gate line 216 are formed of a conductive material that constitutes the pixel electrode 218 and are patterned in substantially the same manner as the gate electrode 221 and the gate line 216, A gate electrode pattern 221 'and a gate line pattern (not shown) are formed.

A second gate insulating layer 215a ", which is formed of the silicon nitride layer, the amorphous silicon layer and the n + amorphous silicon layer and is patterned substantially in the same pattern as the data line 217, is formed under the data line 217, 1 amorphous silicon thin film pattern 220 'and a second n + amorphous silicon thin film pattern 225' are formed.

A part of the source electrode 222 extends in one direction and is connected to the data line 217. A part of the drain electrode 223 extends toward the pixel region and is electrically connected to the etch stopper 215, The first contact hole 240a and the second contact hole 240b and the connection electrode 290 are electrically connected to the pixel electrode 218 through the first contact hole 240a and the second contact hole 240b.

As described above, the common electrode 208 and the pixel electrode 218 are formed in the pixel region to generate a fringe field. In this case, the pixel electrode 218 may be formed in a rectangular shape within the pixel region, The common electrode 208 may be formed to have a plurality of slits 208s in the pixel region. However, the present invention is not limited to the structure of the common electrode 208 and the pixel electrode 218. The present invention can also be applied to a case where a common electrode is formed at a lower portion and a pixel electrode having a plurality of slits is formed at an upper portion It is possible.

A common line 2081 may be disposed in a direction substantially parallel to the gate line 216. The common electrode 208 may be disposed between the etch stopper 215 and the protective film 215b, And is electrically connected to the common line 2081 through the second line 240c.

A gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in an edge region of the array substrate 210, And transmits a scan signal and a data signal applied from a driving circuit (not shown) to the gate line 216 and the data line 217, respectively.

That is, the data line 217 and the gate line 216 extend to the driving circuit portion and are connected to the corresponding data pad line 217p and the gate pad line 216p, The line 216p is connected to a data signal line and a scan signal from the driving circuit through a data pad electrode 227p and a gate pad electrode 226p electrically connected to the data pad line 217p and the gate pad line 216p, .

At this time, the data pad line 217p is electrically connected to the data pad electrode 227p through the fourth contact hole 240d, and the gate pad line 216p is electrically connected to the data pad electrode 227p through the fifth contact hole 240e And is electrically connected to the gate pad electrode 226p.

A third gate insulating layer 215a '' formed of the silicon nitride layer, the amorphous silicon layer and the n + amorphous silicon layer and patterned substantially in the same pattern as the data pad line 217p is formed under the data pad line 217p. A second amorphous silicon thin film pattern 220 "and a third n + amorphous silicon thin film pattern 225 '' are formed on the gate pad line 216 p. A gate pad line pattern 216p 'formed of a conductive material and patterned in substantially the same shape as the gate pad line 216p is formed.

In the fringe field type liquid crystal display device according to the second embodiment of the present invention having the above-described structure, a gate line (that is, the gate electrode 221) is formed using a half-tone mask as in the first embodiment of the present invention, The gate line 216 and the gate pad line 216 p) and the pixel electrode 218 are patterned simultaneously and the active pattern 224 and the data line (that is, the source electrode 222, The drain electrode 223, the data line 217, and the data pad line 217p) are simultaneously patterned, the array substrate 210 can be manufactured through four mask processes. The drain electrode 223 and the pixel electrode 218 are electrically connected to the first contact hole 240a and the second contact hole 240b formed in the etch stopper 215 and the protective film 215b, And the connection electrode 290 may be patterned at the same time when forming the common electrode 208, the data pad electrode 226p, and the gate pad electrode 227p.

That is, the fringe field type liquid crystal display device according to the second embodiment of the present invention maintains the advantages of high resolution and high transmittance, while reducing the number of masks required for manufacturing the array substrate, The cost is reduced. Particularly, in the case of the second embodiment of the present invention, before the gate insulating film is deposited, the etch stopper is deposited on the silicon oxide film, so that the gate insulating film above the pixel electrode can be completely removed during the patterning of the data line, The interval between the common electrode and the common electrode can be minimized, and the rise of the driving voltage can be prevented.

Hereinafter, a manufacturing method of a fringe field type liquid crystal display device according to a second embodiment of the present invention will be described in detail with reference to the drawings.

6A to 6D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.

7A to 7D are cross-sectional views sequentially showing the steps of manufacturing the array substrate shown in FIG. 5, wherein the left side shows the process of manufacturing the array substrate of the pixel portion, and the right side shows the array of data pads and gate pads, Thereby producing a substrate.

6A and 7A, a gate electrode 221, a gate line 216, a common line 2081, and a pixel electrode 218 are formed in a pixel portion of an array substrate 210 made of a transparent insulating material such as glass And a gate pad line 216 p is formed in the gate pad portion of the array substrate 210.

The first conductive layer and the second conductive layer are deposited on the entire surface of the array substrate 210 by the gate electrode 221, the gate line 216, the common line 2081, the pixel electrode 218 and the gate pad line 216p. And then patterned selectively through a photolithography process (first mask process).

The gate electrode 221, the gate line 216, the common line 2081, and the gate pad line 216p are formed of the first conductive film, .

The first conductive layer is formed under the gate electrode 221, the gate line 216, the common line 2081 and the gate pad line 216p and is electrically connected to the gate electrode 221, the gate line 216 ), A gate line pattern (not shown), a common line pattern (not shown), and a gate pad line pattern (not shown) patterned in substantially the same manner as the common line 2081 and the gate pad line 216p (216p ') is formed.

In this manner, the gate wiring (that is, the gate electrode 221 and the gate line 216 and the gate pad line 216 p) and the pixel electrode 218 are formed by a single mask process by using a half-tone mask having a large area The first mask process will be described in detail with reference to the drawings.

8A to 8F are cross-sectional views illustrating a first mask process according to a second embodiment of the present invention shown in FIG. 7A.

8A, the first conductive layer 230 and the second conductive layer 240 are sequentially deposited on the entire surface of the array substrate 210 made of a transparent insulating material such as glass.

The first conductive layer 230 may be formed of a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) .

The second conductive layer 240 may be formed of aluminum (Al), aluminum alloy (Al), tungsten (W), copper (Cu), chromium Cr), molybdenum (Mo), molybdenum alloy, and the like. In addition, the second conductive layer 240 may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

8B, a photosensitive film 260 made of a photosensitive material such as a photoresist is formed on the array substrate 210 on which the second conductive layer 240 is formed. Then, And selectively irradiates light to the photoresist layer 260 through a half-tone mask 270 according to the pattern.

At this time, the half-tone mask 270 is provided with a first transmissive region I through which all the irradiated light is transmitted, a second transmissive region II through which only a part of light is partially blocked, And only the light that has passed through the half-tone mask 270 is irradiated to the photoresist layer 260.

Then, after the photosensitive film 260 exposed through the half-tone mask 270 is developed, light is emitted through the blocking region III and the second transmitting region II, as shown in FIG. 8C. A first photoresist pattern 260a to a third photoresist pattern 260c having a predetermined thickness are left in an area where all the light is blocked or partially blocked and the photoresist layer is completely removed in the first light transmission area I The surface of the second conductive layer 240 is exposed.

At this time, the first photoresist pattern 260a and the second photoresist pattern 260b formed in the blocking region III are thicker than the third photoresist pattern 260c formed through the second transmissive region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 8D, using the first photosensitive film pattern 260a to the third photosensitive film pattern 260c formed as described above as a mask, a first conductive film and a second conductive film A pixel electrode 218 made of the first conductive film is formed on the pixel portion of the array substrate 210. [ At this time, the pixel electrode 218 may be formed in a square shape within the pixel region.

A gate electrode 221, a gate line (not shown), and a common line (not shown) are formed in the pixel portion of the array substrate 210. The gate electrode 221, And a gate pad line 216p formed of the second conductive film is formed on the pad portion.

At this time, a second conductive film pattern 240 'formed of the second conductive film and patterned in substantially the same shape as the pixel electrode 218 is formed on the pixel electrode 218.

The first conductive layer is formed under the gate electrode 221, the gate line, the common line, and the gate pad line 216p. The gate electrode 221, the gate line, the common line, and the gate pad line A gate line pattern (not shown), a common line pattern (not shown), and a gate pad line pattern 216 p 'are formed in substantially the same pattern as the gate line pattern 216 p.

As shown in FIG. 8E, when the ashing process for removing a part of the thickness of the first to third photosensitive film patterns 260a to 260c is performed, The photoresist pattern is completely removed.

At this time, the first photoresist pattern and the second photoresist pattern correspond to the blocking area III by the fourth photoresist pattern 260a 'and the fifth photoresist pattern 260b', which are removed by the thickness of the third photoresist pattern Only in the region where it is located.

8F, using the fourth photoresist pattern 260a 'and the fifth photoresist pattern 260b' as a mask, a second conductive film pattern (not shown) formed on the pixel electrode 218 through etching, .

Next, as shown in FIGS. 6B and 7B, an array substrate (not shown) having the gate electrode 221, the gate line 216, the common line 2081, the pixel electrode 218, and the gate pad line 216p 210, an etch stopper 215, an insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a third conductive film are formed.

Thereafter, the insulating film, the amorphous silicon thin film, the n + amorphous silicon thin film, and the third conductive film are selectively removed through a photolithography process (second mask process) to form a first gate insulating film 215a ' The active layer 224 of the amorphous silicon thin film is formed while the source electrode 222 and the drain electrode 223 of the third conductive film are formed on the active layer 224.

At this time, a data line 217 made of the third conductive film is formed in the data line area of the array substrate 210 through the second mask process, and a data line 217 is formed in the data pad part of the array substrate 210, Thereby forming a data pad line 217p made of a conductive film.

At this time, an n + amorphous silicon thin film is formed on the active layer 224 and an ohmic contact is formed between the source / drain region of the active layer 224 and the source / drain electrodes 222 and 223, A layer 225 is formed.

A second gate insulating layer 215a ", which is formed of the insulating layer, the amorphous silicon layer and the n + amorphous silicon layer and is patterned in substantially the same pattern as the data line 217, is formed under the data line 217, 1 amorphous silicon thin film pattern 220 'and the second n + amorphous silicon thin film pattern 225' are formed.

A third gate insulating layer 215a '', which is formed of the insulating layer, the amorphous silicon layer and the n + amorphous silicon layer and is patterned substantially in the same pattern as the data pad line 217p, is formed under the data pad line 217p. The second amorphous silicon thin film pattern 220 'and the third n + amorphous silicon thin film pattern 225' 'are formed.

In this case, the second mask process according to the second embodiment of the present invention can use a half-tone mask, which will be described in detail with reference to the following drawings.

9A to 9F are cross-sectional views illustrating a second mask process according to a second embodiment of the present invention shown in FIG. 7B.

9A, on an entire surface of the array substrate 210 on which the gate electrode 221, the gate line 216, the common line 2081, the pixel electrode 218, and the gate pad line 216p are formed, An amorphous silicon thin film 220, an n + amorphous silicon thin film 225, and a third conductive film 250 are deposited on the gate insulating layer 215, the insulating layer 215a, the amorphous silicon thin layer 220,

At this time, the etch stopper 215 may be formed of a silicon oxide film having a thickness of about 100 Å to 500 Å, and the insulating film 215a may be formed of a silicon nitride film having a thickness of about 4000 Å.

The third conductive layer 250 may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a source electrode, a drain electrode, and a data line. The third conductive layer 250 may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

9B, a photoresist layer 260 made of a photosensitive material such as photoresist is formed on the entire surface of the array substrate 210 on which the third conductive layer 250 is formed. Then, as shown in FIG. And selectively irradiates the photosensitive film 260 through the half-tone mask 270 according to the example.

At this time, the half-tone mask 270 is provided with a first transmissive region I through which all the irradiated light is transmitted, a second transmissive region II through which only a part of light is partially blocked, And only the light that has passed through the half-tone mask 270 is irradiated to the photoresist layer 260.

Then, after the photoresist layer 260 exposed through the half-tone mask 270 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 9C. The first photosensitive film pattern 260a to the fifth photosensitive film pattern 260e having a predetermined thickness remain in the area where all the light is blocked or partially blocked and the photosensitive film is completely removed in the first transmission area I The surface of the third conductive layer 250 is exposed.

At this time, the first to fourth photoresist patterns 260a to 260d formed in the blocking region III are formed thicker than the fifth photoresist pattern 260e formed through the second transmissive region II. Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 9D, using the first photoresist pattern 260a to the fifth photoresist pattern 260e formed as described above as a mask, the insulating film, the amorphous silicon thin film, the n + amorphous silicon thin film The active layer 224 of the amorphous silicon thin film is formed in a state where the first gate insulating layer 215a 'is interposed between the gate electrode 221 and the first gate insulating layer 215a' . At this time, the first gate insulating layer 215a 'may be formed in an island shape substantially the same as the active layer 224 between the gate electrode 221 and the active layer 224.

A data line 217 made of the third conductive film is formed in the data line region of the array substrate 210 and a data pad line made of the third conductive film is formed in the gate pad portion of the array substrate 210. [ (217p) is formed.

The first n + amorphous silicon thin film pattern 225 ', which is composed of the n + amorphous silicon thin film and the third conductive film and is patterned substantially in the same shape as the active layer 224, is formed on the active layer 224, And the third conductive film pattern 250 'are formed.

A second gate insulating layer 215a ", which is formed of the insulating layer, the amorphous silicon layer and the n + amorphous silicon layer and is patterned substantially in the same pattern as the data line 217, is formed under the data line 217, The amorphous silicon thin film pattern 220 'and the second n + amorphous silicon thin film pattern 225' are formed.

A third gate insulating layer 215a '' formed of the insulating layer, the amorphous silicon thin film and the n + amorphous silicon thin film and patterned substantially in the same pattern as the data pad line 217p is formed under the data pad line 217p. The second amorphous silicon thin film pattern 220 'and the third n + amorphous silicon thin film pattern 225' 'are formed.

At this time, the etch stopper 215 serves to stably remove all of the insulating film on the upper portion of the pixel electrode 218. Thus, when the dry etching of the insulating film is performed, The damage of the pixel electrode 218 and the array substrate 210 under the insulating film can be prevented.

As shown in FIG. 9E, when the ashing process for removing a part of the thickness of the first to fifth photoresist patterns 260a to 260e is performed, The photoresist pattern is completely removed.

At this time, the first to fourth photosensitive film patterns correspond to the blocking region III by the sixth photosensitive film pattern 260a 'to the ninth photosensitive film pattern 260d' which are removed by the thickness of the fifth photosensitive film pattern Only in the region where it is located.

9F, by using the sixth photoresist pattern 260a 'to the ninth photoresist pattern 260d' as masks, a portion of the n + amorphous silicon thin film and the third conductive film, which are formed at the lower portion thereof, The source electrode 222 and the drain electrode 223 of the third conductive layer are formed on the active layer 224.

At this time, the n + amorphous silicon thin film is formed between the active layer 224 and the source / drain electrodes 222 and 223 and is patterned substantially in the same shape as the source / drain electrodes 222 and 223, An ohmic-contact layer 225n for ohmic-contacting the source / drain region of the layer 224 and the source / drain electrodes 222 and 223 is formed.

The second embodiment of the present invention is capable of forming the active layer 224, the source / drain electrodes 222 and 223 and the data line 217 through a single mask process by using a half-tone mask do.

6C and 7C, the array substrate 210 on which the active layer 224, the source / drain electrodes 222 and 223, the data line 217, and the data pad line 217p are formed, A protective film 215b is formed on the entire surface.

At this time, the protective film 215b may be formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film with a thickness of about 6000A.

Thereafter, a first contact hole 240a exposing a part of the drain electrode 223 by selectively removing the etch stopper 215 and the protective film 215b through a photolithography process (a third mask process) A second contact hole 240b exposing a part of the pixel electrode 218 and a third contact hole 240c exposing a part of the common line 2081 are formed.

The etch stopper 215 and the passivation layer 215b may be selectively removed through the third mask process to expose portions of the data pad line 217p and the gate pad line 216p. The second contact hole 240d and the fifth contact hole 240e.

6D and 7D, a fourth conductive layer is formed on the entire surface of the array substrate 210, and then selectively patterned using a photolithography process (fourth mask process) And a common electrode 208 electrically connected to the common line 2081 is formed through the third contact hole 240c. At this time, the common electrode 208 may be formed to have a plurality of slits 208s in the pixel region.

In addition, the fourth conductive film is selectively patterned using the fourth mask process to electrically connect to the drain electrode 223 through the first contact hole 240a, and to electrically connect the second contact hole 240b A connection electrode 290 electrically connected to the pixel electrode 218 is formed.

The fourth conductive film is selectively patterned using the fourth mask process to form the data pad line 217p and the gate pad line 217p through the fourth contact hole 240d and the fifth contact hole 240e, A data pad electrode 227p and a gate pad electrode 226p which are electrically connected to each other are formed.

Here, the fourth conductive layer may be formed of a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As described above, the present invention is also applicable to a case where a common electrode is formed at a lower portion and a pixel electrode having a plurality of slits is formed at a top portion thereof, which will be described in detail with reference to a third embodiment of the present invention.

10 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a third embodiment of the present invention.

11 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to a third embodiment of the present invention. In FIG. 11, the A-A 'line, the BB line and the CC Sectional view taken along a line in FIG.

In this case, one pixel including a pixel portion, a data pad portion, and a gate pad portion is shown for convenience of explanation. In an actual liquid crystal display device, N gate lines and M data lines cross each other and MxN pixels However, in order to simplify the description, one pixel is shown in the drawing.

As shown in the drawings, the array substrate 310 according to the third exemplary embodiment of the present invention includes a gate line 316 and a data line 317, which are vertically and horizontally arranged on the array substrate 310 to define a pixel region. Is formed. In addition, a thin film transistor, which is a switching device, is formed in the intersection region of the gate line 316 and the data line 317. In the pixel region, a common electrode 308 for driving the liquid crystal molecules by generating a fringe field, The pixel electrode 318 having the slit 318s of the pixel electrode 318 is formed.

The thin film transistor includes a gate electrode 321 connected to the gate line 316, a source electrode 322 connected to the data line 317, and a drain electrode 323 electrically connected to the pixel electrode 318 . The thin film transistor includes a first gate insulating layer 315a 'for insulation between the gate electrode 321 and the source / drain electrodes 322 and 323, and a gate electrode And an active layer 324 that forms a conduction channel between the source electrode 322 and the drain electrode 323.

At this time, the source / drain regions of the active layer 324 form ohmic contacts with the source / drain electrodes 322 and 323 through the ohmic-contact layer 325n. The first gate insulating layer 315a 'is formed of a silicon nitride layer having a thickness of about 4000A and is patterned to have substantially the same shape as the active layer 324 thereon.

As described above, the first gate insulating layer 315a 'is formed in an island shape between the gate electrode 321 and the active layer 324, and in particular, the third embodiment of the present invention is different from the second embodiment An etch stopper 315 made of a silicon oxide film having a thickness of about 100 Å to 500 Å is formed on the entire surface of the array substrate 310 between the gate electrode 321 and the first gate insulating film 315a ' .

The gate electrode 321 and the gate line 316 are formed of a conductive material that constitutes the common electrode 308 and are patterned in substantially the same manner as the gate electrode 321 and the gate line 316, A gate electrode pattern 321 'and a gate line pattern (not shown) are formed.

A second gate insulating layer 315a ", which is made of the silicon nitride layer, the amorphous silicon layer and the n + amorphous silicon layer and is patterned substantially in the same pattern as the data line 317, is formed under the data line 317, 1 amorphous silicon thin film pattern 320 'and a second n + amorphous silicon thin film pattern 325' are formed.

A portion of the source electrode 322 extends in one direction and is connected to the data line 317. A portion of the drain electrode 323 extends toward the pixel region to form a first contact And is electrically connected to the pixel electrode 318 through the hole 340a.

As described above, the common electrode 308 and the pixel electrode 318 are formed in the pixel region to generate a fringe field. At this time, the common electrode 308 may be formed in a rectangular shape within the pixel region, The pixel electrode 318 may have a plurality of slits 318s in the pixel region.

A common line 308l may be disposed in a direction substantially parallel to the gate line 316 and the common electrode 308 may extend below the common line 3081 to electrically connect .

A gate pad electrode 326p and a data pad electrode 327p electrically connected to the gate line 316 and the data line 317 are formed in an edge region of the array substrate 310, And transmits a scan signal and a data signal applied from a driving circuit (not shown) to the gate line 316 and the data line 317, respectively.

That is, the data line 317 and the gate line 316 extend to the driving circuit portion and are connected to the corresponding data pad line 317p and the gate pad line 316p, The line 316p is connected to a data signal line and a scan signal from the driving circuit through the data pad electrode 327p and the gate pad electrode 326p which are electrically connected to the data pad line 317p and the gate pad line 316p, .

At this time, the data pad line 317p is electrically connected to the data pad electrode 327p through the second contact hole 340b, and the gate pad line 316p is electrically connected to the data pad electrode 317p through the third contact hole 340c And is electrically connected to the gate pad electrode 326p.

A third gate insulating layer 315a '' formed of the silicon nitride layer, the amorphous silicon layer, and the n + amorphous silicon layer and patterned in substantially the same pattern as the data pad line 317p is formed under the data pad line 317p. A second amorphous silicon thin film pattern 320 "and a third n + amorphous silicon thin film pattern 325 '" are formed on the gate pad line 316p. And a gate pad line pattern 316p 'formed of a conductive material and patterned in substantially the same shape as the gate pad line 316p is formed.

In the fringe field type liquid crystal display device according to the third embodiment of the present invention, a gate line (i.e., the gate electrode 321 and the gate line 316 and the gate pad line 216p ) And the common electrode 308 are patterned simultaneously and the active pattern 324 and the data lines (that is, the source electrode 322, the drain electrode 323, the data line 317, Data pad line 317p) are patterned at the same time, the array substrate 310 can be manufactured through four mask processes.

That is, the fringe field type liquid crystal display device according to the third embodiment of the present invention maintains the advantages of high resolution and high transmittance as it is in the second embodiment of the present invention, The manufacturing process can be simplified and the manufacturing cost can be reduced. In addition, in the case of the third embodiment of the present invention, before the gate insulating film is deposited, the gate insulating film on the common electrode can be completely and stably removed during the patterning of the data line, which is a subsequent process, The interval between the common electrode and the common electrode can be minimized, and the rise of the driving voltage can be prevented.

Hereinafter, a manufacturing method of a fringe field type liquid crystal display device according to a third embodiment of the present invention will be described in detail with reference to the drawings.

12A to 12D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.

13A to 13D are cross-sectional views sequentially showing the manufacturing steps of the array substrate shown in Fig. 11, wherein the left side shows the step of manufacturing the array substrate of the pixel portion, and the right side shows the array of data pads and gate pads, Thereby producing a substrate.

12A and 13A, a gate electrode 321, a gate line 316, a common line 308I, and a common electrode 308I are formed in a pixel portion of an array substrate 310 made of a transparent insulating material such as glass And a gate pad line 316p is formed in the gate pad portion of the array substrate 310. [

The gate electrode 321, the gate line 316, the common line 3081, the common electrode 308 and the gate pad line 316p are formed by depositing a first conductive film and a second conductive film on the entire surface of the array substrate 310 And then patterned selectively through a photolithography process (first mask process).

At this time, the first conductive layer may be formed of a transparent conductive material having high transmittance such as indium-tin-oxide or indium-zinc-oxide to form a common electrode.

The second conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, and molybdenum alloy to form a gate line and a common line. The second conductive layer may be formed in a multi-layered structure in which two or more low-resistance conductive materials are stacked.

The common electrode 308 is formed of the first conductive film and the gate electrode 321, the gate line 316, the common line 3081 and the gate pad line 316p are formed as the second conductive film . At this time, the common electrode 308 may be formed in a rectangular shape within the pixel region, and may extend to a lower portion of the common line 3081 to be electrically connected to the common line 3081.

The first conductive film is formed under the gate electrode 321, the gate line 316, the common line 3081 and the gate pad line 316p and is electrically connected to the gate electrode 321, the gate line 316 ), A gate line pattern (not shown), a common line pattern (not shown), and a gate pad line pattern (not shown) patterned in substantially the same manner as the common line 308l and the gate pad line 316p (316p ') is formed.

Thus, the gate wiring (i. E., The gate electrode 321 and the gate line 316 and the gate pad line 316p) and the common electrode 308 are formed through a single mask process by using a half- The patterning can be performed simultaneously.

Next, as shown in FIGS. 12B and 13B, an array substrate (gate electrode) 321 is formed on the gate electrode 321, the gate line 316, the common line 3081, the common electrode 308 and the gate pad line 316p 310, an insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a third conductive film are formed.

At this time, the etch stopper 315 may be formed of a silicon oxide film having a thickness of about 100 ANGSTROM to 500 ANGSTROM, and the insulating film may be a silicon nitride film having a thickness of about 4000 ANGSTROM.

The third conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, and molybdenum alloy to form a source electrode, a drain electrode, and a data line. In addition, the third conductive film may be formed in a multi-layered structure in which two or more low resistance conductive materials are stacked.

Thereafter, the insulating film, the amorphous silicon film, the n + amorphous silicon film and the third conductive film are selectively removed through a photolithography process (second mask process) to form a first gate insulating film 315a 'on the gate electrode 321, The active layer 324 is formed of the amorphous silicon thin film and the source electrode 322 and the drain electrode 323 of the third conductive film are formed on the active layer 324.

As such, the first gate insulating layer 315a 'may be formed in an island shape substantially the same as the active layer 324 between the gate electrode 321 and the active layer 324. At this time, the etch stopper 315 stably removes the entirety of the insulating film above the common electrode 308. Accordingly, even if the etching is not performed uniformly during the dry etching of the insulating film, The damage of the common electrode 308 and the array substrate 310 at the bottom can be prevented.

At this time, a data line 317 made of the third conductive film is formed in the data line region of the array substrate 310 through the second mask process, and a data line 317 is formed in the data pad portion of the array substrate 310, Thereby forming a data pad line 317p made of a conductive film.

At this time, an n + amorphous silicon thin film is formed on the active layer 324 and an ohmic contact is formed between the source / drain region of the active layer 324 and the source / drain electrodes 322 and 323, A layer 325 is formed.

A second gate insulating layer 315a ", which is formed of the insulating layer, the amorphous silicon layer and the n + amorphous silicon layer, and is patterned substantially in the same pattern as the data line 317, is formed under the data line 317, 1 amorphous silicon thin film pattern 320 'and the second n + amorphous silicon thin film pattern 325' are formed.

A third gate insulating layer 315a '', which is formed of the insulating layer, the amorphous silicon layer and the n + amorphous silicon layer and is patterned substantially in the same pattern as the data pad line 317p, is formed under the data pad line 317p. The second amorphous silicon thin film pattern 320 "and the third n + amorphous silicon thin film pattern 325 '" are formed.

In this case, the second mask process according to the third embodiment of the present invention may use a half-tone mask as in the second embodiment of the present invention described above.

12C and 13C, the array substrate 310 on which the active layer 324, the source / drain electrodes 322 and 323, the data line 317, and the data pad line 317p are formed, A protective film 315b is formed on the entire surface.

At this time, the protective layer 315b may be formed of an inorganic insulating layer such as a silicon nitride layer or a silicon oxide layer with a thickness of about 6000A.

Thereafter, the protective film 315b is selectively removed through a photolithography process (a third mask process) to form a first contact hole 340a exposing a part of the drain electrode 323.

The etch stopper 315 and the protective film 315b are selectively removed through the third mask process to expose portions of the data pad line 317p and the gate pad line 316p. The third contact hole 340b and the third contact hole 340c.

Next, as shown in FIGS. 12D and 13D, a fourth conductive film is formed on the entire surface of the array substrate 310, and then selectively patterned using a photolithography process (fourth mask process) And a pixel electrode 318 which is electrically connected to the drain electrode 323 through the first contact hole 340a is formed. At this time, the pixel electrode 318 may have a plurality of slits 318s in the pixel region.

The fourth conductive film is selectively patterned using the fourth mask process to form the data pad line 317p and the gate pad line 317p through the second contact hole 340b and the third contact hole 340c, A data pad electrode 327p and a gate pad electrode 326p which are electrically connected to the gate electrodes 316p and 316p are formed.

At this time, the fourth conductive layer may be formed of a transparent conductive material having excellent transmittance such as indium-tin-oxide or indium-zinc-oxide.

As described above, in the first to third embodiments of the present invention, the array substrate including the thin film transistors can be manufactured by four mask processes, thereby reducing the manufacturing process and cost.

In the four mask process according to the second embodiment and the second embodiment of the present invention, after the etch stopper is deposited before the gate insulating film is deposited, the gate insulating film above the pixel electrode is removed during the patterning of the data line, The interval between the common electrodes is reduced and low power consumption becomes possible.

The array substrate of the first to third embodiments of the present invention having such a structure as described above is adhered to and opposed to the color filter substrate by a sealant formed on the outer periphery of the image display area. A color filter for realizing the color of the image is formed.

At this time, the color filter substrate and the array substrate are bonded together through an align key formed on the color filter substrate or the array substrate.

The amorphous silicon thin film transistor using the amorphous silicon thin film as the active layer has been described as an example of the fringe field type liquid crystal display of the first to third embodiments of the present invention. However, the present invention is not limited thereto, Is applied to the polycrystalline silicon thin film transistor using the polycrystalline silicon thin film as the active layer and the oxide thin film transistor using the oxide.

In addition, the present invention can be applied not only to a liquid crystal display but also to an organic electroluminescent display device in which organic electroluminescent devices (Organic Light Emitting Diodes) are connected to other display devices manufactured using thin film transistors, for example, driving transistors .

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

108, 208, 308: common electrodes 108s, 208s, 318s:
215a ', 215a'',315a', 315a ', 315a'':
115b, 215b and 315b: protective films 118, 218 and 318:
121, 221, 321: gate electrodes 122, 222, 322:
123, 223, 323: drain electrode 124, 224, 324: active layer
125n, 225n, 325n: ohmic-contact layer 215, 315: etch stopper

Claims (20)

Providing a first substrate divided into a pixel portion and a pad portion;
Forming a first electrode made of a first conductive film in a pixel portion of the first substrate through a first mask process and forming a gate electrode and a gate line and a common line made of a second conductive film;
Sequentially forming an etch stopper and an insulating layer on the entire surface of the first substrate on which the first electrode, the gate electrode, the gate line, and the common line are formed, the etch stopper having different etch selectivities with respect to dry etching;
Forming an active layer in a pixel portion of the first substrate through a second mask process, forming a source electrode and a drain electrode of a third conductive film, and a data line crossing the gate line and defining a pixel region;
Exposing an etch stopper of the pixel region by removing an insulating film over the first electrode through the second mask process;
Forming a protective film on the entire surface of the first substrate on which the active layer, the source electrode, the drain electrode, and the data line are formed;
Forming a first contact hole exposing the drain electrode by selectively removing the protective film through a third mask process;
Forming a second electrode having a plurality of slits in a pixel region where the insulating film is removed through a fourth mask process, the fourth electrode being a fourth conductive film; And
And bonding the first substrate and the second substrate,
And forming a first gate insulating film between the gate electrode and the active layer, the first gate insulating film being made of the insulating film and patterned substantially in the same form as the active layer. The method of claim 1, wherein a gate pad line made of the first conductive film is formed on a pad portion of the first substrate through the first mask process. The method according to claim 1, wherein a data pad line made of the third conductive film is formed in the pad portion of the first substrate through the second mask process. The method according to claim 1, wherein the etch stopper is formed of a silicon oxide (SiO ₂ ) film having a thickness of 100 Å to 500 Å. The manufacturing method of a fringe field type liquid crystal display device according to claim 1, wherein the insulating film is formed of a silicon nitride film (SiNx). delete The method of claim 1, further comprising: forming a second gate insulating layer, the first amorphous silicon thin film pattern, and the second amorphous silicon thin film pattern, which are formed of the insulating film, the amorphous silicon thin film and the n + amorphous silicon thin film, 2 < n > + amorphous silicon thin film pattern is formed on the surface of the fringe field type liquid crystal display device. The semiconductor device according to claim 3, further comprising: a third gate insulating layer formed of the insulating film, the amorphous silicon thin film and the n + amorphous silicon thin film and patterned in substantially the same pattern as the data pad line, Pattern and a third n + amorphous silicon thin film pattern are formed on the first n + amorphous silicon thin film pattern. The method of claim 1, wherein the first electrode forms a rectangular pixel electrode, and the second electrode forms a rectangular common electrode. The manufacturing method of a fringe field type liquid crystal display device according to claim 9, wherein a second contact hole exposing the pixel electrode is formed by selectively removing the etch stopper and the protecting layer using the third mask process . 11. The method of claim 10, further comprising forming a connection electrode electrically connected to the drain electrode through the first contact hole using the fourth mask process and electrically connected to the pixel electrode through the second contact hole Wherein the fringe field type liquid crystal display device is manufactured by a method of manufacturing a fringe field type liquid crystal display device. The method of claim 1, wherein the first electrode forms a rectangular common electrode, and the second electrode forms a rectangular pixel electrode. 13. The method of claim 12, wherein the pixel electrode is electrically connected to the drain electrode through the first contact hole. A gate electrode and a common line formed on the first substrate, the gate electrode being composed of a first electrode and a second conductive film;
An etch stopper formed on the entire surface of the first substrate on which the first electrode, the gate electrode, the gate line, and the common line are formed;
An active layer formed on the gate electrode through a first gate insulating film made of an insulating film having an etch selectivity different from that of the etch stopper;
A data line formed on the active layer and defining a pixel region intersecting the source electrode and the drain electrode of the third conductive film and the gate line;
A protection layer formed on the entire surface of the first substrate on which the source electrode, the drain electrode, and the data line are formed;
A second electrode formed of a fourth conductive film in a pixel region of the first substrate on which the protective film is formed and having a plurality of slits; And
Wherein the first gate insulator film is patterned substantially in the same form as the active layer between the gate electrode and the active layer while the first gate insulator film is patterned in substantially the same form as the active layer between the gate electrode and the active layer, And the insulating film is removed between the electrodes. 15. The fringe field type liquid crystal display of claim 14, wherein the etch stopper is formed of a silicon oxide film having a thickness of 100 ANGSTROM to 500 ANGSTROM. 15. The fringe field type liquid crystal display of claim 14, wherein the insulating layer is formed of a silicon nitride layer. The method of claim 14, further comprising: forming a second gate insulating layer, the first amorphous silicon thin film pattern, and the second amorphous silicon thin film pattern, which are formed of the insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film, 2 < n > + amorphous silicon thin film pattern is formed on the surface of the fringe field type liquid crystal display device. 15. The fringe field type liquid crystal display of claim 14, wherein the first electrode constitutes a rectangular pixel electrode, and the second electrode constitutes a rectangular common electrode. The liquid crystal display according to claim 18, further comprising a first contact hole exposing the drain electrode by selectively removing the etch stopper and the protection layer, and a second contact hole exposing the pixel electrode. Display device. The organic light emitting display as claimed in claim 19, further comprising a connection electrode electrically connected to the drain electrode through the first contact hole and electrically connected to the pixel electrode through the second contact hole, Type liquid crystal display device.

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