KR102183315B1 - Liquid crystal display panel and manufacturing method of the same - Google Patents

Abstract

The present invention is located at the intersection of a gate line formed in one direction on a substrate and a data line cross formed in a direction perpendicular to one direction, and is located on a multilayered gate insulating film and a multilayered gate insulating film located on a gate connected to the gate line. A transistor including a source electrode and a drain electrode, a multilayered protective layer on the transistor, a color conversion layer on at least one of a multilayered protective layer, a photosensitive material layer on the color conversion layer, Liquid crystal including a first contact hole formed on a multilayered protective layer, a color conversion layer, and a photosensitive material layer to expose a part of the source electrode or the drain electrode, and a pixel electrode connected to the source electrode or the drain electrode through the first contact hole A display panel and its manufacturing method are provided.

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD OF THE SAME}

The present invention relates to a liquid crystal display device and a method of manufacturing the same.

Liquid crystal display technology continues to develop and is replacing the existing fixed-type display market using CRT (Cathode-Ray Tube), and the display device for laptops, computer monitors, TVs, etc. are gradually becoming larger and DID (Digital Information Display). ) Or PID (Public Information Display) market. It also holds its place in the mobile field.

A liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display can be divided into a vertical electric field type and a horizontal electric field type. Here, in the vertical electric field type liquid crystal display device, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other, and the liquid crystal in TN (Twisted Nemastic; hereinafter referred to as TN) mode by a vertical electric field formed therebetween. Will drive. Meanwhile, the horizontal electric field type liquid crystal display drives the liquid crystal in an in plane switch (hereinafter referred to as IPS) mode by a horizontal electric field between a pixel electrode and a common electrode arranged in parallel on a lower substrate.

The liquid crystal display device includes a lower substrate including a thin film transistor, an upper substrate including a color filter black matrix, etc., a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the space provided by the spacer. .

In manufacturing a liquid crystal display, as the height of the contact hole formed through the etching process increases, the size of the contact hole becomes too large, and a number of mask processes are required, which complicates the manufacturing process. Occurs.

An object of the present invention is to provide a liquid crystal display panel in which the size of a contact hole is improved and the manufacturing process is simplified.

In order to achieve the above object, in one aspect, the present invention is located at an intersection of a gate line formed in one direction on a substrate and a data line formed in a direction perpendicular to the one direction, and located on a gate connected to the gate line. A transistor including a multilayered gate insulating layer and a source electrode and a drain electrode disposed on the multilayered gate insulating layer; A multi-layered protective layer on the transistor; A color conversion layer positioned on at least one of the multilayered protective layers; A photosensitive material layer on the color conversion layer; A first contact hole formed in the multilayered protective layer, the color conversion layer, and the photosensitive material layer to expose a portion of the source electrode or the drain electrode; And a pixel electrode connected to the source electrode or the drain electrode through the first contact hole.

In another aspect, the present invention provides the steps of forming a gate and a first gate insulating layer on a substrate, and sequentially stacking a second gate insulating layer material layer, a semiconductor material layer, and a source/drain material layer;

A photoresist material is applied on the source/drain material layer, a photoresist pattern is formed through a halftone mask, and the semiconductor material layer and the source/drain material in a region where the photoresist pattern is not applied A first etching step of removing the layer; A second etching step of forming a second gate insulating layer by removing the material layer of the second gate insulating layer in a region where the photoresist pattern is not applied; An ashing step of removing a portion of the photoresist pattern to expose a portion of the source/drain material layer; And a third etching step of forming a source electrode and a drain electrode by removing the exposed source/drain material layer.

The present invention has an effect of improving the size of a contact hole in a liquid crystal display panel and simplifying a manufacturing process.

1 is a system configuration diagram of a liquid crystal display to which embodiments are applied.
2 is a schematic plan view of a liquid crystal display panel according to embodiments.
FIG. 3 is a schematic cross-sectional view of an example of a liquid crystal display panel cut along lines II', II-II', III-III', and IV-IV' of FIG. 2 according to an exemplary embodiment.
FIG. 4 is a schematic cross-sectional view of an example of a liquid crystal display panel cut along lines I-I', II-II', III-III', and IV-IV' of FIG. 2 according to another embodiment.
5A to 5K are diagrams illustrating a method of manufacturing a liquid crystal display panel according to another exemplary embodiment.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to elements of each drawing, it should be noted that the same elements are assigned the same numerals as possible even if they are indicated on different drawings. In addition, in describing embodiments of the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In addition, in describing the constituent elements of the invention, terms such as first, second, A, B, (a), (b) may be used. These terms are only used to distinguish the component from other components, and the nature, order, or order of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but another component between each component It should be understood that elements may be “connected”, “coupled” or “connected”. In the same context, if a component is described as being formed "above" or "below" another component, the component is all formed directly on the other component or indirectly through another component. It should be understood as including.

1 is a system configuration diagram of a liquid crystal display to which embodiments are applied.

Referring to FIG. 1, the liquid crystal display device 100 includes a liquid crystal display panel 140, a data driver 120, a gate driver 130, a timing controller 110, and the like.

First, the timing controller 110 controls the data driver 120 based on external timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync) and video signals (RGB) and clock signals (CLK) input from the host system. A data control signal DCS for controlling the gate driver 130 and a gate control signal GCS for controlling the gate driver 130 are output. In addition, the timing controller 110 converts the image signal RGB input from the host system into a data signal format used by the data driver 120 and converts the converted image signal R'G'B' to the data driver 120 ) Can be supplied.

The data driver 120 receives the converted image signal R'G'B' in response to the data control signal DCS input from the timing controller 110 and the converted image signal R'G'B'. It is converted into a data signal (analog pixel signal or data voltage), which is a voltage value corresponding to the gradation value, and supplied to the data line.

The gate driver 130 sequentially supplies scan signals (gate pulses, scan pulses, and gate-on signals) to the gate lines in response to the gate control signal GCS input from the timing controller 110.

Meanwhile, the liquid crystal display panel 140 may include a transistor, a multilayered protective layer, two substrates and a liquid crystal layer positioned therebetween, an alignment layer, a color filter, a black matrix, and a photosensitive material layer.

The first substrate (lower substrate) of the liquid crystal display panel 140 may be implemented in a color filter on TFT (COT) structure, and in this case, a black matrix and a color filter may be formed on the first substrate.

Here, the transistor includes a semiconductor layer, and a protective layer having a multilayer structure for protecting the semiconductor layer may be provided.

Meanwhile, in the manufacturing process of the liquid crystal display panel 140, the size of the contact holes can be controlled by lowering the height (or thickness) of the plurality of contact holes in the etching process, and the photosensitive material layer is used as a mask during the manufacturing process. By using it, the number of masks and the number of processes can be reduced.

In addition, the first substrate (lower substrate) of the liquid crystal display panel 140 includes a plurality of data lines (D1 to Dm, m is a natural number), and a plurality of gate lines (or scans) intersecting the data lines D1 to Dm. Lines) (G1 to Gn, n is a natural number), a plurality of transistors formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, charging a data voltage to the liquid crystal cells It may include a plurality of pixel electrodes and a storage capacitor connected to the pixel electrodes to maintain the voltage of the liquid crystal cell.

The second substrate (upper substrate) of the liquid crystal display panel 140 may include a black matrix and a color filter.

Meanwhile, the pixels P of the liquid crystal display panel 140 are formed in a pixel region defined by the data lines D1 to Dm and the gate lines G1 to Gn and are arranged in a matrix form. The liquid crystal cell of each of the pixels is driven by an electric field applied according to a voltage difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode to adjust the transmission amount of incident light.

The liquid crystal display panel 140 may be implemented in other liquid crystal modes, such as an IPS (In Plane Switching) mode and a FFS (Fringe Field Switching) mode.

In this case, the common electrode may be formed on the second substrate in a vertical electric field driving method such as TN mode and VA mode, and may be formed on the first substrate together with the pixel electrode in a horizontal electric field driving method such as IPS mode and FFS mode. .

Hereinafter, embodiments of the liquid crystal display panel 140 described in FIG. 1 will be described in detail.

2 is a schematic plan view of a liquid crystal display panel according to embodiments.

Referring to FIG. 2, the liquid crystal display panel 200 is formed on a substrate (not shown) in one direction (a horizontal direction in FIG. 2) and a gate line (GL, 212) formed in a direction perpendicular to one direction (a vertical direction in FIG. 2). Located at the intersection of the cross-formed data lines 220 and on the multilayered gate insulating film (not shown) and the multilayered gate insulating film (not shown) on the gate 212a connected to the gate line 212 Transistor including the semiconductor layer 218a and source and drain electrodes 220a and 220b, a multi-layered protective layer (not shown) positioned on the transistor, and a color conversion layer positioned on the protective layer (not shown) (Not shown), a photosensitive material layer (not shown) located on a color conversion layer (not shown), a multi-layered protective layer (not shown), a color conversion layer (not shown) and a photosensitive material layer (not shown) A pixel electrode connected to the source or drain electrodes 220a and 220b through the first contact hole 230 and the first contact hole 230 which is formed to expose a part of the source electrode or the drain electrodes 220a and 220b ( 232) may be included.

In addition, the liquid crystal display panel 200 is positioned apart from the gate line 212 and includes a common line 212b made of the same material as the gate 212a, a multilayered gate insulating layer (not shown), and a multilayered protective layer (not shown). A common line through the second contact hole 234 and the second contact hole 234 which are formed on the color conversion layer (not shown) and the photosensitive material layer (not shown) to expose a part of the common line 212b. It may further include a common electrode 236 connected to (212b).

Meanwhile, the liquid crystal display panel 200 is formed on a data pad 237 connected to the data line 220 to supply a data signal, and a protective layer (not shown) having a multilayer structure, and is formed under the data pad of the data pad 237. A third contact hole 238 exposing a portion of the electrode 220c, and a data pad upper electrode 240 connected to the data pad lower electrode 220c through the third contact hole 238 may be additionally included. have.

In addition, the liquid crystal display panel 200 is connected to the gate line 212 to supply a gate signal, and is formed on the gate pad 241, a first gate insulating film (not shown), and a multilayered protective layer (not shown). A fourth contact hole 242 exposing a portion of the gate pad lower electrode 212c of the gate pad 241 and a gate pad upper electrode connected to the gate pad lower electrode 212c through the fourth contact hole 242 (244) may be included.

As an example, the liquid crystal display panel 200 of FIG. 2 illustrates an S-IPS (Super In-Plane Switching) mode in which a liquid crystal forms a two domain alignment structure, but embodiments are not limited thereto. An IPS (In-Plane Switching) mode having a domain alignment structure, and a FFS (Fringe Field Switching) mode in which the pixel electrode and the common electrode are not on the same plane may be used.

The liquid crystal display panel 200 may include a plurality of wiring lines, and the plurality of wiring lines include a gate line 212 and a gate line 212 transmitting a scan signal (or gate signal) in a first direction (a horizontal direction in FIG. 2). A data line 220 for transmitting a data signal and a common line 212b formed to be spaced apart from the gate line 212 may be separated from each other in two directions (vertical direction in FIG. 2). At this time, the gate line 212 and the common line 212b may be formed side by side. The gate line 212 extends long to the gate pad 241 in the horizontal direction, and the data line 220 extends to the data pad 237 in the vertical direction.

The gate line 212, the common line 212b, and the data line 220 are metal materials having low resistance characteristics, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy (AlNd), molybdenum ( Mo) and molybdenum alloy (MoTi) may have a single-layer or multi-layered structure of one or more materials selected from.

In the electrical connection relationship, a gate 212a having one end connected to the gate line 212, a semiconductor layer 218a, a source or drain electrode 220a having one end connected to the data line 220, and a first contact hole 230 The drain or source electrode 220b connected to the pixel electrode 232 through the transistor constitutes a transistor. Meanwhile, the common electrode 236 is connected to the common line 212b through the second contact hole 234.

Looking at the electrical function of the liquid crystal display panel 200, first, the gate line 212 supplies a gate signal to the gate electrode 212a of the transistor. The data line 220 supplies a pixel signal to the pixel electrode 232 through the drain or source electrode 220b of the transistor. Meanwhile, the gate line 212 and the data line 220 are formed in an intersecting structure to define a pixel region. The common line 212b supplies a reference voltage for driving the liquid crystal to the common electrode 236.

Accordingly, a horizontal electric field is formed between the pixel electrode 232 supplied with the pixel signal through the transistor and the common electrode 236 supplied with the reference voltage through the common line 212b. Liquid crystal molecules arranged in a horizontal direction between the substrate on which the transistor is formed and the upper substrate by the horizontal electric field are rotated by dielectric anisotropy. An image is realized by changing the light transmittance through the pixel region according to the degree of rotation of the liquid crystal molecules.

Hereinafter, the structure of the liquid crystal display panel 200 will be described through cross-sectional views corresponding to portions cut along lines I-I', II-II', III-III', and IV-IV' of FIG. 2 according to embodiments. .

FIG. 3 is a schematic cross-sectional view of an example of a liquid crystal display panel cut along lines II', II-II', III-III', and IV-IV' of FIG. 2 according to an exemplary embodiment.

2 and 3, the liquid crystal display panel 300 includes gate lines GL and 212 formed on the substrate 310 in one direction (horizontal direction in FIG. 2) and a direction perpendicular to one direction (FIG. 2) may include a transistor positioned at an intersection of the data lines 220 intersected in the vertical direction. Here, the transistor is formed on the front surface of the substrate 310 on the gate 312a connected to the gate line 212 and is formed on the first gate insulating layer 314 and the first gate insulating layer 314 covering the gate 312a. The second gate insulating layer 316a positioned to correspond to the gate 312a and the source or drain electrodes 320a and 320b, and a semiconductor layer positioned on the first gate insulating layer 314 and the second gate insulating layer 316a. 318a) and source and drain electrodes 320a and 320b.

Meanwhile, the liquid crystal display panel 300 includes a first protective layer 322 positioned on a transistor and made of a silicon oxide-based material, and a second protective layer 322 positioned on the first protective layer 322 and made of a silicon nitride-based material ( 324), a color conversion layer 326 disposed on the second passivation layer 324, a photosensitive material layer 328 disposed on the color conversion layer 326, a first passivation layer 322 and a second passivation layer A first contact hole 330 and a first contact hole formed through the color conversion layer 326 and the photosensitive material layer 328 to expose a portion of the source electrode or the drain electrodes 320a and 320b A pixel electrode 332 connected to the source or drain electrodes 320a and 320b through 330 may be included.

The substrate 310 may be not only a glass substrate, but also a plastic substrate including polyethylen terephthalate (PET), polyethylen naphthalate (PEN), polyimide, or the like. In addition, a buffering layer for blocking penetration of impurity elements may be further provided on the first substrate 310. The buffer layer may be formed of, for example, a single layer or multiple layers of silicon nitride or silicon oxide.

The gate 312a connected to the gate line 212 is at least one metal or alloy among Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. As such, it may be formed as a single layer or multiple layers.

On the other hand, the first gate insulating layer 314 and the second gate insulating layer 316 are SiOx, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, ZrO2, BST, inorganic insulating material such as PZT or, for example, benzocyclobutene ( BCB) and an organic insulating material including an acrylic (acryl) resin, or a combination thereof. Also, the first gate insulating layer 314 and the second gate insulating layer 316 may be made of the same material or different materials.

The semiconductor layer 318a may be, for example, a zinc oxide-based oxide of any one of IGZO (Indium Galium Zinc Oxide), ZTO (Zinc Tin Oxide), and ZIO (Zinc Indium Oxide), but is not limited thereto.

Meanwhile, the source and drain electrodes 320a and 320b electrically connected to the pixel electrode 332 are, for example, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, any one metal or an alloy thereof, may be formed in a single layer or multiple layers.

An etch stopper may be formed between the source electrode and the drain electrodes 320a and 320b, but in the case of FIG. 3, a BCE (Back Channel Etch) type transistor is illustrated for convenience of description. Also, for convenience of explanation, an oxide transistor (Oxide TFT) is illustrated. The embodiments are not limited thereto.

A first protective layer 322 and a second protective layer 324 may be formed on the source and drain electrodes 320a and 320b and the exposed semiconductor layer 318a. Specifically, the first protective layer 322 of the liquid crystal display panel 300 according to the exemplary embodiment may be formed of a silicon oxide (SiOx)-based material, and the second protective layer 324 is silicon nitride (SiNx). It may be formed of a series of materials, but is not limited thereto. When a silicon nitride-based material is formed on the exposed semiconductor layer 318a, since the physical properties of the semiconductor layer 318a may change due to hydrogen generation due to SiH4 gas during the process, the first protective layer 322 It can be formed of silicon oxide.

The first protective layer 322 and the second protective layer 324 are layers for protecting the semiconductor layer from external environments such as hydrogen and moisture, compared with a general liquid crystal display panel having a protective layer composed of one layer. , The transistor can be effectively protected. In addition, the first protective layer 322 and the second protective layer 324 are for convenience of description, and may be formed of three or more layers.

Meanwhile, a color conversion layer 326 is formed on the second protective layer 324. Although not shown in the drawing, the color conversion layer 326 is provided in a form in which red, green, and blue color conversion layers 326 are sequentially repeated corresponding to each pixel area.

A photosensitive material layer 328 on the color conversion layer 326 is formed. As an example, the photosensitive material layer 328 may be a photoacrylic photosensitive material, but is not limited thereto. The photosensitive material layer 328 protects the lower layers and serves as a mask in an etching process to be described later to simplify the process.

Referring to II-II' of FIGS. 2 and 3, the liquid crystal display panel 300 is positioned apart from the gate line 212 and includes a common line 312b made of the same material as the gate 312a, and a first gate insulating layer. A second contact hole formed on the 314, the first protective layer 322, the second protective layer 324, the color conversion layer 326, and the photosensitive material layer 328 to expose a part of the common line 312b A common electrode 336 connected to the common line 312b through 334 and the second contact hole 334 may be additionally included.

Here, in II-II', unlike the cross section of I-I', the second gate insulating layer 316a does not exist. Therefore, as will be described later, since the thickness of the portion to be removed through the etching process is small, it is possible to prevent the problem that the size of the contact hole becomes too large according to the etching time.

Meanwhile, referring to III-III' and IV-IV' of FIGS. 2 and 3, the liquid crystal display panel 300 includes a data pad 237 connected to a data line 220 to supply a data signal, and 1 The data pad lower electrode is formed on the protective layer 322 to expose a part of the data pad lower electrode 320c of the data pad 237 through the third contact hole 338 and the third contact hole 338. A data pad upper electrode 340 connected to 320c) may be additionally included. In addition, the gate pad 241 connected to the gate line 212 to supply a gate signal, and the gate pad lower electrode of the gate pad 241 are formed on the first gate insulating layer 314 and the first protective layer 322. A fourth contact hole 342 exposing a portion of the 312c) and a gate pad upper electrode 344 connected to the gate pad lower electrode 312c through the fourth contact hole 342 may be included.

Here, in the case of the fourth contact hole 342, as described above, the size of the fourth contact hole 342 can be controlled because the thickness of the portion to be removed by the etching process is smaller than that of a general liquid crystal display panel. have.

FIG. 4 is a schematic cross-sectional view of an example of a liquid crystal display panel cut along lines I-I', II-II', III-III', and IV-IV' of FIG. 2 according to another embodiment.

In the liquid crystal display panel 400 according to another exemplary embodiment, compared to the exemplary embodiment, the second gate insulating layer 416 is formed on the entire surface of the substrate 310, and the second protective layer 424 is formed with I-I′. It is located on the photosensitive material layer 328 over II-II'. In the case of the remaining components, descriptions are omitted because they are the same as in the embodiment.

In the liquid crystal display panel 400 according to another exemplary embodiment, the first protective layer 322 is provided with the semiconductor layer 318a, the gate pad lower electrode 312c, and the data pad lower electrode 320c from an external environment such as moisture and hydrogen. ), and in addition, the second protective layer 424 serves as a secondary protective layer, so that the life of the liquid crystal display panel may be increased.

5A to 5K are diagrams illustrating a method of manufacturing a liquid crystal display panel according to another exemplary embodiment. 5A to 5K illustrate the manufacturing method of only the part I-I' of FIG. 2 for convenience of explanation, but it should be noted that the same process is applied to the parts II-II', III-III', and IV-IV'.

2, 3, and 5A to 5K, first, a gate 312a and a first gate insulating layer 314 are formed on a substrate 310, and a second gate insulating layer material layer 316a', a semiconductor A step of sequentially stacking the material layer 318a' and the source/drain material layer 320a' is performed.

In other words, after cleaning the substrate through a physical or chemical cleaning method, depositing by sputtering, etc., the gate 312a, the common line 312b, and the lower electrode of the gate pad are photolithographic through the first mask. (312c) is patterned. Thereafter, the first gate insulating layer 314 is formed by sputtering or vapor deposition, and the second gate insulating layer material layer 316a', the semiconductor material layer 318a', the source/drain material layer 320a', and the data pad ( The data pad lower electrode 320c of 237 is sequentially stacked.

5B and 5C, a photoresist material is applied on the source/drain material layer 320a', a photoresist pattern 548 is formed through a halftone mask 550, and the photoresist pattern 548 A first etching step of removing the semiconductor material layer 318a' and the source/drain material layer 320a' in a region to which) is not applied is shown.

Hereinafter, a positive method in which the photoresist material in a light-transmitting region is removed will be described, but a negative method may also be used.

Here, the halftone mask 550 includes a transmissive region 550a, a blocking region 550b, and a transflective region 550c, and is exposed to a photoresist material made of a photosensitive material and developed by developing the transmissive region ( The height h2 of the photoresist pattern 528 in the region corresponding to 550c) may be lower than the height h1 of the photoresist pattern 548 in the blocking region 550b (h2<h1).

The first etching step may be a wet etching method, but is not limited thereto.

Referring to FIG. 5D, a second etching step of forming a second gate insulating layer by removing the second gate insulating layer material layer 316a' in a region where the photoresist pattern 548 is not applied is illustrated.

The second etching step may be a dry etching method such as plasma etching or reactive ion etching, and the first gate insulating layer is formed using a selectivity ratio between a silicon oxide-based material and a silicon nitride-based material. Leaving the 314, only the second gate insulating layer material layer 316a' may be etched. Here, in the second etching step, the second gate insulating layer 316a may be formed by using the photoresist pattern 548 used in the first etching step as it is, thereby simplifying the process and reducing the manufacturing cost.

5E illustrates an ashing step of removing a portion of the photoresist pattern 548 to expose a portion of the source/drain material layer 320a".

The height of the photoresist pattern 548 is lowered by h2 by an ashing process using an ashing gas, so that the photoresist pattern 548 having a height of h2-h1 remains.

5F illustrates a third etching step of forming the source and drain electrodes 320a and 320b by removing the exposed source/drain material layer 320a".

The third etching may be wet etching, and a minimum amount of the semiconductor layer 318a may be left by adjusting an etching rate or an etching time (Etch Back method).

In the third etching step, although not shown, the second gate insulating layer 316b, the semiconductor layer 318b, and the data pad lower electrode 320c of the data pad 237 are simultaneously patterned.

5G shows a step of sequentially stacking the first protective layer 322 and the second protective layer 324 on the source and drain electrodes 320a and 320b.

Here, the first protective layer 322 and the second protective layer 324 are deposited over the entire surface of the substrate 310 to form the source and drain electrodes 320a and 320b, the common line 312b, and the data pad lower electrode 320c. ), the lower electrode 312c of the gate pad may be covered.

The semiconductor layer 318a of the liquid crystal display panel 300 is protected from the external environment through the first protective layer 322 and the second protective layer 324 to increase the lifespan of the panel and reduce parasitic capacitance, etc. It can be effectively prevented.

5H is a step of forming a color conversion layer 326 by forming a color conversion material layer on the second protective layer 324 and patterning a portion of the source electrode or the drain electrodes 320a and 320b to be exposed. Shows.

The color conversion layer 326 may be formed by a photolithography process using a pigment, but is not limited thereto and may be formed by a method such as printing or deposition. In addition, when the color conversion layer 326 is formed, a photopolymerization initiator, a monomer, a binder, and the like may be included.

When the color conversion material layer is applied and exposed through a mask, a photopolymerization initiator receives light and generates a polymer compound through a photopolymerization reaction by radicals. Thereafter, through a development process, a second region 330b of the first contact hole 330 may be formed in a region where the polymer compound is not generated.

Although not shown, the color conversion layer 326 of the portion II-II' is also formed at the same time, and a second region (not shown) of the second contact hole 334 is also formed.

5I illustrates a step of forming the photosensitive material layer 328 by applying a photosensitive material on the color conversion layer 326 and patterning the source electrode or the drain electrodes 320a and 320b to expose portions of the photosensitive material. Specifically, the photosensitive material may be a photosensitive resin including a photoacryl-based material, but is not limited thereto.

A photosensitive material is applied on the color conversion layer 326 and then exposed and developed through a mask to form a third region 330c of the first contact hole 330. Further, although not shown, a third area (not shown) of the second contact hole 334 of II-II' is also formed at the same time.

5J is a fourth etching step of exposing a portion of the source or drain electrodes 320a and 320b by removing the first and second protective layers 322 and 324 using the photosensitive material layer 328 as a mask. Shows.

Here, the fourth etching may be dry etching, but is not limited thereto. In the fourth etching step, the number of processes can be reduced by replacing the photosensitive material layer made of a photosensitive resin with a mask without using a separate mask. That is, a process of applying and patterning a photoresist and a process of stripping a photoresist material may be omitted.

The first protective layer 322 and the second protective layer 324 exposed according to the etching are etched to expose a portion of the source or drain electrodes 320a and 320b. Accordingly, the first region 330a of the first contact hole 330 is formed to complete the first contact hole 330.

Meanwhile, the second contact hole 334 is formed in the same manner as the first contact hole 330. According to another embodiment, the second gate insulating layer 316a is removed around the second contact hole 334. , The thickness of the layers to be removed by the etching process may be relatively thin.

In other words, if the thickness of the structure to be removed through the etching process is thick, the etching time is lengthened and the size of the contact hole becomes excessively large, which may cause a problem of reducing the aperture ratio. The liquid crystal display panel according to another embodiment ( In the case of the second contact hole 316a of 300), the etching process time is relatively short, so that the size of the hole can be controlled.

Likewise, in the case of the fourth contact hole 342 in the portion IV-IV', the planting process time is short, so that the size of the contact hole may be prevented from becoming too large.

5K illustrates a step of forming the pixel electrode 332 in contact with the source or drain electrodes 320a and 320b through the first contact hole 330.

The pixel electrode 332 may be formed by physical vapor deposition or chemical vapor deposition, but is not limited thereto. Further, the pixel electrode 332 is driven by contacting the source or drain electrodes 320a and 320b.

In the area II-II', a common electrode 336 is formed simultaneously with the pixel electrode 332 to be connected to the common line 312b, and in the area III-III', an upper electrode 340 of the data pad is formed to form a lower electrode of the data pad. It is connected to 320c, and a gate pad upper electrode 344 is formed in the region IV-IV' to be connected to the gate pad lower electrode 312c.

In the manufacturing method of the liquid crystal display panel 300 according to another embodiment, the etching process may be performed by using the photoresist pattern formed in the first etching step in the second etching step as it is, and the photosensitive material layer ( 328) Since it is used as a mask, the manufacturing process becomes simple, the manufacturing cost is reduced, and the manufacturing yield can be improved. In addition, in embodiments, since the thickness of the contact holes 334 and 342 is minimized to prevent a problem that the size of the contact holes 334 and 342 becomes excessively large, the aperture ratio may be improved. In addition, by forming the multilayered protective layers 322 and 324, the transistor, the common line 312b, the data pad lower electrode 320c, the gate pad lower electrode 312c, and the like can be effectively protected from an external environment.

The embodiments have been described above with reference to the drawings, but the present invention is not limited thereto.

Terms such as "include", "consist of", or "have" described above, unless otherwise stated, mean that the corresponding component may be included, and thus other components are not excluded. It should be interpreted as being able to further include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms generally used, such as terms defined in the dictionary, should be interpreted as being consistent with the meaning in the context of the related technology, and are not interpreted as ideal or excessively formal meanings unless explicitly defined in the present invention.

The above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

310: substrate 314: first gate insulating film
316a, 316b: second gate insulating layer 318a: semiconductor layer
320a, 320b: source electrode or drain electrode

Claims (12)

A first region in which a transistor is formed, a second region in which the common electrode is connected to the common line, a third region in which the upper data pad electrode and the lower data pad electrode are connected, and a third region in which the upper electrode of the gate pad and the lower electrode of the gate pad are connected. In the liquid crystal display panel including four areas,
A gate insulating layer positioned on a gate connected to the gate line and a source electrode and a drain electrode positioned on the gate insulating layer, positioned at an intersection of a gate line formed in one direction on a substrate and a data line formed crossing in a direction perpendicular to the one direction The transistor including a;
A multi-layered protective layer on the transistor;
A color conversion layer positioned on at least one of the multilayered protective layers;
A photosensitive material layer on the color conversion layer;
A first contact hole formed in the multilayered protective layer, the color conversion layer, and the photosensitive material layer to expose a portion of the source electrode or the drain electrode; And
A pixel electrode connected to the source electrode or the drain electrode through the first contact hole,
The gate insulating layer includes a multi-layered gate insulating layer formed in the first region and a single-layered gate insulating layer formed in the second region or the fourth region. The method of claim 1,
The second region is located apart from the gate line and is a common line made of the same material as the gate,
A second contact hole formed in the single-layered gate insulating layer, the multi-layered protective layer, the color conversion layer, and the photosensitive material layer to expose a part of the common line, and
A liquid crystal display panel including a common electrode connected to the common line through the second contact hole. The method of claim 1,
The multi-layered gate insulating layer formed in the first region is formed of a silicon oxide-based material, is formed on the entire surface of the substrate, and is formed of a silicon nitride-based material, and is formed on the first gate insulating layer. A liquid crystal display panel comprising a second gate insulating layer formed on the gate and corresponding to the source electrode or the drain electrode. The method of claim 1,
The multilayered protective layer is a liquid crystal display panel including a first protective layer disposed on the transistor and made of a silicon oxide-based material, and a second protective layer disposed on the first protective layer and made of a silicon nitride-based material. delete The method of claim 1,
The third area is a data pad connected to the data line to supply a data signal;
A third contact hole formed in the multilayered gate insulating layer and the multilayered protective layer to expose a portion of the lower electrode of the data pad constituting the data pad, and
A liquid crystal display panel including an upper electrode of the data pad connected to a lower electrode of the data pad through the third contact hole. The method of claim 1,
A gate pad connected to the gate line to supply a gate signal in the fourth region;
A fourth contact hole formed in the single-layered gate insulating layer and the multi-layered protective layer to expose a portion of the lower electrode of the gate pad constituting the gate pad, and
A liquid crystal display panel including the gate pad upper electrode connected to the gate pad lower electrode through the fourth contact hole. The method of claim 1,
The protective layer of the multilayer structure includes a first protective layer positioned between the transistor and the color conversion layer, and a second protective layer positioned on the photosensitive material layer,
The first contact hole is formed in the first protective layer, the color conversion layer, the photosensitive material layer, and the second protective layer to expose the source electrode or the drain electrode. A first region in which a transistor is formed, a second region in which the common electrode is connected to the common line, a third region in which the upper data pad electrode and the lower data pad electrode are connected, and a third region in which the upper electrode of the gate pad and the lower electrode of the gate pad are connected. In the manufacturing method of a liquid crystal display panel including four regions,
Forming a gate and a first gate insulating layer on a substrate, and sequentially stacking a second gate insulating layer material layer, a semiconductor material layer, and a source/drain material layer;
A photoresist material is applied on the source/drain material layer, a photoresist pattern is formed through a halftone mask, and the semiconductor material layer and the source/drain material in a region where the photoresist pattern is not applied A first etching step of removing the layer;
A second etching step of forming a second gate insulating layer by removing the second gate insulating layer material layer from the second area or the fourth area to which the photoresist pattern is not applied;
An ashing step of removing a portion of the photoresist pattern to expose a portion of the source/drain material layer; And
And a third etching step of removing the exposed source/drain material layer to form a source electrode and a drain electrode. The method of claim 9,
After the third etching step,
Sequentially laminating a first protective layer and a second protective layer on the source electrode and the drain electrode;
Forming a color conversion layer by forming a color conversion material layer on the second protective layer and patterning a portion of the source electrode or the drain electrode to be exposed;
Forming a photosensitive material layer by coating a photosensitive material on the color conversion layer and patterning a portion of the source electrode or the drain electrode to be exposed; And
The liquid crystal display panel further comprising a fourth etching step of exposing a part of the source electrode or the drain electrode by removing the first protective layer and the second protective layer using the photosensitive material layer as a mask. Manufacturing method.
The method of claim 9,
A method of manufacturing a liquid crystal display panel in which the photoresist pattern used in the first etching step and the photoresist pattern used in the second etching step are the same photoresist pattern. The method of claim 1,
A single-layered gate insulating layer formed in the second region or the fourth region is a first gate insulating film made of a silicon oxide-based material.

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