KR102219668B1 - Thin film transistor substrate and touch device of using the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate capable of improving the aperture ratio,
The thin film transistor substrate according to the present invention includes a first and a second thin film transistor formed in two vertically adjacent pixel regions connected to the same gate line, and a drain electrode of the thin film transistor formed in each of the two vertically neighboring pixel regions. And a connection pattern that is connected to each of the first and second thin film transistors and electrically connects the exposed drain electrode and the pixel electrode to the pixel electrode separately formed for each pixel, and a passivation layer having a pixel contact hole exposing the pixel contact hole.
As a result, the aperture ratio is improved compared to the conventional thin film transistor substrate having pixel contact holes formed in each pixel region.
Furthermore, the thin film transistor substrate according to the present invention has an advantage of implementing a high-resolution display device by improving an aperture ratio.

Description

Thin film transistor substrate and touch device using the same {THIN FILM TRANSISTOR SUBSTRATE AND TOUCH DEVICE OF USING THE SAME}

The present invention relates to a thin film transistor substrate and a touch device using the same, and in particular, to a thin film transistor substrate capable of improving an aperture ratio.

A video display device that embodies a variety of information on a screen is a core technology in the information and communication era, and is developing in a direction of thinner, lighter, portable, and high-performance. Accordingly, a flat panel display device capable of reducing weight and volume, which is a disadvantage of a cathode ray tube (CRT), is in the spotlight.

Among flat panel displays, the liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal by an electric field formed between a pixel electrode and a common electrode connected to the thin film transistor.

In a display device, the resolution is defined as the number of pixels displayed per unit area (PPI: pixel per inch), and the high-resolution product generally refers to a product having a pixel per inch (PPI) or more.

In a display device, in order to realize a high resolution, the number of pixel areas implemented per unit area must be increased. To realize this, the size of each pixel area must be reduced. However, reducing the size of the pixel area consists of components constituting the display device and these components. It is difficult to consider the arrangement of and the aperture ratio of the pixel area.

In particular, in the case of a liquid crystal display among display devices, the aperture ratio has become a very important factor for realizing a high resolution, and in order to realize a high resolution product, a high aperture ratio characteristic must be secured first.

Since one pixel contact hole is provided in each pixel region P, it is a factor of reducing the aperture ratio.

Accordingly, a structure in which pixel contact holes are formed one by one for two pixel regions adjacent to each other up and down has been proposed.

However, the conventional thin film transistor substrate having the above-described configuration may cause defects and a problem of lowering the aperture ratio when implementing pixel electrodes formed upward and downward.

Referring to FIG. 1, if a mask is designed and patterned at a distance M2 equal to the minimum distance d1 required to prevent defects between neighboring pixel electrodes 12, the pixel electrode formed inside the pixel contact hole is inside the hole. Due to the step difference, the distance d3 between the actual pixel regions becomes smaller than the minimum distance (d3<d1), and thus a short circuit may occur.

Therefore, in order to solve the short circuit problem between the upper and lower pixel electrodes 12 in FIG. 1, when the mask is designed with an additional margin and a distance (M2+a) is formed, the area of the pixel contact hole shared vertically increases. A problem of reducing the aperture ratio may arise.

The present invention is to solve the above problems, and to provide a thin film transistor substrate and a touch device using which can improve the aperture ratio.

In order to achieve the above object, the thin film transistor substrate according to the present invention is provided in the first and second thin film transistors and two vertically adjacent pixel regions respectively formed in two vertically adjacent pixel regions connected to the same gate line. A protective film having a pixel contact hole exposing the drain electrode of each formed thin film transistor, and connected to each of the first and second thin film transistors, and a connection that electrically connects the pixel electrode separately formed for each pixel and the exposed drain electrode and the pixel electrode Includes the pattern.

The connection pattern may be formed on at least one drain electrode of the first and second thin film transistors respectively formed in two adjacent pixel regions vertically.

Each of the gate lines is characterized in that it includes a gate electrode formed by branching upward and downward. At this time, the pixel contact hole is characterized in that it vertically overlaps the gate line.

In addition, the second embodiment of the thin film transistor substrate is characterized in that the connection pattern is formed as a double layer.

Also, the upper electrode and the lower electrode of the double layer are patterned to have the same area.

The thin film transistor substrate according to the present invention has a configuration in which pixel contact holes are formed one for two pixel regions adjacent to each other up and down, and a source electrode among the components constituting each thin film transistor is a data line formed at the boundary of the pixel region. By itself, a drain contact hole is provided for each pixel region, and the aperture ratio is improved compared to a conventional thin film transistor substrate in which a source electrode is formed by branching from a data line.

Furthermore, the thin film transistor substrate according to the present invention has an advantage of implementing a high-resolution display device by improving an aperture ratio.

In the thin film transistor substrate according to the present invention, since the connection pattern is formed inside the pixel contact hole, it is possible to minimize the area of the pixel contact hole and prevent the occurrence of a short between the vertically adjacent pixel electrodes. Accordingly, in the present invention, since the pixel contact hole of the smallest area is formed, the exposure amount of the protective layer can be reduced, and the process time can be reduced.

In addition, the connection pattern is formed of the same metal as when the touch sensing line is formed, but since a region to be formed is different, a separate metal layer and a mask for the connection pattern are added, thereby reducing manufacturing cost.

In addition, the thin film transistor substrate according to the present invention has the effect of improving the mobility characteristics of carriers compared to the thin film transistor substrate using amorphous silicon as a semiconductor layer by using the semiconductor layer of polysilicon as a component, and the semiconductor layer of polysilicon It has an effect of suppressing an increase in an off current value due to leakage current by implementing a double gate structure while configuring the provided thin film transistor.

1 is a cross-sectional view showing a thin film transistor substrate according to the prior art.
2 is a plan view showing a thin film transistor substrate according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate cut along the line “I-I” in FIG. 1.
4A and 4E are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG. 3.
5 is a cross-sectional view illustrating a thin film transistor substrate according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing a thin film transistor substrate according to the present invention, and FIG. 3 is a cross-sectional view showing the thin film transistor substrate taken along line “I-I” in FIG. 2.

The thin film transistor substrate shown in FIGS. 2 and 3 includes a thin film transistor, a connection pattern, a common electrode, a touch sensing line, and a pixel electrode.

The gate line 102 and the data line 104 cross each other with the interlayer insulating layer 116 therebetween to define each pixel region. The gate line 102 supplies a scan signal to the gate electrode 106 of the thin film transistor in each pixel region, and the data line 104 supplies a data signal to the source electrode 108 of the thin film transistor in each pixel region.

The thin film transistor substrate includes first and second thin film transistors connected to the same gate line in pixel regions adjacent to each other in the vertical direction.

The thin film transistor causes the data signal of the data line 104 to be charged and maintained in the pixel electrode 122 in response to the scan signal of the gate line 102. To this end, the thin film transistor includes gate electrodes 106A and 106B, a source electrode 108, a drain electrode 110 and an active layer 114,

The gate electrode includes a plurality of gate electrodes included in the gate line 102. In the present invention, a description will be given of an example provided with two gate electrodes, that is, the first and second gate electrodes 106A and 106B.

The first gate electrode 106A overlaps the first channel region 114A of the active layer, and the second gate electrode 106B overlaps the second channel region 114B of the active layer.

A scan signal from the gate line is supplied to the gate electrode. This gate electrode overlaps the channel region of the active layer with the gate insulating film 112 therebetween.

The source electrode 108 is formed as a part of the data line 104 and is connected to the active layer through a source contact hole 124S penetrating the interlayer insulating layer 116 and the gate insulating layer 112.

The drain electrode 110 is connected to the active layer through an interlayer insulating layer 116 and a drain contact hole 124D penetrating through the gate insulating layer 112. In addition, the drain electrode 110 is connected to the pixel electrode through a connection pattern 155 formed in the pixel contact hole 142H.

The active layer 114 forms a channel between the source electrode 108 and the drain electrode 110. As shown in FIG. 2, the active layer 114 may be formed in a "b" shape or an inverted "a" shape on the buffer layer 126, or may be formed in another shape. Since the active layer 114 is formed of a polysilicon thin film, mobility characteristics are improved compared to the amorphous silicon thin film.

The buffer layer 126 is formed of silicon oxide or silicon nitride in a single layer or multilayer structure on a substrate 101 made of a plastic resin such as glass or polyimide (PI). The buffer layer 126 serves to prevent diffusion of moisture or impurities generated in the substrate 101 or to control the transfer rate of heat during crystallization, so that crystallization of the active layer 114 can be performed well.

The protective film protects the thin film transistor by improving the aperture ratio and blocking the inflow of moisture from the outside. Such a protective layer is formed in a multilayer structure, and in the present invention, a case in which the first and second inorganic protective layers 118 and 138 and the organic protective layer 128 are provided will be described as an example.

The first and second inorganic protective layers 118 and 138 are formed of an inorganic insulating material having a denser bonding structure than that of an organic insulating material having a loose bonding structure. The first inorganic protective layer 118 is formed of an inorganic insulating material such as SiNx or SiOx, and an electrode constituting a thin film transistor by blocking moisture from outside through an organic protective layer 128 formed of an organic insulating material having a sparse structure. To prevent corrosion. The organic passivation layer 128 is formed of an organic insulating material such as photoacrylic (PAC) to planarize the lower substrate, and blocks moisture flowing from the outside together with the first inorganic passivation layer 118, and Insulate between the common electrodes 130.

In this case, a pixel contact hole 142H exposing the drain electrode 110 of each of the thin film transistors formed in the pixels vertically adjacent to the first inorganic and organic protective layers 118 and 128 is provided. The pixel contact hole 142H provided in the first inorganic and organic protective layers 118 and 128 is characterized in that only one pixel contact hole 142H is formed for two pixel regions that are vertically adjacent to each other.

One pixel contact hole 142H formed for the two pixel regions P1 and P2 positioned vertically in this way is larger than the area of one pixel contact hole provided in each pixel region of a conventional thin film transistor substrate, but two Since the area is smaller than the area of the two pixel contact holes provided in the pixel area, the aperture ratio is improved compared to the conventional thin film transistor substrate when the entire display area is based.

The connection pattern 155 is formed in the pixel contact hole 142H and is formed in at least one of the first and second thin film transistors. The connection pattern 155 has an effect of further improving the aperture ratio by preventing an increase in the area of the pixel contact hole 142H while preventing a short between the pixel electrodes 122 respectively formed in vertically adjacent pixels.

In the present invention, since the pixel contact hole of the smallest area is formed, the exposure amount of the protective layer can be reduced and the process time can be reduced.

The connection pattern is formed of the same metal as when the touch sensing line is formed, but since a region to be formed is different, a separate metal layer and a mask are added for the connection pattern, thereby reducing manufacturing cost.

In addition, the connection pattern 155 is characterized in that it is formed on at least one of the first and second thin film transistors.

In addition, the pixel electrode connected to the connection pattern in the pixel contact hole is characterized in that the length is shorter than that of the adjacent pixel electrode, and the pixel electrode connected to the drain contact hole of the first transistor is in the drain contact hole of the second thin film transistor. It is characterized in that the length is short compared to the pixel electrode to be connected.

The pixel electrode 122 is formed on the second inorganic passivation layer 138 in each pixel area provided at the intersection of the gate line 102 and the data line 104. The pixel electrode 122 is electrically connected to the drain electrode 110 exposed through the pixel contact hole 142H. Here, the pixel contact hole 142H is formed to pass through the first and second inorganic passivation layers 118 and 138 and the organic passivation layer 128 to expose the drain electrode 110. Further, the pixel electrode includes a plurality of finger portions having a finger shape.

Specifically, the pixel electrode 122 of one of the first and second thin film transistors is electrically connected to the connection pattern exposed through the pixel contact hole 142H, and the pixel electrode 122 of the other pixel is a pixel contact hole. It is characterized in that it is electrically connected to the drain electrode 110 exposed through (142H).

The common electrode 130 is formed on the organic passivation layer 128 in a region other than the region in which the pixel contact hole 142H is formed. Accordingly, the common electrode 130 is integrated with and electrically connected to the common electrode 136 of an adjacent pixel region without a separate common line. In addition, the common electrode 130 overlaps the pixel electrode 122 in each pixel region with the second inorganic passivation layer 138 therebetween to form a fringe field. Accordingly, the common electrode 130 to which the common voltage is supplied forms a fringe field with the pixel electrode 122 to which the pixel voltage signal is supplied through the thin film transistor to form liquid crystals arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate. Molecules rotate due to dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

The touch sensing line 150 is formed on the common electrode 130 to directly contact the common electrode 130. The touch sensing line 150 electrically connects the common electrodes 130 of adjacent pixel regions so that the common electrode 130 can be used as a touch sensing electrode during a non-display period.

That is, during the non-display period, the common electrodes 130 of each pixel area connected by the touch sensing line 150 are driven as the touch sensing electrodes to detect a change in capacitance according to the user's touch. Then, the touch position is detected by comparing the touch capacitance according to the user's touch and the reference capacitance.

4A to 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the present invention. A method of manufacturing a thin film transistor substrate according to the present invention will be described by taking the thin film transistor substrate shown in FIG.

The thin film transistor causes the data signal of the data line 104 to be charged and maintained in the pixel electrode 122 in response to the scan signal of the gate line 102. To this end, the thin film transistor includes gate electrodes 106A and 106B, a source electrode 108, a drain electrode 110 and an active layer 114,

Referring to FIG. 4A, a buffer layer 126 is formed on a substrate, and active layers 114A and 114B are formed thereon.

Specifically, a buffer film 126 and an amorphous silicon thin film are sequentially formed on the substrate through a method such as LPCVD (Low Pressure Chemical Vpeor Deposition) and PECVD (Plasma Enhanced Chemical Vpeor Deposition). Then, the amorphous silicon thin film is crystallized to form a polysilicon thin film. In addition, the active layers 114A and 114B are formed by patterning the polysilicon thin film through a photolithography process and an etching process.

A gate insulating layer 112 is formed on the buffer layer 126 on which the active layer is formed, and a gate line 102 including first and second gate electrodes 106A and 106B is formed thereon.

An interlayer insulating layer 116 having a source contact hole 124S and a drain contact hole 124D is formed on the gate insulating layer 112 on which the gate line 102 including the first and second gate electrodes 106A and 106B is formed. Is formed.

Specifically, an interlayer insulating film 116 is formed on the gate insulating film 112 on which the gate line 102 is formed by a method such as PECVD. Thereafter, the interlayer insulating layer 116 and the gate insulating layer 112 are patterned through a photolithography process and an etching process, thereby simultaneously forming a source contact hole 124S and a drain contact hole 124D. Here, the drain contact hole 124D penetrates the interlayer insulating layer 116 and the gate insulating layer 112 to expose the active layers 114A and 114B.

A source electrode 108, a drain electrode 110, and a data line 104 are formed on the interlayer insulating layer 116.

Specifically, a source/drain metal layer is formed on the interlayer insulating layer 116 having the source contact hole 124S and the drain contact hole 124D by a deposition method such as sputtering. As the source/drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer, or a multilayer structure is used using these. Then, the source electrode 108, the drain electrode 110, and the data line 104 are formed on the interlayer insulating layer 116 by patterning the source/drain metal layers through a photolithography process and an etching process.

The thin film transistor substrate includes first and second gate electrodes connected to the same gate line in pixel regions adjacent vertically, and first and second thin film transistors connected to the same gate line in pixel regions vertically adjacent to each other. It characterized in that it includes.

Referring to FIG. 4B, a pixel contact hole 142H is formed on the interlayer insulating layer 116 on which the source electrode 108, the drain electrode 110, and the data line 104 of the first and second thin film transistors are formed. A first inorganic passivation layer 118 and an organic passivation layer 128 are formed.

Specifically, the first inorganic protective layer 118 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the interlayer insulating layer 116 on which the source electrode 108, the drain electrode 110, and the data line 104 are formed. do. Then, an organic insulating material such as photoacrylic or the like is entirely coated on the first inorganic protective layer 118 to form the organic protective layer 128. Then, the organic passivation layer 128 is selectively patterned through a photolithography process and an etching process. Subsequently, since the first inorganic passivation layer 118 and the organic passivation layer 128 are formed of materials having different characteristics, the first inorganic passivation layer 118 and the organic passivation layer 128 are patterned under different process conditions to form the pixel contact hole 142H. ) To form. Here, the pixel contact hole 142H penetrates the organic passivation layer 128 and the first inorganic passivation layer 118 of the first and second thin film transistors that are vertically adjacent to expose drain electrodes of the first and second thin film transistors. .

Referring to FIG. 4C, a common electrode 130 is formed on the organic passivation layer 128.

Specifically, a transparent metal layer such as ITO is formed on the organic protective layer 128 by a deposition method such as sputtering. The common electrode 130 is formed by patterning the transparent metal layer in a region other than the region in which the pixel contact hole 142H is formed through a photolithography process and an etching process.

Referring to FIG. 4D, a connection pattern 155 is formed in the touch sensing line 150 and the pixel contact hole 142H on the common electrode 130.

Specifically, an opaque metal layer is formed by a vapor deposition method such as sputtering. At this time, as the metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer, or a multilayer structure is used using these. Then, the touch sensing line 150 and the connection pattern 155 are formed by patterning the metal layer through an etching process using a photoresist pattern formed by a photolithography process.

Referring to FIG. 4E, after forming the second inorganic protective layer 138 on the substrate on which the touch sensing line 150 and the connection pattern 155 are formed, the pixel electrode 122 is formed.

Specifically, the second inorganic protective layer 138 is formed by applying an inorganic insulating material such as SiNx or SiOx on the substrate on which the touch sensing line 150 and the connection pattern 155 are formed. Then, a pixel contact hole 142H exposing the drain electrode 110 and the connection pattern 155 is formed through an etching process using a photoresist pattern formed by a photolithography process.

Subsequently, a pixel electrode 122 is formed on the second inorganic passivation layer 138.

Specifically, a transparent metal layer such as ITO is formed on the second inorganic protective layer 138 by a deposition method such as sputtering. Then, the transparent metal layer is patterned through a photolithography process and an etching process, thereby forming the pixel electrode 122. The pixel electrode 122 of one of the first and second thin film transistors is electrically connected to the connection pattern exposed through the pixel contact hole 142H, and the pixel electrode 122 of the other pixel is the pixel contact hole 142H. It is assumed that the drain electrode 110 and the exposed drain electrode 110 are electrically connected to each other.

5 is a cross-sectional view illustrating a thin film transistor substrate according to a second embodiment of the present invention.

The thin film transistor substrate shown in FIG. 5 has the same components as the thin film transistor substrate shown in FIG. 2 except that the connection pattern is formed in a double layer. Accordingly, detailed descriptions of the same components will be omitted.

Each pixel region of the substrate 101 is formed on the buffer layer 126 and includes the active layers 114A and 114B, first and second gate electrodes 106A and 106B, and source/drain electrodes 108, 110) and a connection pattern, a common electrode, a touch sensing line, and a pixel electrode.

Here, a transparent conductive material and an opaque conductive material are sequentially formed on the pixel contact hole 142H exposing the drain electrode 110 on the substrate on which the first and second thin film transistors are formed, and on the second protective layer 128. In addition, a connection pattern 155 is formed by simultaneously patterning an opaque conductive material and a transparent conductive material by a mask process, patterning the opaque conductive material to form the touch sensing electrode 150, and patterning the transparent conductive material to form a common electrode. Form 130. In this case, it is preferable to use a halftone mask.

Specifically, a transparent conductive material and an opaque conductive material are sequentially formed on the second protective layer 128. The transparent conductive material is a material such as tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. to be. And, the opaque conductive material is Mo, Ti, u, AlNd, Al, r, Mo alloy, u alloy, Al alloy, and the like.

Then, a first photoresist pattern is formed on the opaque conductive material using a halftone mask. The first photoresist pattern is formed to correspond only to regions in which the common electrode 130 and the connection pattern 155 are to be formed.

Then, the exposed opaque conductive material and transparent conductive material are removed using the first photoresist pattern as a mask. Subsequently, by ashing the first photoresist pattern, a second photoresist pattern remaining only in an area where the touch sensing electrode 150 is to be formed is formed. Then, the exposed opaque conductive material is removed using the second photoresist pattern as a mask to form a common electrode 130 made of only a transparent conductive material. Then, the second photoresist pattern is removed to form the connection pattern 155.

Specifically, the connection pattern 155 is connected to the exposed drain electrode 110 through the drain contact hole 124D, and is formed in the form of a whole electrode. In addition, the connection pattern 155 is for connecting the drain electrode 110 exposed by the drain contact hole 124D and the pixel electrode 122 to each other, and the upper electrode 157 and the lower electrode ( 137).

Meanwhile, the present invention has been described by taking a fringe electric field type liquid crystal display panel as an example, but it is applicable to all liquid crystal display panels in which common electrodes and pixel electrodes such as a horizontal electric field type are positioned on the same substrate.

The above description is only illustrative of the present invention, and various modifications may be made without departing from the technical spirit of the present invention by those of ordinary skill in the technical field to which the present invention belongs. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be interpreted by the following claims, and all technologies within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

155: connection pattern 122: pixel electrode
110: drain electrode 136: common electrode
150: touch sensing electrodes 114A, 114B: active layer
142H: pixel contact hole

Claims (9)

A gate line and a data line defining a pixel area;
First and second thin film transistors connected to the same gate line among the gate lines;
An organic passivation layer covering the first and second thin film transistors and exposing drain electrodes of each of the thin film transistors through one pixel contact hole;
A pixel electrode connected to the first and second thin film transistors and separated for each pixel;
A thin film transistor substrate having a connection pattern electrically connecting at least one drain electrode of the first and second thin film transistors to the pixel electrode. The method of claim 1,
A thin film transistor substrate in which a pixel electrode connected to a connection pattern in the pixel contact hole is shorter than an adjacent pixel electrode. The method of claim 1,
The pixel electrode connected to the drain contact hole of the first transistor is shorter in length than the pixel electrode connected to the drain contact hole of the second thin film transistor. The method of claim 3,
The drain contact hole is a thin film transistor substrate having the same distance above and below a gate line, respectively. The method of claim 1,
A common electrode forming an electric field with the pixel electrode;
A thin film transistor substrate formed to directly contact the common electrode and having a touch sensing line connecting common electrodes of adjacent pixels so that the common electrode is driven as a touch sensing electrode. The method of claim 5,
The connection pattern is formed of a double layer of an upper electrode and a lower electrode, the upper electrode is of the same material as the touch sensing line, and the lower electrode is of the same material as the common electrode. delete The method of claim 1,
Each of the gate lines is a thin film transistor substrate having a gate electrode branched vertically. A gate line and a data line defining a pixel area;
First and second thin film transistors connected to the same gate line among the gate lines;
An organic passivation layer covering the first and second thin film transistors and exposing drain electrodes of each of the thin film transistors through one pixel contact hole;
A pixel electrode connected to the first and second thin film transistors and separated for each pixel;
A thin film transistor substrate having a connection pattern electrically connecting at least one of the first and second thin film transistors to the pixel electrode;
A common electrode forming an electric field with the pixel electrode;
A touch device having a touch sensing line formed to directly contact the common electrode and connecting common electrodes of adjacent pixels so that the common electrode is driven as a touch sensing electrode.

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