KR102264273B1 - Thin film transistor substrate and liquid crystal display panel having the smae - Google Patents

Abstract

The present invention relates to a thin film transistor substrate capable of improving transmittance and a liquid crystal display panel having the same, wherein the thin film transistor substrate according to the present invention includes a pixel extension electrode positioned between adjacent pixel electrodes with any one of the adjacent pixel electrodes. electrically connected.

Description

A thin film transistor substrate and a liquid crystal display panel having the same {THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL HAVING THE SMAE}

The present invention relates to a thin film transistor substrate and a liquid crystal display panel having the same, and more particularly, to a thin film transistor substrate capable of improving transmittance and a liquid crystal display panel having the same.

A video display device that implements a variety of information on a screen is a key technology in the information and communication era, and is developing in the direction of thinner, lighter, portable and high performance. Accordingly, flat panel display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), are in the spotlight.

Among the flat panel display devices, the liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal by an electric field formed between a pixel electrode connected to a thin film transistor and a common electrode. As shown in FIG. 1 , the pixel electrodes 4 and 6 of the liquid crystal display are formed to be spaced apart from each other by a predetermined interval d to prevent short circuit. Since the electric field is not efficiently applied to the liquid crystals positioned in the spaced region between the pixel electrodes 4 and 6 and light is not transmitted, the spaced region between the pixel electrodes 4 and 6 is formed by the black matrix 2 ) is formed to overlap.

However, when the area of the black matrix 2 is reduced to improve the aperture ratio, some of the spaced areas between the adjacent pixel electrodes 4 and 6 do not overlap the black matrix 2 as shown in FIG. 1 . , exposed outside the black matrix (2). Accordingly, the liquid crystal cannot be driven in the spaced region between the pixel electrodes 4 and 6 exposed outside the black matrix 2 , so that light transmission through the liquid crystal is extremely small, so that transmittance is lowered.

SUMMARY OF THE INVENTION The present invention is to solve the above problems, and the present invention is to provide a thin film transistor substrate capable of improving transmittance and a liquid crystal display panel having the same.

In order to achieve the above object, in the thin film transistor substrate according to the present invention, a pixel extension electrode positioned between adjacent pixel electrodes is electrically connected to any one of the adjacent pixel electrodes.

In the thin film transistor substrate according to the present invention, a pixel extension electrode is formed between adjacent pixel electrodes with at least one signal line of a gate line and a data line interposed therebetween. Accordingly, in the present invention, since the liquid crystal is driven in a spaced region between adjacent pixel electrodes with a signal line interposed therebetween by the electric field formed between the pixel extension electrode and the common electrode, light is transmitted in the spaced region to improve transmittance. do. In addition, since each of the adjacent pixel electrodes and the pixel extension electrode are positioned on different planes, a short circuit can be prevented without considering a separation margin. In addition, due to the improvement in transmittance, the present invention can lower the driving voltage when implementing the same luminance as in the prior art, thereby reducing power consumption.

1 is a plan view showing a pixel electrode and a black matrix of a conventional thin film transistor substrate.
2 is a plan view illustrating a thin film transistor substrate according to a first embodiment of the present invention.
3 is a cross-sectional view showing the thin film transistor substrate taken along the line "I-I'" and the line "II-II'" in FIG. 2;
4A and 4B are cross-sectional views illustrating a thin film transistor substrate according to a second embodiment of the present invention.
5 is a cross-sectional view showing a thin film transistor substrate according to a third embodiment of the present invention.
6 is a plan view illustrating a thin film transistor substrate according to a fourth embodiment of the present invention.
7 is a cross-sectional view showing the thin film transistor substrate taken along the line "III-III'" in FIG.
8 is a view for explaining and comparing transmittance of a liquid crystal display panel having a thin film transistor substrate according to the related art and the present invention.
9A to 9G are cross-sectional views for explaining a method of manufacturing the thin film transistor substrate shown in FIG. 3 .

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view showing a thin film transistor substrate according to the present invention, and FIG. 3 is a cross-sectional view showing the thin film transistor substrate taken along lines "I-I'" and "II-II'" in FIG.

The thin film transistor substrate shown in FIGS. 2 and 3 includes a gate line 102 , a data line 104 , a thin film transistor, a pixel electrode 122 , a common electrode 136 , and a pixel extension electrode 150 .

The gate line 102 and the data line 104 cross each other with the interlayer insulating layer 116 interposed therebetween to define respective pixel regions. The gate line 102 supplies a scan signal to the gate electrodes 106A and 106B of the thin film transistor in each pixel region, and the data line 104 supplies a data signal to the source electrode 108 of the thin film transistor in each pixel region.

The thin film transistor causes the data signal of the data line 104 to be charged and maintained in the pixel electrode 122 in response to the scan signal of the gate line 102 . To this end, the thin film transistor includes gate electrodes 106A and 106B, a source electrode 108 , a drain electrode 110 , and an active layer 114 .

The gate electrodes 106A and 106B have a plurality of gate electrodes that are part of the gate line 102 . In the present invention, two gate electrodes, that is, the first and second gate electrodes 106A and 106B will be described as an example.

The first gate electrode 106A overlaps the first channel region 114A of the active layer, and the second gate electrode 106B overlaps the second channel region 114B of the active layer. Since the first and second gate electrodes 106A and 106B are formed in series, first and second channel regions 114A and 114B are formed between the source and drain regions 114S and 114D. Accordingly, since the total length of the channel regions 114A and 114B of the thin film transistor is increased, the distance between the source electrode 108 connected to the source region 114S and the drain electrode 110 connected to the drain region 114D is increased. resistance increases. Accordingly, when the thin film transistor having a plurality of gate electrodes (ie, a plurality of channel regions) is turned off, the off current can be reduced.

The source electrode 108 is a portion of the data line 104 overlapping the source region 114S of the active layer in the data line 104 and is active through the source contact hole 124S penetrating the interlayer insulating layer 116 . connected to the source region 114S of the layer.

The drain electrode 110 faces the source electrode 108 and is connected to the drain region 114D of the active layer through a drain contact hole 124D passing through the interlayer insulating layer 116 and the gate insulating layer 112 . Also, the drain electrode 110 is connected to the pixel electrode 122 through the first pixel contact hole 120 .

The active layer 114 forms a channel between the source electrode 108 and the drain electrode 110 . As shown in FIG. 2 , the active layer 114 may be formed in a “U” shape or an inverted “U” shape on the buffer layer 126 , or may be formed in another shape. The active layer 114 includes first and second channel regions 114A and 114B, a common region 114C, a source region 114S, and a drain region 114D.

The first channel region 114A overlaps the first gate electrode 106A with the gate insulating layer 112 interposed therebetween, and the second channel region 114B has the second gate electrode ( ) with the gate insulating layer 112 interposed therebetween. 106B). The common region 114C is formed between the first and second channel regions 114A and 114B, and n-type or p-type impurities are implanted. The source region 114S is implanted with n-type or p-type impurities, and is connected to the source electrode 108 which is a part of the data line 104 through the source contact hole 124S. The drain region 114D is implanted with n-type or p-type impurities, and is connected to the drain electrode 110 through the drain contact hole 124D. The same or different impurities may be implanted into the source region 114S, the drain region 114D, and the common region 114C at the same or different concentrations. However, when the same impurities are implanted into the source region 114S, the drain region 114D, and the common region 114C at the same concentration, an increase in the number of mask processes may be prevented.

The buffer film 126 is formed in a single-layer or multi-layer structure of silicon oxide or silicon nitride on a substrate 101 formed of a plastic resin such as glass or polyimide (PI). The buffer layer 126 prevents diffusion of moisture or impurities generated in the substrate 101 or controls a heat transfer rate during crystallization, so that the active layer 114 can be well crystallized.

The first and second protective layers 118 and 128 block the inflow of moisture from the outside to protect the thin film transistor. Each of the first and second passivation layers 118 and 128 is formed of an inorganic insulating material or an organic insulating material.

The first passivation layer 118 is formed of an organic insulating material to planarize the step formed by the thin film transistor to realize high resolution. In addition, the first passivation layer 118 is formed on the thin film transistor and the data line 104 to insulate each of the thin film transistor and the data line 104 and the common electrode 136 .

The second passivation layer 128 is formed between the pixel electrode 122 and the common electrode 136 to insulate the pixel electrode 122 and the common electrode 136 .

The pixel electrode 122 is formed on the second passivation layer 128 of each pixel area provided at the intersection of the gate line 102 and the data line 104 . The pixel electrode 122 includes a pixel connection portion 122B overlapping the gate line 102 , and a plurality of finger-shaped pixel finger portions 122A extending from the pixel connection portion 122B to the pixel region.

In addition, the pixel electrode 122 is electrically connected to the drain electrode 110 exposed through the first pixel contact hole 120 , and is electrically connected to the pixel extension electrode 150 exposed through the second pixel contact hole 152 . electrically connected. Here, the first pixel contact hole 120 is formed to penetrate the first and second passivation layers 118 and 128 to expose the drain electrode 110 , and the second pixel contact hole 152 includes the first and second passivation layers 118 and 128 . 2 It is formed to penetrate the passivation layers 118 and 128 to expose the pixel extension electrode 150 .

The common electrode 136 is formed to have a common opening 134 having a larger area than each of the first and second pixel contact holes 120 and 152 in a region overlapping each of the first and second pixel contact holes 120 and 152 . The common electrode 136 is formed on the first passivation layer 118 in a region other than the common opening 134 . Accordingly, the common electrode 136 is integrated and electrically connected to the common electrode 136 of an adjacent pixel area without a separate common line. In addition, the common electrode 136 overlaps the pixel electrode 122 with the second passivation layer 128 interposed therebetween to form a fringe electric field. Accordingly, the common electrode 136 to which the common voltage is supplied forms a fringe electric field with the pixel electrode 122 to which the pixel voltage signal is supplied through the thin film transistor, so that the liquid crystal molecules arranged between the thin film transistor substrate and the color filter substrate are dielectric. rotation due to anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The pixel extension electrode 150 is formed between the pixel electrodes 122 positioned in each of the upper and lower pixel areas PXL_U and PXL_D that are vertically adjacent to each other with the gate line 102 interposed therebetween. In this case, the pixel extension electrode 150 is positioned on a different plane from the vertically adjacent pixel electrodes 122 . That is, the pixel extension electrode 150 is formed on the same layer as the data line 104 and made of the same material. Specifically, the pixel extension electrode 150 is formed of a single layer of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof on the interlayer insulating layer 116 , or a multilayer structure using them. It is formed from the source/drain metal layer used.

The pixel extension electrode 150 includes an extension connection portion 150B overlapping the pixel connection portion 122B, and a plurality of finger-shaped extension finger portions 150A extending from the extension connection portion 150B to an adjacent pixel area.

Since the extension connection part 150B of the pixel extension electrode 150 is connected to the pixel electrode 122 of each pixel area through the second pixel contact hole 152 , the pixel extension electrode 150 is supplied to the pixel electrode 122 . It achieves an equipotential with the pixel voltage signal.

The extended finger portion 150A of the pixel extension electrode 150 extends from the pixel electrode 122 of each pixel region to the adjacent pixel region across the gate line 102 . That is, the extended finger portion 150A of the pixel extension electrode 150 is formed in a spaced region between the vertically adjacent pixel electrodes 122 with the gate line 102 interposed therebetween. Accordingly, the extended finger portion 150A of the pixel extension electrode 150 forms a fringe electric field with the common electrode 136 in a spaced region between the vertically adjacent pixel electrodes 122 . Since the liquid crystals positioned in the slit area SA between the extended finger portions 150A of the pixel extension electrodes 150 are driven by the fringe electric field, light is transmitted and transmittance is improved.

In addition, the extended finger unit 150A and the pixel finger unit 122A of the lower pixel area PXL_D adjacent to the extended finger unit 150A have the pixel ping of the upper pixel area PXL_U with respect to the extended connection unit 150B. It is formed in a slanted diagonal direction while being symmetrical with the rejection 122A. Accordingly, by the fringe electric field formed between the common electrode 136 and the pixel electrode 122 , the liquid crystal molecules are symmetrically arranged with respect to the extension connection part 150B and the pixel connection part 122B to form a multi-domain. It can improve the viewing angle.

4A and 4B are cross-sectional views illustrating a thin film transistor substrate according to a second embodiment of the present invention.

The thin film transistor substrate shown in FIGS. 4A and 4B has a touch sensing line 160 in comparison with the thin film transistor substrate shown in FIG. 3 , and the pixel extension electrode 150 is made of the same material as the touch sensing line 160 . It has the same components except that it is formed. Accordingly, detailed descriptions of the same components will be omitted.

The touch sensing line 160 shown in FIGS. 4A and 4B is connected to the common electrodes 136 so that the common electrode 136 can be used as a touch sensing electrode during the touch sensing period. That is, during the touch sensing period, the common electrodes 136 of each pixel area connected by the touch sensing line 160 are driven as the touch sensing electrode to sense a change in capacitance according to a user's touch. Then, the touch position is detected by comparing the touch capacitance according to the user's touch with the reference capacitance.

The pixel extension electrode 150 is formed of the same material as the touch sensing line 160 . Specifically, the pixel extension electrode 150 has a single layer of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof on the first passivation layer 118 , or a multilayer structure using them. It is formed of a touch metal layer used as

Since the pixel extension electrode 150 is connected to the pixel electrode 122 of each pixel area through the second pixel contact hole 152 , the pixel extension electrode 150 corresponds to an equipotential with the pixel voltage signal supplied to the pixel electrode 122 . will achieve

Accordingly, the pixel extension electrode 150 forms a fringe electric field or a horizontal electric field with the common electrode 136 in a spaced region between the vertically adjacent pixel electrodes 122 . The electric field drives the liquid crystals in the slit area SA between the extended finger portions 150A of the pixel extension electrodes 150 to transmit light in the slit area SA, so that transmittance is improved.

Meanwhile, the touch sensing line 160 is electrically connected to the common electrode 136 through the touch contact hole 138 penetrating the third passivation layer 148 as shown in FIG. 4A . In this case, since the pixel extension electrode 150 is formed of the same material on the same plane as the touch sensing line 160 , that is, on the first passivation layer 118 , the pixel extension electrode 150 generates a fringe electric field from the common electrode 136 . to form In this case, the touch sensing line 160 and the pixel extension electrode 150 may be simultaneously formed through a single mask process.

In addition, the touch sensing line 160 is directly electrically connected to the common electrode 136 without a touch contact hole as shown in FIG. 4B . In this case, since the pixel extension electrode 150 is formed of the same material as the touch sensing line 160 on the same plane as the common electrode 136 directly connected to the touch sensing line 160 , the pixel extension electrode 150 has a common A horizontal electric field is formed with the electrode 136 . In this case, the pixel extension electrode 150 , the touch sensing line 160 , and the common electrode 136 may be simultaneously formed through a single mask process.

Meanwhile, in the thin film transistor substrate having the touch sensing line 160 shown in FIGS. 4A and 4B , the pixel extension electrode 150 is formed of the same material as the touch sensing line 160 as an example. The electrode 150 may be formed of the same material as the data line 104 on the same plane (ie, the interlayer insulating layer 116 ).

5 is a cross-sectional view showing a thin film transistor substrate according to a third embodiment of the present invention.

The thin film transistor substrate shown in FIG. 5 is formed in a multi-layered structure including a first conductive layer 162a in which the data lines 104 and the source and drain electrodes 108 and 110 are transparent, in contrast to the thin film transistor substrate shown in FIG. 3 . and has the same components except that the pixel extension electrode 150 is formed of the transparent first conductive layer 162a. Accordingly, detailed descriptions of the same components will be omitted.

The data pattern group including the data line 104 and the source and drain electrodes 108 and 110 is disposed on the transparent first conductive layer 162a formed on the interlayer insulating layer 116 and the first conductive layer 162a. It is formed in a multi-layered structure including the second conductive layer 162b having higher conductivity than the first conductive layer 162a. Here, the first conductive layer 162a is formed of a transparent metal layer such as ITO, which is the same as that of the pixel electrode 122 , and the second conductive layer 162b is formed of Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof. It is formed of the same opaque metal layer.

The pixel extension electrode 150 is formed in a single-layer structure including the transparent first conductive layer 162a on the interlayer insulating layer 116 . The transmittance of the pixel extension electrode 150 formed of the transparent first conductive layer 162a is further improved than that of the case of being formed of an opaque material. That is, when a fringe electric field is formed between the pixel extension electrode 150 to which the pixel voltage signal is supplied and the common electrode 136 , the fringe electric field causes a gap between the extension fingers 150A of the pixel extension electrodes 150 . Liquid crystals positioned in the transparent pixel extension electrode 150 as well as the slit area SA are driven. Accordingly, light is transmitted through the transparent pixel extension electrode 150 as well as the slit area SA, so that transmittance is further improved.

Meanwhile, as shown in FIG. 5 , the data pattern group in which the pixel extension electrode 150 formed of the transparent first conductive layer 162a and the first and second conductive layers 162a and 162b are stacked is a slit mask or a half mask. They may be simultaneously formed through a single mask process using a transmission mask, or may be individually formed through each mask process.

In addition, the pixel extension electrode 150 may be formed of a transparent first conductive layer 162a, and the data pattern group may be formed of an opaque second conductive layer 162b. In this case, the pixel extension electrode 162a and the data pattern group are individually formed through each mask process.

6 is a plan view showing a thin film transistor substrate according to a fourth embodiment of the present invention, and FIG. 7 is a cross-sectional view showing the thin film transistor substrate taken along line "III-III'" in FIG.

In contrast to the thin film transistor substrates shown in FIGS. 2 and 3 , the thin film transistor substrates shown in FIGS. 6 and 7 have a pixel extension electrode 150 interposed between the data lines 104 and adjacent pixel electrodes ( 122), except that it has the same components. Accordingly, detailed descriptions of the same components will be omitted.

The pixel electrode 122 shown in FIGS. 6 and 7 is symmetrical with respect to the data line 104 and is formed in an inclined direction. The pixel electrode 122 includes a pixel connection part 122B overlapping the data line 104 and a pixel finger part 122A extending from the pixel connection part 122B.

The pixel extension electrode 150 is formed between the left and right adjacent pixel electrodes 122 with the data line 104 interposed therebetween. The pixel extension electrode 150 includes an extension connection part 150B overlapping the pixel connection part 122B, and an extension finger part 150A extending from the extension connection part 150B. In this case, the extended finger part 150A is formed in an inclined direction while being symmetrical with the pixel finger part 122A with respect to the extended connection part 150B. Accordingly, by the fringe electric field formed between the common electrode 136 and the pixel electrode 122 , the liquid crystal molecules are symmetrically arranged with respect to the extension connection part 150B and the pixel connection part 122B to form a multi-domain. It can improve the viewing angle.

Also, the pixel extension electrode 150 is made of the same material as the gate line 102 or the touch sensing line 160 and is positioned on the same plane. In this case, when the pixel extension electrode 150 is made of the same material as the gate line 102 and is positioned on the same plane, the pixel extension electrode 150 forms the gate insulating layer 112 and the first and second passivation layers 118 and 128 . It is exposed through the second pixel contact hole 152 formed to pass therethrough. In addition, as shown in FIG. 7 , when the pixel extension electrode 150 is made of the same material as the touch sensing line 160 and is positioned on the same plane, the pixel extension electrode 150 passes through the second passivation layer 128 . It is exposed through the formed second pixel contact hole 152 .

Accordingly, the pixel extension electrode 150 is electrically connected to any one of the left and right pixel electrodes 122 adjacent to each other with the data line 104 interposed therebetween through the second pixel contact hole 152 . The pixel extension electrode 150 forms an electric field with the common electrode 136 in a spaced region between the left and right adjacent pixel electrodes 122 . The liquid crystals positioned in the slit region between the extended fingers 150B of the pixel extension electrodes 150 are driven by this electric field, so that light is transmitted through the slit region, thereby improving transmittance.

8 is a view for explaining a comparison of transmittance of a thin film transistor substrate according to the present invention and the related art.

As shown in FIG. 8, when the maximum driving voltage is 5V when driving the liquid crystal, the conventional thin film transistor substrate realizes a transmittance of about 4.96%, whereas the thin film transistor substrate of the present invention has a transmittance of about 5.10%, which is higher than that of the conventional one. can be implemented In this case, when the thin film transistor substrate having the transparent pixel extension electrode shown in FIG. 5 is applied, a transmittance exceeding 5.10%, which is higher than that of the related art, may be realized. Accordingly, the present invention can obtain a transmittance improvement of about 2.6% or more compared to the prior art. Due to this improvement in transmittance, the present invention can lower the driving voltage when implementing the same luminance as in the prior art, thereby reducing power consumption.

9A to 9G are cross-sectional views for explaining a method of manufacturing a thin film transistor substrate according to the present invention. The manufacturing method of the thin film transistor substrate according to the present invention will be described by taking the thin film transistor substrate shown in FIG. 3 as an example.

Referring to FIG. 9A , a buffer layer 126 is formed on a substrate 101 , and an active layer 114 is formed thereon.

Specifically, a buffer film 126 and an amorphous silicon thin film are sequentially coated on the substrate 101 . Then, it is formed into a polysilicon thin film by crystallizing the amorphous silicon thin film. Then, the active layer 114 is formed by patterning the polysilicon thin film through a photolithography process and an etching process.

Referring to FIG. 9B , a gate insulating layer 112 is formed on the buffer layer 126 on which the active layer 114 is formed, and the gate line 102 including first and second gate electrodes 106A and 106B thereon. ) is formed.

Specifically, a gate insulating film 112 is formed on the buffer film 126 on which the active layer 114 is formed, and a gate metal layer is formed thereon by a deposition method such as sputtering. An inorganic insulating material such as SiOx or SiNx is used as the gate insulating layer 112 . As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer, or a multi-layer structure using these materials is used. Then, the gate line 102 including the first and second gate electrodes 106A and 106B is formed on the gate insulating layer 112 by patterning the gate metal layer through a photolithography process and an etching process.

In addition, n+ type or p+ type impurities are implanted into the active layer 114 using the first and second gate electrodes 106A and 106B as masks, thereby forming the common region 114C of the active layer 114 into which the impurities are implanted. , a source region 114S, a drain region 114D, and first and second channel regions 114A and 114B of the active layer 114 to which impurities are not implanted are formed.

Referring to FIG. 9C , an interlayer insulating film having source and drain contact holes 124S and 124D on the gate insulating film 112 in which the gate line 102 including the first and second gate electrodes 106A and 106B is formed ( 116) is formed.

Specifically, the interlayer insulating film 116 is formed on the gate insulating film 112 on which the gate line 102 is formed by a method such as PECVD. Then, the interlayer insulating layer 116 and the gate insulating layer 112 are patterned through a photolithography process and an etching process to form source and drain contact holes 124S and 124D. Here, the source and drain contact holes 124D penetrate the interlayer insulating layer 116 and the gate insulating layer 112 to expose the source and drain regions 114S and 114D.

Referring to FIG. 9D , a data pattern including a source electrode 108 , a drain electrode 110 , a data line 104 , and a pixel extension electrode 150 is formed on the interlayer insulating layer 116 .

Specifically, a source/drain metal layer is formed on the interlayer insulating film 116 having the source and drain contact holes 124S and 124D by a deposition method such as sputtering. As the source/drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer, or a multilayer structure is used using these materials. Then, the source electrode 108 , the drain electrode 110 , the data line 104 , and the pixel extension electrode 150 are formed on the interlayer insulating film 116 by patterning the source/drain metal layer through a photolithography process and an etching process. do.

Referring to FIG. 9E , a first passivation layer 118 is formed on the interlayer insulating layer 116 on which the source electrode 108 , the drain electrode 110 , the data line 104 and the pixel extension electrode 150 are formed, and the second passivation layer 118 is formed. 1 A common electrode 136 having a common opening 134 is formed on the passivation layer 118 .

Specifically, the first passivation layer 118 is formed by applying an inorganic insulating material such as SiNx or SiOx or an organic insulating material to the entire surface of the interlayer insulating layer 116 . Then, a transparent metal layer such as ITO is formed on the first passivation layer 118 by a deposition method such as sputtering. A common electrode 136 having a common opening 134 is formed by patterning the transparent metal layer through a photolithography process and an etching process. In this case, the common opening 134 of the common electrode 136 is formed to surround the first and second pixel contact holes 120 and 152 with a width wider than that of the first and second pixel contact holes 120 and 152 to be formed later. .

Referring to FIG. 9F , a second inorganic passivation layer 128 is formed on the first passivation layer 118 on which the common electrode 136 is formed, and first and second pixel contact holes 120 and 152 are formed.

Specifically, an inorganic insulating material such as SiNx or SiOx or an organic insulating material is coated on the first passivation layer 118 in which the common electrode 136 having the common opening 134 is formed, thereby forming the second passivation layer 128 . . Then, the first and second passivation layers 118 and 128 are patterned through an etching process using the photoresist pattern formed by the photolithography process as a mask, thereby exposing the drain electrode 110, the first pixel contact hole 120 and the pixel; A second pixel contact hole 152 exposing the extension electrode 150 is formed.

Referring to FIG. 9G , the pixel electrode 122 is formed on the substrate 101 on which the first and second pixel contact holes 120 and 152 are formed.

Specifically, a transparent metal layer such as ITO is formed on the second passivation layer 128 by a deposition method such as sputtering. Then, the pixel electrode 122 is formed by patterning the transparent metal layer through a photolithography process and an etching process.

Meanwhile, the thin film transistor substrate according to the present invention is disposed to face the color filter substrate with the liquid crystal layer interposed therebetween, thereby completing the liquid crystal display panel. In this case, although the fringe electric field structure has been described as an example in the present invention, it is applicable to all liquid crystal display panel structures such as a horizontal electric field type or a vertical electric field type.

Also, in the present invention, the pixel extension electrode is positioned in a spaced region between adjacent pixel electrodes with a gate line or a data line interposed therebetween. In addition, the pixel extension electrode has a gate line and a data line interposed therebetween. It may be located in a spaced region between adjacent pixel electrodes.

The above description is merely illustrative of the present invention, and various modifications may be made by those of ordinary skill in the art to which the present invention pertains without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be interpreted by the following claims, and all technologies within the scope equivalent thereto should be construed as being included in the scope of the present invention.

114: active layer 122: pixel electrode
130: common electrode 150: pixel extension electrode
160: touch sensing line

Claims (8)

pixel electrodes disposed adjacent to each other with at least one of a gate line and a data line interposed therebetween;
a pixel extension electrode positioned between the adjacent pixel electrodes;
The thin film transistor substrate in which the pixel extension electrode directly contacts only one of the adjacent pixel electrodes. The method of claim 1,
the pixel extension electrode is positioned on a different plane from the pixel electrode;
the pixel extension electrode is exposed through a contact hole penetrating through at least one insulating layer covering the pixel extension electrode;
The pixel electrode is connected to the pixel extension electrode through the contact hole. 3. The method of claim 2,
The pixel electrodes are vertically adjacent to each other with the gate line interposed therebetween;
the pixel extension electrode is positioned on the same plane as the data line;
The pixel extension electrode is a thin film transistor substrate made of the same material as the data line or the pixel electrode. 4. The method of claim 3,
The data line has a multilayer structure including a transparent first conductive layer made of the same material as the pixel electrode and a second conductive layer positioned on the first conductive layer,
The pixel extension electrode is a thin film transistor substrate made of the transparent first conductive layer. 3. The method of claim 2,
a common electrode forming an electric field with the pixel electrode;
Further comprising a touch sensing line connected to the common electrode,
The pixel extension electrode is positioned on the same plane as the touch sensing line, and the thin film transistor substrate is made of the same material as any one of the touch sensing line and the data line. 6. The method of claim 5,
The pixel electrodes are positioned adjacent to each other with the data line interposed therebetween,
The pixel extension electrode is made of the same material as the touch sensing line and is positioned on the same plane as the thin film transistor substrate. The method of claim 1,
The pixel electrode is
a pixel connection part overlapping at least one of the gate line and the data line;
a plurality of pixel fingers extending from the pixel connection part;
The pixel extension electrode is
an extension connecting portion overlapping the pixel connecting portion;
A thin film transistor substrate having extended fingers extending from the extension connection part and forming a symmetric structure with a plurality of pixel fingers based on the extension connection part. The thin film transistor substrate of any one of claims 1 to 7;
a color filter substrate facing the thin film transistor substrate;
A liquid crystal display panel comprising a liquid crystal layer positioned between the thin film transistor substrate and the color filter substrate.

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