KR20150142205A - Thin film transistor substrate, liquid crystal display panel having the same, and method of fabricating liquid crystal display panel - Google Patents

Abstract

The present invention relates to a thin film transistor substrate in which an optical leakage electric current may be reduced, and transmittance may be improved, a liquid crystal display panel having the same, and a method for producing a liquid crystal panel. The thin film transistor substrate according to the present invention comprises: a gate line and a data line configured to cross each other on a substrate to form a pixel region; a thin film transistor formed in a crossing part between the gate line and the data line, and including an active layer which has a source region, a drain region, and multiple channel regions, a gate electrode which is overlapped with the channel regions, a source electrode which is overlapped with the source region of the active layer, and a drain electrode which is overlapped with the drain region of the active layer; a pixel electrode connected to the thin film transistor; and a light-shielding pattern formed on the substrate to be disposed in a lower side of the active layer, and overlapped with each of the channel regions. The light-shielding patterns overlapped with the channel region adjacent to the drain region among the channel regions are separated from each other with a slit therebetween.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor substrate, a liquid crystal display panel having the thin film transistor substrate, and a method of manufacturing the liquid crystal display panel using the thin film transistor substrate.

The present invention relates to a thin film transistor substrate, a liquid crystal display panel having the thin film transistor substrate, and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor substrate capable of reducing light leakage current and improving transmittance, And a method of manufacturing a liquid crystal display panel.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, a flat panel display device capable of reducing weight and volume, which is a disadvantage of a cathode ray tube (CRT), has attracted attention.

A flat panel display device includes a thin film transistor formed on a substrate and used as a switching element and a driving element. The thin film transistor has an active layer forming a channel region, a gate electrode formed so as to overlap the channel region, and source and drain electrodes facing each other with the channel region interposed therebetween.

The light is incident on the channel region of the active layer and the light leakage current is increased to cause deterioration of image quality such as flicker. In order to solve this problem, when the light blocking pattern and the black matrix are formed so as to completely overlap the active layer, there is a problem that the aperture ratio and the transmittance are reduced and the power consumption is increased.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a thin film transistor substrate, a liquid crystal display panel having the thin film transistor substrate, and a method of manufacturing a liquid crystal display panel capable of reducing light leakage current and improving transmittance .

According to an aspect of the present invention, there is provided a thin film transistor substrate comprising: a gate line and a data line formed on a substrate so as to intersect with each other to form a pixel region; An active layer formed at an intersection of the gate line and the data line and having a source region, a drain region and a plurality of channel regions, a gate electrode overlapping the plurality of channel regions, a source electrode overlapping the source region of the active layer, A thin film transistor including a drain electrode overlapping a drain region of the active layer; A pixel electrode connected to the thin film transistor; And a light blocking pattern formed on the substrate so as to be positioned below the active layer and overlapping each of the plurality of channel regions, wherein the light blocking pattern overlaps with the channel region adjacent to the drain region, And the light blocking patterns are spaced apart from each other with the slit interposed therebetween.

Here, the first embodiment of the light blocking patterns overlapping the channel region adjacent to the source region may be spaced apart from each other with the slit interposed therebetween.

In this case, the light blocking patterns may be formed in the form of a stripe parallel to or perpendicular to the gate line, or the light blocking patterns may be formed in a dot shape spaced apart by the slits in a lattice form, Or in the form of a plate having slits in the form of dots.

The second embodiment of the light blocking patterns overlapping the channel region adjacent to the source region is formed in a plate shape without the slit.

The active layer may include a common region formed between the source region, the drain region, the first and second channel regions, and the first and second channel regions.

According to an aspect of the present invention, there is provided a liquid crystal display panel comprising: a color filter substrate having a black matrix and a color filter; And a thin film transistor substrate facing the color filter substrate with a liquid crystal interposed therebetween, wherein the thin film transistor substrate includes a gate line and a data line formed on the substrate so as to intersect with each other to form a pixel region; An active layer formed at an intersection of the gate line and the data line and having a source region, a drain region and a plurality of channel regions, a gate electrode overlapping the plurality of channel regions, a source electrode overlapping the source region of the active layer, A thin film transistor including a drain electrode overlapping a drain region of the active layer; A pixel electrode connected to the thin film transistor; A common electrode which forms an electric field with the pixel electrode; And a light blocking pattern formed on the substrate so as to be positioned below the active layer and overlapping each of the plurality of channel regions, wherein the light blocking pattern overlaps with the channel region adjacent to the drain region, And the light blocking patterns are spaced apart from each other with the slit interposed therebetween.

Wherein the active layer has a common region formed between the source region, the drain region, the first and second channel regions, and the first and second channel regions, And the common region adjacent to the drain region overlaps with the color filter.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display panel, including: providing a thin film transistor substrate; a color filter substrate having a black matrix and a color filter; Forming a color filter substrate having a black matrix and a color filter with the thin film transistor substrate, wherein the step of forming the thin film transistor substrate comprises: forming a light blocking pattern on the substrate; Forming a buffer layer to cover the light blocking pattern; An active layer having a source region, a drain region, a common region, and a plurality of channel regions overlapping the light blocking pattern, a gate electrode overlapping the plurality of channel regions, a source electrode overlapping a source region of the active layer, Forming a thin film transistor on the buffer layer, the thin film transistor including a drain electrode overlapping a drain region of the active layer; Forming a pixel electrode connected to the thin film transistor; And forming a common electrode that forms an electric field with the pixel electrode, wherein the light blocking patterns overlapping the channel region adjacent to the drain region among the plurality of channel regions are spaced apart from each other with the slit therebetween .

In the thin film transistor substrate, the liquid crystal display panel having the thin film transistor substrate, and the method of manufacturing the liquid crystal display panel according to the present invention, light blocking patterns overlapping the channel region are formed to be spaced apart from each other with the slit therebetween. Accordingly, the present invention can guide light to the outside of the active area, that is, the area that does not overlap with the black matrix, by the diffraction phenomenon by the light blocking patterns, thereby improving the transmittance and the aperture ratio. In addition, according to the present invention, since the light shielding pattern is provided, light can be prevented from being absorbed into the active region as compared with the structure having no light shielding pattern, and thus the off current can be reduced. . ≪ / RTI >

1 is a plan view showing a thin film transistor substrate according to a first embodiment of the present invention.
Fig. 2 is a cross-sectional view showing a thin film transistor substrate cut along the line "I-I" in Fig. 1. Fig.
FIGS. 3A to 3F are plan views illustrating various embodiments of the light blocking pattern shown in FIGS. 1 and 2. FIG.
FIG. 4 is a view for explaining the diffraction phenomenon using the light blocking pattern shown in FIG. 1 to FIG.
5A and 5B are a plan view and a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
6 is a plan view showing a thin film transistor substrate according to a second embodiment of the present invention.
7 is a cross-sectional view showing a thin film transistor substrate cut along the line "II-II"" in Fig.
8A and 8B are a plan view and a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor substrate shown in FIGS. 6 and 7. FIG.
9A to 9I are cross-sectional views illustrating a method of manufacturing a liquid crystal display panel according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view showing a thin film transistor substrate according to the present invention, and FIG. 2 is a cross-sectional view showing a thin film transistor substrate taken along a line "I-I '" in FIG.

The thin film transistor substrate shown in FIGS. 1 and 2 has a gate line 102, a data line 104, a thin film transistor, a light blocking pattern 130, a pixel electrode 122 and a common electrode 136.

The gate line 102 and the data line 104 intersect each other with the interlayer insulating film 116 therebetween to define respective pixel regions. The gate line 102 supplies a scan signal to the gate electrode 106 of the thin film transistor in each pixel region and the data line 104 supplies a data signal to the source electrode 108 of the thin film transistor in each pixel region.

The pixel electrode 122 is formed on the second protective film 128 of each pixel region provided at the intersection of the gate line 102 and the data line 104. The pixel electrode 122 includes a first horizontal portion 122A connected to the drain electrode 110 exposed through the pixel contact hole 120 and a second horizontal portion 122A connected to the first horizontal portion 122A and the gate line 102 A second horizontal part 122B formed and a plurality of pixel parts 122C connected between the first and second horizontal parts 122A and 122B.

The common electrode 136 is formed to have an opening 134 that is larger in area than the pixel contact hole 120 in a region overlapping the pixel contact hole 120. This common electrode 136 is formed on the first protective film 118 in the remaining region except for the opening portion 134. Thus, the common electrode 136 is electrically connected to the common electrode 136 of the adjacent pixel region without a separate common line. The common electrode 136 overlaps the pixel electrode 122 with the second protective film 118 therebetween to form a fringe field in each pixel region. Accordingly, the common electrode 124 to which the common voltage is supplied forms the fringe field with the pixel electrode 122 to which the video signal is supplied through the thin film transistor, and the liquid crystal molecules Are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The thin film transistor causes the data signal of the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. To this end, the thin film transistor has a gate electrode 106, a source electrode 108, a drain electrode 110 and an active layer 114.

The gate electrode 106 has a plurality of gate electrodes included in the gate line 102. In the present invention, two gate electrodes, that is, first and second gate electrodes 106A and 106B will be described as an example.

The first gate electrode 106A overlaps the first channel region 114A of the active layer and the second gate electrode 106B overlaps the second channel region 114B of the active layer. Since the first and second gate electrodes 106A and 106B are formed in series, the first and second channel regions 114A and 114B are formed between the source region and the drain region 114S and 114D. As a result, the total length of the channel regions 114A and 114B of the thin film transistor becomes longer, so that the distance between the source electrode 108 connected to the source region 114S and the drain electrode 110 connected to the drain region 114D The resistance increases. Accordingly, the off current can be lowered when the thin film transistor having a plurality of gate electrodes (i.e., a plurality of channel regions) is turned off.

The source electrode 108 is connected to the data line 104 and is connected to the source region 114S of the active layer through the interlayer insulating film 116 and the source contact hole 124S penetrating the gate insulating film 112. [

The drain electrode 110 faces the source electrode 108 and is connected to the drain region 114D of the active layer through the interlayer insulating film 116 and the drain contact hole 124D penetrating the gate insulating film 112. [ The drain electrode 110 is connected to the pixel electrode 122 through the pixel contact hole 120 passing through the first and second protective films 118 and 128.

The active layer 114 forms a channel between the source electrode 108 and the drain electrode 110. The active layer 114 may be formed in the form of a "U" character or a reverse "U" character on the buffer film 126 as shown in FIG. 1, or may be formed in another form. The active layer 114 includes first and second channel regions 114A and 114B, a common region 114C, a source region 114S, and a drain region 114D.

The first channel region 114A overlaps the first gate electrode 106A with the gate insulating film 112 interposed therebetween and the second channel region 114B overlaps the second gate electrode 106A with the gate insulating film 112 interposed therebetween. 106B. A common region 114C is formed between the first and second channel regions 114A and 114B, and an n-type or p-type impurity is implanted. The source region 114S is implanted with n-type or p-type impurity, and is connected to the source electrode 108 through the source contact hole 124S. The drain region 114D is implanted with an n-type or p-type impurity, and is connected to the drain electrode 110 through the drain contact hole 124D, respectively. The same or different impurities may be implanted into the source region 114S, the drain region 114D, and the common region 114C at the same or different concentrations with respect to each other. However, when the same impurity is implanted into the source region 114S, the drain region 114D, and the common region 114C at the same concentration, an increase in the number of mask processes can be prevented.

The buffer film 126 is formed as a single layer or a multilayer structure of silicon oxide or silicon nitride on a substrate 101 formed of a plastic resin such as glass or polyimide (PI) or the like. The buffer layer 126 serves to prevent the diffusion of moisture or impurities generated in the substrate 101 and to control the transfer rate of heat during crystallization so that the crystallization of the active layer 114 can be performed well. The buffer layer 126 is formed to cover the light blocking pattern 130 formed on the substrate 101 and is formed to have a thickness of 0.1 mu m to several mu m to obtain the diffraction effect and the transmittance improving effect of the light blocking pattern 130 .

The light blocking pattern 130 is formed to be spaced apart from the adjacent light blocking pattern 130 with a fine slit 132 interposed therebetween. These light blocking patterns 130 are arranged on the substrate 101 at equal intervals so as to overlap with the first and second channel regions 114A and 114B. The light blocking pattern 130 is formed of an opaque metal such as Mo, Ti, Al, Cu, Cr, Co, W, Ta, or Ni. In particular, the light blocking pattern 130 is formed of a material having good heat resistance capable of withstanding a high temperature thermal process applied when forming a plurality of thin films formed on the light blocking pattern 130.

The light shielding pattern 130 is formed in the stripe shape shown in Figs. 1 and 3A, the dot shape shown in Figs. 3B to 3E, or the plate shape shown in Fig. 3F.

That is, the stripe-shaped light blocking pattern 130 is formed parallel to the gate line 102 as shown in FIG. 1 or perpendicular to the gate line 102 as shown in FIG. 3A. The stripe-shaped light intercepting patterns 130 are formed to be spaced apart from each other with the slit 132 in the form of a stripe therebetween.

The light blocking pattern 130 in the form of a dot is formed in a polygonal or elliptical shape such as a square or rhombus, as shown in Figs. 3B to 3E. The light blocking pattern 130 may be arranged in parallel with the light blocking pattern 130 adjacent to the upper, lower, left, and right sides as shown in FIGS. 3B and 3C, or may be arranged in the next row (or column) And the light blocking patterns 130 located in the light blocking patterns 130. The dot-shaped light blocking patterns 130 are formed to be spaced apart from each other with the lattice-shaped slit 132 therebetween.

The plate-shaped light shielding pattern 130 is formed to have a plurality of polygonal or elliptical slits 132 as shown in FIG. 3F.

Since the light blocking pattern 130 absorbs or reflects the light emitted from the backlight unit (not shown) and incident on the first and second channel regions 114A and 114B, the first and second channel regions 114A , And 114B can be minimized. As a result, the light leakage current can be reduced, so that the off current can be maintained at a level that does not cause any abnormality in the screen driving.

The light incident on the slit 132 located between the light blocking patterns 130 is diffracted without going straight as it is and spreads out to regions other than the first and second channel regions 114A and 114B, The light reaching the second channel regions 114A and 114B decreases. 4, the light passing through the center of the slit 132 having the length Dx and the width Dy formed in the light blocking pattern 130 is larger than the width Dy of the slit 132 It is a phenomenon that spreads by θy. As described above, the light that has passed through the slit 132 due to the diffraction phenomenon is guided to a region other than the first and second channel regions 114A and 114B, thereby improving the transmittance using the induced light. That is, as shown in FIGS. 5A and 5B, the black matrix 152 formed on the upper substrate 111 positioned in the traveling direction of light led to the regions other than the first and second channel regions 114A and 114B Remove. Particularly, the common region 114C overlapping the pixel electrode 122 is adjacent to the drain region 114D and removes the black matrix 152 located above the common region 114C adjacent to the drain region 114D . In this case, the common region 114C adjacent to the source region 114S overlaps with the black matrix 152, and the common region 114C adjacent to the drain region 114D overlaps with the color filter 154. [ Thus, the light guided to the regions other than the first and second channel regions 114A and 114B exits to the outside through the color filter 154 overlapping with the common region 114C adjacent to the drain region 114D The transmittance can be improved and the power consumption can be reduced.

FIG. 6 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a thin film transistor substrate taken along line II-II '' in FIG.

The thin film transistor substrate shown in FIGS. 6 and 7 is different from the thin film transistor substrate according to the first embodiment in that the light blocking patterns 140 and 144 formed in the first and second channel regions 114A and 114B, respectively, Except that they are formed in different shapes. Accordingly, detailed description of the same constituent elements will be omitted.

The light blocking pattern includes a first light blocking pattern 140 formed on the substrate 101 so as to overlap with the first channel region 114A and a second light blocking pattern 140 formed on the substrate 101 to overlap the second channel region 114B. And a light shielding pattern 144. The first and second light shielding patterns 140 and 144 are formed of opaque metals such as Mo, Al, Cu, Cr, Co, W, Ta and Ni.

The first light blocking pattern 140 is formed in the form of a slit-free plate and completely overlaps with the first channel region 114A. Here, the first channel region 114A is formed adjacent to the source region 114S. The light incident on the first channel region 114A can be blocked by the first light blocking pattern 140, thereby reducing the light leakage current.

The second light intercepting pattern 144 is formed to be spaced apart from the adjacent second light intercepting pattern 144 at equal intervals with a fine slit 142 interposed therebetween. The second light blocking pattern 144 is formed in the stripe shape shown in Figs. 1 and 3A, the dot shape shown in Figs. 3B to 3E, or the plate shape shown in Fig. 3F as described above.

The light incident on the slit 142 located between the second light blocking patterns 144 is diffracted without going straight as it is and spreads to the region other than the second channel region 114B, The increase of the off current due to the photoelectric effect can be prevented. Further, since the light having passed through the slit 144 due to the diffraction phenomenon is guided to a region other than the second channel region 114B, the transmitted light is used to improve the transmittance. That is, as shown in FIGS. 8A and 8B, the black matrix 152 formed on the upper substrate 111 positioned in the traveling direction of light led to the region other than the second channel region 114B is removed. Particularly, the common region 114C overlapping the pixel electrode 122 is adjacent to the drain region 114D and removes the black matrix 152 located above the common region 114C adjacent to the drain region 114D . In this case, the common region 114C adjacent to the source region 114S overlaps with the black matrix 152, and the common region 114C adjacent to the drain region 114D overlaps with the color filter 154. [ Accordingly, the light guided to the regions other than the second channel regions 114A and 114B is emitted to the outside through the color filter 154 overlapping the common region 114C adjacent to the drain region 114D, And the power consumption can be reduced.

FIGS. 9A to 9I are cross-sectional views illustrating a method of manufacturing the liquid crystal display panel shown in FIG.

Referring to FIG. 9A, light blocking patterns 140 and 144 are formed on a lower substrate 101.

Specifically, an opaque metal layer is formed on the lower substrate 101 through a deposition process. Then, the opaque metal layer is patterned through the photolithography process and the etching process, thereby forming the light shielding patterns 140 and 144.

Referring to FIG. 9B, a buffer layer 126 is formed on a lower substrate 101 on which light blocking patterns 140 and 144 are formed, and an active layer 114 is formed thereon.

Specifically, a buffer film 126 and an amorphous silicon thin film are formed on a lower substrate 101 on which light blocking patterns 140 and 144 are formed by a method such as LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) . Then, the amorphous silicon thin film is crystallized to form a polysilicon thin film. Then, the active layer 114 is formed by patterning the polysilicon thin film by a photolithography process and an etching process.

9C, a gate insulating film 112 is formed on a buffer film 126 on which an active layer 114 is formed, and a gate line 102 (including a first gate electrode 106A and a second gate electrode 106B) Is formed.

Specifically, a gate insulating film 112 is formed on the buffer film 126 on which the active layer 114 is formed, and a gate metal layer is formed thereon by a deposition method such as sputtering. As the gate insulating film 112, an inorganic insulating material such as SiOx, SiNx, or the like is used. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof may be used as a single layer, or may be used as a multi-layer structure by using them. Then, the gate line 102 including the first and second gate electrodes 106A and 106B is formed on the gate insulating film 112 by patterning the gate metal layer through the photolithography process and the etching process.

The n + -type or p + -type impurity is implanted into the active layer 114 using the first and second gate electrodes 106A and 106B as masks to form the common region 114C and the source region 114S of the active layer 114 And a drain region 114D are formed.

9D, a source contact hole 124S and a drain contact hole 124D are formed on the gate insulating film 112 on which the gate line 102 including the first and second gate electrodes 106A and 106B is formed An interlayer insulating film 116 is formed.

Specifically, an interlayer insulating film 116 is formed on the gate insulating film 112 on which the gate line 102 is formed by a method such as PECVD. Then, the interlayer insulating film 116 and the gate insulating film 112 are patterned through a photolithography process and an etching process, thereby forming a source contact hole 124S and a drain contact hole 124D. The source contact hole 124S exposes the source region 114S through the interlayer insulating film 116 and the gate insulating film 112 and the drain contact hole 124D exposes the interlayer insulating film 116 and the gate insulating film 112, To expose the drain region 114D.

Referring to FIG. 9E, a source electrode 108, a drain electrode 110, and a data line 104 are formed on an interlayer insulating film 116.

Specifically, a data metal layer is formed on an interlayer insulating film 116 having a source contact hole 124S and a drain contact hole 124D by an evaporation method such as sputtering. As the data metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof may be used as a single layer, or may be used as a multi-layer structure by using them. Then, the source electrode 108, the drain electrode 110, and the data line 104 are formed on the interlayer insulating film 116 by patterning the data metal layer through the photolithography process and the etching process.

9F, a first protective film 118 is formed on an interlayer insulating film 116 on which a source electrode 108, a drain electrode 110 and a data line 104 are formed, and a common electrode 136 is formed thereon .

Specifically, on the interlayer insulating film 116 on which the source electrode 108, the drain electrode 110 and the data line 104 are formed, a photoacid or the like is formed by spin coating or spinless coating. A first protective film 118 of the same organic insulating material is formed, and a transparent metal layer is formed thereon by a vapor deposition method such as sputtering. Then, the transparent electrode layer is patterned through the photolithography process and the etching process, thereby forming the common electrode 136 having the opening portion 134.

Referring to FIG. 9G, a second passivation layer 128 having a pixel contact hole 120 is formed on a first passivation layer 118 having a common electrode 136 formed thereon.

Specifically, a second protective film 128 of an organic insulating material or an inorganic insulating material is formed on the first protective film 118 on which the common electrode 134 is formed. Then, the second protective film 128 is patterned through the photolithography process and the etching process, thereby forming the pixel contact hole 120. Here, the pixel contact hole 120 exposes the drain electrode 110 through the first and second protective films 118 and 128.

Referring to FIG. 9H, a pixel electrode 122 is formed on a second passivation layer 128 having a pixel contact hole 120.

Specifically, a transparent metal layer is formed on the second protective film 128 having the pixel contact hole 120 by a vapor deposition method such as sputtering. Then, the transparent electrode layer is patterned through the photolithography process and the etching process, thereby forming the pixel electrode 122. [

Referring to FIG. 9I, a liquid crystal display panel is completed by adhering a thin film transistor substrate on which a pixel electrode 122 is formed and a color filter substrate prepared by a separate process using a sealant (not shown). Here, the color filter substrate is completed by sequentially stacking a black matrix 152 and a color filter 154 on the upper substrate 111.

Meanwhile, although the present invention has been described by taking a fringe field type liquid crystal display panel as an example, the present invention is applicable to all liquid crystal display panels such as a vertical electric field type and a horizontal electric field type.

In addition, although the light blocking pattern according to the present invention is applied to a liquid crystal display panel, the present invention is applicable to all flat panel display panels including thin film transistors as well as organic light emitting display panels including thin film transistors.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

114: active layer 122: pixel electrode
130, 140. 144: light blocking pattern 132, 142: slit
136: common electrode 152: black matrix
154: Color filter

Claims (11)

A gate line and a data line formed on the substrate so as to intersect with each other to form a pixel region;
An active layer formed at an intersection of the gate line and the data line and having a source region, a drain region and a plurality of channel regions, a gate electrode overlapping the plurality of channel regions, a source electrode overlapping the source region of the active layer, A thin film transistor including a drain electrode overlapping a drain region of the active layer;
A pixel electrode connected to the thin film transistor;
And a light blocking pattern formed on the substrate so as to be positioned below the active layer and overlapping each of the plurality of channel regions,
Wherein the light blocking patterns overlapping the channel region adjacent to the drain region among the plurality of channel regions are spaced apart from each other with the slit interposed therebetween. The method according to claim 1,
Wherein the light blocking patterns overlapping the channel region adjacent to the source region are spaced apart from each other with the slit interposed therebetween. 3. The method of claim 2,
The light blocking patterns may be formed in a stripe shape parallel to or perpendicular to the gate lines,
The light blocking patterns may be formed in a dot shape spaced apart by the slits in a lattice form,
Wherein the light blocking patterns are formed in the form of a plate having slits in the form of stripes or dots. The method according to claim 1,
Wherein the light blocking patterns overlapping the channel region adjacent to the source region are formed in a plate shape without the slit. The method according to claim 1,
Wherein the active layer has a common region formed between the source region, the drain region, the first and second channel regions, and the first and second channel regions. A color filter substrate having a black matrix and a color filter;
And a thin film transistor substrate facing the color filter substrate and the liquid crystal therebetween,
The thin film transistor substrate
A gate line and a data line formed on the substrate so as to intersect with each other to form a pixel region;
An active layer formed at an intersection of the gate line and the data line and having a source region, a drain region and a plurality of channel regions, a gate electrode overlapping the plurality of channel regions, a source electrode overlapping the source region of the active layer, A thin film transistor including a drain electrode overlapping a drain region of the active layer;
A pixel electrode connected to the thin film transistor;
A common electrode which forms an electric field with the pixel electrode;
And a light blocking pattern formed on the substrate so as to be positioned below the active layer and overlapping each of the plurality of channel regions,
Wherein the light blocking patterns overlapping the channel region adjacent to the drain region among the plurality of channel regions are spaced apart from each other with the slit interposed therebetween. The method according to claim 6,
Wherein the active layer has a common region formed between the source region, the drain region, the first and second channel regions, and the first and second channel regions,
Wherein the common region adjacent to the source region overlaps with the black matrix,
And the common region adjacent to the drain region overlaps the color filter. Providing a thin film transistor substrate, a color filter substrate having a black matrix and a color filter, respectively;
And bonding a color filter substrate having a black matrix and a color filter to the thin film transistor substrate,
The step of providing the thin film transistor substrate
Forming a light blocking pattern on the substrate;
Forming a buffer layer to cover the light blocking pattern;
An active layer having a source region, a drain region, a common region, and a plurality of channel regions overlapping the light blocking pattern, a gate electrode overlapping the plurality of channel regions, a source electrode overlapping a source region of the active layer, Forming a thin film transistor on the buffer layer, the thin film transistor including a drain electrode overlapping a drain region of the active layer;
Forming a pixel electrode connected to the thin film transistor;
And forming a common electrode that forms an electric field with the pixel electrode,
Wherein the light blocking patterns overlapping the channel region adjacent to the drain region among the plurality of channel regions are spaced apart from each other with the slit interposed therebetween. 9. The method of claim 8,
The step of forming the light blocking pattern on the substrate
And forming the light blocking patterns overlapping the channel region adjacent to the source region to be spaced apart from each other with the slit interposed therebetween. 9. The method of claim 8,
The step of forming the light blocking pattern on the substrate
Wherein the light blocking patterns overlapping the channel region adjacent to the source region are formed in a plate shape without the slit. 9. The method of claim 8,
The step of providing the color filter substrate
Forming the black matrix so as to overlap with the common region adjacent to the source region;
And forming the color filter so as to overlap the common region adjacent to the drain region.

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