KR20120133130A - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A fringe field switching liquid crystal display device and a method for fabricating the same are provided to form a common electrode and a black matrix on an array panel by a half-tone exposure process. CONSTITUTION: A gate line(116) and a data line(117) are formed. A thin film transistor is formed. A common electrode(108) is formed in a pixel portion of a first substrate by using a half tone mask. A black matrix(106) is formed on the common electrode. A passivation film is formed on the first substrate. A pixel electrode(118) is formed on the first substrate. The first substrate is attached to the second substrate.

Description

Fringe field type liquid crystal display device and manufacturing method therefor {FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a fringe field type liquid crystal display device and a method for manufacturing the same, and more particularly, to a fringe field type liquid crystal display device and a method for manufacturing the same that can realize a high resolution and a wide viewing angle.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

Hereinafter, a general liquid crystal display device will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.

As shown in the figure, a general liquid crystal display device is largely a color filter substrate 5 and an array substrate 10 and a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix (BM) 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common that applies a voltage to the liquid crystal layer 30. It consists of an electrode 8.

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a panel, and the color filter substrate 5 And the bonding of the array substrate 10 is made through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules oriented horizontally with the substrate are oriented almost perpendicular to the substrate when a voltage is applied to the panel.

Accordingly, there is an In Plane Switching (IPS) type liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve the viewing angle to 170 degrees or more.

FIG. 2 is a cross-sectional view of a portion of a transverse electric field type liquid crystal display device, in which a fringe field formed between a pixel electrode and a common electrode penetrates a slit to drive liquid crystal molecules positioned on a pixel region and a common electrode to implement an image A portion of a fringe field switching (FFS) liquid crystal display is schematically shown.

In the fringe field type liquid crystal display, the liquid crystal molecules are horizontally aligned, and as the common electrode is formed at the bottom and the pixel electrode is formed at the top, an electric field is generated in the horizontal and vertical directions so that the liquid crystal molecules are twisted. It is tilted and driven.

As shown in the drawing, a gate line (not shown) and a data line 17 are arranged in the array substrate 10 of a typical fringe field type liquid crystal display device to be vertically and horizontally arranged on the transparent array substrate 10 to define a pixel area. And a thin film transistor, which is a switching element, is formed in an intersection region of the gate line and the data line 17.

The thin film transistor includes a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor is formed by the gate insulating film 15a for insulation between the gate electrode 21 and the source / drain electrodes 22 and 23 and the gate electrode supplied by the gate voltage supplied to the gate electrode 21. An active layer 24 is formed between the 22 and the drain electrode 23 to form a conductive channel.

In this case, the source / drain regions of the active layer 24 form ohmic contacts with the source / drain electrodes 22 and 23 through an ohmic contact layer 25n.

The common electrode 8 and the pixel electrode 18 are formed in the pixel region, wherein the box-shaped pixel electrode 18 is formed together with the common electrode 8 to generate a fringe field. 18, a plurality of slits 18s are included.

In this case, the pixel electrode 18 is electrically connected to the drain electrode 23 through contact holes formed in the first passivation layer 15b, the second passivation layer 15c, and the third passivation layer 15d.

The array substrate 10 configured as described above is bonded to the color filter substrate 5 by sealants (not shown) formed on the outer side of the image display area in a state where a constant cell gap is maintained by the column spacer 50. In this case, the color filter substrate 5 includes a BM 6 which prevents light from leaking to the thin film transistor, the gate line, and the data line 17, and a sub-color filter 7 that implements red, green, and blue colors. The color filter and the overcoat layer 9 which consist of) are formed.

The fringe field type liquid crystal display device has a wide viewing angle, and when the common electrode is formed on the data line, the BM area can be reduced and the aperture ratio is improved.

However, in the case of forming the resin BM using negative photo acryl to realize high resolution, there is a limit in resolution due to the use of a proximity type exposure machine, unlike the array process. Accordingly, the BM having a line width of 10 μm or less is limited. There are disadvantages in that it is difficult to secure the characteristics. In addition, the photolithography process is increased compared to the general transverse electric field type liquid crystal display, and thus there is a problem in that productivity is lowered.

The present invention is to solve the above problems, in the fringe field type liquid crystal display device for realizing high resolution and wide viewing angle, the fringe field to simplify the process and to secure the characteristics of the BM of line width of less than 10㎛ A liquid crystal display device and a method of manufacturing the same are provided.

Other objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the fringe field type liquid crystal display device of the present invention comprises: a first substrate including a pixel portion; A gate line and a data line crossing the pixel portion of the first substrate to define a pixel region; A thin film transistor formed at an intersection of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, and a source / drain electrode; A common electrode formed in a single pattern over the entire pixel portion of the first substrate; A black matrix formed on the common electrode above the thin film transistor, the gate line, and the data line to prevent light leakage from the thin film transistor, the gate line, and the data line; A protective film formed on the first substrate on which the black matrix is formed; A pixel electrode formed on the first substrate on which the passivation layer is formed, having a box shape in the pixel region, and having a plurality of slits in each pixel region; And a second substrate bonded to face the first substrate.

A method of manufacturing a fringe field type liquid crystal display device according to the present invention comprises the steps of: providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate line and a data line crossing the pixel portion of the first substrate to define a pixel area; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a common electrode on the pixel portion of the first substrate by using a half-tone mask in one mask process, and forming a black matrix on the thin film transistor and the common electrode on the gate line and the data line; Forming a protective film on the first substrate on which the black matrix is formed; Forming a pixel electrode on the first substrate on which the passivation layer is formed, the pixel electrode having a box shape in the pixel region and having a plurality of slits in each pixel region; And bonding the first substrate and the second substrate to each other.

The forming of the thin film transistor, the gate line, and the data line in the pixel portion of the first substrate may include forming a gate electrode and a gate line in the pixel portion of the first substrate; Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active layer on the gate electrode on which the gate insulating film is formed; Forming a source electrode and a drain electrode on the active layer of the first substrate on which the active layer is formed, and forming a data line crossing the gate line to define a pixel region; And forming a first passivation layer and a second passivation layer on the first substrate on which the source electrode, the drain electrode, and the data line are formed.

In this case, when the gate electrode and the gate line to form the pixel portion of the first substrate, the gate pad portion of the first substrate further comprises the step of forming a gate pad line.

The method may further include forming a data pad line on the data pad of the first substrate when the source electrode, the drain electrode, and the data line are formed on the pixel portion of the first substrate.

In this case, the first protective layer and the second protective layer may be selectively removed to form a first contact hole exposing the drain electrode, and a second contact hole and a third contact exposing the data pad line and the gate pad line, respectively. And forming a hole.

In this case, when the common electrode and the black matrix are formed on the first substrate, the data pad line and the gate pad portion are electrically connected to the data pad line and the gate pad line through the second contact hole and the third contact hole, respectively. The method may further include forming a data pad line pattern and a gate pad line pattern to be connected to each other.

In this case, a third passivation layer may be formed on the first substrate on which the black matrix is formed.

In this case, the fourth passivation layer may be selectively removed to form a fourth contact hole exposing the drain electrode, and the fifth contact hole and the sixth contact hole exposing the data pad line pattern and the gate pad line pattern, respectively. It characterized in that it further comprises the step of forming.

In this case, when the pixel electrode is formed in the pixel region of the first substrate, the data pad electrode and the gate pad electrode electrically connected to the data pad line pattern and the gate pad line pattern, respectively, It characterized in that it further comprises the step of forming.

The first passivation layer may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide layer (SiO ₂ ), and the second passivation layer may be formed of an organic insulating layer such as photoacrylic.

The common electrode may be formed of a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this case, the black matrix is a copper alloy, such as aluminum (Al), copper (Cu), copper nitride (CuNx), molybdenum (Mo) and molybdenum titanium (MoTi) having a low reflection effect when used as a double layer with the ITO or IZO And an opaque conductive material such as molybdenum alloy).

The common electrode may be formed in a single pattern over the entire pixel portion except for the contact region between the drain electrode and the pixel electrode of the thin film transistor.

And forming a color filter formed of a sub-color filter implementing red, green, and blue colors on the second substrate, and forming an overcoat layer on the color filter.

As described above, the fringe field type liquid crystal display according to the present invention and a method of manufacturing the same are formed by forming a black matrix (BM) together with a common electrode on an array substrate by using half-tone exposure. Omission of the photolithography process provides the effect of reducing the manufacturing cost.

The fringe field type liquid crystal display device and the manufacturing method thereof according to the present invention provide an effect of improving the yield as the BM formation of a line width of 10 μm or less is facilitated and improving the performance as the resistance of the common electrode is improved. .

1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display device.
2 is a cross-sectional view schematically showing a part of a typical fringe field type liquid crystal display device.
3 is a cross-sectional view schematically illustrating a part of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention.
4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention.
6A to 6G are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.
7A to 7G are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 5.
8A to 8F are cross-sectional views illustrating the fifth mask process shown in FIGS. 6E and 7E in detail.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the fringe field type liquid crystal display device and a method of manufacturing the same.

3 is a cross-sectional view schematically illustrating a portion of a fringe field type liquid crystal display according to an exemplary embodiment of the present invention, in which a fringe field formed between the pixel electrode and the common electrode is positioned on the pixel region and the pixel electrode through the slit. A portion of a fringe field type liquid crystal display device which realizes an image by driving liquid crystal molecules is shown.

4 is a plan view schematically illustrating a part of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 5 is a part of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention. It is sectional drawing which shows schematically.

In this case, for convenience of description, one pixel including a pixel unit, a data pad unit, and a gate pad unit is illustrated. In an actual LCD device, N gate lines and M data lines intersect to form MxN pixels. Although present, one pixel is shown in the drawing for simplicity of explanation.

As shown in the drawings, an array substrate 110 according to an embodiment of the present invention includes a gate line 116 and a data line 117 arranged vertically and horizontally on the array substrate 110 to define a pixel area. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117, and a common electrode 108 and a plurality of common electrodes 108 driving a liquid crystal molecule by generating a fringe field in the pixel region. A pixel electrode 118 having a slit 118s of is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. The thin film transistor may further include a gate voltage supplied to the gate insulating film 115a and the gate electrode 121 for insulation between the gate electrode 121 and the source / drain electrodes 122 and 123. The active layer 124 forms a conductive channel between the source electrode 122 and the drain electrode 123.

In this case, the source / drain regions of the active layer 124 form ohmic contacts with the source / drain electrodes 122 and 123 through the ohmic contact layer 125n.

A portion of the source electrode 122 extends in one direction to be connected to the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to extend the first passivation layer 115b and the second passivation layer. The pixel electrode 118 is electrically connected to the pixel electrode 118 through the first contact hole 140a and the fourth contact hole 140d formed in the 115c and the third passivation layer 115d.

As described above, the common electrode 108 and the pixel electrode 118 are formed in the pixel region to generate a fringe field, wherein the common electrode 108 is the drain electrode 123 and the pixel electrode 118. The pixel electrode 118 is formed in a single pattern over the entire pixel portion except for the contact region between the pixels, and has a plurality of slits 118s in each pixel region. It is characterized by being formed.

In addition, the fringe field type liquid crystal display according to the exemplary embodiment of the present invention includes the thin film transistors and the gate lines 116 and the thin film transistors to prevent light leakage from the thin film transistors, the gate lines 116, and the data lines 117. The BM 106 is formed of an opaque metal material on the common electrode 108 on the data line 117, wherein the array substrate is formed together with the common electrode 108 by using half-tone exposure. By forming the BM 106 in the 110, it is characterized in that one photolithography step can be omitted.

In addition, as the BM 106 is formed on the lower array substrate 110 as described above, it is not necessary to consider the alignment margin with the array substrate 110, thereby reducing the line width, and as a result, the opening ratio (˜52.13%). ) Is improved. In addition, since the BM 106 is formed on the lower array substrate 110, a projection type exposure machine may be used instead of the conventional proximity type exposure machine, so that the BM 106 having a line width of 10 μm or less may be easily formed. As a result, the yield is improved.

In other words, the high-resolution fringe field type liquid crystal display device has an additional process compared to the conventional transverse electric field type liquid crystal display device, so it is incompatible with the existing process and has a narrow line width process necessary for coping with high resolution. There was a problem with the yield. However, the present invention can simplify the process by incorporating a conventional resin BM process using a negative photo acrylic into the electrode forming process of the lower array substrate, in particular, the common electrode is a simple pattern and formed on the entire surface of the array substrate Therefore, when half-tone exposure is used, it is possible to form a superimposed pattern of dissimilar metals, and thus, BM can be formed of dissimilar metal materials having low reflectivity such as MoTi and CuNx on ITO (Indium Tin Oxide). .

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

In this case, the data pad line 117p is electrically connected to the data pad line pattern 117p 'through a second contact hole (not shown), and the data pad line pattern 117p' is connected to the fifth contact hole 140e. Is electrically connected to the data pad electrode 127p. In addition, the gate pad line 116p is electrically connected to the gate pad line pattern 116p 'through a third contact hole (not shown), and the gate pad line pattern 116p' is the sixth contact hole 140f. Is electrically connected to the gate pad electrode 126p through

As illustrated in FIG. 3, the array substrate 110 configured as described above is a color filter substrate formed by a sealant (not shown) formed at an outside of the image display area in a state where a constant cell gap is maintained by the column spacer 150. Opposite to the 105, wherein the color filter substrate 105 is formed with a color filter and an overcoat layer 109 made of a sub-color filter 107 for implementing red, green and blue colors. .

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

6A to 6G are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A through 7G are cross-sectional views sequentially illustrating a process of manufacturing the array substrate illustrated in FIG. 5, and a process of manufacturing an array substrate of a pixel portion is shown on the left side, and an array substrate of a data pad portion and a gate pad portion are sequentially formed on the right side. The manufacturing process is shown.

6A and 7A, a gate electrode 121 and a gate line 116 are formed in a pixel portion of the array substrate 110 made of a transparent insulating material such as glass, and the array substrate 110 may be formed. A gate pad line 116p is formed in the gate pad portion.

In this case, the gate electrode 121, the gate line 116, and the gate pad line 116p are selectively deposited through a photolithography process (first mask process) after depositing a first conductive layer on the entire surface of the array substrate 110. It is formed by patterning.

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum It may be formed of a low resistance opaque conductive material such as an alloy. The first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIGS. 6B and 7B, the gate insulating layer 115a and the amorphous silicon are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the gate pad line 116p are formed. A thin film and an n + amorphous silicon thin film are formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 124 made of the amorphous silicon thin film on the pixel portion of the array substrate 110. do.

In this case, the n + amorphous silicon thin film pattern 125 is formed on the active layer 124 and patterned in substantially the same shape as the active layer 124.

Next, as illustrated in FIGS. 6C and 7C, a second conductive layer is formed on the entire surface of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern 125 are formed. In this case, the second conductive layer may be formed of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line. The second conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the second conductive film are selectively removed through a photolithography process (third mask process), so that the source electrode 122 and the drain electrode formed of the second conductive film on the active layer 124. 123 is formed.

In this case, a data line 117 made of the second conductive layer is formed in the data line region of the array substrate 110 through the third mask process, and the second data pad portion of the array substrate 110 is formed. A data pad line 117p made of a conductive film is formed.

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active layer 124 and ohmic contact between the source / drain region of the active layer 124 and the source / drain electrodes 122 and 123. 125n is formed.

6D and 7D, the first passivation layer 115b is formed on the entire surface of the array substrate 110 on which the source / drain electrodes 122 and 123, the data line 117, and the data pad line 117p are formed. ) And the second passivation film 115c are formed.

In this case, the first passivation layer 115b may be formed of an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiO ₂ ), and the second passivation layer 115c may be formed of an organic insulating layer such as photoacryl. have.

Thereafter, the first contact hole 140a exposing a part of the drain electrode 123 by selectively removing the first passivation layer 115b and the second passivation layer 115c through a photolithography process (a fourth mask process). The second contact hole 140b and the third contact hole 140b which exposes a portion of the data pad line 117p and the gate pad line 116p, respectively, are formed in the data pad portion and the gate pad portion of the array substrate 110. The contact hole 140c is formed.

Next, as shown in FIGS. 6E and 7E, after the third conductive film and the fourth conductive film are sequentially formed on the entire surface of the array substrate 110 on which the second protective film 115c is formed, a photolithography process is performed. By selectively removing the same through a five mask process to form a common electrode 108 formed of the third conductive layer on the pixel portion of the array substrate 110, while the thin film transistor, the gate line 116, and the data line 117 are formed. The BM 106 formed of the fourth conductive layer is formed on the common electrode 108.

In addition, the data pad line pattern 117p 'and the gate pad line pattern 116p' formed of the third conductive layer are respectively formed in the data pad portion and the gate pad portion of the array substrate 110 through the fifth mask process. To form.

At this time, the common electrode 108, the data pad line pattern 117p ', the gate pad line pattern 116p' and the BM 106 can be formed through a single mask process by using half-tone exposure. This will be described in detail with reference to the following drawings.

8A to 8F are cross-sectional views illustrating the fifth mask process illustrated in FIGS. 6E and 7E in detail.

As shown in FIG. 8A, the third conductive layer 130 and the fourth conductive layer 140 are sequentially formed on the entire surface of the array substrate 110 on which the second protective layer 115c is formed.

In this case, the third conductive layer 130 may be formed of indium tin oxide (ITO) or indium zinc oxide (Indium Zinc Oxide) to form a common electrode, a data pad line pattern, and a gate pad line pattern. It can be formed of a transparent conductive material having excellent transmittance such as IZO). In addition, the fourth conductive layer 140 is a heterogeneous metal material with the third conductive layer 130. When used as the double layer with the ITO, copper, such as aluminum, copper, and copper nitride (CuNx), has a low reflection effect. It may be formed of an opaque conductive material such as an alloy, molybdenum and molybdenum alloys such as molybdenum titanium (MoTi).

As shown in FIG. 8B, the photosensitive film 160 made of a photosensitive material such as photoresist is formed on the array substrate 110 on which the fourth conductive film 140 is formed, and then, according to an embodiment of the present invention. Light is selectively irradiated to the photosensitive film 160 through the tone mask 170.

In this case, the half-tone mask 170 includes a first transmission region I for transmitting all of the irradiated light, a second transmission region II for transmitting only a portion of the light, and a part of blocking the light, and blocking all the irradiated light. The region III is provided, and only the light passing through the half-tone mask 170 is irradiated to the photosensitive film 160.

Subsequently, after developing the photoresist layer 160 exposed through the half-tone mask 170, as shown in FIG. 8C, light passes through the blocking region III and the second transmission region II. The first photoresist pattern 160a to the fourth photoresist pattern 160d having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist is completely removed in the first transmission region I through which all the light is transmitted. The surface of the fourth conductive layer 140 is exposed.

In this case, the first photoresist pattern 160a formed in the blocking region III is formed thicker than the second photoresist pattern 160b to the fourth photoresist pattern 160d formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use it.

Next, as shown in FIG. 8D, partial regions of the third conductive film and the fourth conductive film formed below the first photosensitive film pattern 160a to the fourth photosensitive film pattern 160d formed as a mask are used as masks. When selectively removed, the common electrode 108 made of the third conductive layer is formed in the pixel portion of the array substrate 110.

In addition, a data pad line pattern 117p 'and a gate pad line pattern 116p' formed of the third conductive layer may be formed in the data pad portion and the gate pad portion of the array substrate 110, respectively.

In addition, the common electrode 108 and the data pad line pattern 117p 'and the gate pad line pattern 116p' are formed of the four conductive layers, respectively, the common electrode 108 and the data pad line pattern 117p '. And fourth conductive film patterns 140 ', 140 ", and 140'" patterned in substantially the same form as the gate pad line pattern 116p '.

In this case, the common electrode 108 has a single pattern over the entire pixel portion except for the contact region between the drain electrode 123 and the pixel electrode so that the drain electrode 123 and the pixel electrode (to be formed later) may be connected. It will be formed.

In addition, the data pad line pattern 117p 'is electrically connected to the lower data pad line 117p through the second contact hole, and the gate pad line pattern 116p' connects the third contact hole. It is electrically connected to the gate pad line 116p below.

Subsequently, when the ashing process of removing a part of the thickness of the first photoresist pattern 160a to the fourth photoresist pattern 160d is performed, as illustrated in FIG. 8E, a second portion of the second transmission region II is formed. The photoresist pattern to the fourth photoresist pattern are completely removed.

In this case, the first photoresist pattern is a fifth photoresist pattern 160a 'from which the thickness of the second photoresist pattern to the fourth photoresist pattern is removed and remains only in the region corresponding to the blocking region III.

Subsequently, as shown in FIG. 8F, when the fifth photoresist pattern 160a ′ is used as a mask and a partial region of the fourth conductive layer pattern formed under the fifth photoresist layer is selectively removed, the thin film transistor and the gate line may be removed. 116 and a BM 106 formed of the fourth conductive layer are formed on the common electrode 108 on the data line 117.

Next, as shown in FIGS. 6F and 7F, a third passivation layer 115d is formed on the entire surface of the array substrate 110 on which the BM 106 is formed.

Thereafter, the third protective layer 115d is selectively removed through a photolithography process (a sixth mask process) to form a fourth contact hole 140d exposing a part of the drain electrode 123, while the array A fifth contact hole 140e and a sixth contact hole exposing portions of the data pad line pattern 117p 'and the gate pad line pattern 116p', respectively, of the data pad portion and the gate pad portion of the substrate 110. 140f).

Next, as shown in FIGS. 6G and 7G, after forming a fifth conductive film made of a transparent conductive material on the entire surface of the array substrate 110 on which the third protective film 115d is formed, a photolithography process (seventh mask) By selectively patterning the pixel electrodes 118 having the plurality of slits 118s in the pixel region of the array substrate 110.

In this case, by selectively patterning the fifth conductive layer using the seventh mask process, the data pad portion and the gate pad portion respectively pass through the fifth contact hole 140e and the sixth contact hole 140f. The data pad electrode 127p and the gate pad electrode 126p electrically connected to the line pattern 117p 'and the gate pad line pattern 116p' are formed.

The array substrate according to the embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the color filter substrate has a color for implementing red, green, and blue colors. A filter is formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

In the fringe field type liquid crystal display device according to the embodiment of the present invention, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active layer is described as an example. However, the present invention is not limited thereto, and the present invention is not limited thereto. The same applies to polycrystalline silicon thin film transistors using thin films.

In addition, the fringe field type liquid crystal display device according to an exemplary embodiment of the present invention has been described, for example, in which a common electrode is formed at a lower portion and a pixel electrode is formed at an upper portion thereof, but the present invention is not limited thereto. It is also applicable to the case where the pixel electrode is formed and the common electrode is formed on the pixel electrode.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

106: black matrix 108: common electrode
110: array substrate 116: gate line
116p: Gate Padline 116p ': Gate Padline Pattern
117: data line 117p: data pad line
117p ': Data pad line pattern 118: Pixel electrode
118s: slit 121: gate electrode
122 source electrode 123 drain electrode
124: active layer 126: gate pad electrode
127: data pad electrode

Claims (18)

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion;
Forming a gate line and a data line crossing the pixel portion of the first substrate to define a pixel area;
Forming a thin film transistor at an intersection of the gate line and the data line;
Forming a common electrode on the pixel portion of the first substrate by using a half-tone mask in one mask process, and forming a black matrix on the thin film transistor and the common electrode on the gate line and the data line;
Forming a protective film on the first substrate on which the black matrix is formed;
Forming a pixel electrode on the first substrate on which the passivation layer is formed, the pixel electrode having a box shape in the pixel region and having a plurality of slits in each pixel region; And
A method of manufacturing a fringe field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate. The method of claim 1, wherein the forming of the thin film transistor, the gate line, and the data line in the pixel portion of the first substrate is performed.
Forming a gate electrode and a gate line on the pixel portion of the first substrate;
Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed;
Forming an active layer on the gate electrode on which the gate insulating film is formed;
Forming a source electrode and a drain electrode on the active layer of the first substrate on which the active layer is formed, and forming a data line crossing the gate line to define a pixel region; And
And forming a first passivation layer and a second passivation layer on the first substrate on which the source electrode, the drain electrode, and the data line are formed. The fringe of claim 2, further comprising forming a gate pad line on the gate pad of the first substrate when the gate electrode and the gate line are formed on the pixel portion of the first substrate. Method of manufacturing field type liquid crystal display device. The method of claim 3, further comprising forming a data pad line on the data pad of the first substrate when the source electrode, the drain electrode, and the data line are formed on the pixel portion of the first substrate. A method of manufacturing a fringe field type liquid crystal display device. The second contact hole of claim 4, wherein the first and second passivation layers are selectively removed to form a first contact hole for exposing the drain electrode, and the second contact hole for exposing the data pad line and the gate pad line, respectively. And forming a third contact hole. The data pad line and the gate pad of claim 5, wherein when the common electrode and the black matrix are formed in the first substrate, the data pad line and the gate pad portion are formed through the second contact hole and the third contact hole, respectively. And forming a data pad line pattern and a gate pad line pattern electrically connected to the line. The method of claim 6, wherein a third passivation layer is formed on the first substrate on which the black matrix is formed. The fifth contact hole and the fifth contact hole of claim 7, wherein the third passivation layer is selectively removed to form a fourth contact hole exposing the drain electrode, and the fifth contact hole exposing the data pad line pattern and the gate pad line pattern, respectively. 6. A method of manufacturing a fringe field type liquid crystal display further comprising the step of forming a contact hole. The data pad electrode of claim 8, wherein when the pixel electrode is formed in the pixel region of the first substrate, the data pad electrode and the gate pad portion are electrically connected to the data pad line pattern and the gate pad line pattern, respectively. A method of manufacturing a fringe field type liquid crystal display further comprising the step of forming a gate pad electrode. The fringe of claim 2, wherein the first passivation layer is formed of an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiO ₂ ), and the second passivation layer is formed of an organic insulating layer such as photoacrylic. Method of manufacturing field type liquid crystal display device. The method of claim 1, wherein the common electrode is formed of a transparent conductive material having excellent transmittance, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Method for manufacturing fringe field type liquid crystal display device. The method of claim 11, wherein the black matrix is a copper alloy, such as aluminum (Al), copper (Cu), copper nitride (CuNx), molybdenum (Mo) and the like having a good low reflection effect when used as the double layer with the ITO or IZO A method for manufacturing a fringe field type liquid crystal display device, which is formed of an opaque conductive material such as molybdenum alloy such as molybdenum titanium (MoTi). 2. The method of claim 1, wherein the common electrode is formed in a single pattern over the entire pixel portion except for the contact region between the drain electrode and the pixel electrode of the thin film transistor. 2. The method of claim 1, further comprising forming a color filter on the second substrate, the color filter comprising a sub-color filter implementing red, green, and blue colors, and forming an overcoat layer on the color filter. A method of manufacturing a fringe field type liquid crystal display device. A first substrate including a pixel portion;
A gate line and a data line crossing the pixel portion of the first substrate to define a pixel region;
A thin film transistor formed at an intersection of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, and a source / drain electrode;
A common electrode formed in a single pattern over the entire pixel portion of the first substrate;
A black matrix formed on the common electrode above the thin film transistor, the gate line, and the data line to prevent light leakage from the thin film transistor, the gate line, and the data line;
A protective film formed on the first substrate on which the black matrix is formed;
A pixel electrode formed on the first substrate on which the passivation layer is formed, having a box shape in the pixel region, and having a plurality of slits in each pixel region; And
A fringe field type liquid crystal display device comprising a second substrate bonded to and opposed to the first substrate. 16. The fringe field type liquid crystal display device according to claim 15, wherein the second substrate is formed with a color filter and an overcoat layer formed of sub-color filters for implementing red, green, and blue colors. The fringe of claim 15, wherein the common electrode is made of a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO). Field type liquid crystal display device. 18. The method according to claim 17, wherein the black matrix is a copper alloy such as aluminum (Al), copper (Cu), copper nitride (CuNx), molybdenum (Mo) A fringe field type liquid crystal display device comprising an opaque conductive material such as a molybdenum alloy such as molybdenum titanium (MoTi).

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