KR20110012111A - Method of fabricating in plane switching mode liquid crystal display device - Google Patents

Abstract

In the method of manufacturing an In-Plane Switching (IPS) liquid crystal display device according to the present invention, the H-horizontal (IP) liquid crystal display device having an internal electrode arranged in a direction parallel to the gate line includes a half-tone mask ( A gate wiring and a common electrode formed of a heterogeneous conductive film are formed using a first mask, an active pattern and a data wiring are formed using a half-tone mask (second mask), and a half-tone mask (third mask). And the number of masks can be reduced by forming a pixel electrode, a pad electrode, and a protective film by using a lift-off process, thereby simplifying a manufacturing process and reducing manufacturing costs.

In particular, a method of manufacturing a liquid crystal display according to the present invention forms common wiring using indium-tin-oxide (ITO) or molybdenum titanium (MoTi), and finely forms a pixel electrode using the lift-off process to thereby transmittance. In addition, the voltage rise of the common wiring can be suppressed and the voltage can be suppressed.

Transverse electric field method, common electrode, pixel electrode, half-tone mask, lift-off, transmittance

Description

Manufacturing method of transverse electric field type liquid crystal display device {METHOD OF FABRICATING IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a method of manufacturing a transverse electric field liquid crystal display device, and more particularly, to a transverse electric field liquid crystal device capable of improving transmittance in an H-IPS liquid crystal display device in which internal electrodes are disposed in a direction parallel to the gate line. A method for manufacturing a display device.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 defining a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is narrow. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules aligned horizontally with the substrate are aligned in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device in which internal electrodes are arranged in a direction parallel to the gate line.

It is another object of the present invention to provide a method of manufacturing a transverse electric field type liquid crystal display device in which an array substrate including a thin film transistor is manufactured by three mask processes.

Another object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device which can improve transmittance and suppress voltage rise of a common wiring.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, a method of manufacturing a transverse electric field type liquid crystal display device of the present invention comprises the steps of providing a first substrate divided into a pixel portion, a data pad portion and a gate pad portion; Forming a common electrode formed of a first conductive layer on the pixel portion of the first substrate through a first mask process; Forming a gate electrode and a gate line formed of a second conductive layer on the pixel portion of the first substrate using the first mask process; Forming a gate electrode pattern and a gate line pattern formed of the first conductive layer under the gate electrode and the gate line using the first mask process; Forming a gate insulating film on the first substrate; Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate through a second mask process, and forming a data line crossing the gate line to define a pixel region; Forming a protective film on the first substrate; Forming a first to fifth photoresist pattern having a first thickness to a fifth photoresist pattern, a sixth photoresist pattern having a second thickness, and a seventh photoresist pattern on the passivation layer through a third mask process; Forming a first contact hole exposing a portion of the drain electrode by selectively removing a portion of the passivation layer using the first to seventh photoresist patterns as a mask; Removing portions of the first to seventh photoresist patterns to remove the sixth and seventh photoresist patterns, and simultaneously forming eighth to twelve photoresist patterns having a third thickness; Forming a transparent conductive film on the first substrate while the eighth photosensitive film pattern to the twelfth photosensitive film pattern remain; A pixel electrode electrically connected to the drain electrode through the first contact hole by removing the eighth photosensitive film pattern and the twelfth photosensitive film pattern and simultaneously removing the transparent conductive film formed on the surface of the eighth photosensitive film pattern. Forming; And bonding the first substrate and the second substrate, wherein the common electrode, the pixel electrode, and the outermost common electrode are formed in a direction parallel to the gate line.

As described above, the method of manufacturing the transverse electric field type liquid crystal display device according to the present invention provides the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost. In particular, compared to the four mask process, the five-step process can be omitted, and a process reduction effect of approximately 17% can be obtained.

In addition, the method of manufacturing a transverse electric field liquid crystal display device according to the present invention forms a common wiring by using indium-tin-oxide (ITO) or molybdenum titanium (MoTi), and finely forms a pixel electrode by using a lift-off process. By forming it, the transmittance can be improved and the voltage rise of the common wiring can be suppressed. In addition, the viewing angle and clarity can be improved by optimizing the electrode line width and angle, and the black luminance can be improved by applying the molybdenum titanium, thereby providing an effect of improving the contrast ratio.

In addition, in the method of manufacturing a transverse electric field type liquid crystal display device according to the present invention, a gate line and a common electrode are formed of a heterogeneous conductive film, and short and pattern are formed by forming the common electrode and the pixel electrode on different layers. The loss can be prevented to provide an effect of improving yield.

Hereinafter, exemplary embodiments of a transverse electric field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a first embodiment of the present invention, and includes a pixel portion including a thin film transistor, a gate pad portion, and a data pad portion for convenience of description. One pixel to be shown is shown.

3 is a cross-sectional view taken along lines IIa-IIa ', IIb-IIb and IIc-IIc of the array substrate shown in FIG. 2.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

In this case, in the case of the first embodiment of the present invention, a transverse electric field type liquid crystal display device in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate and the viewing angle is improved to 170 degrees or more is illustrated.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 according to the first embodiment of the present invention, which are arranged vertically and horizontally on the array substrate 110 to define a pixel region. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117, and a plurality of fingers for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel region. The common electrodes 108 'and 108 "in the form of fingers and the pixel electrodes 118' and 118" are alternately formed.

The thin film transistor includes a gate electrode 121 constituting a portion of the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode connected to the pixel electrodes 118 ′ and 118 ″. In addition, the thin film transistor is connected to a gate insulating film 115a for insulating the gate electrode 121 and the source / drain electrodes 122 and 123 and a gate voltage supplied to the gate electrode 121. The active pattern 124 forms a conductive channel between the source electrode 122 and the drain electrode 123.

As described above, the common electrodes 108 ′ and 108 ″ and the pixel electrodes 118 ′ and 118 ″ are alternately arranged in the pixel region to generate a transverse electric field.

In this case, the common electrodes 108 ′ and 108 ″ may be divided into, for example, a first common electrode 108 ′ positioned below the pixel region and a second common electrode 108 ″ positioned above the pixel region. have. In addition, the pixel electrodes 118 ′ and 118 ″ are disposed under the pixel area and disposed on the first pixel electrode 118 ′ alternately with the first common electrode 108 ′ and on the pixel area. And may be divided into a second pixel electrode 118 ″ alternately disposed with the second common electrode 108 ″.

As such, the pixel area includes the lower pixel area in which the first common electrode 108 ′ and the first pixel electrode 118 ′ have a first inclination angle with respect to the rubbing direction, and the second common electrode 108 ″ and the second pixel area. The pixel electrode 118 ″ may be divided into an upper pixel region having a second tilt angle with respect to the rubbing direction, wherein the rubbing direction may be substantially parallel to the gate line 116.

The first common electrode 108 ′, the second common electrode 108 ″, the first pixel electrode 118 ′, and the second pixel electrode 118 ″ have a structure symmetrical with respect to the rubbing direction, respectively. .

As described above, in the transverse electric field type liquid crystal display according to the first exemplary embodiment, the common electrodes 108 ′ and 108 ″ and the pixel electrodes 118 ′ and 118 ″ are inclined in different directions in the upper and lower pixel regions. The upper and lower pixel regions can be divided into two domains, thereby improving the viewing angle.

In this case, the pixel electrodes 118 ′ and 118 ″ are connected to the pixel electrode line 118L and electrically connected to the drain electrode 123 through the first contact hole 140a formed in the passivation layer 115b. That is, one side of the pixel electrodes 118 ′ and 118 ″ is connected to the second connection line 118a formed in a direction substantially parallel to the data line 117. The second connection line 118a is connected to the pixel electrode line 118L formed in a direction substantially parallel to the gate line 116.

In addition, one side of the common electrode 108 ′ and 108 ″ is connected to the first connection line 108a to be electrically connected to the common line 108L. In this case, the first connection line 108a is connected to the pixel area. The left and right edges may be formed in a direction substantially parallel to the data line 117, and the common line 108L may be formed in a direction substantially parallel to the gate line 116 above and below the pixel area. do.

A portion of the pixel electrode line 118L overlaps with a portion of the common line 108L below the gate insulating layer 115a and the gate insulating layer 115a and the passivation layer 115b, respectively. The storage capacitor Cst1 and the second storage capacitor Cst2 are formed.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140b and 140c indicate a second contact hole and a third contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the second contact hole 140b. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c.

On the other hand, the transverse electric field type liquid crystal display device according to the first embodiment of the present invention is active using a half-tone mask or a diffraction mask (hereinafter referred to as a half-tone mask). Since the pattern and the data wirings, that is, the source electrode, the drain electrode, and the data line are formed in one mask process, the array substrate can be manufactured in a total of four mask processes.

However, when the dual domain is used to improve the viewing angle as in the transverse electric field type liquid crystal display device according to the first embodiment of the present invention, the aperture ratio may be reduced. When formed of an opaque conductive material constituting the transmittance is reduced.

In addition, power consumption increases due to the use of a high voltage common voltage, and a phenomenon in which the common voltage does not maintain a stable DC level and periodically rises by a predetermined level appears. Such a phenomenon causes a greenish phenomenon (green stain), which tends to be more severe at higher resolutions.

In order to improve this, when the common electrode is formed of the ITO by using a double conductive film of copper and ITO, a haze phenomenon occurs in which the gate insulating film becomes cloudy as the copper residual material grows.

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a second exemplary embodiment of the present invention. For convenience of description, a pixel part including a thin film transistor, a gate pad part, and a data pad part are included. One pixel to be shown is shown.

As shown in the figure, a gate line 216 and a data line 217 are formed in the array substrate 210 according to the second embodiment of the present invention, which are arranged horizontally and horizontally on the array substrate 210 to define a pixel area. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 216 and the data line 217, and a plurality of finger types for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel area. The common electrodes 208 'and 208 "and the pixel electrodes 218' and 218" are alternately formed.

The thin film transistor includes a gate electrode 221 constituting a part of the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode connected to the pixel electrodes 218 ′ and 218 ″. The thin film transistor includes a gate insulating film (not shown) for insulating the gate electrode 221 and the source / drain electrodes 222 and 223 and a gate voltage supplied to the gate electrode 221. The active pattern may include an active pattern (not shown) that forms a conductive channel between the source electrode 222 and the drain electrode 223.

As described above, the common electrodes 208 'and 208 "and the pixel electrodes 218' and 218" are alternately arranged in the pixel region to generate a transverse electric field.

In this case, the common electrodes 208 ′ and 208 ″ may be divided into, for example, a first common electrode 208 ′ positioned below the pixel region and a second common electrode 208 ″ positioned above the pixel region. have. In addition, the pixel electrodes 218 ′ and 218 ″ are disposed under the pixel area, and are disposed on the first pixel electrode 218 ′ alternately with the first common electrode 208 ′ and the upper part of the pixel area. And may be divided into a second pixel electrode 218 "alternately arranged with the second common electrode 208".

As such, the pixel region includes a lower pixel region in which the first common electrode 208 'and the first pixel electrode 218' have a first inclination angle with respect to the rubbing direction, and the second common electrode 208 " The pixel electrode 218 ″ may be divided into an upper pixel region having a second tilt angle with respect to the rubbing direction, wherein the rubbing direction may be substantially parallel to the gate line 216.

The first common electrode 208 ′, the second common electrode 208 ″, and the first pixel electrode 218 ′ and the second pixel electrode 218 ″ each have a symmetrical structure with respect to the rubbing direction. . At this time, the first inclination angle and the second inclination angle may have a range of about 5 ~ 20 °.

As described above, in the transverse electric field type liquid crystal display device according to the second embodiment of the present invention, the common electrodes 208 'and 208 "are inclined in different directions in the upper and lower pixel areas as in the first embodiment of the present invention. By forming the pixel electrodes 218 'and 218 ", the upper and lower pixel regions can be divided into two domains, thereby improving the viewing angle.

In this case, the pixel electrodes 218 ′ and 218 ″ are connected to the pixel electrode line 218L to be electrically connected to the drain electrode 223 through the first contact hole 240a formed in the passivation layer (not shown). That is, one side of the pixel electrodes 218 ′ and 218 ″ may be connected to the second connection line 218a formed in a direction substantially parallel to the data line 217. The second connection line 218a is connected to the pixel electrode line 218L formed in a direction substantially parallel to the gate line 216.

In addition, one side of the common electrode 208 ′ and 208 ″ is connected to the first connection line 208a and electrically connected to the common line 208L. In this case, the first connection line 208a is connected to the pixel area. The left and right edges may be formed in a direction substantially parallel to the data line 217, and the common line 208L may be formed in a direction substantially parallel to the gate line 216 above and below the pixel area. do.

A portion of the pixel electrode line 218L overlaps the first storage capacitor Cst1 and the second storage by overlapping a portion of the common line 208L therebetween with the gate insulating layer, the gate insulating layer and the passivation layer interposed therebetween. The capacitor Cst2 is formed. The first and second storage capacitors Cst1 and Cst2 maintain a constant voltage until the next signal is applied to the liquid crystal capacitor. In addition to maintaining the signal, the storage capacitor has effects such as stabilization of gray scale display and reduction of flicker and afterimage.

The gate pad electrode 226p and the data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad The line 217p receives a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

For reference, reference numerals 240b and 240c represent second and third contact holes, respectively, wherein the data pad electrode 227p is electrically connected to the data pad line 217p through the second contact hole 240b. The gate pad electrode 226p is electrically connected to the gate pad line 216p through the third contact hole 240c.

Here, in the transverse electric field type liquid crystal display device according to the second embodiment of the present invention, a gate wiring and a common electrode formed of different conductive layers are formed using a half-tone mask (first mask), and a half-tone mask is formed. Two masks) to form an active pattern and a data wiring, and a pixel electrode, a pad electrode, and a protective film are formed by using a half-tone mask (third mask) and a lift-off process. It is possible to fabricate an array substrate, thereby reducing the manufacturing process and cost.

In addition, the transverse electric field type liquid crystal display device according to the second embodiment of the present invention is a gate using a heterogeneous conductive film of copper and molybdenum titanium (MoTi) or copper and molybdenum titanium (MoTi) and indium tin oxide (ITO). By forming the wiring and the common electrode and forming the pixel electrode finely using the lift-off process, the transmittance can be improved, the haze phenomenon can be improved, and the voltage rise of the common wiring can be suppressed to improve the greenish phenomenon. do.

Further, in the transverse electric field type liquid crystal display device according to the second embodiment of the present invention, the gate wiring and the common electrode are formed of different conductive layers, and the common electrode and the pixel electrode are formed on different layers, and thus a short circuit is generated. And the pattern loss can be prevented to provide an effect of improving the yield, which will be described in detail by the following method of manufacturing a transverse electric field type liquid crystal display device.

5A to 5C are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc' of the array substrate illustrated in FIG. 4, and an array substrate is manufactured on the left side of the array substrate. A process of manufacturing an array substrate of a data pad portion and a gate pad portion is sequentially shown on the right side.

6A to 6C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

As shown in FIGS. 5A and 6A, the gate electrode 221, the gate line 216, the first connection line 208a, and the common line are disposed on the pixel portion of the array substrate 210 made of a transparent insulating material such as glass. (208L) and common electrodes 208 ', 208 "are formed, and a gate pad line 216p is formed in the gate pad portion.

In this case, the common line 208L is formed in a direction substantially parallel to the gate line 216, and the first connection line 208a is formed at an edge of the pixel area to form the common line 208L. Will be connected to In addition, one side of the common electrodes 208 ′ and 208 ″ is connected to the first connection line 208a to receive a common voltage through the common line 208L.

In this case, the gate electrode 221, the gate line 216, the first connection line 208a, the common line 208L, and the common electrodes 208 ′ and 208 ″ may include a first conductive layer and a second conductive layer in the array. After depositing on the entire surface of the substrate 210 is formed by selectively patterning through a half-tone mask (first mask process).

In this case, the first connection line 208a and the common electrodes 208 'and 208 "are made of the first conductive layer.

In addition, the gate electrode 221, the gate line 216, the common line 208L, and the gate pad line 216p may be formed of the second conductive layer, and be formed of the first conductive layer under the gate. A gate electrode pattern 221 ', a gate line pattern (not shown), and a common line pattern that are patterned in substantially the same form as the electrode 221, the gate line 216, the common line 208L, and the gate pad line 216p. 208L 'and the gate pad line pattern 216p' are formed.

However, the present invention is not limited thereto. For example, the common line 208L may be formed of the first conductive layer.

Aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy as the second conductive layer Low resistance opaque conductive materials such as the like can be used. In addition, the first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

In this case, when copper is used as the second conductive layer, a conductive material such as molybdenum titanium (MoTi) may be used to prevent diffusion of the copper and improve adhesion characteristics to the first conductive layer.

In addition, when the second conductive layer is formed of a double layer of copper and molybdenum titanium, the first conductive layer may include indium tin oxide (ITO) or indium zinc oxide (IZO). The same transparent conductive material can be used.

Next, as shown in FIGS. 5B and 6B, the gate electrode 221, the gate line 216, the first connection line 208a, the common line 208L, and the common electrode 208 ′ and 208 ″ are formed. The gate insulating film 215a, the amorphous silicon thin film, the n + amorphous silicon thin film, and the third conductive film are formed on the entire surface of the formed array substrate 210, and then selectively removed through a photolithography process (second mask process). An active pattern 224 formed of the amorphous silicon thin film is formed on the pixel portion 210, and a source / drain electrode made of the third conductive layer and electrically connected to the source / drain region of the active pattern 224. (222, 223).

In addition, a data line 217 defining a pixel region is formed in the pixel portion of the array substrate 210 by crossing the gate line 216 through the second mask process, and the data of the array substrate 210 is formed. A data pad line 217p formed of the third conductive layer is formed in the pad portion.

In this case, an ohmic contact layer 225n formed of the n + amorphous silicon thin film and patterned in the same form as the source / drain electrodes 222 and 223 is formed on the active pattern 224.

In addition, the first amorphous silicon thin film pattern 220 ′ formed of the amorphous silicon thin film and the n + amorphous silicon thin film and patterned in substantially the same shape as the data pad line 217p is formed below the data pad line 217p. A second n + amorphous silicon thin film pattern 225 ″ is formed.

Here, the active pattern 224, the source / drain electrodes 222 and 223, and the data line 217 according to the second exemplary embodiment of the present invention use a half-tone mask to perform one mask process (second mask process). At the same time, the second mask process will be described in detail with reference to the accompanying drawings.

7A to 7F are cross-sectional views illustrating a second mask process according to a second embodiment of the present invention in the array substrate illustrated in FIGS. 5B and 6B.

As shown in FIG. 7A, the array substrate 210 on which the gate electrode 221, the gate line 216, the first connection line 208a, the common line 208L, and the common electrodes 208 ′ and 208 ″ are formed. The gate insulating film 215a, the amorphous silicon thin film 220, the n + amorphous silicon thin film 225, and the third conductive film 230 are formed on the entire surface of the substrate.

In this case, the third conductive layer 230 may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line. In addition, the third conductive layer 230 may have a multilayer structure in which two or more low resistance conductive materials are stacked.

As shown in FIG. 7B, the first half-tone mask 280 of the present invention is formed after forming the first photoresist layer 270 made of photosensitive material such as photoresist on the entire surface of the array substrate 210. Light is selectively irradiated to the first photoresist layer 270 through.

In this case, the first half-tone mask 280 blocks the first transmission region I through which all of the irradiated light is transmitted and the second transmission region II through which only a part of the light is transmitted and partly blocks the light. The blocking region III is provided, and only the light passing through the first half-tone mask 280 is irradiated to the first photosensitive film 270.

Subsequently, after developing the first photoresist layer 270 exposed through the first half-tone mask 280, as shown in FIG. 7C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 270a to the fourth photoresist pattern 270d having a predetermined thickness remain in a region where all of the light is blocked or partially blocked by the light, and the first transmission region I through which all the light is transmitted The first photoresist film is completely removed to expose the surface of the third conductive film 230.

In this case, the first photoresist pattern 270a to the third photoresist pattern 270c formed in the blocking region III are formed thicker than the fourth photoresist pattern 270d formed through the second transmission region II. In addition, the first photoresist film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a photoresist.

Next, as shown in FIG. 7D, an amorphous silicon thin film, an n + amorphous silicon thin film, and a third formed on the lower portion of the first photosensitive film pattern 270a to the fourth photosensitive film pattern 270d formed as described above are used as a mask. When the conductive film is selectively removed, an active pattern 224 made of the amorphous silicon thin film is formed on the pixel portion of the array substrate 210, and the second conductive layer is formed on the data pad portion of the array substrate 210. The formed data pad line 217p is formed.

In this case, the first n + amorphous silicon thin film pattern 225 ′ formed of the n + amorphous silicon thin film and the third conductive layer and patterned in substantially the same shape as the active pattern 224 is formed on the active pattern 224, respectively. The third conductive film pattern 230 ′ is formed.

In addition, the first amorphous silicon thin film pattern 220 ′ formed of the amorphous silicon thin film and the n + amorphous silicon thin film and patterned in substantially the same shape as the data pad line 217p is formed below the data pad line 217p. A second n + amorphous silicon thin film pattern 225 ″ is formed.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 270a to the fourth photoresist pattern 270d is performed, as shown in FIG. 7E, the second transmission region II may be formed. The fourth photoresist pattern is completely removed.

In this case, the first photoresist pattern to the third photoresist pattern correspond to the blocking region III by the fifth photoresist pattern 270a 'through the seventh photoresist pattern 270c', in which the thickness of the fourth photoresist pattern is removed. Only the source electrode region, the drain electrode region, and the upper portion of the data pad line 217p remain.

Subsequently, as shown in FIG. 7F, the array substrate 210 is removed by removing a portion of the third conductive film pattern using the remaining fifth photoresist pattern 270a ′ to seventh photoresist pattern 270c ′ as a mask. The source electrode 222, the drain electrode 223, and the data line 217 formed of the third conductive layer are formed in the pixel portion of the N-th cross section.

Subsequently, the n + amorphous silicon thin film pattern is selectively removed by using the second mask process to form the n + amorphous silicon thin film, and the source / drain regions and the source / drain electrodes of the active pattern 224 ( An ohmic contact layer 225n for ohmic contact between 222 and 223 is formed.

As described above, according to the second embodiment of the present invention, the active pattern 224, the source / drain electrodes 222 and 223, and the data line 217 may be formed through a single mask process by using a half-tone mask. Will be.

Next, as shown in FIGS. 5C and 6C, the passivation layer 215b may be disposed on the entire surface of the array substrate 210 on which the active patterns 224, the source / drain electrodes 222 and 223, and the data lines 217 are formed. After the fourth conductive film is formed, the photolithography process (third mask process) and the lift-off process are applied to the fourth conductive film in the pixel portion of the array substrate 210 in one mask process. The pixel electrodes 218 'and 218 ", the pixel electrode line 218L, and the second connection line 218a are formed.

In addition, the data pad electrode 227p and the gate pad electrode 226p formed of the fourth conductive layer may be formed in the data pad portion and the gate pad portion of the array substrate 210 through the third mask process.

In this case, the data pad electrode 227p and the gate pad electrode 226p are respectively disposed through the second contact hole 240b and the third contact hole 240c formed in the passivation layer 215b. And gate pad lines 216p, respectively.

As described above, the third mask process uses a half-tone mask (or a multi-tone mask) and a lift-off process, so that the pixel electrodes 218 'and 218 " ), The second connection line 218a, the gate pad electrode 226p, the data pad electrode 227p, and the passivation layer 215b can be formed. Hereinafter, the third mask process will be described in detail with reference to the accompanying drawings.

8A to 8G are cross-sectional views illustrating a third mask process according to a second embodiment of the present invention in the array substrate illustrated in FIGS. 5C and 6C.

As shown in FIG. 8A, a passivation layer 215b is formed on the entire surface of the array substrate 210 on which the active pattern 224, the source / drain electrodes 222 and 223, and the data line 217 are formed.

Next, as shown in FIG. 8B, the second half-tone mask 380 of the present invention is formed after forming the second photoresist layer 370 made of photosensitive material such as photoresist on the entire surface of the array substrate 210. Light is selectively irradiated to the second photoresist layer 370 through.

In this case, the second half-tone mask 380 used in the second embodiment of the present invention includes a first transmission region I for transmitting all of the irradiated light and a second transmission region for transmitting only part of the light and blocking part of the light ( II) and a blocking region III for blocking all irradiated light are provided, and only the light passing through the second half-tone mask 380 is irradiated to the second photosensitive film 370.

Subsequently, after developing the second photoresist layer 370 exposed through the second half-tone mask 380, the blocking region III and the second transmission region II may be formed as illustrated in FIG. 8C. The first photoresist pattern 370a to the seventh photoresist pattern 370g having a predetermined thickness remain in an area where light is partially blocked or partially blocked, and the second transmission region I is provided in the first transmission region I through which all light is transmitted. The photoresist film is completely removed to expose the surface of the protective film 215b.

In this case, the first photoresist pattern 370a to the fifth photoresist pattern 370e formed in the blocking region III may include the sixth photoresist pattern 370f and the seventh photoresist pattern 370g formed through the second transmission region II. It is thicker than). In addition, the second photoresist film is completely removed in the region where all the light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a resist.

Next, as shown in FIG. 8D, the gate insulating film 215a and the protective film 215b formed under the first photosensitive film pattern 370a to the seventh photosensitive film pattern 370g formed as a mask are used as a mask. When selectively removed, a first contact hole 240a for exposing a part of the drain electrode 223 is formed in the pixel portion of the array substrate 210 and at the same time the data pad portion and the gate pad portion of the array substrate. A second contact hole 240b and a third contact hole 240c exposing portions of the data pad line 217p and the gate pad line 216p are formed.

Subsequently, when the ashing process of removing a portion of the first photoresist pattern 370a to the seventh photoresist pattern 370g is performed, as shown in FIG. 8E, the sixth photoresist of the second transmission region II is formed. The pattern and the seventh photoresist pattern are completely removed.

In this case, the first photoresist pattern to the fifth photoresist pattern include the eighth photoresist pattern 370a 'to the twelfth photoresist pattern 370e' where the thickness of the sixth photoresist pattern and the seventh photoresist pattern is removed. Only the predetermined area corresponding to (III) remains.

8F, the fourth conductive layer 250 is formed on the entire surface of the array substrate 210 while the eighth photosensitive layer patterns 370a ′ to 12th photoresist pattern 370e ′ remain. do.

Subsequently, as shown in FIG. 8G, the eighth to 12th photoresist patterns are removed through a lift-off process, wherein the eighth to 12th photoresist patterns of the blocking region III are disposed on the eighth photoresist pattern. The deposited fourth conductive film is removed together with the eighth photosensitive film pattern to the twelfth photosensitive film pattern.

As a result, a pixel electrode 218 ′ (not shown), a pixel electrode line 218L, and a second connection line (not shown) formed of the fourth conductive layer are formed in the pixel portion of the array substrate 210.

In addition, a data pad electrode 227p and a gate pad electrode 226p formed of the fourth conductive layer are formed in the data pad part and the gate pad part of the array substrate 210, respectively.

In this case, the data pad electrode 227p and the gate pad electrode 226p are electrically connected to the lower data pad line 217p and the gate pad line 216p through the second contact hole and the third contact hole, respectively. Done.

The array substrate according to the first and second embodiments of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor is attached to the color filter substrate. A black matrix is formed to prevent light leakage from the gate line and the data line, and a color filter for realizing red, green, and blue colors is formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

As described above, the first and second embodiments of the present invention describe an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern as an example, but the present invention is not limited thereto. The present invention is also applied to a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as an active pattern.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display device.

2 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention;

3 is a cross-sectional view taken along lines IIa-IIa ', IIb-IIb, and IIc-IIc of the array substrate shown in FIG. 2;

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a second exemplary embodiment of the present invention.

5A to 5C are cross-sectional views sequentially showing manufacturing processes taken along lines IVa-IVa ', IVb-IVb and IVc-IVc of the array substrate shown in FIG.

6A to 6C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A to 7F are cross-sectional views illustrating a second mask process according to a second embodiment of the present invention in the array substrate shown in FIGS. 5B and 6B.

8A through 8G are cross-sectional views illustrating a third mask process according to a second embodiment of the present invention in the array substrate illustrated in FIGS. 5C and 6C.

DESCRIPTION OF REFERENCE NUMERALS

108 ', 208': First common electrode 108 ", 208": Second common electrode

108a, 208a: First connection line 108L, 208L: Common line

116,216 Gate line 117,217 Data line

118 ', 218': first pixel electrode 118 ", 218": second pixel electrode

118a, 218a: second connection line 121, 221: gate electrode

122,222 source electrode 123,223 drain electrode

Claims (9)

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a common electrode formed of a first conductive layer on the pixel portion of the first substrate through a first mask process; Forming a gate electrode and a gate line formed of a second conductive layer on the pixel portion of the first substrate using the first mask process; Forming a gate electrode pattern and a gate line pattern formed of the first conductive layer under the gate electrode and the gate line using the first mask process; Forming a gate insulating film on the first substrate; Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate through a second mask process, and forming a data line crossing the gate line to define a pixel region; Forming a protective film on the first substrate; Forming a first to fifth photoresist pattern having a first thickness to a fifth photoresist pattern, a sixth photoresist pattern having a second thickness, and a seventh photoresist pattern on the passivation layer through a third mask process; Forming a first contact hole exposing a portion of the drain electrode by selectively removing a portion of the passivation layer using the first to seventh photoresist patterns as a mask; Removing portions of the first to seventh photoresist patterns to remove the sixth and seventh photoresist patterns, and simultaneously forming eighth to twelve photoresist patterns having a third thickness; Forming a transparent conductive film on the first substrate while the eighth photosensitive film pattern to the twelfth photosensitive film pattern remain; A pixel electrode electrically connected to the drain electrode through the first contact hole by removing the eighth photosensitive film pattern and the twelfth photosensitive film pattern and simultaneously removing the transparent conductive film formed on the surface of the eighth photosensitive film pattern. Forming; And And bonding the first substrate and the second substrate to each other, wherein the common electrode, the pixel electrode, and the outermost common electrode are formed in a direction parallel to the gate line. The liquid crystal display device of claim 1, further comprising forming a gate pad line formed of the second conductive layer on a gate pad portion of the first substrate by using the first mask process. Manufacturing method. The method of claim 1, wherein the second conductive layer is made of a low resistance opaque conductive material such as copper, and the first conductive layer is formed of a conductive material such as molybdenum titanium (MoTi) to prevent diffusion of the copper and improve adhesion characteristics. A method of manufacturing a transverse electric field type liquid crystal display device, characterized in that it is made of a material. The method of claim 1, wherein the second conductive film is formed of a double layer of copper and molybdenum titanium, and the first conductive film is indium tin oxide (ITO) or indium zinc oxide (IZO). Made of a transparent conductive material such as The method of claim 2, further comprising forming a data pad line on the data pad portion of the first substrate by using the second mask process. The second contact hole of claim 5, further comprising: selectively removing a portion of the gate insulating layer and the passivation layer using the first to seventh photoresist patterns as a mask to expose a portion of the data pad line and the gate pad line; A method for manufacturing a liquid crystal display device, further comprising the step of forming a third contact hole. The ohmic contact of claim 1, wherein the n + amorphous silicon thin film is formed using the second mask process, and has ohmic contact between a source / drain region of the active pattern and the source / drain electrode. A method of manufacturing a liquid crystal display device, further comprising the step of forming a layer. The method of claim 1, wherein the common electrode comprises a first common electrode disposed below the pixel region and a second common electrode disposed above the pixel region. 9. The pixel electrode of claim 8, wherein the pixel electrode is disposed under the pixel region and alternately disposed with the first common electrode, and the pixel electrode is alternately disposed with the second common electrode positioned above the pixel region. A method for manufacturing a liquid crystal display device, comprising a second pixel electrode.

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