KR20080062930A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to remove signal interference of a data line according as a tail of an active pattern is not present and increase an opening ratio as much as a tail width of the active pattern. A first substrate(110) divided into a pixel unit and first and second pad units is provided. Through a first mask process, a gate electrode(121), a gate line and a pixel electrode(118) are formed in a pixel unit of the first substrate. Through a second mask process, an active pattern(124) of an island shape is formed on the gate electrode in a state when a first insulating layer(115a) is interposed. On the active pattern, an n+ amorphous silicon thin film pattern is formed. Through a third mask process, source and drain electrodes(122,123) are formed in the pixel unit of the first substrate. Through the third mask process, a data line(117) defining a pixel area by crossing the gate line is formed. Through a fourth process, a second insulating layer(115b) is formed on the first substrate. The first substrate and a second substrate are attached to each other.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

4A to 4D are cross-sectional views sequentially illustrating a manufacturing process along lines IIIa-IIIa ', IIIb-IIIb, IIIc-IIIc', and IIId-IIId 'of the array substrate shown in FIG.

5A through 5D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

6A to 6F are cross-sectional views illustrating in detail the first mask process illustrated in FIGS. 4A and 5A.

7A to 7F are cross-sectional views illustrating the second mask process shown in FIGS. 4B and 5B in detail.

8 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

9A to 9D are cross-sectional views sequentially showing manufacturing processes taken along lines VIIIa-VIIIa ', VIIIb-VIIIb, VIIIc-VIIIc', and VIIId-VIIId 'of the array substrate shown in FIG. 8;

** Explanation of symbols for main parts of drawings **

110,210: array substrate 116,216: gate line

116p, 216p: Gate pad line 117,217: Data line

117p, 217pp: Data pad line 118,218: Pixel electrode

119,219 Storage electrodes 121,221 Gate electrodes

122,222 source electrode 123,223 drain electrode

124,224 active patterns 126p and 226p gate pad electrodes

127p, 227p: Data pad electrode

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to reduce the number of masks to simplify the manufacturing process, improve the yield and at the same time prevent the defects of bright spots caused by foreign objects and a manufacturing method thereof It is about.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the drawing, the liquid crystal display device is largely a liquid crystal layer formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10. It consists of 30.

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 using a photolithography process (first mask process).

Next, as shown in FIG. 2B, the first insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed. The active pattern 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same shape as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 2C, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (third mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process, thereby forming an ohmic − between the active pattern 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25 'is formed.

Next, as shown in FIG. 2D, a second insulating film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process (fourth mask). The contact hole 40 exposing a part of the drain electrode 23 is formed by removing a part of the second insulating layer 15b through the process).

Finally, as shown in FIG. 2E, the contact hole 40 is formed by depositing a transparent conductive metal material on the entire surface of the array substrate 10 and then selectively patterning the photoresist using a photolithography process (fifth mask process). The pixel electrode 18 which is electrically connected to the drain electrode 23 is formed.

As described above, fabrication of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active pattern, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. It has the disadvantage of dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

At this time, by forming the active pattern and the source / drain electrodes in a single mask process using a diffraction mask, a technique for manufacturing an array substrate using a total of four mask processes has been developed.

However, the liquid crystal display of the structure uses a diffraction mask to pattern the active pattern and the source / drain electrodes through two etching processes, so that the active pattern protrudes around the bottom of the source electrode, the drain electrode, and the data line. Will remain.

The active pattern is made of a pure amorphous silicon thin film, and the protruding active pattern is exposed to the backlight of the lower portion, so that photocurrent is generated by the backlight. At this time, due to the minute flickering of the backlight light, the amorphous silicon thin film reacts finely, and the activation and deactivation states are repeated, thereby causing a change in the photocurrent. The photocurrent component is coupled with a signal flowing to a neighboring pixel electrode to distort the movement of the liquid crystal located in the pixel electrode. As a result, wavy noise in which wavy thin lines appear on the screen of the liquid crystal display is generated.

In addition, the active pattern under the data line protrudes a predetermined distance to both sides of the data line, so that the opening ratio of the liquid crystal display device is reduced as the opening area of the pixel portion is eroded by the protruding distance.

An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which fabricate an array substrate by four mask processes.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can realize high brightness by enlarging the opening area and at the same time not generating wave noise.

It is still another object of the present invention to provide a liquid crystal display and a method of manufacturing the same, which can reduce the response time of liquid crystals and at the same time improve the afterimage improvement and the level difference.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display of the present invention includes a first substrate divided into a pixel portion, a first pad portion and a second pad portion; A gate electrode and a gate line formed in the pixel portion of the first substrate; A gate electrode pattern and a gate line pattern formed under the gate electrode and the gate line and patterned in the same form as the gate electrode and the gate line; An active pattern formed on the gate electrode with the first insulating layer interposed therebetween, the active pattern having an island shape having a smaller width than the gate electrode; An ohmic contact layer formed on the first substrate and formed on the source / drain regions of the active pattern; A source / drain electrode formed on the pixel portion of the first substrate and electrically connected to the source / drain region of the active pattern through the ohmic contact layer; A data line formed in the pixel portion of the first substrate and defining a pixel region crossing the gate line; A pixel electrode formed of a first conductive layer constituting the gate electrode pattern and the gate line pattern and formed on the same layer as the gate electrode pattern and the gate line pattern; A second insulating layer formed on the first substrate and covering the pixel electrode; And a second substrate bonded to face the first substrate.

In addition, the manufacturing method of the liquid crystal display of the present invention includes the steps of providing a first substrate divided into a pixel portion, a first pad portion and a second pad portion; Forming a gate electrode, a gate line, and a pixel electrode on the pixel portion of the first substrate through a first mask process; Forming an island-type active pattern with a first insulating layer interposed on the gate electrode through a second mask process, and forming an n + amorphous silicon thin film pattern on the active pattern; Forming a source electrode and a drain electrode on the pixel portion of the first substrate through a third mask process, and forming a data line crossing the gate line to define a pixel region; Forming a second insulating film on the first substrate through a fourth mask process; And bonding the first substrate and the second substrate to each other.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention. For convenience of description, one pixel including a thin film transistor including a gate pad part, a data pad part, and a pixel part is provided. It is shown.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged vertically and horizontally on the array substrate 110 to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

In this case, a gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140a 'and 140b' denote data pad part open holes and gate pad part open holes, respectively, through the data pad part open holes 140a 'and the gate pad part open holes 140b', respectively. A portion of the data pad electrode 127p and the gate pad electrode 126p are exposed to the outside.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. In addition, the thin film transistor includes an active pattern 124 that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

The active pattern 124 according to the present invention is formed of an amorphous silicon thin film, and is formed in an island shape only on the gate electrode 121 to reduce the off current of the thin film transistor.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to be electrically connected to the pixel electrode 118. do.

In this case, a portion of the front gate line 116 ′ overlaps a portion of the storage electrode 119 therebetween with a first insulating layer (not shown) therebetween to form a storage capacitor Cst. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. In general, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is input and is leaked. Disappear. Therefore, in order to maintain the applied voltage, the storage capacitor Cst needs to be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stability of gray scale display and reduction of flicker and afterimage in addition to signal retention.

Here, the gate electrode 121 and the gate lines 116 and 116 ′ of the present invention made of an opaque conductive material are made of a transparent conductive material under the gate electrode 121 and the gate lines 116 and 116, respectively. A gate electrode pattern (not shown) and a gate line pattern (not shown) are patterned in the same form as ''.

In this case, the pixel electrode 118 is formed on the same layer as the gate electrode pattern and the gate line pattern, and is made of the same transparent conductive material constituting the gate electrode pattern and the gate line pattern.

In addition, the gate electrode 121, the pixel electrode 118, and the pad electrode 126p and 127p of the present invention can be fabricated in one mask process to manufacture the array substrate 110 through a total of four mask processes. This will be described in detail through the following manufacturing method of the liquid crystal display.

4A through 4D are cross-sectional views sequentially illustrating a manufacturing process along lines IIIa-IIIa ', IIIb-IIIb, IIIc-IIIc', and IIId-IIId 'of the array substrate illustrated in FIG. A process of manufacturing an array substrate of a pixel portion to be included is shown, and a process of manufacturing an array substrate of a data pad portion and a gate pad portion is sequentially shown on the right side.

5A to 5D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

As shown in FIGS. 4A and 5A, gate electrodes 121, gate lines 116 and 116 ′, and pixel electrodes 118 are formed in the pixel portion of the array substrate 110 made of a transparent insulating material such as glass. The gate pad line 116p is formed in the gate pad part.

In addition, a data pad electrode 127p and a gate pad electrode 126p are formed in each of the data pad portion and the gate pad portion of the array substrate 110.

In this case, the gate electrode 121 and the gate lines 116 and 116 'are made of a transparent conductive material below the gate electrode patterned in the same shape as the gate electrode 121 and the gate lines 116 and 116', respectively. An electrode pattern 130 ′ and a gate line pattern 130 ″ are formed.

In this case, the pixel electrode 118 is formed on the same layer as the gate electrode pattern and the gate line pattern, and is made of the same transparent conductive material constituting the gate electrode pattern and the gate line pattern.

In this case, reference numeral 116 'denotes a gate line of the front end of the corresponding pixel, and the gate line 116 and the front gate line 116' of the corresponding pixel are formed in the same manner.

The gate electrode 121, the gate lines 116 and 116 ′, the pixel electrode 118, the gate pad line 116p and the pad part electrodes 127p and 126p may be formed of the first conductive layer and the second conductive layer. After the deposition on the entire surface of the array substrate 110, one mask process using a half-tone mask or a diffraction mask (hereinafter referred to as a half-tone mask to include a diffraction mask) (first mask process At the same time, the first mask process will be described in detail with reference to the accompanying drawings.

6A through 6F are cross-sectional views illustrating in detail the first mask process illustrated in FIGS. 4A and 5A.

As shown in FIG. 6A, the first conductive layer 130 and the second conductive layer 160 are formed on the entire surface of the array substrate 110 made of a transparent insulating material such as glass.

In this case, the first conductive layer 130 may be formed of aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), and chromium to form a pixel electrode and a pad electrode. Low resistance opaque conductive materials such as (chromium; Cr) and molybdenum (Mo) may be used. In addition, the first conductive layer 130 may have a multilayer structure in which two or more low resistance conductive materials are stacked.

In addition, the second conductive layer 160 may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO) to form a gate electrode, a gate line, and a gate pad line. It contains the same transparent conductive material with excellent transmittance.

6B, after forming the first photoresist film 170 made of photosensitive material such as photoresist on the entire surface of the array substrate 110, the first half-tone mask 180 of the present invention is formed. Light is selectively irradiated to the first photoresist film 170 through.

In this case, the first half-tone mask 180 used in the first embodiment includes a first transmission region I for transmitting all of the irradiated light, a second transmission region II for transmitting only a part of the light, and blocking a part of the light; A blocking region III for blocking all irradiated light is provided, and only the light passing through the half-tone mask 180 is irradiated to the first photosensitive film 170.

Subsequently, after the first photoresist film 170 exposed through the first half-tone mask 180 is developed, as shown in FIG. 6C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 170a to the sixth photoresist pattern 170f having a predetermined thickness remain in an area where light is partially blocked or partially blocked, and the first transmission region I through which all light is transmitted is first The photoresist film is completely removed to expose the surface of the second conductive film 160.

In this case, the first photoresist pattern 170a to the third photoresist pattern 170c formed in the blocking region III may include the fourth photoresist pattern 170d to the sixth photoresist pattern 170f formed through the second transmission region II. It is thicker than). In addition, the first photoresist film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto. It is okay.

Next, as shown in FIG. 6D, the first conductive film and the second conductive film formed below are selectively formed using the first photosensitive film pattern 170a to the sixth photosensitive film pattern 170f formed as described above as a mask. When removed, the gate electrode 121 made of the second conductive layer, the gate line 116 ′, and the pixel electrode 118 made of the first conductive layer are formed in the pixel portion of the array substrate 110. .

In addition, a data pad electrode 127p and a gate pad electrode 126p formed of the first conductive layer are formed in each of the data pad portion and the gate pad portion of the array substrate 110.

In this case, the gate electrode pattern 130 formed of the first conductive layer under the gate electrode 121 and the gate line 116 ′ and patterned in the same shape as the gate electrode 121 and the gate line 116 ′. And the gate line pattern 130 " are formed.

The pixel electrode 118, the data pad electrode 127p, and the gate pad electrode 126p are formed of the second conductive layer, and the pixel electrode 118, the data pad electrode 127p, and the gate pad are disposed on the pixel electrode 118. The pixel electrode pattern 160 ′, the data pad electrode pattern 160 ″, and the gate pad electrode pattern 160 ′ ″ patterned in the same form as the electrode 126p remain.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a to the sixth photoresist pattern 170f is performed, as illustrated in FIG. 6E, a fourth photoresist layer of the second transmission region II is formed. The pattern to the sixth photosensitive film pattern are completely removed.

In this case, the first photoresist pattern to the third photoresist pattern may include the blocking region as the seventh photoresist pattern 170a 'through the ninth photoresist pattern 170c', from which the thickness of the fourth photoresist pattern to the sixth photoresist pattern is removed. The gate electrode 121, the gate line 116 'and the gate pad line region corresponding to (III) remain only in the upper portion.

6F, all of the pixel electrode pattern, the data pad electrode pattern, and the gate pad electrode are formed by using the remaining seventh photoresist pattern 170a ′ to ninth photoresist pattern 170c ′ as a mask. By removing a portion of the pattern to expose the surface of the pixel electrode 118 and the data pad electrode 127p, a gate made of the second conductive layer in the gate pad portion and electrically connected to the gate pad electrode 126p. The pad line 116p is formed.

Next, as shown in FIGS. 4B and 5B, the gate electrode 121, the gate lines 116 and 116 ′, the pixel electrode 118, the gate pad line 116p and the pad part electrodes 127p and 126p are shown. ), The first insulating film 115b, the amorphous silicon thin film, and the n + amorphous silicon thin film are formed on the entire surface of the array substrate 110 on which the gate electrode 121 is formed, and then selectively removed through a photolithography process (second mask process). A data pad part contact hole 140a and a gate pad part exposing a portion of the data pad electrode 127p and the gate pad electrode 126p, respectively, while forming an active pattern 124 made of the amorphous silicon thin film The contact hole 140b is formed.

In this case, a sixth n + amorphous silicon thin film pattern 150 ″ ″ ″ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 remains on the active pattern 124.

In addition, a portion of the first insulating layer 115a formed on the pixel electrode 118 is removed to expose the surface of the pixel electrode 118 of the pixel region.

Here, the active pattern 124 according to the present invention is formed in an island shape only on the gate electrode 121 with the first insulating layer 115a therebetween, and the active pattern 124 and the data pad part contact hole. 140a and the gate pad part contact hole 140b are simultaneously formed in one mask process (second mask process) using a half-tone mask. Hereinafter, the second mask process will be described in detail with reference to the accompanying drawings. .

7A to 7F are cross-sectional views illustrating in detail the second mask process illustrated in FIGS. 4B and 5B.

As shown in FIG. 7A, the array substrate 110 includes the gate electrode 121, the gate line 116 ′, the pixel electrode 118, the gate pad line 116p, and the pad part electrodes 127p and 126p. The first insulating film 115b, the amorphous silicon thin film 120, and the n + amorphous silicon thin film 150 are formed on the entire surface.

As shown in FIG. 7B, the second half-tone mask 280 of the present invention is formed after forming the second photoresist layer 270 made of a photoresist such as a photoresist on the entire surface of the array substrate 110. Light is selectively irradiated to the second photoresist layer 270 through.

In this case, the second half-tone mask 280 used in the first embodiment includes a first transmission region I for transmitting all of the irradiated light, a second transmission region II for transmitting only a part of the light, and blocking a part of the light; A blocking region III for blocking all the irradiated light is provided, and only the light passing through the second half-tone mask 280 is irradiated to the second photosensitive film 270.

Subsequently, after the second photoresist layer 270 exposed through the second half-tone mask 280 is developed, as shown in FIG. 7C, the blocking region III and the second transmission region II may be formed. The first photoresist layer pattern 270a and the second photoresist layer pattern 270b having a predetermined thickness remain in the region where all the light is blocked or partially blocked through the second photoresist. The photoresist is completely removed to expose the surface of the n + amorphous silicon thin film 150.

In this case, the first photoresist layer pattern 270a formed in the blocking region III is thicker than the second photoresist layer pattern 270b formed through the second transmission region II. In addition, the second photoresist film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto. It is okay.

Next, as shown in FIG. 7D, the first insulating film 115a and the amorphous silicon thin film formed under the first photosensitive film pattern 270a and the second photosensitive film pattern 270b formed as masks are used as masks. And selectively removing the n + amorphous silicon thin film, exposing an open hole H exposing the pixel electrode 118 of the pixel region and a portion of the data pad electrode 127p and the gate pad electrode 126p, respectively. The data pad part contact hole 140a and the gate pad part contact hole 140b are formed.

Here, reference numerals 120 ', 120 ", 120'", 120 "", and 120 '"" respectively denote a first amorphous silicon thin film pattern, a second amorphous silicon thin film pattern, and a third amorphous silicon thin film pattern made of the amorphous silicon thin film. , A fourth amorphous silicon thin film pattern and a fifth amorphous silicon thin film pattern. Also, reference numerals 150 ', 150 ", 150'", 150 "", and 150 '"" respectively refer to the first n + amorphous silicon thin film pattern, the second n + amorphous silicon thin film pattern, and the third n + consisting of the n + amorphous silicon thin film. An amorphous silicon thin film pattern, a fourth n + amorphous silicon thin film pattern, and a fifth n + amorphous silicon thin film pattern are shown.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 270a and the second photoresist pattern 270b is performed, as illustrated in FIG. 7E, the second photoresist layer of the second transmission region II is formed. The pattern will be completely removed.

In this case, the first photoresist pattern is a third photoresist pattern 270a ′ removed by the thickness of the second photoresist pattern and remains only in the active pattern region corresponding to the blocking region III.

7F, a portion of the first amorphous silicon thin film pattern and the first n + amorphous silicon thin film pattern are removed by using the remaining third photoresist pattern 270a ′ as a mask. 121. An island-type active pattern 124 formed of the amorphous silicon thin film is formed on the upper portion.

In this case, the second amorphous silicon thin film pattern to the fifth amorphous silicon thin film pattern and the second n + amorphous silicon thin film pattern to the fifth n + amorphous silicon thin film pattern are completely removed.

In this case, a sixth n + amorphous silicon thin film pattern 150 ″ ″ ″ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 remains on the active pattern 124.

As such, since the active pattern 124 according to the present invention is formed in an island shape only on the gate electrode 124, the off current of the thin film transistor is reduced.

Next, as shown in FIGS. 4C and 5C, after depositing a third conductive film on the entire surface of the array substrate 110 on which the active pattern 124 is formed, the photolithography process (third mask process) is used. By removing a portion of the third conductive layer, a source electrode 122 and a drain electrode 123 formed of the third conductive layer are formed in the pixel portion of the array substrate 110, and the data line of the array substrate 110 is formed. The data line 117 formed of the third conductive layer is formed in the portion.

The data pad of the array substrate 110 may be formed of the third conductive layer through the third mask process, and may be electrically connected to the data pad electrode 127p through the data pad contact hole. Line 117p is to be formed.

In addition, a storage electrode 119 formed of the three conductive layers and electrically connected to the pixel electrode 118 is formed on the gate line 116 ′, and the storage electrode 119 is formed under the first first electrode. The storage capacitor Cst is formed by overlapping a portion of the gate line 116 ′ with the insulating layer 115a therebetween.

In this case, the sixth n + amorphous silicon thin film pattern formed on the active pattern 124 is removed from the active pattern 124 and the source / drain electrodes 122 and 123 by removing a predetermined region through the third mask process. An ohmic contact layer 125 for ohmic contact is formed.

The third conductive layer may include aluminum (Al), aluminum alloy, tungsten (W), to form the source electrode 122, the drain electrode 123, and the data line 117. It may be made of a low resistance opaque conductive material such as copper (Cu), chromium (Cr), molybdenum (Mo), or the like.

The data line 117 according to the present invention does not have a tail of an active pattern made of an amorphous silicon thin film at the bottom thereof, and thus there is no signal interference of the data line 117 by the tail of the active pattern. For reference, the tail of the active pattern is formed under the data line in the process of forming the active pattern, the source / drain electrode, and the data line by using a diffraction mask in a single mask process, and is smaller than the width of the data line. As a result of having a wide width, signal interference of the data line and a decrease in aperture ratio are caused.

4D and 5D, after forming the second insulating film 115b on the entire surface of the array substrate 110, the second insulating film 115b is formed by using a photolithography process (fourth mask process). ) Selectively removes a portion of the data pad electrode 127p and the gate pad electrode 126p to form a data pad part open hole 140a 'and a gate pad part open hole 140b', respectively. do.

In the case of the present invention, the second insulating film 115b is formed on the pixel electrode 118 so that even if foreign matter occurs in the cell gap, the pixel electrode 118 of the array substrate 110 and the color filter substrate (not shown) may be formed. It is possible to prevent a short between the common electrodes.

In this case, the thickness of the second insulating layer 115b may be as thin as about 100 to about 500 kHz to reduce the cell gap of the liquid crystal display device to reduce the response time of the liquid crystal.

However, the thickness of the second insulating film 115b should be about 2000 μs in order to effectively prevent short circuit defects caused by the foreign matter. And there is a disadvantage that the brightness is reduced.

In the liquid crystal display according to the second embodiment of the present invention, the second insulating film is formed in a two-layer structure of an inorganic insulating film and an organic insulating film, thereby minimizing the increase in the driving voltage and the decrease in luminance. The liquid crystal display and its manufacturing method will be described in detail.

FIG. 8 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention, except that the second insulating layer has a two-layer structure of an inorganic insulating layer and an organic insulating layer. It has the same structure as the example array substrate.

That is, in the second embodiment, the second insulating film is formed on the pixel electrode to prevent short-circuit defects caused by foreign substances, and the second insulating film is formed in the two-layer structure of the inorganic insulating film and the organic insulating film, thereby increasing the driving voltage or increasing the luminance. It is characterized by being able to minimize the phenomenon of deterioration.

In addition, the second insulating film having a two-layer structure can form a thick organic insulating film, thereby making it possible to effectively improve the step difference.

As shown in the figure, a gate line 216 and a data line 217 are formed on the array substrate 210 of the second embodiment to be arranged vertically and horizontally on the array substrate 210 to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed.

In this case, a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in an edge region of the array substrate 210. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad The line 217p receives a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

For reference, reference numerals 240a 'and 240b' denote data pad part open holes and gate pad part open holes, respectively, through the data pad part open holes 240a 'and the gate pad part open holes 240b', respectively. A portion of the data pad electrode 227p and the gate pad electrode 226p are exposed to the outside.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the pixel electrode 218. In addition, the thin film transistor includes an active pattern 224 that forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

The active pattern 224 according to the present invention is formed of an amorphous silicon thin film, and is formed in an island shape only on the gate electrode 221 to reduce the off current of the thin film transistor.

A portion of the source electrode 222 extends in one direction to form a portion of the data line 217, and a portion of the drain electrode 223 extends toward the pixel region to be electrically connected to the pixel electrode 218. do.

In this case, a portion of the front gate line 216 ′ overlaps a portion of the storage electrode 219 therebetween with a first insulating layer (not shown) therebetween to form a storage capacitor Cst.

Here, the gate electrode 221 and the gate lines 216 and 216 'of the present invention, which are made of an opaque conductive material, are made of a transparent conductive material under the gate electrode 221 and the gate lines 216 and 116, respectively. A gate electrode pattern (not shown) and a gate line pattern (not shown) are patterned in the same form as ''.

In this case, the pixel electrode 218 is formed on the same layer as the gate electrode pattern and the gate line pattern, and is made of the same transparent conductive material constituting the gate electrode pattern and the gate line pattern.

In addition, the gate electrode 221, the pixel electrode 218, and the pad part electrodes 226p and 227p of the present invention are patterned in one mask process, so that the array substrate 210 can be manufactured through a total of four mask processes. In addition, a second insulating film (not shown) having a two-layer structure of an inorganic insulating film and an organic insulating film is formed on the pixel electrode 218 to prevent short circuit defects caused by foreign substances and to improve a step. It demonstrates in detail through the manufacturing method of a display apparatus.

9A to 9D are cross-sectional views sequentially illustrating a manufacturing process along lines VIIIa-VIIIa ', VIIIb-VIIIb, VIIIc-VIIIc', and VIIId-VIIId 'of the array substrate illustrated in FIG. A process of manufacturing an array substrate of a pixel portion to be included is shown, and a process of manufacturing an array substrate of a data pad portion and a gate pad portion is shown on the right.

As shown in FIG. 9A, a gate electrode 221, a gate line 216 ′, and a pixel electrode 218 are formed in a pixel portion of the array substrate 210 made of a transparent insulating material such as glass, and formed in the gate pad portion. The gate pad line 216p is formed.

In addition, a data pad electrode 227p and a gate pad electrode 226p are formed in each of the data pad portion and the gate pad portion of the array substrate 210.

In this case, the gate electrode 221 and the gate line 216 'are made of a transparent conductive material below the gate electrode pattern 230 patterned in the same shape as the gate electrode 221 and the gate line 216', respectively. And a gate line pattern 230 " are formed.

In this case, the pixel electrode 218 is formed on the same layer as the gate electrode pattern and the gate line pattern, and is made of the same transparent conductive material constituting the gate electrode pattern and the gate line pattern.

In this case, reference numeral 216 'denotes a gate line of the front end of the corresponding pixel, and the gate line and the front gate line 216' of the corresponding pixel are formed in the same manner.

Here, the gate electrode 221, the gate line 216 ′, the pixel electrode 218, the gate pad line 216p, and the pad part electrodes 227p and 226p are the same as the first embodiment. After the film and the second conductive film are deposited on the entire surface of the array substrate 210, the film is simultaneously formed in one mask process (first mask process) using a half-tone mask.

In this case, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or the like may be used to form the pixel electrode 218 and the pad part electrodes 227p and 226p. In addition, the first conductive film may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

In addition, the second conductive layer may be formed of a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form the gate electrode 221, the gate line 216 ′, and the gate pad line 216p. Include.

Next, as shown in FIG. 9B, an array substrate on which the gate electrode 221, the gate line 216 ′, the pixel electrode 218, the gate pad line 216p, and the pad part electrodes 227p and 226p are formed. The first insulating layer 215b, the amorphous silicon thin film, and the n + amorphous silicon thin film are formed on the entire surface of the 210 and then selectively removed through a photolithography process (a second mask process). A data pad part contact hole 240a and a gate pad part contact hole 240b that form an active pattern 224 made of a silicon thin film and simultaneously expose a portion of the data pad electrode 227p and the gate pad electrode 226p, respectively. To form.

In this case, a sixth n + amorphous silicon thin film pattern 250 ″ ″ ″ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 224 remains on the active pattern 224.

In addition, a portion of the first insulating layer 215a formed thereon is removed from the pixel electrode 218 to expose the surface of the pixel electrode 218 of the pixel region.

Here, the active pattern 224 according to the present invention is formed in an island shape only on the gate electrode 221 with the first insulating layer 215a therebetween, and the active pattern 224 is the same as the first embodiment described above. The pattern 224, the data pad part contact hole 240a and the gate pad part contact hole 240b are simultaneously formed in one mask process (second mask process) using a half-tone mask.

Next, as shown in FIG. 9C, after depositing a third conductive layer on the entire surface of the array substrate 210 on which the active pattern 224 is formed, the third conductive layer is formed by using a photolithography process (third mask process). The source electrode 222 and the drain electrode 223 formed of the third conductive layer are formed in the pixel portion of the array substrate 210 by removing a portion of the film, and the data line portion of the array substrate 210 is A data line 217 made of a third conductive film is formed.

The data pad of the array substrate 210 may be formed of the third conductive layer through the third mask process, and may be electrically connected to the data pad electrode 227p through the data pad contact hole. Line 217p is formed.

In addition, a storage electrode 219 formed of the three conductive layers and electrically connected to the pixel electrode 218 is formed on the gate line 216 ′, and the storage electrode 219 is formed on a lower portion thereof. The storage capacitor Cst is formed by overlapping a portion of the gate line 216 ′ with an insulating layer 215a therebetween.

In this case, in the sixth n + amorphous silicon thin film pattern formed on the active pattern 224, a predetermined region is removed through the third mask process so that the active pattern 224 and the source / drain electrodes 222 and 223 are removed. An ohmic contact layer 225 is formed to ohmic contact therebetween.

Here, the third conductive layer is made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, etc. to form the source electrode 222, the drain electrode 223, and the data line 217. Can be.

In the data line 217 according to the present invention, there is no tail of an active pattern made of an amorphous silicon thin film under the signal line, and thus there is no signal interference of the data line 217 by the tail of the active pattern.

As shown in FIG. 9D, second insulating films 215b and 215b 'are formed on the entire surface of the array substrate 210 and then the second insulating film 215b is formed by using a photolithography process (fourth mask process). 215b ') by selectively removing a portion of the data pad electrode 227p and the gate pad electrode 226p to respectively expose the data pad part open hole 240a' and the gate pad part open hole 240b '. Will be formed.

At this time, the second insulating films 215b and 215b 'of the second embodiment have a two-layer structure of an inorganic insulating film 215b and an organic insulating film 215b'.

Here, the inorganic insulating film 215b includes an inorganic insulating material such as a silicon nitride film or a silicon oxide film, and the organic insulating film 215b 'includes an organic insulating material such as photoacryl or benzocyclobutene (BCB). .

In the second exemplary embodiment of the present invention, the second insulating films 215b and 215b 'are formed on the pixel electrode 218 with a thickness of 2000 GPa or more, so that even if foreign matter occurs in the cell gap, the pixel electrode of the array substrate 210 is formed. It is possible to effectively prevent a short circuit between the 218 and the common electrode of the color filter substrate (not shown).

In this case, the inorganic insulating film 215b may be thinned to about 100 to 500 mW in order to reduce the cell gap of the liquid crystal display device to reduce the response time of the liquid crystal, and as the thickness of the inorganic insulating film 215b is reduced. Afterimage can be improved.

In addition, since the organic insulating layer 215b 'is formed of an organic insulating layer having a low dielectric constant, the organic insulating layer 215b' may be formed to have a sufficiently thick thickness, thereby effectively improving the level difference of the array substrate 210.

The array substrates of the first and second embodiments configured as described above are bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor, the gate line, and the data are attached to the color filter substrate. A black matrix is formed to prevent light leaking into the lines, and a color filter is formed to realize red, green, and blue colors.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

In the first and second embodiments, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern is described as an example, but the present invention is not limited thereto, and the present invention is not limited thereto. The same applies to the polysilicon thin film transistors used.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the liquid crystal display and the method of manufacturing the same according to the present invention do not have a tail of the active pattern, and thus there is no signal interference of the data line, and the aperture ratio increases by the tail width of the active pattern.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention does not generate wave noise provides an effect that can produce a high-quality liquid crystal display device.

In addition, the liquid crystal display according to the present invention and a method of manufacturing the same can form an insulating film having a two-layer structure of an inorganic insulating film and an organic insulating film on a pixel electrode, thereby preventing short-circuit defects caused by foreign substances and at the same time, effectively improving the afterimage and the step. Will be.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention can shorten the response time of the liquid crystal by minimizing the thickness of the inorganic insulating film.

Claims (36)

Providing a first substrate divided into a pixel portion, a first pad portion, and a second pad portion; Forming a gate electrode, a gate line, and a pixel electrode on the pixel portion of the first substrate through a first mask process; Forming an island-type active pattern with a first insulating layer interposed on the gate electrode through a second mask process, and forming an n + amorphous silicon thin film pattern on the active pattern; Forming a source electrode and a drain electrode on the pixel portion of the first substrate through a third mask process, and forming a data line crossing the gate line to define a pixel region; Forming a second insulating film on the first substrate through a fourth mask process; And And attaching the first substrate and the second substrate to each other. The method of claim 1, further comprising forming a data pad electrode on the first pad portion of the first substrate through the first mask process. The method of claim 2, further comprising forming a gate pad electrode on the second pad portion of the first substrate through the first mask process. 4. The liquid crystal display of claim 3, further comprising forming a gate pad line electrically connected to the gate pad electrode in a second pad portion of the first substrate through the first mask process. Method of manufacturing the device. The method of claim 3, wherein the pixel electrode, the data pad electrode, and the gate pad electrode are formed of a first conductive film made of a transparent conductive material. The method of claim 4, wherein the gate electrode, the gate line, and the gate pad line are formed of a second conductive film made of an opaque conductive material. The method of claim 5, further comprising: forming a gate electrode pattern and a gate line pattern formed of the first conductive layer under the gate electrode and the gate line and patterned in the same form as the gate electrode and the gate line. Method of manufacturing a liquid crystal display device characterized in that. 3. The method of claim 2, further comprising forming a data pad part contact hole exposing a part of the data pad electrode by removing a part of the first insulating layer through the second mask process. Method of manufacturing a liquid crystal display device. 4. The method of claim 3, further comprising forming a gate pad contact hole for exposing a portion of the gate pad electrode by removing a portion of the first insulating layer through the second mask process. Method of manufacturing a liquid crystal display device. The method of claim 1, wherein a partial region of the first insulating layer is removed through the second mask process to expose the pixel electrode of the pixel region. The liquid crystal display of claim 1, further comprising forming a storage electrode on the pixel electrode to overlap a portion of the pixel electrode to form a storage capacitor through the third mask process. Manufacturing method. The method of claim 8, further comprising: forming a data pad line formed on the first pad portion of the first substrate through the third mask process, and electrically connected to the data pad electrode through the data pad portion contact hole. Method of manufacturing a liquid crystal display device further comprising. The method of claim 1, wherein the n + amorphous silicon thin film pattern is formed in the same shape as the active pattern. The method of claim 1, further comprising exposing a portion of the active pattern by removing a portion of the n + amorphous silicon thin film pattern through the third mask process. 12. The method of claim 11, wherein a part of the pixel electrode is electrically connected to the drain electrode, and the other part is electrically connected to the storage electrode. 3. The method of claim 2, further comprising forming a data pad part open hole exposing a part of the data pad electrode by removing a part of the second insulating layer through the fourth mask process. Method of manufacturing a liquid crystal display device. 4. The method of claim 3, further comprising forming a gate pad portion open hole exposing a portion of the gate pad electrode by removing a portion of the second insulating layer through the fourth mask process. Method of manufacturing a liquid crystal display device. The method of claim 1, wherein the forming of the second insulating film Forming an inorganic insulating film made of an inorganic insulating material on the first substrate; And And forming an organic insulating film formed of an organic insulating material on the first substrate. 19. The method of claim 18, wherein the inorganic insulating film is formed to a thickness of 100 to 500 kHz. 19. The method of claim 18, wherein the organic insulating material comprises photoacryl and benzocyclobutene. A first substrate divided into a pixel portion, a first pad portion, and a second pad portion; A gate electrode and a gate line formed in the pixel portion of the first substrate; A gate electrode pattern and a gate line pattern formed under the gate electrode and the gate line and patterned in the same form as the gate electrode and the gate line; An active pattern formed on the gate electrode with the first insulating layer interposed therebetween, the active pattern having an island shape having a smaller width than the gate electrode; An ohmic contact layer formed on the first substrate and formed on the source / drain regions of the active pattern; A source / drain electrode formed on the pixel portion of the first substrate and electrically connected to the source / drain region of the active pattern through the ohmic contact layer; A data line formed in the pixel portion of the first substrate and defining a pixel region crossing the gate line; A pixel electrode formed of a first conductive layer constituting the gate electrode pattern and the gate line pattern and formed on the same layer as the gate electrode pattern and the gate line pattern; A second insulating layer formed on the first substrate and covering the pixel electrode; And And a second substrate bonded to the first substrate. 22. The liquid crystal display device according to claim 21, further comprising a data pad electrode formed of a first conductive film constituting the pixel electrode and formed on the first pad portion of the first substrate. 23. The liquid crystal display device according to claim 22, further comprising a gate pad electrode formed of the first conductive film and formed on the second pad portion of the first substrate. 24. The liquid crystal display device according to claim 23, further comprising a gate pad line formed on the second pad portion of the first substrate and electrically connected to the gate pad electrode. The liquid crystal display of claim 23, wherein the first conductive layer is made of a transparent conductive material. 25. The liquid crystal display of claim 24, wherein the gate electrode, the gate line, and the gate pad line are formed of a second conductive film made of an opaque conductive material. 23. The liquid crystal display of claim 22, further comprising a data pad contact hole to remove a portion of the first insulating layer to expose a portion of the data pad electrode. 24. The liquid crystal display device of claim 23, further comprising a gate pad portion contact hole to remove a portion of the first insulating layer to expose a portion of the gate pad electrode. 22. The liquid crystal display of claim 21, further comprising a storage electrode formed on the pixel electrode and overlapping a portion of the pixel electrode to form a storage capacitor. 28. The liquid crystal display of claim 27, further comprising a data pad line formed on the first pad portion of the first substrate and electrically connected to the data pad electrode through the data pad portion contact hole. Device. 30. The liquid crystal display device according to claim 29, wherein a part of the pixel electrode is electrically connected to the drain electrode and another part is electrically connected to the storage electrode. 23. The liquid crystal display of claim 22, further comprising a data pad portion open hole through which a portion of the second insulating layer is removed to expose a portion of the data pad electrode. 24. The liquid crystal display of claim 23, further comprising a gate pad portion open hole through which a portion of the second insulating layer is removed to expose a portion of the gate pad electrode. 22. The liquid crystal display device according to claim 21, wherein the second insulating film has a two-layer structure of an inorganic insulating film made of an inorganic insulating material and an organic insulating film made of an organic insulating material. 35. The liquid crystal display device according to claim 34, wherein the inorganic insulating film has a thickness of 100 to 500 Å. 35. The liquid crystal display device according to claim 34, wherein the organic insulating material comprises photoacryl and benzocyclobutene.

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