KR20090061469A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A liquid crystal display device and a manufacturing method thereof are provided to prevent the leakage of light caused by the misalignment between an array substrate and a color filter substrate. A method of manufacturing a liquid crystal display device comprises the following steps of: providing the first substrate; forming an intaglio pattern by etching a portion of the first substrate through the first mask process; forming a black matrix(106) within the intaglio pattern of the first substrate; forming the first insulating layer on the first substrate; forming source/drain electrodes(122, 123), a data line(117) and a pixel electrode(118) on the black matrix of the first substrate through the second mask process; and forming an active pattern on the black matrix through the third mask process.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to reduce the number of masks to simplify the manufacturing process, improve the yield and at the same time minimize the margin of the black matrix liquid crystal display device and It relates to a manufacturing method.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 using a photolithography process (first mask process).

Next, as shown in FIG. 2B, the first insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed. The active pattern 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same shape as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 2C, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (third mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process, thereby forming an ohmic − between the active pattern 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25 'is formed.

Next, as shown in FIG. 2D, a second insulating film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process (fourth mask). The contact hole 40 exposing a part of the drain electrode 23 is formed by removing a part of the second insulating layer 15b through the process).

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned by using a photolithography process (a fifth mask process) through the contact hole 40. The pixel electrode 18 electrically connected to the drain electrode 23 is formed.

As described above, fabrication of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active pattern, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development. As a result, many photolithography processes reduce the production yield, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display increases in proportion.

At this time, by forming the active pattern and the source / drain electrodes in a single mask process using a diffraction mask, a technique for manufacturing an array substrate using a total of four mask processes has been developed.

However, the liquid crystal display of the above structure is patterned by the diffraction mask, and thus patterned the active pattern and the source / drain electrodes through two etching processes. The active pattern remains.

The active pattern is formed of a pure amorphous silicon thin film, wherein the active pattern under the data line is exposed to the backlight light below the gate line, ie, except for the portion covered by the gate electrode and the gate line, thereby being exposed by the backlight light. Photocurrent is generated. At this time, due to the minute flickering of the backlight light, the amorphous silicon thin film reacts finely, and the activation and deactivation states are repeated, thereby causing a change in the photocurrent. The photocurrent component is coupled with a signal flowing to a neighboring pixel electrode to distort the movement of the liquid crystal located in the pixel electrode. As a result, wavy noise in which wavy thin lines appear on the screen of the liquid crystal display is generated.

In addition, the active pattern disposed below the data line protrudes a predetermined distance to both sides of the data line, so that the opening ratio of the liquid crystal display device is reduced as the opening area of the pixel portion is eroded by the protruding distance.

On the other hand, the array substrate thus manufactured is bonded to the upper color filter substrate in a state where a constant cell gap is maintained by the column spacer to form a liquid crystal display device.

In this case, as described above, the color filter substrate distinguishes between the color filter composed of a plurality of sub-color filters that implement red, green, and blue colors on the transparent color filter substrate and the sub-color filter and transmits the liquid crystal layer. It consists of a black matrix to block light, and a transparent common electrode to apply a voltage to the liquid crystal layer.

Here, the black matrix is patterned on the boundary region of the pixels to block leakage of light generated from the backlight of the lower portion of the liquid crystal display, and to prevent color mixing of adjacent pixels, and bonding of the color filter substrate and the array substrate. Due to misalignment that occurs during the time to have a predetermined margin to improve the light leakage phenomenon. Such margin of the black matrix is a factor that lowers the aperture ratio of the liquid crystal display device, and improvement thereof is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which fabricate an array substrate having a top gate structure in three mask processes.

Another object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same, which can realize a high brightness by enlarging the opening area and at the same time improve light leakage defects caused by misalignment.

It is still another object of the present invention to provide a liquid crystal display device and a method of manufacturing the same, which can realize high quality without generation of wave noise.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display of the present invention comprises a first substrate having a recessed pattern by etching a portion of the area; A black matrix formed in the intaglio pattern of the first substrate and formed of a first conductive film; A first insulating film formed on the first substrate; A pixel electrode formed on the black matrix of the first substrate and a source / drain electrode and a data line formed of a third conductive film; A gate electrode formed of a fourth conductive film in an active pattern formed on the black matrix and a second insulating film interposed therebetween; A gate line positioned above the black matrix and defining a pixel area crossing the data line; And a second substrate bonded to and opposed to the first substrate.

In addition, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate; Etching a portion of the first substrate through a first mask process to form an intaglio pattern, and then forming a black matrix in the intaglio pattern of the first substrate; Forming a first insulating film on the first substrate; Forming a source / drain electrode, a data line, and a pixel electrode on the black matrix of the first substrate through a second mask process; Forming an active pattern on the black matrix through a third mask process, and forming a gate electrode with a second insulating layer interposed therebetween; Forming a gate line on the black matrix through the third mask process and crossing the data line to define a pixel area; And bonding the first substrate and the second substrate to each other.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost. In particular, the liquid crystal display according to the present invention and a method of manufacturing the same are maximized by manufacturing an array substrate by three mask processes.

In addition, the liquid crystal display and the method of manufacturing the same according to the present invention can prevent the light leakage due to misalignment when the array substrate and the color filter substrate are bonded by forming a black matrix on the lower array substrate. As a result, the yield is improved.

In addition, the liquid crystal display device and the method of manufacturing the same according to the present invention provide an effect of improving the aperture ratio by minimizing the margin of the black matrix.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention does not generate wave noise and light leakage provides an effect that can produce a high-quality liquid crystal display device.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 3 illustrates one pixel including a gate pad part, a data pad part, and a pixel part thin film transistor for convenience of description. It is shown.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 according to an embodiment of the present invention, which are arranged vertically and horizontally on the array substrate 110 to define a pixel region. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. .

In this case, the thin film transistor according to an exemplary embodiment of the present invention has a top gate structure in which the gate electrode 121 is positioned on the source electrode 122, the drain electrode 123, and the active pattern 124. do.

In addition, the array substrate 110 according to an exemplary embodiment of the present invention may include a gate wiring, that is, the gate electrode 121, a gate line 116, and a data wiring, that is, the source electrode 122, the drain electrode 123, and the data. A black matrix 106 made of an opaque conductive material such as chromium is formed below the line 117, and the black matrix 106 is configured to transmit light through the thin film transistor, the gate wiring, and the data wiring. It is to block the work.

In this case, a portion of the gate line 116 positioned at the front end may overlap a portion of the pixel electrode 118 therebetween with a first insulating layer (not shown) therebetween to form a storage capacitor. The storage capacitor serves to maintain a constant voltage applied to the liquid crystal capacitor until the next signal. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. In general, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is input and is leaked. It disappears. Therefore, in order to maintain the applied voltage, the storage capacitor must be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stability of gray scale display and reduction of flicker and afterimage in addition to signal retention.

A gate pad line 116p and a data pad line 117p electrically connected to the gate line 116 and the data line 117 are formed in an edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

Here, the liquid crystal display according to the exemplary embodiment of the present invention uses a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask to include a diffraction mask) and uses the data line and the pixel electrode once. By forming a mask process, the active pattern and the gate wiring are formed in one mask process, so that an array substrate can be manufactured by a total of three mask processes.

In this case, in the liquid crystal display according to the exemplary embodiment of the present invention, a black matrix is disposed at a lowermost layer and a source / drain electrode, an active pattern, and a second are sequentially formed on the lower layer to form the active pattern and the gate wiring in one mask process. The top gate method in which an insulating film, that is, a gate insulating film is formed, and a gate electrode is formed on the uppermost layer is applied.

In addition, the black matrix according to an embodiment of the present invention does not have a step by etching a portion of the array substrate made of an insulating material such as glass and then forming it in the etched array substrate using a lift off process. This will be described in detail through the manufacturing method of the following liquid crystal display.

4A to 4C are cross-sectional views sequentially illustrating a manufacturing process along lines IIIa-IIIa ', IIIb-IIIb, and IIIc-IIIc of the array substrate illustrated in FIG. 3, and a process of manufacturing an array substrate of a pixel portion is shown on the left side. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

5A to 5C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

4A and 5A, a black matrix 106 according to an embodiment of the present invention is formed of an opaque metal material such as chromium in an etched partial region of the array substrate 110 made of a transparent insulating material such as glass. ).

In this case, the black matrix 106 may not have a step by etching a portion of the array substrate 110 made of an insulating material such as glass and then forming it in the etched array substrate 110 using a lift-off process. This will be described in detail with reference to the drawings.

6A through 6D are cross-sectional views illustrating a first mask process according to an exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 4A and 5A.

As shown in FIG. 6A, a first mask pattern 170 is formed on the array substrate 110 made of an insulating material such as glass.

In this case, the first mask pattern 170 may be formed of a predetermined photoresist, and the thin film transistor region, gate wiring, and data wiring, on which the black matrix is to be formed, are formed to form the black matrix on the lower array substrate 110. It is characterized in that the light irradiated to the area to be transmitted is patterned. This is because a positive type photoresist is used, and the present invention is not limited thereto, and a negative type photoresist may be used.

Subsequently, as shown in FIG. 6B, a portion of the array substrate 110 is etched using hydrofluoric acid (HF) using the first mask pattern 170 as a mask to form a predetermined portion of the array substrate 110. An intaglio pattern H is formed.

In this case, the intaglio pattern H is formed in the thin film transistor region where the black matrix is to be formed, the region in which the gate wiring and the data wiring are located, and is formed by isotropic etching by hydrofluoric acid HF. The array substrate 110 may be over-etched to the bottom of the first mask pattern 170.

Next, as illustrated in FIG. 6C, the first conductive layer 190 is deposited on the entire surface of the array substrate 110 including the intaglio pattern H while the first mask pattern 170 remains. do.

In this case, the first conductive layer 190 may be made of an opaque metal material such as chromium to form a black matrix according to an embodiment of the present invention.

Thereafter, as illustrated in FIG. 6D, the black mask 106 according to the embodiment of the present invention is formed in the intaglio pattern by removing the first mask pattern through a lift-off process. The first conductive layer formed on the first mask pattern except for the first mask pattern is removed together with the first mask pattern.

In the lift-off process, the metal material is deposited by depositing a conductive metal material such as the first conductive layer to a predetermined thickness on a photosensitive material such as the first mask pattern, and then depositing the same in a solution such as a stripper. In the process of removing the photosensitive material together with the metal material, the metal material formed inside the intaglio pattern is not removed to form the black matrix 106.

As described above, in the exemplary embodiment of the present invention, the black matrix 106 is formed by etching the partial region of the array substrate 110 and then forming the black matrix 106 in a predetermined intaglio pattern by using a lift-off process. There is no step with respect to the surface of 110.

In addition, as the black matrix 106 is formed on the lower array substrate 110, it is not necessary to consider the margin of the black matrix 106, thereby increasing the opening area of the pixel, thereby providing an effect of substantially improving the opening ratio. do.

In addition, even when misalignment occurs when the color filter substrate and the array substrate 110 are bonded together, an opaque conductive material is formed in the thin film transistor region of the array substrate 110 and the lower portion of the gate wiring and the data wiring according to the embodiment of the present invention. The black matrix 106 is formed to block the leakage of light generated from the lower backlight.

Next, as shown in FIGS. 4B and 5B, the first insulating film 115a, the second conductive film, the third conductive film, and the n + amorphous silicon thin film are formed on the entire surface of the array substrate 110 on which the black matrix 106 is formed. Deposit.

Thereafter, the second conductive film, the third conductive film, and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process), thereby forming the second conductive film in the pixel region of the array substrate 110. A pixel electrode 118 is formed, and a source electrode 122, a drain electrode 123, and a data line 117 formed of the third conductive layer are formed in the pixel portion of the array substrate 110.

In addition, the data pad line 117p formed of the third conductive layer is formed on the data pad portion of the array substrate 110 by using the second mask process.

In this case, the data line 117 including the source electrode 122 and the data pad line 117p are formed under the second conductive layer and include the data line 117 and the data pad including the source electrode 122. The first conductive film pattern 130 ′ and the second conductive film pattern 130 ″ patterned in the same shape as the line 117p are formed.

The data line 117 including the source electrode 122, the drain electrode 123, and the data pad line 117p are formed of the n + amorphous silicon thin film and include the source electrode 122. The first ohmic contact pattern 125na and the second ohmic contact pattern 125nb patterned in the same manner as the 117, the drain electrode 123, and the data pad line 117p are formed.

Here, the source / drain electrodes 122 and 123, the data line 117, and the pixel electrode 118 according to the exemplary embodiment of the present invention use a half-tone mask to process a single mask (second mask process). It is possible to form simultaneously through, with reference to the drawings will be described in detail the second mask process.

7A to 7G are cross-sectional views illustrating a second mask process according to an exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 4B and 5B.

As shown in FIG. 7A, the first insulating film 115a, the second conductive film 130, the third conductive film 140, and the n + amorphous silicon thin film are formed on the entire surface of the array substrate 110 on which the black matrix 106 is formed. Forms 125.

In this case, the second conductive layer 130 is a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a pixel electrode. It may be made of.

In addition, the third conductive layer 140 may include aluminum (Al), aluminum alloy, tungsten (W), and copper (Cu) to form a source electrode, a drain electrode, and a data line. It may be made of a low resistance opaque conductive material such as, chromium, molybdenum (Mo) and molybdenum alloy (Moally).

As shown in FIG. 7B, after forming the second photoresist layer 270 made of photosensitive material such as photoresist on the entire surface of the array substrate 110, the half-tone mask 180 according to the embodiment of the present invention. The light is selectively irradiated to the second photoresist layer 270 through the.

In this case, the half-tone mask 180 has a first transmission region I for transmitting all of the irradiated light, a second transmission region II for transmitting only a part of the light, and a part of blocking the light, and a blocking for blocking all the irradiated light. The region III is provided, and only the light passing through the half-tone mask 180 is irradiated to the second photosensitive layer 270.

Subsequently, after the second photoresist layer 270 exposed through the half-tone mask 180 is developed, as shown in FIG. 7C, through the blocking region III and the second transmission region II, as shown in FIG. The first photoresist pattern 270a to the fourth photoresist pattern 270d having a predetermined thickness remain in the region where all the light is blocked or partially blocked, and the second photoresist in the first transmission region I through which all the light is transmitted. This is completely removed to expose the surface of the n + amorphous silicon thin film 125.

In this case, the first photoresist pattern 270a to the third photoresist pattern 270c formed in the blocking region III are formed thicker than the fourth photoresist pattern 270d formed through the second transmission region II. In addition, the second photoresist film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a photoresist.

Next, as shown in FIG. 7D, the second conductive film, the third conductive film, and n + formed under the first photosensitive film pattern 270a to the fourth photosensitive film pattern 270d formed as a mask are used as a mask. When the amorphous silicon thin film is selectively removed, the drain electrode pattern including the data line 117 including the source electrode 122 made of the third conductive layer and the drain electrode may be formed in the pixel portion of the array substrate 110. 140 ').

In addition, a data pad line 117p formed of the third conductive layer is formed in the data pad portion of the array substrate 110, and a pixel electrode formed of the second conductive layer is formed in the pixel region of the array substrate 110. 118 is formed.

In this case, the second conductive layer is formed under the data line 117 including the source electrode 122, the drain electrode pattern 140 ′, and the data pad line 117p and includes the source electrode 122. The first conductive layer pattern 130 ′ and the pixel electrode 118 and the second conductive layer pattern 130 patterned in the same shape as the data line 117, the drain electrode pattern 140 ′, and the data pad line 117p. ") Is formed.

Further, the n + amorphous silicon thin film is formed on the data line 117 including the source electrode 122, the drain electrode pattern 140 ′, and the data pad line 117p and includes the source electrode 122. The first ohmic contact pattern 125na, the first n + amorphous silicon thin film pattern 125 ′, and the second patterned pattern having the same shape as the data line 117, the drain electrode pattern 140 ′, and the data pad line 117p. An n + amorphous silicon thin film pattern 125 "is formed.

Subsequently, as shown in FIG. 7E, an ashing process of removing a portion of the first to fourth photoresist patterns may be performed to completely remove the fourth photoresist pattern of the second transmission region II. .

In this case, the first photoresist pattern to the third photoresist pattern correspond to the blocking region III by the fifth photoresist pattern 170a 'through the seventh photoresist pattern 170c', in which the thickness of the fourth photoresist pattern is removed. Only the upper portion of the data line 117 including the source electrode 122, the drain electrode region, and the upper portion of the data pad line 117p remain.

7F and 7G, the first n + amorphous silicon thin film pattern and the drain electrode pattern are formed by using the remaining fifth photoresist pattern 170a ′ through seventh photoresist pattern 170c ′ as a mask. By removing a portion, the drain electrode 123 formed of the third conductive layer is formed in the pixel portion of the array substrate 110, and the pixel electrode 118 of the pixel region is exposed.

In this case, a second ohmic contact pattern 125nb formed of the n + amorphous silicon thin film and substantially patterned in the same shape as the drain electrode 123 is formed on the drain electrode 123.

Next, as shown in FIGS. 4C and 5C, an active pattern (pixel pattern) of the array substrate 110 on which the source / drain electrodes 122 and 123, the data line 117, and the pixel electrode 118 are formed is formed. A gate electrode 121 and a gate line 116 are formed in a state where the second insulating film 115b is interposed therebetween, and a gate pad line 116p is formed in the gate pad portion of the array substrate 110. ).

In this case, the active pattern 124, the gate electrode 121, the gate line 116, and the gate pad line 116p may include the source / drain electrodes 122 and 123, the data line 117, and the pixel electrode 118. ) Is formed by depositing an amorphous silicon thin film, a second insulating film 115b, and a fourth conductive film on the entire surface of the array substrate 110 on which is formed) and then selectively patterning the same through a photolithography process (third mask process).

In this case, the second n + amorphous silicon thin film pattern on the data pad line 116p is removed through the third mask process, and a part of the first and second ohmic contact patterns is removed to form the active pattern 124. An ohmic contact layer 125n that ohmic-contacts between the source / drain region of the NEL and the source / drain electrodes 122 and 123 is formed.

Here, as the fourth conductive film, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy may be used. The fourth conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

In this case, the thin film transistor according to the embodiment of the present invention has a top gate structure in which the gate electrode 121 is positioned on the array substrate 110 on which the source / drain electrodes 122 and 123 and the active pattern 124 are formed. It characterized in that it has, and with reference to the drawings will be described in detail the third mask process.

8A through 8C are cross-sectional views illustrating a third mask process according to an exemplary embodiment of the present invention in the array substrate illustrated in FIGS. 4C and 5C.

As shown in FIG. 8A, the amorphous silicon thin film 120 and the second insulating film are formed on the entire surface of the array substrate 110 on which the source / drain electrodes 122 and 123, the data line 117, and the pixel electrode 118 are formed. 115b and the fourth conductive film 150 are formed.

In this case, the fourth conductive layer 150 may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form the gate electrode, the gate line and the gate pad line. . The fourth conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

As illustrated in FIG. 8B, a predetermined second mask pattern 370 is formed on the array substrate 110.

In this case, the second mask pattern 370 may be formed of a predetermined photoresist and irradiated to the gate electrode region, the gate line region, and the gate pad line region to form an active pattern and a gate wiring on the lower array substrate 110. It is characterized in that the light is patterned to block. This is because a positive type photoresist is used, and the present invention is not limited thereto, and a negative type photoresist may be used.

Subsequently, as shown in FIG. 8C, the amorphous silicon thin film, the second insulating film 115b, the fourth conductive film, and a portion of the n + amorphous silicon thin film are selectively removed by using the second mask pattern 370 as a mask. A gate electrode made of the fourth conductive layer is formed while the active pattern 124 made of the amorphous silicon thin film is formed on the pixel portion of the array substrate 110 and the second insulating layer 115b is interposed thereon. 121).

In addition, a portion of the pixel electrode 118 overlaps with the pixel portion of the array substrate 110 to form a gate line 116 constituting a storage capacitor with the second insulating layer 115b therebetween, and the array A gate pad line 116p formed of the fourth conductive layer is formed in the gate pad portion of the substrate 110.

In this case, the amorphous silicon thin film is formed under the gate line 116 and the gate pad line 116p with the second insulating film 115b interposed therebetween. The first amorphous silicon thin film pattern 120 ′ and the second amorphous silicon thin film pattern 120 ″ patterned in the same shape as 116p are formed.

In addition, a second n + amorphous silicon thin film pattern on the data pad line 116p is removed through the third mask process, and a part of the first and second ohmic contact patterns is removed to form the active pattern 124. ) Forms an ohmic contact layer 125n that ohmic-contacts between the source / drain region and the source / drain electrodes 122 and 123.

The array substrate according to the embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the color filter substrate includes light through the thin film transistor, the gate line, and the data line. Black matrix to prevent leakage and color filter for red, green and blue color are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

In addition, the embodiment of the present invention has been described using an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern, for example, but the present invention is not limited thereto, and the present invention is polycrystalline using a polycrystalline silicon thin film as the active pattern. The same applies to silicon thin film transistors.

In addition, the present invention can be used not only in liquid crystal display devices, but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

4A to 4C are cross-sectional views sequentially showing manufacturing processes taken along lines IIIa-IIIa ', IIIb-IIIb and IIIc-IIIc of the array substrate shown in FIG.

5A to 5C are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

6A through 6D are cross-sectional views illustrating a first mask process according to an embodiment of the present invention in the array substrate shown in FIGS. 4A and 5A.

7A to 7G are cross-sectional views illustrating a second mask process according to an embodiment of the present invention in the array substrate shown in FIGS. 4B and 5B.

8A to 8C are cross-sectional views illustrating a third mask process according to an embodiment of the present invention in the array substrate shown in FIGS. 4C and 5C.

** Explanation of symbols for main parts of drawings **

106: black matrix 110: array substrate

116: gate line 117: data line

118: pixel electrode 121: gate electrode

122 source electrode 123 drain electrode

124: active pattern

Claims (15)

Providing a first substrate; Etching a portion of the first substrate through a first mask process to form an intaglio pattern, and then forming a black matrix in the intaglio pattern of the first substrate; Forming a first insulating film on the first substrate; Forming a source / drain electrode, a data line, and a pixel electrode on the black matrix of the first substrate through a second mask process; Forming an active pattern on the black matrix through a third mask process, and forming a gate electrode with a second insulating layer interposed therebetween; Forming a gate line on the black matrix through the third mask process and crossing the data line to define a pixel area; And And attaching the first substrate and the second substrate to each other. The method of claim 1, wherein the first mask process Forming a first mask pattern on the first substrate; Etching a portion of the first substrate using the first mask pattern as a mask to form an intaglio pattern in a gate line, a data line, and a thin film transistor region; Forming a first conductive film on the entire surface of the first substrate; And And selectively removing the first mask pattern and the first conductive layer to form a black matrix formed of the first conductive layer in the intaglio pattern. The method of claim 2, wherein the first substrate is etched using fluorine. The method of claim 2, wherein the first mask pattern and the first conductive layer are selectively removed by using a lift-off process. The method of claim 1, wherein the second mask process Forming a second conductive layer, a third conductive layer, and an n + amorphous silicon thin film on the first substrate; A first photosensitive film pattern on the first substrate by applying a mask having a first transmission region that transmits all of the irradiated light, a second transmission region that transmits only a portion of the light, and a portion that blocks a portion of the light, and a blocking region that blocks all the irradiated light; Forming a fourth photoresist pattern; A source formed with the third conductive layer on the black matrix of the first substrate by selectively removing the second conductive layer, the third conductive layer, and the n + amorphous silicon thin film using the first to fourth photosensitive layer patterns as a mask. Forming an electrode, a data line and a drain electrode pattern, and forming a pixel electrode formed of the second conductive layer under the drain electrode pattern; Removing the fourth photoresist pattern through an ashing process and simultaneously removing a portion of the first to third photoresist patterns to form a fifth to seventh photoresist pattern; And The drain electrode pattern and the n + amorphous silicon thin film are selectively removed using the fifth to seventh photoresist patterns as a mask to form a drain electrode formed of the third conductive layer on the black matrix of the first substrate. A method of manufacturing a liquid crystal display device, comprising exposing a pixel electrode of a region. The method of claim 5, wherein the first ohmic contact pattern and the second ohmic contact pattern formed of the n + amorphous silicon thin film are formed on the data line and the drain electrode including the source electrode through the second mask process. Method of manufacturing a liquid crystal display device further comprising. The method of claim 6, wherein the third mask process Forming an amorphous silicon thin film, a second insulating film, and a fourth conductive film on the first substrate; And Selectively removing the amorphous silicon thin film, the second insulating film, and the fourth conductive film to form an active pattern on the black matrix, and forming a gate electrode with the second insulating film interposed therebetween. A method of manufacturing a liquid crystal display device. The ohmic contact of claim 7, wherein the first mask and the second ohmic contact pattern are selectively removed through the third mask process to ohmic contact between the source / drain region and the source / drain electrode of the active pattern. A method of manufacturing a liquid crystal display device, further comprising the step of forming a layer. A first substrate having an engraved pattern by etching a portion of the region; A black matrix formed in the intaglio pattern of the first substrate and formed of a first conductive film; A first insulating film formed on the first substrate; A pixel electrode formed on the black matrix of the first substrate and a source / drain electrode and a data line formed of a third conductive film; A gate electrode formed of a fourth conductive film in an active pattern formed on the black matrix and a second insulating film interposed therebetween; A gate line positioned above the black matrix and defining a pixel area crossing the data line; And And a second substrate bonded to and opposed to the first substrate. The liquid crystal display of claim 9, wherein the black matrix is disposed under the thin film transistor region, the data line, and the gate line. 10. The liquid crystal display device according to claim 9, further comprising a conductive film pattern formed under the data line including the source electrode and comprising the second conductive film. 10. The liquid crystal display device according to claim 9, further comprising an ohmic contact layer for ohmic contact between the source / drain region and the source / drain electrode of the active pattern. The liquid crystal display of claim 9, wherein the first conductive layer is made of an opaque metal material such as chromium. The liquid crystal display of claim 9, wherein the second conductive layer is made of a transparent conductive material such as indium tin oxide and indium zinc oxide. 10. The liquid crystal display of claim 9, wherein the third conductive layer and the fourth conductive layer are made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy.

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