KR20120075109A - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A fringe field switching liquid crystal display device and a manufacturing method thereof are provided to enhance charging features of a pixel. CONSTITUTION: A gate electrode(121) and a gate line are formed in a pixel part of a first substrate. A gate insulating film(115a) is formed on the first substrate. An active layer(124) is formed on the gate electrode. A pixel electrode(118) is formed on a pixel area of the first substrate. A source electrode(122) and a drain electrode(123) are formed on the active layer. A data line(117) crosses the gate line to define the pixel area.

Description

Fringe field type liquid crystal display device and manufacturing method therefor {FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a fringe field type liquid crystal display device and a manufacturing method thereof, and more particularly, to a fringe field type liquid crystal display device and a method of manufacturing the same to reduce the load of the data line.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a panel, and the color filter substrate 5 And the bonding of the array substrate 10 is made through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules oriented horizontally with the substrate are oriented almost perpendicular to the substrate when a voltage is applied to the panel.

Accordingly, there is an in-plane switching (IPS) type liquid crystal display device in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle to 170 degrees or more.

FIG. 2 is a cross-sectional view illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device, in which a fringe field formed between the pixel electrode and the common electrode passes through the slit to drive the liquid crystal molecules positioned on the pixel region and the common electrode. A portion of an array substrate of a fringe field switching (FFS) liquid crystal display is shown.

In the fringe field type liquid crystal display, the liquid crystal molecules are horizontally aligned, and as the pixel electrode is formed at the bottom and the common electrode is formed at the top, an electric field is generated in the horizontal and vertical directions so that the liquid crystal molecules are twisted. It is tilted and driven.

As shown in the drawing, a gate line (not shown) and a data line 17 are arranged in the array substrate 10 of a typical fringe field type liquid crystal display device to be vertically and horizontally arranged on the transparent array substrate 10 to define a pixel area. And a thin film transistor, which is a switching element, is formed in an intersection region of the gate line and the data line 17.

The thin film transistor includes a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor is formed by the gate insulating film 15a for insulation between the gate electrode 21 and the source / drain electrodes 22 and 23 and the gate electrode supplied by the gate voltage supplied to the gate electrode 21. An active layer 24 is formed between the 22 and the drain electrode 23 to form a conductive channel.

In this case, the source / drain regions of the active layer 24 form ohmic contacts with the source / drain electrodes 22 and 23 through an ohmic contact layer 25n.

The common electrode 8 and the pixel electrode 18 are formed in the pixel region, and the common electrode 8 is formed together with the pixel electrode 18 in a box shape to generate a fringe field. 8, a plurality of slits 8s are included.

In this case, the pixel electrode 18 is electrically connected to the drain electrode 23 through contact holes formed in the first passivation layer 15b and the second passivation layer 15c.

The gate pad electrode 26p and the data pad electrode 27p electrically connected to the gate line and the data line 17 are formed in the edge region of the array substrate 10 configured as described above. The scan signal and the data signal applied from (not shown) are transferred to the gate line and the data line 17, respectively.

That is, the gate line and the data line 17 extend toward the driving circuit part and are connected to the corresponding gate pad line 16p and the data pad line 17p, respectively, and the gate pad line 16p and the data pad line 17p. The scan signal and the data signal are respectively applied from the driving circuit unit through the gate pad electrode 26p and the data pad electrode 27p electrically connected to the gate pad line 16p and the data pad line 17p, respectively. .

For reference, reference numeral 15d denotes a third protective film.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device configured as described above will be described in detail with reference to the accompanying drawings.

3A to 3G are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 2.

As shown in FIG. 3A, a gate electrode 21 made of a conductive metal material, a gate line (not shown), and a gate pad line 16p are formed on the array substrate 10 using a photolithography process (first mask process). To form.

Next, as shown in FIG. 3B, the gate insulating film 15a and the amorphous silicon thin film are sequentially formed on the entire surface of the array substrate 10 on which the gate electrode 21, the gate line, and the gate pad line 16p are formed. And n + amorphous silicon thin film.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form an active layer 24 formed of the amorphous silicon thin film on the gate electrode 21. .

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same manner as the active layer 24 is formed on the active layer 24.

Next, as illustrated in FIG. 3C, a conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (third mask process) to form an upper portion of the active layer 24. The source electrode 22 and the drain electrode 23 made of the conductive metal material are formed on the substrate, and the data line 17 defining the pixel region is formed together with the gate line.

In addition, the conductive metal material is selectively patterned through the third mask process to form a data pad line 17p made of the conductive metal material.

At this time, the n + amorphous silicon thin film pattern formed on the active layer 24 is removed between the active layer 24 and the source / drain electrodes 22 and 23 by removing a predetermined region through the third mask process. The ohmic contact layer 25n to be contacted is formed.

Next, as shown in FIG. 3D, the first passivation layer 15b and the second passivation layer 15c are formed on the entire surface of the array substrate 10, and then the photolithography process (fourth mask process) is used. By selectively patterning partial regions of the first passivation layer 15b and the second passivation layer 15c, a first contact hole 40a exposing a part of the drain electrode 23 is formed.

In this case, the second passivation layer 15c may have organic insulation having a low dielectric constant (˜3.5), such as photoacryl, to reduce parasitic capacitance caused by overlap between the data line 17 and the common electrode, which will be described later. Material is used.

Next, as shown in FIG. 3E, the transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a fifth mask process). A pixel electrode 18 electrically connected to the drain electrode 23 is formed through 40a.

As shown in FIG. 3F, after the third passivation layer 15d is formed on the entire surface of the array substrate 10, the third passivation layer 15d and the second passivation layer are formed using a photolithography process (sixth mask process). Second contact holes exposing portions of the data pad line 17p and the gate pad line 16p, respectively, by selectively patterning partial regions of the second passivation layer 15c, the first passivation layer 15b, and the gate insulating layer 15a. 40b and the third contact hole 40c are formed.

Next, as illustrated in FIG. 3G, a transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (seventh mask process) to common the entire pixel portion. A data pad electrode which forms an electrode 8 and is electrically connected to the data pad line 17p and the gate pad line 16p through the second contact hole 40b and the third contact hole 40c, respectively. 27p and the gate pad electrode 26p are formed.

In this case, the common electrode 8 includes a plurality of slits 8s in the common electrode 8 to generate a fringe field together with the pixel electrode 18 under the common electrode 8.

The fringe field type liquid crystal display device has a wide viewing angle, and when the common electrode 8 is formed even on the data line 17, the black matrix area can be reduced and the aperture ratio is improved.

However, parasitic capacitance is generated due to overlap between the common electrode 8 and the data line 17. To reduce this, even when a photoacryl having a low dielectric constant is applied, the capacitance is higher than that of the conventional transverse type liquid crystal display device. Will occur greatly. This causes a decrease in charging characteristics, an increase in size of the thin film transistor, and an increase in power consumption as the load of the data line 17 increases.

An object of the present invention is to provide a fringe field type liquid crystal display and a method of manufacturing the same to reduce the load on a data line.

Other objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the fringe field type liquid crystal display device of the present invention comprises a gate electrode and a gate line formed on the first substrate; A gate insulating film formed on the first substrate on which the gate electrode and the gate line are formed; An active layer formed on the gate electrode on which the gate insulating film is formed; A pixel electrode formed in the pixel region of the first substrate on which the active layer is formed; A data line defining the pixel region by crossing the source electrode, the drain electrode, and the gate line formed on the active layer of the first substrate on which the pixel electrode is formed; A first passivation layer formed on the first substrate on which the source electrode, the drain electrode and the data line are formed; A second passivation layer formed on the first substrate on which the first passivation layer is formed, the second passivation layer including an air gap filled with air over the data line; A common electrode formed to overlap the data line on the first substrate on which the second passivation layer is formed; And a second substrate bonded to and opposed to the first substrate.

In this case, an n + amorphous silicon thin film is formed on the active layer, and further includes an ohmic contact layer which ohmic-contacts the source / drain region of the active layer and the source / drain electrode.

The drain electrode is positioned on the lower pixel electrode and directly connected to the pixel electrode.

The air gap is formed in the second passivation layer on the data line and has a narrower width than the data line.

And at least one first contact hole formed at both ends of the air-gap.

The common electrode is formed in a single pattern over the entire pixel portion in which an image is displayed, and has a plurality of slits in each pixel region.

A method of manufacturing a fringe field type liquid crystal display device according to the present invention comprises the steps of: providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line on the pixel portion of the first substrate; Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active layer on the gate electrode on which the gate insulating film is formed; Forming a pixel electrode in the pixel region of the first substrate on which the active layer is formed; Forming a source electrode and a drain electrode on the active layer of the first substrate on which the pixel electrode is formed, and forming a data line crossing the gate line to define the pixel region; Forming a first passivation layer on the first substrate on which the source electrode, the drain electrode, and the data line are formed; Forming a sacrificial layer made of a conductive material on the data line on which the first passivation layer is formed; Forming a second passivation layer on the first substrate on which the sacrificial layer is formed; Selectively removing the second passivation layer to form a first contact hole exposing the sacrificial layer; Removing the sacrificial layer through the first contact hole to form an air gap in the second passivation layer on the data line; Forming a common electrode to overlap the data line in the pixel portion of the first substrate on which the air-gap is formed; And bonding the first substrate and the second substrate to each other.

In this case, when forming the gate electrode and the gate line, the first substrate further comprises forming a gate pad line on the gate pad portion.

And forming an ohmic contact layer formed of an n + amorphous silicon thin film on the active layer and ohmic-contacting the source / drain region of the active layer and the source / drain electrode.

The method may further include forming a data pad line on the data pad portion of the first substrate when the source electrode, the drain electrode, and the data line are formed.

The sacrificial layer may be formed to have a narrower width than the data line on the data line.

The second passivation layer is formed to have a thickness of 2000 kV to 3000 kV using inorganic insulating films such as silicon nitride film (SiNx) and silicon oxide film (SiO ₂ ), and the sacrificial layer is formed to have a thickness of 1500 kV to 2000 kPa. do.

When forming the first contact hole, selectively removing the second protective layer, the first protective layer, and the gate insulating layer to form a second contact hole and a third contact hole exposing the data pad line and the gate pad line, respectively. It further comprises a step.

At least one first contact hole may be formed at both ends of the sacrificial layer.

The sacrificial layer may be removed using an etchant for etching the conductive material constituting the sacrificial layer.

The etchant may include an etchant capable of selectively etching the conductive material constituting the data pad line and the gate pad line, respectively.

The common electrode may be formed to have a single pattern over the entire pixel portion and to have a plurality of slits in each pixel region.

When forming the common electrode, a data pad electrode and a gate pad electrode electrically connected to the data pad line and the gate pad line through the second contact hole and the third contact hole, respectively, in the data pad part and the gate pad part. It characterized in that it further comprises the step of forming.

As described above, in the fringe field type liquid crystal display device and the manufacturing method thereof, the charging characteristic of the pixel is improved as the load of the data line is reduced. As a result, while the performance of the thin film transistor is improved, the size of the thin film transistor can be reduced, thereby providing an effect of improving the aperture ratio.

In addition, as the load on the data line is reduced, the power consumption required to drive the panel is also reduced.

1 is an exploded perspective view schematically showing a general liquid crystal display device.
2 is a cross-sectional view showing a part of an array substrate of a typical fringe field type liquid crystal display device.
3A to 3G are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 2.
4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention.
6A to 6G are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.
7A to 7G are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 5.
8A to 8G are cross-sectional views sequentially illustrating a manufacturing process along line DD of the array substrate illustrated in FIG. 4.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the fringe field type liquid crystal display device and a method of manufacturing the same.

4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention, in which a fringe field formed between the pixel electrode and the common electrode penetrates a slit and is formed on the pixel region and the pixel electrode. A portion of an array substrate of a fringe field type liquid crystal display device for realizing an image by driving liquid crystal molecules positioned is shown.

In this case, for convenience of description, one pixel including a pixel unit, a data pad unit, and a gate pad unit is illustrated. In an actual LCD device, N gate lines and M data lines intersect to form MxN pixels. Although present, one pixel is shown in the drawing for simplicity of explanation.

FIG. 5 is a cross-sectional view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display according to an exemplary embodiment of the present invention, and is cut along lines A-A ', BB, and CC of the array substrate illustrated in FIG. 4. It shows a cross section.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 according to an embodiment of the present invention, which are arranged vertically and horizontally on the array substrate 110 to define a pixel region. have. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 116 and the data line 117, and a plurality of slits 108s for generating a fringe field to drive liquid crystal molecules are formed in the pixel area. The common electrode 108 and the box-shaped pixel electrode 118 are formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active layer 124 that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

In this case, the source / drain regions of the active layer 124 form ohmic contacts with the source / drain electrodes 22 and 23 through the ohmic contact layer 125n.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to directly contact the pixel electrode 118. Electrical connection.

As described above, the common electrode 108 and the pixel electrode 118 for generating a fringe field are formed in the pixel region, wherein the pixel electrode 118 is formed in a box shape in the pixel region. The common electrode 108 is formed in a single pattern over the entire pixel portion and is formed to have a plurality of slits 108s in each pixel region.

In this case, the liquid crystal display device according to the embodiment of the present invention shows a fringe field type liquid crystal display device which drives a liquid crystal molecule by inducing a fringe field which is a parabolic transverse electric field in the liquid crystal layer.

As the common electrode 108 is formed on the data line 117 as described above, the black matrix area can be reduced and the aperture ratio is improved. The left and right ends of the pixel electrode 118 are the outermost edges around the data line 117. It is present in the slit 108s to maximize the transmittance around the data line 117.

In the fringe field type liquid crystal display according to the exemplary embodiment of the present invention, the passivation layer is formed by forming the pixel electrode 118 on the gate insulating film 115a and the source / drain electrodes 122 and 123 thereon. The formation process may be omitted, and a predetermined air gap 135 is formed in the second passivation layer 115c on the data line 117, so that the data line 117 and the common electrode 108 may be formed. This can reduce the parasitic capacitance of. That is, the air-gap 135 of low dielectric constant (~ 1) is formed between the data line 117 and the common electrode 108 to reduce the capacitance therebetween, thereby reducing the load of the data line 117. Will be. As a result, the performance of the thin film transistor can be improved, while the size of the thin film transistor can be reduced, thereby improving the aperture ratio.

In addition, as the load on the data line 117 is reduced, power consumption required to drive the panel is also reduced.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140b and 140c indicate a second contact hole and a third contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the second contact hole 140b. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c.

In addition, reference numerals 115b and 140a represent a first passivation layer and a first contact hole, respectively, and are formed of a conductive material in the second passivation layer 115c on the data line 117 through the first contact hole 140a. By removing the layer it is possible to form the air-gap 135 described above.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device according to an exemplary embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

6A to 6G are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A through 7G are cross-sectional views sequentially illustrating a process of manufacturing the array substrate illustrated in FIG. 5, and a process of manufacturing an array substrate of a pixel portion is shown on the left side, and an array substrate of a data pad portion and a gate pad portion are sequentially formed on the right side. The manufacturing process is shown.

8A to 8G are cross-sectional views sequentially illustrating a manufacturing process along a line D-D of the array substrate illustrated in FIG. 4.

6A and 7A, a gate electrode 121 and a gate line 116 are formed in a pixel portion of the array substrate 110 made of a transparent insulating material such as glass, and the array substrate 110 may be formed. A gate pad line 116p is formed in the gate pad portion.

In this case, the gate electrode 121, the gate line 116, and the gate pad line 116p are selectively deposited through a photolithography process (first mask process) after depositing a first conductive layer on the entire surface of the array substrate 110. It is formed by patterning.

Here, the first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and Low resistance opaque conductive materials such as molybdenum alloys can be used. The first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as illustrated in FIGS. 6B, 7B, and 8A, the gate insulating layer 115a is formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the gate pad line 116p are formed. And an amorphous silicon thin film and an n + amorphous silicon thin film.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 124 made of the amorphous silicon thin film on the pixel portion of the array substrate 110. do.

In this case, the n + amorphous silicon thin film pattern 125 is formed on the active layer 124 and patterned in substantially the same shape as the active layer 124.

Next, as illustrated in FIGS. 6C and 7C, a second conductive layer is formed on the entire surface of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern 125 are formed. In this case, the second conductive layer includes a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a pixel electrode.

Thereafter, the second conductive layer is selectively removed through a photolithography process (a third mask process) to form a box-shaped pixel electrode 118 formed of the second conductive layer in the pixel region of the array substrate 110. .

6D, 7D, and 8B, a third conductive layer is formed on the entire surface of the array substrate 110 on which the pixel electrode 118 is formed. In this case, the third conductive layer may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line. The third conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the third conductive film are selectively removed through a photolithography process (a fourth mask process), so that the source electrode 122 and the drain electrode formed of the third conductive film on the active layer 124. 123 is formed.

In this case, a data line 117 made of the third conductive layer is formed in the data line region of the array substrate 110 through the fourth mask process, and at the same time, the third data pad portion of the array substrate 110 is formed. A data pad line 117p made of a conductive film is formed.

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active layer 124 and ohmic contact between the source / drain region of the active layer 124 and the source / drain electrodes 122 and 123. 125n is formed.

In this case, a part of the drain electrode 123 is directly formed on the pixel electrode 118 below and electrically connected to the pixel electrode 118.

Next, as illustrated in FIGS. 6E, 7E, and 8C, the source / drain electrodes 122 and 123, the data line 117, and the data pad line 117p may be formed on the entire surface of the array substrate 110. After forming the first passivation layer 115b and the fourth conductive layer, the sacrificial layer 130 including the fourth conductive layer is formed on the data line 117 by selectively removing the first passivation layer 115b and the fourth conductive layer through a photolithography process (a fifth mask process). Form.

In this case, the sacrificial layer 130 is removed by an etching etchant during a contact hole forming process to be described later to form an air gap in the second passivation layer, and the data line (above the data line 117). It may be formed to have a narrower width than 117). However, the present invention is not limited thereto, and may be formed to have substantially the same shape as the data line 117 or to have a wider width than the data line 117. In addition, the sacrificial layer 130 of the present invention is not limited to the rectangular shape as shown in FIG. 6E.

Next, as shown in FIG. 8D, the second passivation layer 115c is formed on the entire surface of the array substrate 110 on which the sacrificial layer 130 is formed.

In this case, the second passivation layer 115c may be formed of an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiO ₂ ), and may be formed to have a thickness of 2000 μs to 3000 μm. In this case, the sacrificial layer 130 may be formed to have a thickness of 1500 kPa to 2000 kPa.

6F, 7F, 8E, and 8F, the second passivation layer 115c, the first passivation layer 115b, and the gate insulation layer 115a are selectively selected through a photolithography process (a sixth mask process). The first contact hole 140a exposing a part of the sacrificial layer 130 is formed to be removed, and the data pad line 117p and the gate pad portion of the array substrate 110 are respectively formed. A second contact hole 140b and a third contact hole 140c exposing a portion of the gate pad line 116p are formed.

In this case, at least one first contact hole 140a may be formed, and each one of the first contact holes 140a may be formed at both ends of the sacrificial layer 130 as shown in FIG. 6F.

Thereafter, the sacrificial layer 130 is removed through the first contact hole 140a to form an air-gap 135 filled with air in the second passivation layer 115c on the data line 117. In this case, a predetermined etchant for etching the fourth conductive layer constituting the sacrificial layer 130 is used to remove the sacrificial layer 130, and the data pad line 117p and the gate pad line 116p are removed. An etchant capable of selective etching for the first conductive film and the third conductive film, respectively, should be used.

6G, 7G, and 8G, after forming a fifth conductive layer made of a transparent conductive material on the entire surface of the array substrate 110 on which the second passivation layer 115c is formed, a photolithography process is performed. By selectively patterning using a 7 mask process), a common electrode 108 having a plurality of slits 108s is formed in the pixel portion.

In this case, by selectively patterning the fifth conductive layer using the seventh mask process, the data pad portion and the gate pad portion respectively pass through the second contact hole 140b and the third contact hole 140c. The data pad electrode 127p and the gate pad electrode 126p electrically connected to the line 117p and the gate pad line 116p are formed.

As such, when the air-gap 135 filled with the low dielectric constant air (~ 1) is formed in the second passivation layer 115c on the data line 117 by using the sacrificial layer, the silicon nitride film (-6.7) is formed. The dielectric constant is reduced to 1/7 and only 1/3 of photoacrylic (~ 3.5), which will be effective in reducing data line load.

The load reduction of the data line 117 has an effect similar to that of improving the performance of the thin film transistor. The size of the thin film transistor in the pixel can be reduced, thereby increasing the aperture ratio. In addition, as the load of the data line 117 decreases, power consumption required to drive the panel is reduced. In addition, the embodiment of the present invention has the advantage that it can use the existing process line.

In particular, the embodiment of the present invention is applicable to a structure in which the common electrode and the data line overlap in the large model or the low resolution model.

The array substrate according to the embodiment of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outer side of the image display area. Black matrix to prevent leakage and color filter for red, green and blue color are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

In the fringe field type liquid crystal display device according to the embodiment of the present invention, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active layer is described as an example. However, the present invention is not limited thereto, and the present invention is not limited thereto. The same applies to polycrystalline silicon thin film transistors using thin films.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

108: common electrode 108s: slit
110: array substrate 116: gate line
117 data line 118 pixel electrode
121: gate electrode 122: source electrode
123: drain electrode 124: active layer
130: sacrificial layer 135: air-gap

Claims (18)

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion;
Forming a gate electrode and a gate line on the pixel portion of the first substrate;
Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed;
Forming an active layer on the gate electrode on which the gate insulating film is formed;
Forming a pixel electrode in the pixel region of the first substrate on which the active layer is formed;
Forming a source electrode and a drain electrode on the active layer of the first substrate on which the pixel electrode is formed, and forming a data line crossing the gate line to define the pixel region;
Forming a first passivation layer on the first substrate on which the source electrode, the drain electrode, and the data line are formed;
Forming a sacrificial layer made of a conductive material on the data line on which the first passivation layer is formed;
Forming a second passivation layer on the first substrate on which the sacrificial layer is formed;
Selectively removing the second passivation layer to form a first contact hole exposing the sacrificial layer;
Removing the sacrificial layer through the first contact hole to form an air-gap in a second passivation layer on the data line;
Forming a common electrode on the pixel portion of the first substrate on which the air-gap is formed to overlap the data line; And
A method of manufacturing a fringe field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate. The fringe field type liquid crystal display device of claim 1, further comprising forming a gate pad line on the gate pad in the first substrate when the gate electrode and the gate line are formed. Way. The method of claim 1, further comprising: forming an ohmic contact layer formed of an n + amorphous silicon thin film on the active layer and ohmic contacting a source / drain region of the active layer and the source / drain electrode. A method of manufacturing a fringe field type liquid crystal display device. 3. The fringe field type liquid crystal display of claim 2, further comprising forming a data pad line on the data pad of the first substrate when the source electrode, the drain electrode, and the data line are formed. Method of manufacturing the device. The method of claim 1, wherein the sacrificial layer is formed on the data line to have a narrower width than the data line. The method of claim 1, wherein the second passivation layer is formed to have a thickness of 2000 μm to 3000 μm using an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiO ₂ ), and the sacrificial layer has a thickness of 1500 μm to 2000 μm. The fringe field type liquid crystal display device manufacturing method characterized in that it is formed to. The second contact hole and the second contact hole of claim 4, wherein the second contact layer, the first passivation layer, and the gate insulating layer are selectively removed when the first contact hole is formed, thereby exposing the data pad line and the gate pad line. 3. A method of manufacturing a fringe field type liquid crystal display further comprising the step of forming a contact hole. The method of claim 1, wherein at least one first contact hole is formed at both ends of the sacrificial layer. The method of claim 4, wherein the sacrificial layer is removed using an etchant for etching the conductive material constituting the sacrificial layer. 10. The method of claim 9, wherein the etchant comprises an etchant capable of selectively etching the conductive material constituting the data pad line and the gate pad line, respectively. 2. The method of claim 1, wherein the common electrode is formed in a single pattern over the entire pixel portion and has a plurality of slits in each pixel region. 8. The method of claim 7, wherein when the common electrode is formed, data electrically connected to the data pad line and the gate pad line through the second contact hole and the third contact hole, respectively, in the data pad part and the gate pad part. A method of manufacturing a fringe field type liquid crystal display device further comprising the step of forming a pad electrode and a gate pad electrode. A gate electrode and a gate line formed on the first substrate;
A gate insulating film formed on the first substrate on which the gate electrode and the gate line are formed;
An active layer formed on the gate electrode on which the gate insulating film is formed;
A pixel electrode formed in the pixel region of the first substrate on which the active layer is formed;
A data line defining the pixel region by crossing the source electrode, the drain electrode, and the gate line formed on the active layer of the first substrate on which the pixel electrode is formed;
A first passivation layer formed on the first substrate on which the source electrode, the drain electrode and the data line are formed;
A second passivation layer formed on the first substrate on which the first passivation layer is formed, the second passivation layer including an air gap filled with air over the data line;
A common electrode formed to overlap the data line on the first substrate on which the second passivation layer is formed; And
A fringe field type liquid crystal display device comprising a second substrate bonded to and opposed to the first substrate. 15. The method of claim 13, wherein the active layer is formed of an n + amorphous silicon thin film, and further comprises an ohmic contact layer for ohmic-contacting the source / drain region and the source / drain electrode of the active layer. Fringe field type liquid crystal display device. 14. The fringe field type liquid crystal display device according to claim 13, wherein the drain electrode is disposed on a pixel electrode below the drain electrode and is electrically connected to the pixel electrode. The fringe field type liquid crystal display of claim 13, wherein the air gap is formed in a second passivation layer on the data line and has a narrower width than the data line. The fringe field type liquid crystal display of claim 13, further comprising a first contact hole formed at least one of both ends of the air-gap. 14. The fringe field type liquid crystal display device according to claim 13, wherein the common electrode is formed in a single pattern over the entire pixel portion where the image is displayed and has a plurality of slits in each pixel region.

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