KR102433260B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and the display device according to the present invention includes a substrate including a pad area, a plurality of planarization patterns disposed on the pad area on the substrate, and a plurality of pads disposed on the plurality of planarization patterns, Electrical connection between the plurality of pads and the data driver may be improved.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device having improved electrical connection between a plurality of pads and an external module.

Recently, as we enter the information age in earnest, the field of display that visually expresses electrical information signals has developed rapidly. Device) has been developed and is rapidly replacing the existing cathode ray tube (CRT).

Specific examples of the flat panel display include a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), a plasma display (PDP), and an electrowetting display (EWD). have.

The display device includes a display area in which an image is implemented and a non-display area surrounding the display area. A plurality of pads may be disposed in the non-display area, and a chip on film (COF) may be disposed on the plurality of pads. The plurality of pads and the COF may be electrically connected to each other using an adhesive including conductive balls made of a conductive material. As pressure is applied to the COF disposed on the plurality of pads and the conductive ball is broken, the COF and the pad are electrically connected.

Recently, in order to realize a high-resolution display device or to reduce the size of the non-display area, the width of each of the plurality of pads and the distance between the pads adjacent to each other are gradually decreasing. Accordingly, it is required to refine the bonding process of each of the plurality of pads and the COF. However, since the step difference between the plurality of pads and the space between the plurality of pads is not large, when the plurality of pads and the COF are bonded, adjacent pads may be electrically connected to each other by conductive balls. Accordingly, an alignment defect and a contact defect occur, such as electrically connecting neighboring pads.

The problem to be solved by the present invention is that the plurality of pads are made of the same material as the conductive layer disposed on the planarization layer disposed in the display area, and a plurality of planarization patterns extending from the planarization layer are disposed under each of the plurality of pads. , to provide a display device in which a step difference between an area in which a pad is disposed and an area between adjacent pads is increased.

Another problem to be solved by the present invention is that a plurality of planarization patterns disposed under a plurality of pads in a pad area where a plurality of pads are disposed are separated from each other and spaced apart from each other, so that a contact defect is improved when a plurality of pads and a COF are bonded. to provide the device.

Another object of the present invention is to provide a display device in which a step difference between a plurality of pads and an adjacent pad is further increased by forming a plurality of planarization patterns disposed under each of a plurality of pads in a plurality of layers will do

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an embodiment of the present invention provides a substrate including a pad area, a plurality of planarization patterns disposed on the pad area on the substrate, and a plurality of pads disposed on the plurality of planarization patterns. includes Accordingly, a step difference between an area in which a plurality of pads is disposed and an area in which the plurality of pads are not disposed in the pad area is increased, thereby preventing the pads adjacent to each other from being connected to each other.

In order to solve the above problems, a display device according to another exemplary embodiment includes a display area, a substrate including a non-display area surrounding the display area and having a pad area, a transistor disposed in the display area, and an upper portion of the transistor. and a planarization layer disposed on the display area to be planarized, a plurality of planarization patterns extending from the planarization layer to the pad area, and a plurality of pads disposed on the plurality of planarization patterns. Accordingly, the electrical connection between the plurality of pads and the external module may be improved.

The details of other embodiments are included in the detailed description and drawings.

The present invention has the effect of improving the electrical connection between the COF and the plurality of pads as the step difference between the plurality of pads and the adjacent pads increases.

In addition, since the plurality of planarization patterns disposed under each of the plurality of pads are spaced apart from each other, the present invention has an effect of reducing alignment and contact defects between the COF and the plurality of pads.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a plan view of a display device according to an exemplary embodiment.
FIG. 2 is an enlarged view of area A of FIG. 1 .
3A is a cross-sectional view taken along line IIIa-IIIa' of FIG. 2 .
3B is a cross-sectional view taken along line IIIb-IIIb' of FIG. 2 .
4 is an enlarged plan view of a display device according to another exemplary embodiment.
FIG. 5 is a cross-sectional view taken along line V-V' of FIG. 4 .
6 is an enlarged plan view of a display device according to still another exemplary embodiment.
7 is a cross-sectional view taken along line VII-VII' of FIG. 6 .
8 is a cross-sectional view of a display device according to another exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of another device.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other, It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an exemplary embodiment. In FIG. 1 , for convenience of explanation, among various components of the display device 100 , a substrate 110 , a data driver 120 , a gate driver 130 , a plurality of signal wires DL and GL, and a plurality of link wires ( DLL, GLL) only.

Referring to FIG. 1 , a substrate 110 is a base member for supporting various components of the display device 100 , and may be made of an insulating material. For example, the substrate 110 may be made of a plastic material such as glass or polyimide, but is not limited thereto.

A display area AA and a non-display area NA surrounding the display area AA may be defined in the substrate 110 . The display area AA is an area where an image is actually displayed in the display device 100 , and various driving elements and signal lines DL and GL for driving the display unit and the display unit may be disposed in the display area AA. For example, the display unit may be a liquid crystal display unit that drives the liquid crystal by an electric field generated by a voltage applied to the pixel electrode and the common electrode. However, the present invention is not limited thereto, and the display unit may be an organic light emitting display unit including an organic light emitting device including an anode, an organic layer, and a cathode. In addition, various driving devices such as transistors and capacitors for driving the display unit may be disposed in the display area AA. In the present specification, the display device 100 has been described as a liquid crystal display, but the present disclosure is not limited thereto, and the display device 100 may be an organic light emitting diode display.

A plurality of transistors may be disposed in the display area AA. The transistor may include a gate electrode, an active layer disposed on the gate electrode, and a source electrode and a drain electrode disposed on the active layer. Specifically, a gate electrode is formed on the substrate 110 of the display area AA. A gate insulating layer is formed on the gate electrode, and an active layer in which a channel of a transistor is formed is formed on the gate insulating layer. The gate insulating layer may electrically insulate the active layer and the gate electrode. The gate insulating layer is made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), and may be a single layer or a plurality of layers thereof, but is not limited thereto. A source electrode and a drain electrode of the transistor may be formed on the active layer. The transistor may be a bottom gate type transistor as described above, but the stacked structure of the transistor is not limited thereto, and may be a top gate type transistor.

A plurality of pixels are disposed in the display area AA. The plurality of pixels is a minimum unit emitting light and may include a red pixel, a green pixel, and a blue pixel. Each of the plurality of pixels may be connected to the signal lines DL and GL, that is, the gate line GL and the data line DL.

The non-display area NA is an area in which an image is not displayed and surrounds the display area AA. Various components for driving a plurality of pixels disposed in the display area AA may be disposed in the non-display area NA. For example, as shown in FIG. 1 , the data driver 120 , the gate driver 130 , and the link wires GLL and DLL connected to the various signal wires GL and DL of the display area AA are provided. It may be disposed in the non-display area NA.

A pad area PA may be defined in the non-display area NA. The pad area PA is an area in which a plurality of pads are formed. An external module, for example, the data driver 120 and the gate driver 130 may be bonded to the plurality of pads in the pad area PA. That is, the pad area PA is an area where the data driver 120 and the gate driver 130 and the substrate 110 overlap each other. The plurality of pads disposed in the pad area PA may be connected to the link lines GLL and DLL, and may be connected to the signal lines DL and GL through the link lines GLL and DLL. Accordingly, each of the plurality of pads may be electrically connected to each of the plurality of pixels.

The data driver 120 is configured to process data for displaying an image and a driving signal for processing the data, and is configured to supply signals to a plurality of pixels in the display area AA. The data driver 120 may be bonded to the pad area PA of the non-display area NA. The data driver 120 supplies a data voltage to a plurality of pixels in the display area AA through various wirings disposed in the non-display area NA. Specifically, the data driver 120 may supply a data voltage to a plurality of pixels through a plurality of pads disposed in the pad area PA of the non-display area NA and a data link line DLL connected to the plurality of pads. have. In FIG. 1 , a plurality of data drivers 120 is illustrated, but the present invention is not limited thereto, and one data driver 120 may be disposed on the substrate 110 .

Referring to FIG. 1 , the data driver 120 includes a base film 121 , a driver IC 122 , and a plurality of data pads. The base film 121 is a film supporting the data driver 120 . The base film 121 may be made of an insulating material, for example, may be made of an insulating material having flexibility. The driving IC 122 is configured to process a data voltage for displaying an image and a driving signal for processing the data voltage. The driving IC 122 may be disposed in a method such as a chip on glass (COG), a chip on film (COF), or a tape carrier package (TCP) depending on a method of being mounted on the substrate 110 of the display device 100 . have. The plurality of data pads are electrically connected to the plurality of pads on which the data driver 120 is disposed in the non-display area NA to transmit signals to the plurality of pads. The plurality of data pads may be disposed 1:1 on the plurality of pads disposed in the non-display area NA to electrically connect the data driver 120 and the plurality of pads. 1 illustrates that the data driver 120 is a COF method mounted on the base film 121 for convenience of explanation, but is not limited thereto. The data pad will be described in more detail with reference to FIG. 3B .

The gate driver 130 may output a gate signal under the control of the timing controller and select a pixel to which the data voltage is charged through the gate link line GLL. The gate driver 130 may sequentially supply the gate signal to the gate line GL using a shift register. The gate driver 130 includes a base film 131 , a driving IC 132 , and a plurality of gate pads. The base film 131 is a film supporting the gate driver 130 . The base film 131 may be made of an insulating material, for example, may be made of an insulating material having flexibility. The driving IC 132 is configured to process a gate voltage for displaying an image and a driving signal for processing the gate voltage. The driving IC 132 may be disposed in a method such as a chip on glass (COG), a chip on film (COF), or a tape carrier package (TCP) depending on a method of being mounted on the substrate 110 of the display device 100 . have. The plurality of gate pads are pads for transmitting signals to the plurality of pads by electrically connecting the gate driver 130 to the plurality of pads disposed in the non-display area NA. The gate pad may be disposed on the plurality of pads disposed in the non-display area NA to electrically connect the gate driver 130 and the plurality of pads.

1 illustrates that the gate driver 130 is a COF method mounted on the base film 131 for convenience of explanation, but is not limited thereto. Also, although it is illustrated that there are a plurality of gate drivers 130 , the present invention is not limited thereto, and one gate driver 130 may be disposed on the substrate 110 .

Hereinafter, for a more detailed description of the pad area PA of the non-display area NA of the substrate 110, FIGS. 2 to 3B are also referred to.

FIG. 2 is an enlarged view of area A of FIG. 1 . 3A is a cross-sectional view taken along line IIIa-IIIa' of FIG. 2 . 3B is a cross-sectional view taken along line IIIb-IIIb' of FIG. 2 . 2 to 3A, the data driver 120 is omitted for convenience of description.

2 to 3A , a gate insulating layer 111 , a planarization layer 140 , and a data line DL are disposed in the display area AA on the substrate 110 . Specifically, a gate insulating layer 111 that insulates the gate electrode and the active layer of the transistor is disposed on the substrate 110 . A plurality of data lines DL are disposed on the gate insulating layer 111 . Each of the plurality of data lines DL is connected to each of the plurality of pixels disposed in the display area AA and transmits a data signal to each of the plurality of pixels.

The plurality of data lines DL may be formed of the same material as a source electrode and a drain electrode of a transistor disposed in the display area AA. The plurality of data lines DL may be formed of a conductive metal material, for example, aluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy, molybdenum (Mo), Silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Tialloy), moly tungsten (MoW), moly titanium (MoTi) ), copper/motitanium (Cu/MoTi), and titanium (Ti)/aluminum (Al)/titanium (Ti), but is not limited thereto.

A planarization layer 140 is disposed on the plurality of data lines DL. The planarization layer 140 is a layer for planarizing an upper portion of a device such as a transistor disposed in the display area AA. The planarization layer 140 may be an insulating layer made of an organic material. The planarization layer 140 may be disposed over the plurality of data lines DL and the entire display area AA to planarize the upper portions of the plurality of data lines DL.

2 to 3A , a gate insulating layer 111 , a data link line DLL, and a planarization layer 140 are disposed in the non-display area NA except for the pad area PA. Specifically, the gate insulating layer 111 extends from the display area AA to an area of the non-display area NA except for the pad area PA and is disposed on the substrate 110 . That is, the gate insulating layer 111 extends from the display area AA to one side of the pad area PA and is disposed on the substrate 110 .

A data link line DLL is disposed on the gate insulating layer 111 . The data link line DLL is a line that connects the pad 160 and the data line DL to transmit data signals to the plurality of pixels. The data link line DLL extends from the data line DL disposed in the display area AA and is electrically connected to the data line DL.

The data link line DLL may be made of the same material as the data line DL. Accordingly, as described above, the data link line DLL may be formed of the same material as the source electrode and the drain electrode of the transistor. The data link wiring (DLL) may be formed of a conductive metal material, for example, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Tialloy), molytungsten (MoW), moly titanium (MoTi) , copper/motitanium (Cu/MoTi) and titanium (Ti)/aluminum (Al)/titanium (Ti), but is not limited thereto.

The data link line DLL and the data line DL are simultaneously formed to form a single line. That is, the data link line DLL may be disposed to extend from the data line DL. Accordingly, the data link line DLL and the data line DL may be formed of the same material. However, it is not limited thereto.

Meanwhile, unlike illustrated in FIGS. 1 to 3A , the plurality of data lines DL may be made of the same material as the gate electrode of the transistor disposed in the display area AA. Also, the data link line DLL may be formed of the same material as the data line DL, that is, the same material as the gate electrode of the transistor. However, it is not limited thereto.

A planarization layer 140 is disposed on the plurality of data link lines DLL. That is, each of the plurality of data link lines DLL is disposed under the planarization layer 140 . The planarization layer 140 is disposed in an area of the non-display area NA except for the pad area PA to planarize an area of the non-display area NA except for the pad area PA. The planarization layer 140 may be an insulating layer made of an organic material. The planarization layer 140 may be disposed over the plurality of data link lines DLL and the entire non-display area NA except for the pad area PA to planarize upper portions of the plurality of data link lines DLL. .

In the non-display area NA except for the pad area PA, the planarization layer 140 disposed on the plurality of data link lines DLL extends from the planarization layer 140 disposed in the display area AA. can be placed. Specifically, the planarization layer 140 disposed in the non-display area NA is the same layer as the planarization layer 140 disposed in the display area AA, and may be formed at the same time. However, it is not limited thereto.

The planarization layer 140 disposed in an area other than the pad area PA of the non-display area NA shown in FIG. 2 is disposed on the plurality of data link lines DLLs in the pad area PA of the non-display area NA. ) to cover the entire area except for However, unlike this, the planarization layer 140 is disposed only in an area overlapping the plurality of data link lines DLL in the non-display area NA except for the pad area PA, and the plurality of data link lines DLLs. ) may not be disposed in a region between the data link lines DLL. That is, the planarization layer 140 disposed in an area of the non-display area NA except for the pad area PA may include a plurality of patterns, and each of the plurality of padns overlaps a plurality of data link lines DLL. can do.

2 to 3B , a plurality of planarization patterns 150 are disposed in the pad area PA of the non-display area NA. The plurality of planarization patterns 150 are a plurality of patterns having a flat top surface.

The plurality of planarization patterns 150 may be made of the same material as the planarization layer 140 disposed in the display area AA. That is, the plurality of planarization patterns 150 may be formed of an organic insulating material. However, it is not limited thereto.

Also, the plurality of planarization patterns 150 may extend from the planarization layer 140 disposed in the display area AA. Specifically, the planarization layer 140 disposed in the non-display area NA except for the pad area PA may be disposed to extend from the planarization layer 140 disposed in the display area AA. Accordingly, the planarization layer 140 disposed in the display area AA and the planarization layer 140 disposed in an area other than the pad area PA among the non-display area NA may be simultaneously formed and made of the same material. can In addition, the plurality of planarization patterns 150 disposed in the pad area PA of the non-display area NA extend from the planarization layer 140 disposed in an area of the non-display area NA except for the pad area PA. and can be placed. Accordingly, the plurality of planarization patterns 150 disposed in the pad area PA of the non-display area NA and the planarization layer 140 disposed in the area other than the pad area PA of the non-display area NA may be simultaneously formed. may be formed, and may be made of the same material. That is, the planarization layer 140 disposed in the display area AA, the planarization layer 140 disposed in an area other than the pad area PA among the non-display area NA, and the plurality of planarization layers disposed in the pad area PA. The planarization pattern 150 may be formed simultaneously and may be made of the same material. The plurality of planarization patterns 150 extend from the planarization layer 140 disposed in the display area AA, and thus, the planarization layer 140 disposed in the display area AA and a pad area of the non-display area NA. Upper portions of the planarization layer 140 disposed in the area except PA and the plurality of planarization patterns 150 disposed in the pad area PA may be flat. A gate insulating layer 111 and devices such as a transistor are disposed in the display area AA, and a data link line DLL and the like are disposed in an area of the non-display area NA except for the pad area PA. Accordingly, the thickness of the planarization layer 140 disposed in the display area AA and the planarization layer 140 disposed in an area other than the pad area PA among the non-display area NA is greater than the thickness of the planarization layer 140 disposed in the pad area PA. The plurality of planarization patterns 150 may have a greater thickness.

The plurality of planarization patterns 150 are spaced apart from each other in the pad area PA. In detail, the plurality of planarization patterns 150 may be disposed in the pad area PA and may be sequentially disposed at a predetermined distance apart from each other. Accordingly, the plurality of planarization patterns 150 may be separated from each other and disposed in the pad area PA. The plurality of planarization patterns 150 may be formed by patterning a planarization layer disposed to correspond to the entire pad area AA. That is, a planarization layer having a relatively thick thickness (eg, a passivation layer or a gate insulating layer) may be formed over the entire pad area PA, and the planarization layer having a thick thickness is formed into a plurality of planarization patterns 150 . can be patterned. Accordingly, in the display device according to an embodiment of the present invention, the occurrence of contact defects can be reduced by forming the planarization pattern 150 by patterning a relatively thick planarization layer to stably break the conductive ball. Also, as described above, the thickness of the planarization layer 140 disposed in the display area AA may be thicker than the thickness of the gate insulating layer 111 . Since the plurality of planarization patterns 150 disposed in the pad area PA may be formed to extend from the planarization layer 140 disposed in the display area AA, the thickness of the plurality of planarization patterns 150 may be equal to that of the gate insulating layer. It may be greater than the thickness of (111). Accordingly, the plurality of planarization patterns 150 may be thicker than the gate insulating layer 111 , and a planarization layer disposed to correspond to the entire pad area PA may be patterned and formed.

Since the plurality of planarization patterns 150 are disposed to be separated from each other, a region in which the plurality of planarization patterns 150 are not disposed may exist between the plurality of planarization patterns 150 . Accordingly, a step d3 may exist between an area in which the planarization pattern 150 is disposed in the non-display area NA and an area in which the planarization pattern 150 is not disposed as an area between the adjacent planarization patterns 150 . .

A plurality of pads 160 are disposed on the plurality of planarization patterns 150 . The plurality of pads 160 is a pad 160 that connects the substrate 110 and the data driver 120 , and may receive a data signal from the data driver 120 and transmit it to each of the plurality of data link lines DLL. .

Each of the plurality of pads 160 includes a metal layer 161 and a transparent conductive layer 162 . The metal layer 161 is disposed on the plurality of planarization patterns 150 and is a layer made of a metal material. The metal layer 161 may be made of the same material as the auxiliary wiring disposed in the display area AA. The auxiliary wiring is a wiring disposed on the planarization layer 140 in the display area AA, and is a wiring electrically connected to the common electrode disposed in the display area AA. The auxiliary wiring may be disposed between a plurality of pixels defined in the display area AA to apply a high potential voltage to the common electrode. In one embodiment of the present invention, the reason that the metal layer 161 is formed of the same material as the auxiliary wiring disposed in the display area AA is that the gate electrode, the source electrode, or the drain electrode is formed under the planarization layer 140 . This is because the layer or auxiliary wiring is a layer disposed on the planarization layer 140 , and thus is advantageous in the process of forming the pad. Accordingly, in the exemplary embodiment of the present invention, although it has been described that the metal layer 161 is formed of the same material as the auxiliary wiring disposed in the display area AA, the present invention is not limited thereto, and any metal layer formed on the planarization layer 140 may be used. any material is possible.

The common electrode forms an electric field together with the pixel electrode disposed in the display area AA, and the liquid crystal disposed in the display area AA is driven by the electric field. The metal layer 161 of the plurality of pads 160 may be made of the same material as the auxiliary electrode, for example, may be made of a conductive material such as copper (Cu) or silver (Ag). However, it is not limited thereto.

The metal layers 161 of the plurality of pads 160 are connected to the data link line DLL through the contact hole CH. Specifically, the metal layer 161 is electrically connected to the data link line DLL through the contact hole CH formed in the planarization layer 140 .

The transparent conductive layers 162 of the plurality of pads 160 are disposed on the metal layer 161 . The transparent conductive layer 162 is a layer made of a transparent conductive oxide such as indium tin oxide (ITO). The transparent conductive layer 162 may be disposed on the metal layer 161 to cover the entire metal layer 161 . When the metal layer 161 is the outermost layer, it may be corroded. When the metal layer 161 is oxidized as described above, the data signal transmitted to the plurality of pads 160 may not be smoothly transmitted to the data link line DLL. Alternatively, the transparent conductive layer 162 made of the transparent conductive oxide may be less corroded than the metal layer 161 . Accordingly, in the display device 100 according to an embodiment of the present invention, the transparent conductive layer 162 may be disposed on the metal layer 161 , and the transparent conductive layer 162 may cover the entire metal layer 161 . Accordingly, the transparent conductive layer 162 may be disposed on the metal layer 161 to protect the metal layer 161 from being oxidized. Accordingly, oxidation of the metal layer 1610 may be prevented, and signal transmission of the display device 100 may be improved.

3A to 3B , the adhesive layer 170 and the data driver 120 are disposed on the plurality of pads 160 . Specifically, the adhesive layer 170 is disposed on the plurality of pads 160 , and the data driver 120 is disposed on the adhesive layer 170 .

The data driver 120 includes a base film 121 and a plurality of data pads 123 . A plurality of data pads 123 may be disposed under the base film 121 , and the base film 121 on which the plurality of data pads 123 are disposed may be disposed on the plurality of pads 160 . The plurality of data pads 123 may electrically connect the data driver 120 and the plurality of pads 160 , and may transmit data signals to the plurality of pads 160 . Each of the plurality of data pads 123 may overlap the plurality of pads 160 .

The adhesive layer 170 is a layer made of an adhesive material disposed between the data driver 120 and the plurality of pads 160 . The adhesive layer 170 bonds the plurality of pads 160 and the plurality of data pads 123 of the data driver 120 to each other. The adhesive layer 170 includes a plurality of dispersed conductive balls EB. The conductive balls EB are conductive particles for electrically connecting each of the plurality of data pads 123 and each of the plurality of pads 160 . An adhesive layer 170 including a plurality of conductive balls EB may be disposed between the plurality of pads 160 and the plurality of data pads 123 , and each of the plurality of pads 160 and the plurality of data pads 123 may be disposed. ), pressure may be applied to the plurality of pads 160 and the plurality of data pads 123 to be attached to each other. The conductive balls EB disposed between the plurality of pads 160 and the data pad 123 may be broken or deformed by pressure, and the plurality of conductive balls EB may be connected to each other. Accordingly, each of the plurality of pads 160 and each of the plurality of data pads 123 may be electrically connected to each other by a broken or deformed conductive ball EB. As each of the plurality of pads 160 and each of the plurality of data pads 123 are connected, a data signal may be transmitted from the data driver 120 to the plurality of pads 160 . The data signal transmitted to the plurality of pads 160 may be transmitted to the plurality of pixels through the plurality of data link lines DLL and the plurality of data lines DL.

In the display device 100 according to an embodiment of the present invention, each of the plurality of planarization patterns 150 is disposed under each of the plurality of pads 160 , so that the data driver 120 to the plurality of pads 160 . It is possible to improve the transmission of data signals. Specifically, when the planarization pattern 150 is not disposed under the pad 160 , the separation distance d1 from the lower surface of the data pad 123 to the upper surface of the pad 160 and the lower surface of the data pad 123 . The difference in the separation distance d2 to the substrate 110 may be very small. That is, when the planarization pattern 150 is not disposed under the pad 160 , the difference between the separation distance d1 to the upper surface of the pad 160 and the separation distance d2 to the substrate 110 is the pad 160 . ) may be the thickness of At this time, when the difference between the separation distance d1 to the upper surface of the pad 160 and the separation distance d2 to the substrate 110 is very small, the conductive ball EB may be broken even in the area between the plurality of pads 160 . can Accordingly, each of the plurality of pads 160 is electrically connected to the data pad 123 disposed adjacent to the overlapping data pad 123 and not the data pad 123 disposed to overlap each pad 160 . can be connected to Therefore, instead of the data signal to be transmitted to the corresponding pad 160, the data signal to be transmitted to the neighboring pad 160 is transmitted to the corresponding pad 160, and an erroneous data signal may be transmitted to a plurality of pixels, Accordingly, the display device 100 may malfunction.

On the other hand, when the plurality of planarization patterns 150 are respectively disposed under each of the plurality of pads 160 , the separation distance d1 from the lower surface of the data pad 123 to the upper surface of the pad 160 and the data pad 123 are ) The difference in the separation distance d2 from the lower surface of the substrate 110 may be increased compared to a case in which the plurality of planarization patterns 150 are not disposed. That is, the difference between the separation distance d1 to the upper surface of the pad 160 and the separation distance d2 to the substrate 110 may be the sum of the thickness of the pad 160 and the thickness of the planarization pattern 150 . Accordingly, the step d3 between the area in which the plurality of pads 160 is disposed and the area in which the pad 160 is not disposed between the adjacent pads 160 may increase. When the step d3 is increased, the conductive balls EB disposed in an area where the pads 160 are not disposed between the plurality of pads 160 may not be deformed, such as being broken. That is, in the case of the area between the adjacent pads 160 where the plurality of pads 160 are not disposed, the separation distance d2 from the lower surface of the data pad 123 to the substrate 110 may be increased. The conductive ball EB disposed in this area may not be broken. Accordingly, the pad 160 may not be connected to the data pad 123 disposed adjacent to the data pad 123 disposed to overlap the pad 160 . Accordingly, in the display device 100 according to an embodiment of the present invention, each of the plurality of planarization patterns 150 is disposed under each of the plurality of pads 160 , so that the data driver 120 and the plurality of pads 160 are disposed. ) may be improved in alignment or contact failure, and electrical connection between the data driver 120 and the plurality of pads 160 may be improved.

2 to 3B have described the pad area PA to which the data driver 120 is bonded, the same pad 160 structure as described above may also be applied to the pad area to which the gate driver 130 is bonded. .

4 is an enlarged plan view of a display device according to another exemplary embodiment. FIG. 5 is a cross-sectional view taken along line V-V' of FIG. 4 . The display device 200 of FIGS. 4 to 5 is different from the display device 100 of FIGS. 1 to 3B except that the plurality of pads 260A and 260B and the plurality of data link wires DLL1 and DLL2 are different. When it is substantially the same, a duplicate description will be omitted.

4 to 5 , a gate insulating layer 211 , a planarization layer 140 , and a data line DL are disposed on the substrate 110 of the display area AA. Specifically, the gate insulating layer 211 is disposed on the substrate 110 . A plurality of data lines DL are disposed on the gate insulating layer 211 . The plurality of data lines DL may be formed of the same material as the source electrode and the drain electrode of the transistor disposed in the display area AA. A planarization layer 140 is disposed on the plurality of data lines DL. The planarization layer 140 may be disposed over the plurality of data lines DL and the entire display area AA to planarize the upper portions of the plurality of data lines DL. The thickness of the planarization layer 140 may be greater than the thickness of the gate insulating layer 211 disposed in the display area AA. That is, the planarization layer 140 may be a layer having a thickness greater than that of the gate insulating layer 211 .

4 to 5 , in the non-display area NA except for the pad area PA, the gate insulating layer 211 , the first data link line DLL1 , the second data link line DLL2 and the A planarization layer 140 is disposed. The gate insulating layer 211 extends from the display area AA to an area of the non-display area NA except for the pad area PA and is disposed on the substrate 110 .

A first data link line DLL1 and a second data link line DLL2 are disposed on the gate insulating layer 211 . The first data link line DLL1 and the second data link line DLL2 are alternately disposed adjacent to each other. That is, the first data link line DLL1 and the second data link line DLL2 are alternately disposed.

The first data link line DLL1 may be made of the same material as the data line DL. Specifically, as described above, the data line DL may be formed of the same material as the source electrode and the drain electrode of the transistor. In this case, the first data link line DLL1 may be formed of the same material as the data line DL, that is, the same material as the source electrode and the drain electrode of the transistor.

As the first data link line DLL1 is made of the same material as the data line DL, the first data link line DLL1 may extend from the data line DL. That is, the first data link line DLL1 and the data line DL are simultaneously formed to form a single line. However, it is not limited thereto.

The second data link line DLL2 may be formed of a material different from that of the data line DL. Specifically, as described above, the data line DL may be formed of the same material as the source electrode and the drain electrode of the transistor. In this case, the second data link line DLL2 may be formed of a material different from that of the data line DL, that is, the same material as the gate electrode of the transistor. However, it is not limited thereto.

The second data link line DLL2 and the data line DL may be electrically connected through the second contact hole CH2 . The data line DL may be electrically connected to the second data link line DLL2 through the second contact hole CH2 formed in the gate insulating layer 211 in the non-display area NA.

A planarization layer 140 is disposed on the first data link line DLL1 and the second data link line DLL2 . That is, each of the first data link line DLL1 and the second data link line DLL2 is disposed under the planarization layer 140 . The planarization layer 140 is disposed over the plurality of data link lines DLL1 and DLL2 and over the non-display area NA except for the pad area PA to cover upper portions of the plurality of data link lines DLL1 and DLL2. can be flattened.

In this case, the planarization layer 140 disposed on the first data link line DLL1 and the second data link line DLL2 may extend from the planarization layer 140 disposed in the display area AA. That is, the planarization layer 140 disposed in the non-display area NA is the same layer as the planarization layer 140 disposed in the display area AA and may be simultaneously formed. Accordingly, the planarization layer 140 disposed on the first data link line DLL1 and the second data link line DLL2 and the planarization layer 140 disposed on the display area AA may be made of the same material. However, it is not limited thereto.

Meanwhile, as described above, the plurality of data lines DL may be made of the same material as the gate electrode of the transistor. In this case, the first data link line DLL1 may be formed of the same material as the data line DL, that is, the same material as the gate electrode of the transistor. Also, the second data link line DLL2 may be made of a material different from that of the data line DL, that is, the same material as that of the source electrode and the drain electrode of the transistor. However, it is not limited thereto.

4 to 5 , a plurality of planarization patterns 150 and a plurality of pads 260A and 260B are disposed in the pad area PA of the non-display area NA.

The plurality of planarization patterns 150 are spaced apart from each other in the pad area PA. That is, the plurality of planarization patterns 150 may be separated from each other and disposed in the pad area PA. Accordingly, a step may exist between an area in which the planarization pattern 150 is disposed in the non-display area NA and an area in which the planarization pattern 150 is not disposed as an area between the adjacent planarization patterns 150 .

Also, the plurality of planarization patterns 150 may extend from the planarization layer 140 disposed in the display area AA. Specifically, the planarization layer 140 disposed in the non-display area NA except for the pad area PA may be disposed to extend from the planarization layer 140 disposed in the display area AA. Accordingly, the planarization layer 140 disposed in the display area AA and the planarization layer 140 disposed in an area other than the pad area PA among the non-display area NA may be simultaneously formed and made of the same material. can In addition, the plurality of planarization patterns 150 disposed in the pad area PA of the non-display area NA extend from the planarization layer 140 disposed in an area of the non-display area NA except for the pad area PA. and can be placed. Accordingly, the plurality of planarization patterns 150 disposed in the pad area PA of the non-display area NA and the planarization layer 140 disposed in the area other than the pad area PA of the non-display area NA may be simultaneously formed. may be formed, and may be made of the same material. That is, the planarization layer 140 disposed in the display area AA, the planarization layer 140 disposed in an area other than the pad area PA among the non-display area NA, and the plurality of planarization layers disposed in the pad area PA. The planarization pattern 150 may be formed simultaneously and may be made of the same material.

A plurality of pads 260A and 260B are respectively disposed on each of the plurality of planarization patterns 150 . The plurality of pads 260A and 260B includes a first pad 260A and a second pad 260B. The first pad 260A and the second pad 260B are alternately disposed adjacent to each other. That is, the first pad 260A and the second pad 260B are alternately disposed along the direction in which the pad area PA extends. The extending direction of the pad area PA refers to the same direction as the extending direction of the gate line GL illustrated in FIG. 1 .

Each of the plurality of pads 260A and 260B includes a metal layer and a transparent conductive layer. Specifically, the first pad 260A among the plurality of pads 260A and 260B includes a first metal layer and a first transparent conductive layer. The first metal layer is disposed on the planarization pattern 150 disposed under the first pad 260A. In addition, the second pad 260B of the plurality of pads 260A and 260B includes a second metal layer 261B and a second transparent conductive layer 261B. The second metal layer 261B is disposed on the planarization pattern 150 disposed under the second pad 260B. The first metal layer and the second metal layer 261B may be formed of the same material as the auxiliary wiring disposed in the display area AA.

The first pad 260A is connected to the first data link line DLL1 . The first metal layer of the first pad 260A is electrically connected to the first data link line DLL1 through the third contact hole CH3 formed in the planarization layer 140 . In addition, the second pad 260B is connected to the second data link line DLL2 . The second metal layer 261B of the second pad 260B is electrically connected to the second data link line DLL2 through the first contact hole CH1 formed in the planarization layer 140 and the gate insulating layer 211 . .

A first transparent conductive layer is disposed on the first metal layer of the first pad 260A. The first transparent conductive layer may be disposed on the first metal layer to cover the entire first metal layer. A second transparent conductive layer 261B is disposed on the second metal layer 261B of the second pad 260B. The second transparent conductive layer 261B may be disposed on the second metal layer 261B to cover the entire second metal layer 261B. The first and second metal layers 261B may be more easily corroded than the first and second transparent conductive layers 261B. Therefore, each of the first and second metal layers 261B is covered by the first and second transparent conductive layers, respectively, so that oxidation of the first and second metal layers 261B can be prevented. have.

In the display device 200 according to another embodiment of the present invention, each of the plurality of planarization patterns 150 is disposed under each of the plurality of pads 260A and 260B, so that the data driver 120 and the plurality of pads 260A are disposed. , 260B) can be improved. As described above, when each of the plurality of planarization patterns 150 is disposed under each of the plurality of pads 260A and 260B, the distance from the lower surface of the data pad 123 to the upper surface of the plurality of pads 260A and 260B, and A difference in a separation distance from the lower surface of the data pad 123 to the substrate 110 may be increased compared to a case in which the plurality of planarization patterns 150 are not disposed. Accordingly, a step difference between an area in which the plurality of pads 260A and 260B is disposed and an area in which the plurality of pads 260A and 260B is not disposed between the adjacent pads 260A and 260B may be increased. Accordingly, the plurality of pads 260A and 260B may not be electrically connected to an overlapping data pad and a neighboring data pad instead of the overlapping data pad.

Also, in the display device 200 according to another embodiment of the present invention, the first data link line DLL1 and the second data link line DLL2 are made of different materials, so that the plurality of data link lines DLL1 and DLL2 are formed of different materials. The area of the non-display area NA in which the DLL2 is disposed may be reduced. Specifically, the first data link line DLL1 may be formed of a source electrode and a drain electrode of a transistor, and the second data link line DLL2 may be formed of a gate electrode of the transistor. The first data link line DLL1 and the second data link line DLL2 are alternately disposed adjacent to each other. As the adjacent first data link line DLL1 and the second data link line DLL2 are made of different materials, the gap between the first data link line DLL1 and the second data link line DLL2 is narrowed. can get When the first data link line DLL1 and the second data link line DLL2 are formed of the same material on the same layer, a minimum process margin is required in a photolithography process, etc., so the distance between the lines is constant. should be maintained over the gap. However, when the first data link line DLL1 and the second data link line DLL2 are formed of different materials on different layers, they are formed by different photolithography processes, so that the distance between the wires is formed on the same layer. can be reduced than when formed. Accordingly, in the display device 200 according to another exemplary embodiment of the present invention, since the first data link line DLL1 and the second data link line DLL2 disposed adjacent to each other are made of different materials, the non-display area ( NA) can be reduced.

6 is an enlarged plan view of a display device according to still another exemplary embodiment. 7 is a cross-sectional view taken along line VII-VII' of FIG. 6 . The display device 300 of FIGS. 6 to 7 is substantially different from the display device 100 of FIGS. 1 to 3B except that the plurality of pads 360 and the plurality of data link lines DLL are different. Since it is the same, a duplicate description will be omitted.

6 to 7 , a gate insulating layer 311 , a planarization layer 140 , and a data line DL are disposed in the display area AA. Specifically, a gate insulating layer 311 is disposed on the substrate 110 . A plurality of data lines DL are disposed on the gate insulating layer 311 . Each of the plurality of data lines DL is connected to each of the plurality of pixels disposed in the display area AA.

The plurality of data lines DL may be formed of the same material as a source electrode and a drain electrode of a transistor disposed in the display area AA. A planarization layer 140 is disposed on the plurality of data lines DL. The planarization layer 140 may be disposed over the plurality of data lines DL and the entire display area AA to planarize the upper portions of the plurality of data lines DL. The thickness of the planarization layer 140 may be greater than the thickness of the gate insulating layer 311 disposed in the display area AA. That is, the planarization layer 140 may be a layer having a thickness greater than that of the gate insulating layer 311 .

The planarization layer 140 and the plurality of data link lines DLL are disposed in the non-display area NA except for the pad area PA. Specifically, the planarization layer 140 is disposed on the substrate 110 . The planarization layer 140 may be disposed in an area of the non-display area NA except for the pad area PA to planarize an upper portion of the planarization layer 140 . The planarization layer 140 may be disposed to extend from the planarization layer 140 disposed in the display area AA. Specifically, the planarization layer 140 disposed in the non-display area NA is the same layer as the planarization layer 140 disposed in the display area AA, and may be formed at the same time. Accordingly, the planarization layer 140 disposed in the non-display area NA and the planarization layer 140 disposed in the display area AA may be formed of the same material. However, it is not limited thereto.

A plurality of data link lines DLL is disposed on the planarization layer 140 disposed in the non-display area NA. That is, the plurality of data link lines DLL is disposed on the planarization layer 140 extending from the display area AA to one side of the pad area PA. In this case, the plurality of data link lines DLL may be formed of the same material as the auxiliary lines disposed in the display area AA. As described above, the auxiliary wiring is disposed on the planarization layer 140 and refers to a wiring electrically connected to the common electrode.

Each of the plurality of data link lines DLL is electrically connected to each of the plurality of data lines DL disposed in the display area AA. In detail, each of the plurality of data link lines DLL may be electrically connected to each of the plurality of data lines DL through a contact hole CH formed in the planarization layer 140 .

A transparent conductive layer 362 may be disposed on the data link line DLL. The transparent conductive layer 362 is a layer made of a transparent conductive material, and may be made of, for example, indium tin oxide (ITO). However, it is not limited thereto. Specifically, the transparent conductive layer 362 is disposed on the data link line DLL to cover the entire data link line DLL. Since the transparent conductive layer 362 is disposed to cover the entire data link line DLL, oxidation of the data link line DLL may be prevented.

6 to 7 , a plurality of planarization patterns 150 are disposed in the pad area PA of the non-display area NA. The plurality of planarization patterns 150 may be disposed to extend from the planarization layer 140 disposed in the display area AA. The planarization layer 140 disposed in the non-display area NA except for the pad area PA may extend from the planarization layer 140 disposed in the display area AA, and may be disposed in the pad area PA. The plurality of planarization patterns 150 may be disposed to extend from the planarization layer 140 disposed in an area of the non-display area NA except for the pad area PA. Accordingly, the planarization layer 140 disposed in the display area AA, the planarization layer 140 disposed in a region excluding the pad area PA among the non-display area NA, and the plurality of planarization layers disposed in the pad area PA The planarization patterns 150 may be simultaneously formed, and all may be made of the same material. However, it is not limited thereto.

The plurality of planarization patterns 150 are spaced apart from each other in the pad area PA. In detail, the plurality of planarization patterns 150 may be separated from each other at a predetermined interval and disposed in the pad area PA. Since the plurality of planarization patterns 150 are disposed to be separated from each other, a region in which the plurality of planarization patterns 150 are not disposed may exist between the plurality of planarization patterns 150 . Accordingly, a step may exist between an area in which the planarization pattern 150 is disposed in the non-display area NA and an area in which the planarization pattern 150 is not disposed as an area between the adjacent planarization patterns 150 .

A plurality of pads 360 are disposed on the plurality of planarization patterns 150 . Each of the plurality of pads 360 includes a metal layer 361 and a transparent conductive layer 362 . Specifically, the metal layer 361 is disposed on the planarization pattern 150 , and a transparent conductive layer 362 is disposed on the metal layer 361 . In this case, each of the plurality of pads 360 may be formed of the same material as each of the plurality of data link lines DLL. That is, the metal layer 361 may be made of the same material as the plurality of data link lines DLL. The metal layer 361 may be made of the same material as the auxiliary electrode disposed in the display area AA, and thus the metal layer 361 may be disposed to extend from the plurality of data link lines DLL. The metal layer 361 and the plurality of data link lines DLL may be formed of the same material and may be electrically connected to each other.

A transparent conductive layer 362 is disposed on the metal layer 361 of the plurality of pads 360 . The transparent conductive layer 362 may be disposed on the metal layer 361 to cover the entire metal layer 361 . Accordingly, oxidation of the metal layer 361 may be prevented. In this case, the transparent conductive layer 362 on the metal layer 361 extends from the transparent conductive layer 362 on each of the plurality of data link lines DLL and is formed as one layer. That is, the transparent conductive layer 362 disposed on the plurality of data link lines DLL and the transparent conductive layer 362 disposed on the metal layer 361 of the plurality of pads 360 are formed through the same process to form one single process. It can be arranged in layers.

In the display device 300 according to another embodiment of the present invention, each of a plurality of planarization patterns 150 is disposed under each of a plurality of pads 360 , and a plurality of data link lines DLLs are connected to a plurality of pads. By forming the same material as 360 , a contact defect between the data driver 120 and the plurality of pads 360 may be improved. As described above, when each of the plurality of planarization patterns 150 is disposed under each of the plurality of pads 360 , the distance from the lower surface of the data pad 123 to the upper surface of the pad 360 and the lower surface of the data pad 123 . The difference in the separation distance from the to the substrate 110 may be increased compared to the case in which the plurality of planarization patterns 150 are not disposed. Accordingly, a step difference between an area in which the plurality of pads 360 is disposed and an area in which the pad 360 is not disposed between two adjacent pads 360 may be increased. Conductive balls disposed in a region between adjacent pads 360 where the plurality of pads 360 are not disposed may not be broken. Accordingly, the plurality of pads 360 may be correctly electrically connected to the data pad 123 overlapping each of the plurality of pads 360 , and the non-overlapping data pad 123 and the plurality of pads 360 may be electrically connected to each other. Misconnection can be prevented. Accordingly, in the display device 300 according to another embodiment of the present invention, misalignment and contact between the plurality of pads 360 and the plurality of data pads 123 electrically connected to the plurality of pads 360 . It is possible to improve defects and prevent electrical connection between neighboring pads 360 .

8 is a cross-sectional view of a display device according to another exemplary embodiment. The display device 400 of FIG. 8 is substantially different from the display device 300 of FIGS. 6 to 7 , except that the planarization layer 440 , the data link line DLL, and the plurality of pads 460 are different. As the same bar, duplicate description will be omitted.

Referring to FIG. 8 , a gate insulating layer 311 , a data line DL, and a planarization layer 440 are disposed in the display area AA. Specifically, a gate insulating layer 311 is disposed on the substrate 110 . A plurality of data lines DL are disposed on the gate insulating layer 311 . Each of the plurality of data lines DL is connected to each of the plurality of pixels disposed in the display area AA. In this case, the plurality of data lines DL may be formed of the same material as the source electrode and the drain electrode of the transistor disposed in the display area AA.

A planarization layer 440 is disposed on the plurality of data lines DL. The planarization layer 440 includes a first planarization layer 441 and a second planarization layer 442 . A first planarization layer 441 is disposed on the plurality of data lines DL, and a second planarization layer 442 is disposed on the first planarization layer 441 . The first planarization layer 441 is a layer for planarizing upper portions of devices such as transistors in the display area AA. The second planarization layer 442 is a layer for planarizing upper portions of devices disposed on the first planarization layer 441 . As the second planarization layer 442 is disposed in the display area AA, a conductive layer may be disposed between the first planarization layer 441 and the second planarization layer 442 . Accordingly, an additional wiring made of a conductive layer may be disposed. The first planarization layer 441 and the second planarization layer 442 may be formed of an organic insulating material, but is not limited thereto. The thickness of the first planarization layer 441 and the thickness of the second planarization layer 442 may be greater than the thickness of the gate insulating layer 311 disposed in the display area AA. That is, the first planarization layer 441 and the second planarization layer 442 may be layers having a thickness greater than that of the gate insulating layer 311 .

A first planarization layer 441 , a second planarization layer 442 , a plurality of data link lines DLL, and a transparent conductive layer 462 are disposed in the non-display area NA except for the pad area PA. . Specifically, a first planarization layer 441 is disposed on the substrate 110 . The first planarization layer 441 may extend from the first planarization layer 441 disposed in the display area AA. That is, the first planarization layer 441 disposed in the non-display area NA except for the pad area PA is the same layer as the first planarization layer 441 disposed in the display area AA and is formed at the same time. can be Also, the first planarization layer 441 disposed in the non-display area NA except for the pad area PA and the first planarization layer 441 disposed in the display area AA may be made of the same material. . However, it is not limited thereto.

A second planarization layer 442 is disposed on the first planarization layer 441 . The second planarization layer 442 may extend from the second planarization layer 442 disposed in the display area AA. That is, the second planarization layer 442 disposed in the non-display area NA except for the pad area PA is the same layer as the second planarization layer 442 disposed in the display area AA and is formed at the same time. can be Also, the second planarization layer 442 disposed in the non-display area NA except for the pad area PA and the second planarization layer 442 disposed in the display area AA may be made of the same material. . However, it is not limited thereto.

A plurality of data link lines DLL is disposed on the second planarization layer 442 disposed in the non-display area NA. That is, the plurality of data link lines DLL is disposed on the second planarization layer 442 . In this case, the plurality of data link lines DLL may be formed of the same material as the auxiliary lines disposed in the display area AA. The auxiliary wiring is disposed on the second planarization layer 442 of the display area AA and refers to a wiring electrically connected to the common electrode.

Each of the plurality of data link lines DLL is electrically connected to each of the plurality of data lines DL disposed in the display area AA. Specifically, each of the plurality of data link lines DLL may be electrically connected to each of the plurality of data lines DL through a contact hole CH formed in the first planarization layer 441 and the second planarization layer 442 . have.

A transparent conductive layer 462 may be disposed on the plurality of data link lines DLL. Specifically, the transparent conductive layer 462 is disposed on the data link line DLL to cover the entire data link line DLL. Since the transparent conductive layer 462 is disposed to cover the entire data link line DLL, oxidation of the data link line DLL may be prevented.

Referring to FIG. 8 , a plurality of planarization patterns 450 are disposed in the pad area PA of the non-display area NA. Specifically, the plurality of planarization patterns 450 include a first layer 451 and a second layer 452 . A first layer 451 is disposed on the substrate 110 . The first layer 451 of the planarization pattern 450 of the pad area PA is an area other than the pad area PA among the first planarization layer 441 disposed in the display area AA and the non-display area NA. It may be disposed to extend from the first planarization layer 441 disposed on the . Accordingly, the first layer 451 includes the first planarization layer 441 disposed in the display area AA and the first planarization layer 441 disposed in an area other than the pad area PA among the non-display area NA. It may be made of the same material as A second layer 452 is disposed on the first layer 451 of the plurality of planarization patterns 450 . The second layer 452 of the planarization pattern 450 of the pad area PA is an area other than the pad area PA among the second planarization layer 442 disposed in the display area AA and the non-display area NA. It may be disposed to extend from the second planarization layer 442 disposed on the . Accordingly, the second layer 452 includes the second planarization layer 442 disposed in the display area AA and the second planarization layer 442 disposed in an area of the non-display area NA except for the pad area PA. It may be made of the same material as A plurality of pads 460 are disposed on the plurality of planarization patterns 450 . Specifically, each of the plurality of pads 460 is disposed on the second layer 452 of each of the plurality of planarization patterns 450 . The plurality of pads 460 include a metal layer 461 and a transparent conductive layer 462 . Specifically, the metal layer 461 is disposed on the second layer 452 of the planarization pattern 450 , and a transparent conductive layer 462 is disposed on the metal layer 461 . In this case, the metal layer 461 may be disposed to extend from the plurality of data link lines DLL. In addition, each of the plurality of pads 460 may be formed of the same material as each of the plurality of data link lines DLL. That is, the metal layer 461 may be made of the same material as the plurality of data link lines DLL. The metal layer 461 and the plurality of data link lines DLL may be formed of the same material and may be electrically connected to each other.

A transparent conductive layer 462 is disposed on the metal layer 461 of the plurality of pads 460 . The transparent conductive layer 462 may be disposed on the metal layer 461 to cover the entire metal layer 461 . Accordingly, oxidation of the metal layer 461 may be prevented. In this case, the transparent conductive layer 462 on the metal layer 461 extends from the transparent conductive layer 462 on each of the plurality of data link lines DLL and is formed as one layer. That is, the transparent conductive layer 462 disposed on the plurality of data link lines DLL and the transparent conductive layer 462 disposed on the metal layer 461 of the plurality of pads 460 are formed through the same process to form one single process. It can be arranged in layers.

In the display device 400 according to another exemplary embodiment of the present invention, the planarization layer 440 includes a plurality of planarization layers. Specifically, the planarization layer 440 includes a first planarization layer 441 and a second planarization layer 442 . As the planarization layer 440 includes a plurality of layers, a wiring or device may be disposed between the first planarization layer 441 and the second planarization layer 442 . Accordingly, in the display device 400 according to another embodiment of the present invention, since the planarization layer 440 includes the first planarization layer 441 and the second planarization layer 442 , the wiring of the display device 400 or Additional space required for the arrangement of the device may be secured.

In addition, in the display device 400 according to another exemplary embodiment of the present invention, by disposing each of the plurality of planarization patterns 450 including a plurality of layers under each of the plurality of pads 460 , the plurality of pads 460 . ) and the electrical connection of the data driver 120 may be improved. Specifically, the plurality of planarization patterns 450 include a first layer 451 made of the same material as the first planarization layer 441 disposed in the display area AA and a second planarization layer disposed in the display area AA. and a second layer 452 of the same material as 442 . Accordingly, the thickness of the plurality of planarization patterns 450 may be increased compared to a case in which a single layer is formed. In other words, in the pad area PA, the separation distance from the lower surface of the data pad 123 of the data driver 120 to the upper surface of the pad 460 and the distance from the lower surface of the data pad 123 to the substrate 110 are The difference in the separation distance may be further increased. A step difference between the area in which the pad 460 is disposed and the area between the two pads 460 in which the pad 460 is not disposed may increase. Accordingly, the plurality of pads 460 may not be electrically connected to the data pad 123 overlapping the pad 460 and not to the data pad adjacent to the data pad 123 overlapping the pad 460 . In the display device 400 according to another embodiment of the present invention, since the planarization pattern 450 includes the first layer 451 and the second layer 452 , the plurality of data pads ( 123) and each of the plurality of pads 460 may be clarified, and contact failure and alignment failure may be suppressed.

Display devices according to embodiments of the present invention may be described as follows.

A display device according to an exemplary embodiment may include a substrate including a pad area, a plurality of planarization patterns disposed on the pad area on the substrate, and a plurality of pads disposed on the plurality of planarization patterns.

According to another feature of the present invention, each of the plurality of pads may include a metal layer on the plurality of planarization patterns and a transparent conductive layer covering the metal layer.

According to another feature of the present invention, the plurality of planarization patterns may be spaced apart from each other in the pad area.

According to another aspect of the present invention, the substrate may include a display area and a non-display area surrounding the display area and including a pad area, and the plurality of planarization patterns may be made of the same material as a planarization layer disposed on the display area.

According to another feature of the present invention, the plurality of planarization patterns may extend from the planarization layer.

According to another feature of the present invention, the planarization layer includes a first planarization layer and a second planarization layer on the first planarization layer, and each of the plurality of planarization patterns includes a first layer and a first planarization layer made of the same material as the first planarization layer. A second layer made of the same material as the second planarization layer may be included on the first layer.

According to another aspect of the present invention, the plurality of pads may be formed of the same material as the auxiliary wiring disposed on the planarization layer and electrically connected to the common electrode disposed in the display area.

A display device according to another exemplary embodiment includes a display area, a substrate including a non-display area surrounding the display area and having a pad area, a transistor disposed in the display area, and a planarization layer disposed in the display area to planarize an upper portion of the transistor , a plurality of planarization patterns extending from the planarization layer to the pad area, and a plurality of pads disposed on the plurality of planarization patterns.

According to another feature of the present invention, the plurality of planarization patterns may be separated from each other in the pad area.

According to another feature of the present invention, the plurality of pads may be formed of the same material as the auxiliary wiring disposed on the planarization layer and electrically connected to the common electrode disposed in the display area.

According to another feature of the present invention, each of the plurality of pads may include a metal layer on the plurality of planarization patterns and a transparent conductive layer covering the metal layer.

According to another aspect of the present invention, the display device is disposed in the display area, disposed in a plurality of signal lines electrically connected to the transistor and in the non-display area, and electrically connects each of the plurality of signal lines and each of the plurality of pads. It may further include a plurality of link wiring.

According to another feature of the present invention, the plurality of link wirings may be made of the same material as the gate electrode of the transistor or the source electrode and the drain electrode of the transistor.

According to another feature of the present invention, the planarization layer may be disposed to extend to one side of the pad area of the non-display area, and each of the plurality of link wires may be disposed under the planarization layer.

According to another feature of the present invention, the plurality of link wirings may be made of the same material as the plurality of pads.

According to another feature of the present invention, the planarization layer may be disposed to extend to one side of the pad area of the non-display area, and each of the plurality of link wires may be disposed on the planarization layer.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100, 200, 300, 400: display device
110: substrate
111, 211, 311: gate insulating layer
120: data driving unit
121: base film
122: driving IC
123: data pad
130: gate driver
131: base film
132: driving IC
133: gate pad
140: planarization layer
150: flattening pattern
160, 360, 460: pad
161, 361, 461: metal layer
162, 362, 462: transparent insulating layer
170: adhesive layer
260A: first pad
260B: second pad
261B: second metal layer
261B: second transparent insulating layer
440: planarization layer
441: first planarization layer
442: second planarization layer
450: flattening pattern
451: first planarization pattern
452: second planarization pattern
AA: display area
NA: non-display area
GL: gate wiring
DL: data wiring
GLL: gate link wiring
DLL: Data Link Wiring
DLL1: first data link wiring
DLL2: Second data link wiring
PA: pad area

Claims (16)

a substrate including a display area and a non-display area surrounding the display area and including a pad area;
a thin film transistor disposed in the display area;
a planarization layer disposed on the display area and planarizing an upper portion of the thin film transistor;
a plurality of planarization patterns disposed on the pad area on the substrate; and
a plurality of pads disposed on the plurality of planarization patterns;
The plurality of planarization patterns extend from the planarization layer and are made of the same material as the planarization layer,
The plurality of pads are disposed on the planarization layer and made of the same material as an auxiliary wire electrically connected to the common electrode disposed in the display area;
The plurality of planarization patterns are disposed between the substrate and the plurality of pads. According to claim 1,
Each of the plurality of pads includes a metal layer on the plurality of planarization patterns and a transparent conductive layer covering the metal layer. According to claim 1,
The plurality of planarization patterns are spaced apart from each other in the pad area. delete delete According to claim 1,
The planarization layer consists of a first planarization layer and a second planarization layer on the first planarization layer,
Each of the plurality of planarization patterns includes a first layer made of the same material as the first planarization layer and a second layer on the first layer made of the same material as the second planarization layer. delete a substrate including a display area and a non-display area surrounding the display area and having a pad area;
a transistor disposed in the display area;
a planarization layer disposed on the display area to planarize an upper portion of the transistor;
a plurality of planarization patterns extending from the planarization layer to the pad area and made of the same material as the planarization layer; and
a plurality of pads disposed on the plurality of planarization patterns;
the plurality of pads are disposed on the planarization layer and made of the same material as an auxiliary wire electrically connected to the common electrode disposed in the display area;
The plurality of planarization patterns are disposed between the plurality of pads and the substrate. 9. The method of claim 8,
and the plurality of planarization patterns are separated from each other in the pad area. delete 9. The method of claim 8,
Each of the plurality of pads includes a metal layer on the plurality of planarization patterns and a transparent conductive layer covering the metal layer. 9. The method of claim 8,
a plurality of signal lines disposed in the display area and electrically connected to the transistors; and
and a plurality of link wires disposed in the non-display area and electrically connecting each of the plurality of signal wires and each of the plurality of pads. 13. The method of claim 12,
The plurality of link wirings are made of the same material as a gate electrode of the transistor or a source electrode and a drain electrode of the transistor. 14. The method of claim 13,
The planarization layer is disposed to extend to one side of the pad area of the non-display area,
Each of the plurality of link wirings is disposed under the planarization layer. 13. The method of claim 12,
The plurality of link wirings are made of the same material as the plurality of pads. 16. The method of claim 15,
The planarization layer is disposed to extend to one side of the pad area of the non-display area,
each of the plurality of link wirings is disposed on the planarization layer.

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