KR100558716B1 - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes and prevent corrosion of the shorting line connecting the shorting bar and the pad.

According to an exemplary embodiment of the present invention, a liquid crystal display panel includes a gate line and a data line insulated from a substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and a protection of the thin film transistor. A thin film transistor array substrate connected to at least one of a passivation layer, the gate line, and the data line, the pad having a transparent conductive layer, and wherein the transparent conductive layer is exposed to a side of the substrate; A color filter array substrate opposed to and bonded to the thin film transistor array substrate; The passivation layer may be formed in an area overlapping the color filter array substrate to expose the transparent conductive layer included in the pad.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}             

1 is a plan view showing a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line " II-II '. FIG.

3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4A and 4B are plan views and cross-sectional views illustrating gate shorting bars and data shorting bars extended from the gate pads and the data pads shown in FIGS. 1 and 2.

5 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the thin film transistor array substrate of FIG. 5 taken along the line "VI-VI '".

7A to 7C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention.

8A to 8E are cross-sectional views illustrating a third mask process in detail in a method of manufacturing the thin film transistor array substrate illustrated in FIG. 7C.

9 is a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor array substrate of FIG. 6.

FIG. 10 is a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor array substrate illustrated in FIG. 6.

<Description of Symbols for Main Parts of Drawings>

2,102: gate line 4,104: data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 12 gate insulating film

14,114 active layer 16,116 ohmic contact layer

18,118: protective film 20,56,66,120: contact hole

22,122: pixel electrode 30,130: storage electrode

40,140: Storage capacitor 50,150: Gate pad

52: gate pad lower electrode 54: gate pad upper electrode

60, 160: data pad 62: data pad lower electrode

64: data pad upper electrode 112: gate insulating pattern

152: gate link 168: data link

170: transparent conductive film 172: gate metal film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes and prevent corrosion of the shorting line connecting the shorting bar and the pad.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a lower array substrate (thin film transistor array substrate) and an upper array substrate (color filter array substrate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The lower array substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation and a black matrix for light leakage prevention, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a lower array substrate.

FIG. 1 is a plan view illustrating a lower array substrate using a conventional four mask process, and FIG. 2 is a cross-sectional view illustrating a lower array substrate taken along a line “II-II ′” in FIG. 1.

The lower array substrate illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect on the lower substrate 1 with a gate insulating layer 12 interposed therebetween, and a thin film transistor formed at each intersection thereof. 30, the pixel electrode 22 formed in the cross-sectional structure of the pixel, the gate pad 50 connected to the gate line 2, and the data pad 60 connected to the data line 4. Equipped.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The thin film transistor 30 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor 30 further includes an active layer 14 overlapping with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 8. .

The active layer 14 also overlaps the data line 4, the data pad lower electrode 62, and the storage electrode 28. An ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, the drain electrode 8, and the data pad lower electrode 62 is further formed on the active layer 14.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 40 penetrating the passivation layer 18 and is formed in the pixel region 5.

Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor 30 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the lower array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The gate pad 50 is connected to a gate driver (not shown) to supply a gate signal to the gate line 2. The gate pad 50 includes a gate pad lower electrode 52 extending from the gate line 2 and a second gate hole 56 penetrating through the gate insulating layer 12 and the passivation layer 18. And a gate pad upper electrode 54 connected to 52.

The data pad 60 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through a data pad lower electrode 62 extending from the data line 4 and a third contact hole 66 passing through the passivation layer 18. It consists of a data pad upper electrode 64.

A method of manufacturing a thin film transistor array substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, a first conductive pattern group including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on the lower substrate 1 by using a first mask process. .

In detail, the gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a first conductive pattern group including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52. . Here, an aluminum metal or the like is used as the gate metal layer.

Referring to FIG. 3B, a gate insulating layer 12 is coated on the lower substrate 1 on which the first conductive pattern group is formed. A semiconductor pattern including an active layer 14 and an ohmic contact layer 16 on the gate insulating layer 12 using a second mask process; A second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, and the data pad lower electrode 62 is formed.

In detail, the gate insulating layer 12, the amorphous silicon layer, the n + amorphous silicon layer, and the data metal layer are sequentially formed on the lower substrate 1 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. do. Here, as the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Subsequently, a photoresist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the second conductive layer includes a data line 4, a source electrode 8, and a drain electrode 10 integrated with the source electrode 8. A pattern group is formed.

Then, the ohmic contact layer 14 and the active layer 16 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

The source / drain metal pattern and the ohmic contact layer 16 of the channel portion are etched after the photoresist pattern having a relatively low height is removed from the channel portion by an ashing process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 8 and the drain electrode 10.

Subsequently, the photoresist pattern remaining on the second conductive pattern group is removed by a stripping process.

Referring to FIG. 3C, the passivation layer 18 including the first to third contact holes 20, 56, and 66 may be formed on the gate insulating layer 12 on which the second conductive pattern group is formed by using a third mask process. Is formed.

In detail, the protective film 18 is entirely formed on the gate insulating film 12 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the passivation layer 18 is patterned by a photolithography process and an etching process using a third mask to form first to third contact holes 20, 56, and 66. The first contact hole 20 penetrates the passivation layer 18 to expose the drain electrode 10, and the second contact hole 56 penetrates the passivation layer 18 and the gate insulating layer 12 to form a gate pad lower electrode ( 52 is exposed, and the third contact hole 66 penetrates through the passivation layer 18 to expose the data pad lower electrode 62. Here, when a dry etch ratio metal such as molybdenum (Mo) is used as the data metal, each of the first and third contact holes 20 and 66 penetrates to the drain electrode 10 and the data pad lower electrode 62. To expose their sides.

As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 is formed on the passivation layer 18 by using a fourth mask process. do.

In detail, the transparent conductive film is apply | coated on the protective film 18 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is etched through a photolithography process and an etching process using a fourth mask, thereby forming a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64. Is formed. The pixel electrode 22 is electrically connected to the drain electrode 10 through the first contact hole 20. The gate pad upper electrode 54 is electrically connected to the gate pad lower electrode 52 through the second contact hole 56. The data pad upper electrode 64 is electrically connected to the data lower electrode 62 through the third contact hole 66.

Herein, materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). ) Is used.

As described above, the conventional thin film transistor array substrate and the method of manufacturing the same can reduce the number of manufacturing steps and reduce manufacturing costs in proportion to the case of using the 5 mask process by employing a four mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

In addition, the thin film transistor array substrate of the conventional liquid crystal display panel is formed by a four mask process and then inspects a plurality of gate pads 50 and gates as shown in FIG. 4A to check for defects including short circuits and disconnections in signal lines. A gate shorting bar 80 connected through the shorting line 82, a plurality of data pads 60, and a data shorting bar 90 connected through the data shorting line 92 are provided. After detecting whether the liquid crystal display panel is defective by using the shorting bars 80 and 90, the lower substrate 101 is cut along the cut line SCL that intersects the gate shorting line 82 and the data shorting line 92. As shown in FIG. 4B, the gate shorting line 82 and the data shorting line 92 are exposed to the side of the lower substrate 101. At this time, the gate shorting line 82 formed of a metal having low corrosion resistance, for example, aluminum or copper, is easily corroded in a high temperature and high humidity environment or an electric field applied during TFT driving, and the corrosion phenomenon propagates. Such corrosion may progress to the gate pad 50 and the data pad 60 as time passes.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes and prevent corrosion of the shorting line connecting the shorting bar and the pad.

In order to achieve the above object, a liquid crystal display panel according to the present invention includes a gate line and a data line insulated on a substrate, a thin film transistor formed at an intersection of the gate line and the data line, and a pixel electrode connected to the thin film transistor. A thin film transistor array substrate connected to at least one of a passivation layer for protecting the thin film transistor, at least one of the gate line and the data line, and having a pad formed of a transparent conductive film, and having the transparent conductive film exposed to a side of the substrate; A color filter array substrate opposed to and bonded to the thin film transistor array substrate; The passivation layer may be formed in an area overlapping the color filter array substrate to expose the transparent conductive layer included in the pad.

A gate pad connected to the gate line and formed of the transparent conductive film included in the gate line; And a data pad connected to the data line and formed of the transparent conductive film.

The LCD panel may include a shorting bar formed on the substrate to remove defects of the gate line, data line, and thin film transistor and removed by a scribing process, and connecting the shorting bar and the pad to each other. And a shorting line formed by the transparent conductive film that is removed based on the cutting line of the substrate by the process and is exposed to the side surface of the substrate.

The shorting bar may be formed of a transparent conductive film and a gate metal film formed on the transparent conductive film.

The shorting line may include a transparent conductive film and a gate metal film formed on the transparent conductive film and formed to expose the transparent conductive film in a region corresponding to the cut line.

The thin film transistor may include a gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor layer overlapping the gate electrode with the gate insulating pattern therebetween and forming a channel portion between the source electrode and the drain electrode.

The gate line and the gate electrode are formed of the transparent conductive film and a gate metal film formed on the transparent conductive film.

The transparent conductive film may include at least one of TO, ITO, IZO, and ITZO.

The gate metal layer may include at least one of aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), tantalum (Ta), and titanium (Ti).

The liquid crystal display panel may further include an alignment layer formed on the passivation layer in the same pattern as the passivation layer.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention includes a gate pattern including a gate line, a gate electrode, a gate pad, and a data pad including a transparent conductive film on a substrate, and the gate pad and data pad. Forming a shorting line connected to at least one of the at least one of the at least one of the at least one of the shorting lines connected to the shorting lines and the pixel electrodes; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns, the inspection patterns, and the pixel electrode are formed; Forming a data pattern including a data line, a source electrode, and a drain electrode on the substrate on which the semiconductor pattern and the gate insulating pattern are formed; Forming a protective film on the entire surface of the substrate to protect the thin film transistor; Forming an alignment layer on the passivation layer except for the pad region including the gate pad and the data pad; Exposing the transparent conductive film included in the pad area by removing the protective film formed to cover the pad area using the alignment layer as a mask; And scribing the substrate to expose the transparent conductive film to the side of the substrate across the shorting line.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention includes a gate line and a data line insulated on a substrate, a thin film transistor formed at an intersection of the gate line and the data line, and a connection with the thin film transistor. A thin film transistor array substrate having a pad formed of a transparent conductive film connected to at least one of a pixel electrode, a protective film for protecting the thin film transistor, the gate line and a data line, and exposing the transparent conductive film to a side of the substrate. Steps; Providing a color filter array substrate facing the thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate to expose a pad region including the gate pad and the data pad; And exposing the transparent conductive film of the pad area using the color filter array substrate as a mask.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 10.

FIG. 5 is a plan view illustrating a TFT array substrate of a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view illustrating a TFT array substrate taken along a line “VI-VI ′” in FIG. 5.

The TFT array substrate shown in FIGS. 5 and 6 includes a display unit for implementing an image, a pad unit for supplying a driving signal to signal lines of the display unit, and a shorting unit for preventing defects in the display unit due to static electricity.

The display unit has a gate line 102 and a data line 104 formed on the lower substrate 101 with the gate insulating pattern 112 interposed therebetween, a thin film transistor 130 formed at each intersection thereof, and a cross structure thereof. The pixel electrode 122 formed in the provided pixel region 105 is provided.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure to define the pixel region 105.

The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode connected to the pixel electrode 122. 110). In addition, the thin film transistor 130 further includes an active layer 116 overlapping with the gate electrode 106 and the gate insulating pattern 112 therebetween to form a channel between the source electrode 108 and the drain electrode 110. do. An ohmic contact layer 116 for ohmic contact with the data line 104, the drain electrode 110, and the storage electrode 128 is further formed on the active layer 116.

The pixel electrode 122 is directly connected to the drain electrode 110 of the thin film transistor 130 and formed in the pixel region 105. The pixel electrode 122 includes a transparent conductive film 170 formed to be exposed in the pixel region 105, and a gate metal film 172 formed on a region overlapping the drain electrode 110 on the transparent conductive film 170. do.

Accordingly, an electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 105 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The pad portion includes a gate pad 150 extending from the gate line 102 and a data pad 160 extending from the data line 104.

The gate pad 150 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102 through the gate link 152. The gate pad 150 has a structure in which the transparent conductive layer 170 included in the gate link 152 connected to the gate line 102 is exposed.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104 through the data link 168. The data pad 160 has a structure in which the transparent conductive layer 170 included in the data link 168 connected to the data line 104 is exposed. The data link 168 includes a data link lower electrode 162 formed at the same time as the gate link 152 and a data link upper electrode 166 connected to the data line 104.

The shorting part is supplied with an inspection signal to inspect the defect of the signal line including the gate line 102 and the data line 104 and the defect of the thin film transistor 130, and the signal lines 102 and 104 of the liquid crystal display panel during the manufacturing process. A shorting bar is connected to a ground voltage source (GND) to block the static electricity transmitted to the side to protect the thin film transistor 130 from static electricity.

  To this end, the shorting part may include a gate shorting bar 180 connected to the plurality of gate lines 102 through the gate pads 150, and data connected to the plurality of data lines 104 through the data pads 160. The shorting bar 190 is provided.

The gate shorting bar 180 has a structure in which a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170 are stacked. The gate shorting bar 180 is electrically connected to the gate pad 150 through the gate shorting line 182.

The data shorting bar 190 has a structure in which a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170 are stacked. The data shorting bar 190 is electrically connected to the data pad 160 through the data shorting line 192.

The shorting line of at least one of the data shorting line 182 and the gate shorting line 192 is formed of the transparent conductive film 170. Or a transparent conductive film 170 and a gate metal film 172 partially exposing the transparent conductive film 170 on the transparent conductive film 170. That is, the shorting lines 182 and 192 are formed to expose the transparent conductive film in a region corresponding to the scribing line SCL of the lower substrate. This is to prevent the gate metal film from being exposed to the side by the scribing process to be corroded when the shorting lines 182 and 192 of the region corresponding to the scribing line SCL are formed to include the gate metal film. Accordingly, when the lower substrate 101 is cut along the scribing line SCL, the transparent conductive film 170 is exposed to the side of the substrate, thereby eliminating the risk of corrosion.

7A to 7C are cross-sectional views illustrating a method of manufacturing a TFT array substrate of a liquid crystal display panel according to the present invention.

Referring to FIG. 7A, the pixel electrode 122 is formed on the lower substrate 101 by a first mask process; Two-layered gate line 102, gate electrode 106, gate link 152, gate pad 150, data pad 160, data link lower electrode 162, gate shorting bar 180, gate A gate pattern including the shorting line 182, the data shorting bar 190, and the data shorting line 192 is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive film 170 may be formed of indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). A transparent conductive material such as) is used, and a metal such as aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), tantalum (Ta), titanium (Ti), or the like is used as the gate metal film 172. Subsequently, the transparent conductive film 170 and the gate metal film 172 are patterned by a photolithography process and an etching process using a first mask to form the pixel electrode 122; A two-layer gate line 102, a gate electrode 106, a gate link 152, a gate pad 150, a data pad 160, a data link lower electrode 162, a gate shorting bar 180, A gate pattern including the gate shorting line 182, the data shorting bar 190, and the data shorting line 192 is formed.

Referring to FIG. 7B, the gate insulating pattern 112 may be formed on the lower substrate 101 on which the gate pattern is formed; A semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed.

To this end, the gate insulating film and the first and second semiconductor layers are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. Herein, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film, and the first semiconductor layer is made of amorphous silicon without doping impurities, and the second semiconductor layer is made of N. Amorphous silicon doped with impurities of type or P type is used. Subsequently, the first and second semiconductor layers and the gate insulating layer are patterned by a photolithography process and an etching process using a second mask to form a gate line 102, a gate electrode 106, a gate link 152, and a data link 162. ) And a semiconductor pattern including an active insulating layer 114 and an ohmic contact layer 116 having a width wider than the gate pattern is formed on the gate insulating pattern 112. This is to prevent the channel characteristics when the semiconductor pattern is narrower than the width of the gate electrode 106.

Referring to FIG. 7C, the data line 104, the source electrode 108, the drain electrode 110, the storage electrode 128, and the data link are formed on the lower substrate 101 on which the gate insulating pattern 112 and the semiconductor pattern are formed. The data pattern including the upper electrode 166 is formed. In addition, the gate metal layer 172 included in the data pad 160, the gate pad 150, the pixel electrode 122, the gate shorting line 182, and the data shorting line 192 is removed to form the transparent conductive film 170. Is exposed. The third mask process will be described in detail with reference to FIGS. 8A to 8E as follows.

As shown in FIG. 8A, the data metal layer 109 and the photoresist layer 228 are sequentially formed on the lower substrate 101 on which the semiconductor pattern is formed by a deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, the third mask 220, which is a partial exposure mask, is aligned above the lower substrate 101. The third mask 220 includes a mask substrate 222 made of a transparent material, a blocking portion 224 formed in the blocking region S2 of the mask substrate 222, and a partial exposure region S3 of the mask substrate 222. The formed diffraction exposure part 226 (or semi-transmissive part) is provided. Here, the region where the mask substrate 222 is exposed becomes the exposure region S1. After exposing and developing the photoresist film 228 using the third mask 220, as shown in FIG. 8B, the blocking part 224 and the diffraction exposure part 226 of the third mask 220 may be formed. A photoresist pattern 230 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 230 formed in the partial exposure region S3 has a second height lower than that of the photoresist pattern 230 having the first height formed in the blocking region S2.

The data metal layer 109 is patterned by a wet etching process using the photoresist pattern 230 as a mask, so that the storage electrode 128, the data line 104, the source electrode 108 connected to the data line 104, and the drain are formed. A data pattern including an electrode 110 and a data link upper electrode 166 connected to the other side of the data line 104 is formed, and the gate metal layer 172 formed under the data pattern is formed of the gate insulating pattern 112. The mask is removed using a mask to expose the transparent conductive film 170 included in the data pad 160, the gate pad 150, the pixel electrode 122, the gate shorting line 182, and the data shorting line 192.

The active layer 114 and the ohmic contact layer 116 are formed along the data pattern by a dry etching process using the photoresist pattern 230 as a mask. At this time, the active layer 114 and the ohmic contact layer 116 positioned in the remaining region except for the active layer 114 and the ohmic contact layer 116 overlapping the data pattern are removed. This is to prevent a short circuit between cells due to the semiconductor pattern including the active layer 114 and the ohmic contact layer 116.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 230 having the second height in the partial exposure region S3 is removed as shown in FIG. 8C, and the blocking region S2 is removed. The photoresist pattern 230 having the first height h1 is in a state where the height is lowered. In the etching process using the photoresist pattern 230, the data metal layer and the ohmic contact layer 116 formed in the channel portion of the thin film transistor, ie, the channel portion of the thin film transistor, are removed, thereby draining the drain electrode 110 and the source electrode 108. This is separated. The photoresist pattern 230 remaining on the data pattern is removed by a strip process as shown in FIG. 8D.

Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed as shown in FIG. 8E. As the passivation layer 118, an inorganic insulating material such as the gate insulating pattern 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used.

FIG. 9 is a cross-sectional view illustrating a liquid crystal display panel including the TFT array substrate illustrated in FIG. 6.

The liquid crystal display panel shown in FIG. 9 includes a color filter array substrate 300 and a TFT array substrate 302 bonded by a material 254.

The color filter array substrate 300 has a color filter array 252 including a black matrix and a color filter formed on the upper substrate 250. In the TFT array substrate 302, a region overlapping with the color filter array substrate 300 is protected by the protection pattern 304, and a pad region not overlapping with the color filter array substrate 300 includes the gate pad 150 and the data. The transparent conductive film 170 included in the pads 160 is formed to be exposed.

Referring to the manufacturing method of the liquid crystal display panel, first, the color filter array substrate 300 and the TFT array substrate 302 illustrated in FIG. 6 are separately formed and then bonded to the real material 254. Then, the protective film 118 of the TFT array substrate 302 shown in FIG. 6 is patterned by a pad opening process using the color filter array substrate 300 as a mask to form a protective pattern 304 in the display area. The gate pad 150 of the display area and the transparent conductive film 170 of the data pad 160 are exposed. Then, the non-display area including the gate shorting part and the data shorting part is cut based on the scribing line by the scribing process. At this time, since the transparent conductive film 170 is exposed to the side surface of the substrate 101 cut by the scribing line SCL, corrosion of the metal is prevented.

Meanwhile, in the pad opening process, each pad exposed by the color filter array substrate 300 is sequentially scanned using the plasma generated by the atmospheric pressure plasma generating unit, or the pads are collectively scanned for each pad unit to form the gate pad 150. And the transparent conductive film 170 of the data pad 160 is exposed. Alternatively, after inserting a plurality of liquid crystal cells in which the color filter array substrate 300 and the TFT array substrate 302 are bonded into the chamber, the protective film 118 of the pad region exposed by the color filter array substrate 300 using atmospheric pressure plasma. ) Is etched to expose the transparent conductive film 170 of the gate pad 150 and the data pad 160. Alternatively, the entire liquid crystal cell, to which the color filter array substrate 300 and the TFT array substrate 302 are bonded, may be immersed in an etchant, or only a pad region including the gate pad 150 and the data pad 160 may be immersed in the etchant. 150 and the transparent conductive film 170 of the data pad 160 are exposed.

FIG. 10 is a cross-sectional view illustrating another form of the liquid crystal display panel including the TFT array substrate illustrated in FIG. 6.

The liquid crystal display panel shown in FIG. 10 includes a color filter array substrate 300 and a TFT array substrate 302 bonded by a material 254.

The color filter array substrate 300 has a color filter array 252 including a black matrix and a color filter formed on the upper substrate 250. In the TFT array substrate 302, the display area defined by the alignment layer 282 is protected by the protection pattern 118, and the gate pad 150 and the data pad of the pad area included in the region overlapping with the alignment layer 282. The transparent conductive film 170 of 160 is formed to be exposed. In this case, the protective pattern 118 is patterned and formed by an etching process using the alignment layer 382 as a mask. Then, the non-display area including the gate shorting part and the data shorting part is cut based on the scribing line by the scribing process. At this time, since the transparent conductive film 170 is exposed to the side surface of the substrate 10 cut by the scribing line SCL, corrosion of the metal is prevented.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention are formed such that the transparent conductive film is exposed in the region corresponding to the scribing line and the shorting line crossing the scribing line to connect the pad and the shorting bar. . Accordingly, since the transparent conductive film is exposed to the side of the substrate after the scribing process, corrosion of the signal line can be prevented. In addition, in the thin film transistor array substrate, a gate pattern and a pixel electrode are formed by a first mask process, a semiconductor pattern is formed by a second mask process, a data pattern is formed by a third mask process, and a transparent conductive film included in the pixel electrode is formed. Exposed. As such, by forming the thin film transistor array substrate in a three mask process, the structure and manufacturing process may be simplified, manufacturing cost may be reduced, and manufacturing yield may be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (25)

A gate line and a data line insulated from each other with a gate insulating pattern interposed therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and a thin film transistor for protecting the thin film transistor A thin film transistor array substrate having a pad connected to at least one of a passivation layer, the gate line, and a data line and having a pad formed of a transparent conductive film, wherein the transparent conductive film is exposed to a side of the substrate; A color filter array substrate opposed to and bonded to the thin film transistor array substrate; The passivation layer is formed in an area overlapping the color filter array substrate to expose the transparent conductive layer included in the pad. Each of the pixel electrode, the gate line, and the gate electrode includes a transparent conductive film formed on the substrate, and each of the gate line and the gate electrode includes a gate metal film formed on the transparent conductive film. Display panel. The method of claim 1, The pad A gate pad connected to the gate line and formed of the transparent conductive film included in the gate line; And a data pad connected to the data line and formed of the transparent conductive film. The method of claim 1, A shorting bar formed on the substrate and removed by a scribing process; And a shorting line connecting the shorting bar and the pad and formed of the transparent conductive film exposed to the side surface of the substrate by being removed based on the cutting line of the substrate by the scribing process. . The method of claim 3, wherein And the shorting bar comprises a transparent conductive film and a gate metal film formed on the transparent conductive film. The method of claim 4, wherein And the shorting line includes a transparent conductive film and a gate metal film formed on the transparent conductive film and formed to expose the transparent conductive film in a region corresponding to the perforated line. The method of claim 1, The thin film transistor is A gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor layer overlapping the gate electrode and the gate insulating pattern therebetween and forming a channel portion between the source electrode and the drain electrode. delete The method of claim 1, The transparent conductive film includes at least one of TO, ITO, IZO and ITZO. The method according to claim 4 or 5, The gate metal layer includes at least one of aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), tantalum (Ta), and titanium (Ti). The method of claim 1, And an alignment layer formed on the protective layer in the same pattern as the protective layer. A gate pattern including a transparent conductive film on a substrate, a gate line including a gate metal film on the transparent conductive film, a gate electrode, a gate pad, and a data pad, and a cutout line connected to at least one of the gate pad and the data pad. Forming a shorting line including the transparent conductive film, test patterns including a shorting bar connected to the shorting line, and a pixel electrode on the shorting line; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns, the inspection patterns, and the pixel electrode are formed; Forming a data pattern including a data line, a source electrode, and a drain electrode on the substrate on which the semiconductor pattern and the gate insulating pattern are formed; Forming a protective film on the entire surface of the substrate to protect the thin film transistor; Forming an alignment layer on the passivation layer except for the pad region including the gate pad and the data pad; Exposing the transparent conductive film included in the pad area by removing the protective film formed to cover the pad area using the alignment layer as a mask; And scribing the substrate and the shorting line across the shorting line along the perforation line to expose the transparent conductive film to the side surface of the substrate. The method of claim 11, And exposing the transparent conductive film included in the shorting line, the pixel electrode, the gate pad, and the data pad using at least one of the data pattern, the gate insulating pattern, and the semiconductor pattern as a mask. Method of manufacturing a liquid crystal display panel. The method of claim 11, The shorting line includes a gate metal film formed on the transparent conductive film, And the gate metal film of the shorting line is removed in a region corresponding to the cut line. The method of claim 11, Wherein the shorting bar, the gate line, and the gate electrode are formed of the transparent conductive film and a gate metal film formed on the transparent conductive film. The method of claim 11, The transparent conductive film includes at least one of TO, ITO, IZO and ITZO manufacturing method of the liquid crystal display panel. The method according to any one of claims 13 and 14, The gate metal layer may include at least one of aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), tantalum (Ta), and titanium (Ti). The method of claim 11, Exposing the transparent conductive film included in the pad area by removing the protective film formed to cover the pad area using the alignment layer as a mask; Printing an alignment layer on the substrate on which the protective layer is formed; And etching the passivation layer formed to cover at least one of the gate pad and the data pad by using the alignment layer as a mask. A gate line and a data line insulated from the substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, a protective film for protecting the thin film transistor, the gate line and data A transparent conductive film having a pad connected to at least one of the lines, wherein the pixel electrode includes a transparent conductive film formed on the substrate, and the gate line, the gate electrode of the thin film transistor, and each of the pads are formed on the substrate and the transparency. Providing a thin film transistor array substrate including a gate metal film formed on an entire film, wherein the transparent conductive film is exposed at a side of the substrate; Providing a color filter array substrate facing the thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate to expose a pad region including the gate pad and the data pad; And exposing a transparent conductive film in a pad area using the color filter array substrate as a mask. The method of claim 18, Preparing the thin film transistor array substrate A gate pattern including a gate line, a gate electrode, a gate pad, and a data pad including a transparent conductive layer on the substrate, and a shorting line and a shorting line connected to at least one of a pixel electrode, a gate pad, and a data pad. Forming inspection patterns including a shorting bar; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns, pixel electrodes, and inspection patterns are formed; Forming a data pattern including a data line, a source electrode, and a drain electrode on the substrate on which the semiconductor pattern and the gate insulating pattern are formed; Forming a protective film on the substrate on which the data pattern is formed; And scribing the substrate across the shorting line along a perforation line to remove the inspection pattern. The method of claim 19, Exposing a transparent conductive film included in the shorting line, the pixel electrode, the gate pad, and the data pad by using at least one of the data pattern, the gate insulating pattern, and the semiconductor pattern as a mask. Method of manufacturing a liquid crystal display panel. The method of claim 18, And the shorting line includes a transparent conductive film, and a gate metal film formed on the transparent conductive film and formed to expose the transparent conductive film in a region corresponding to the cutout line. The method of claim 19, Wherein the shorting bar, the gate line, and the gate electrode are formed of the transparent conductive film and a gate metal film formed on the transparent conductive film. The method of claim 18, The transparent conductive film includes at least one of TO, ITO, IZO and ITZO manufacturing method of the liquid crystal display panel. The method according to any one of claims 21 and 22, The gate metal layer may include at least one of aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), tantalum (Ta), and titanium (Ti). The method of claim 18, Exposing the transparent conductive film of the pad area using the color filter array substrate as a mask And removing the protective layer of the pad area by an etching process using the color filter array substrate as a mask.

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