KR101177117B1 - Thin film transistor array substrate and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate of a liquid crystal display device and a method of manufacturing the liquid crystal display device capable of stabilizing a manufacturing process of a liquid crystal display device including a lift-off process.

The thin film transistor substrate includes a gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A gate pad lower electrode extending from the gate line to apply a gate signal to the gate line; A data pad lower electrode configured to apply a data signal to the data line; A first electrode hole penetrating the gate pad lower electrode at the center portion of the gate pad lower electrode to expose the substrate; A second electrode hole penetrating the data pad lower electrode at the center of the data pad lower electrode to expose the substrate; A passivation layer covering the gate insulating layer and the data line; A first contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the first electrode hole and exposing a part of the gate pad lower electrode; A second contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the second electrode hole and exposing a portion of the lower electrode of the data pad; A gate pad upper electrode formed in the first contact hole and connected to the gate pad lower electrode; And a data pad upper electrode formed in the second contact hole and connected to the data pad lower electrode.

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF}

1 is a plan view illustrating a thin film transistor substrate formed through a mask process including a conventional lift-off process.

FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate taken along lines II ′, II-II ′, III-III ′, and IV-IV ′ of FIG. 1.

3A to 3J are diagrams for sequentially illustrating a manufacturing process of the thin film transistor substrate illustrated in FIG. 2.

4 is a diagram for explaining an auto probe inspection process.

5 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a thin film transistor substrate taken along lines VV ′, VIVVI ′, VIII-VIII, and VIII-VIII shown in FIG. 5.

FIG. 7 is a cross-sectional view illustrating a pad portion of a thin film transistor substrate taken along the lines VIII-VIII and VIII-VIII shown in FIG.

8A and 8B are plan and cross-sectional views illustrating a first mask process of a thin film transistor substrate according to an exemplary embodiment of the present invention.

9A and 9B are plan and cross-sectional views illustrating a second mask process of a thin film transistor substrate according to an exemplary embodiment of the present invention.

10A and 10B are a plan view and a cross-sectional view for describing a third mask process of a thin film transistor substrate according to an embodiment of the present invention.

11 is a plan view and a sectional view for explaining a first mask process of a thin film transistor substrate according to an embodiment of the present invention.

12 is a plan view and a sectional view for explaining a second mask process of a thin film transistor substrate according to an embodiment of the present invention.

13 is a plan view and a sectional view for explaining a third mask process of a thin film transistor substrate according to an embodiment of the present invention.

14 is a plan view and a sectional view for explaining the auto probe inspection of the thin film transistor substrate according to the embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: lower substrate 20, 120: gate line

30, 130: data line 40, 140: thin film transistor

80, 180: gate pad 90, 190: data pad

81, 181: gate pad lower electrode 91, 191: data pad lower electrode

82, 182: gate pad upper electrode 92, 192: data pad upper electrode

60, 160: pixel electrodes 51, 52, 95, 151, 152, 195: contact holes

201 and 202: electrode holes 50 and 150: protective film

25, 125: gate insulating film 61, 161: pixel hole

194, 195: link electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate of a liquid crystal display device and a method of manufacturing the liquid crystal display device capable of stabilizing a manufacturing process of a liquid crystal display device including a lift-off process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a thin film transistor substrate and a color filter substrate bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel.

In order to solve the problems described above, the thin film transistor substrate is developing in a direction of reducing the number of mask processes, which means that one mask process includes a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection. It is because it includes many processes, such as a process.

Therefore, recently, a three-mask process using a lift-off method or a passiless method that reduces one mask process in a five mask or four mask process, which is a standard mask process of a thin film transistor substrate, has emerged. have.

First, the structure and operation of a thin film transistor substrate manufactured through a conventional three mask process will be described with reference to FIGS. 1 and 2. 1 is a plan view of a thin film transistor substrate fabricated through a three-mask process using a conventional lift-off method, and FIG. 2 is a line I-I ', II-II', III-III ', and IV-IV in FIG. 1. A cross-sectional view of a thin film transistor substrate taken along a line.

1 and 2, a thin film transistor substrate manufactured by a three-mask process using a conventional lift-off method may include a gate line 20 and a gate insulating film 25 interposed therebetween. A data line 30 crossing each other to define a pixel region, a thin film transistor 40 formed at each intersection thereof, a pixel electrode 60 and a gate line connected to the thin film transistor 40 and formed in the pixel hole 61 of the pixel region. A storage capacitor 70 formed at an overlapping portion of the 20 and the storage electrode 65, a gate pad 80 connected to the gate line 20, and a data pad 90 connected to the data line 30. .

Here, the thin film transistor 40 keeps the pixel signal supplied to the data line 30 charged in the pixel electrode 60 in response to the gate signal supplied from the gate line 20. To this end, the thin film transistor 40 faces the gate electrode 22 connected to the gate line 20, the source electrode 32 connected to the data line 30, and the source electrode 32 and at the same time the pixel electrode 60. ), And a drain electrode 33 connected thereto.

In addition, the thin film transistor 40 may be formed to overlap the gate electrode 22 with the gate insulating layer 25 therebetween to form a channel between the source electrode 32 and the drain electrode 33. An ohmic contact layer 35 formed on the active layer 34 except for the channel part is further provided for ohmic contact between the electrode 32 and the drain electrode 33.

In this case, the semiconductor pattern 37 including the active layer 34 and the ohmic contact layer 35 is formed to overlap the data line 30, the data pad lower electrode 91, and the storage electrode 65.

The passivation 50 covers the thin film transistor 40 formed on the gate insulating layer 25, thereby protecting the active layer 34 forming the channel from moisture or scratches that may occur in a subsequent process. Do this.

The pixel electrode 60 is formed in a defined pixel region by crossing the gate line 20 and the data line 30. In this pixel region, a pixel hole 61 penetrating the passivation layer 50 and the gate insulating layer 25 to expose the lower substrate 10 is formed, and the pixel electrode 60 is formed in the pixel hole 61. In addition, the drain electrode 33 of the thin film transistor 40 is in lateral contact.

The pixel electrode 60 charges a pixel signal supplied from the thin film transistor 40 to generate a potential difference with a common electrode formed on a color filter substrate (not shown). Due to this potential difference, the liquid crystals positioned on the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy, and the amount of light incident through the pixel electrode 60 from a light source (not shown) is controlled to be transmitted to the color filter substrate.

The storage capacitor 70 includes a gate line 20, and a storage electrode 65 overlapping the gate line 20 with the gate insulating layer 25, the active layer 34, and the ohmic contact layer 35 therebetween. do. Here, the pixel electrode 60 formed in the area of the pixel hole 61 is connected to the side surface of the storage electrode 65. The storage capacitor 70 allows the pixel signal charged in the pixel electrode 60 to remain stable until the next pixel signal is charged.

The gate pad 80 is connected to a gate driver (not shown) to supply a gate signal to the gate line 20. The gate pad 80 includes a gate pad lower electrode 81 extending from the gate line 20, a first contact hole 51 penetrating through the gate insulating layer 25 and the passivation layer 50, and a first contact hole. The gate pad upper electrode 82 is formed on the inner surface of the 51 and connected to the gate pad lower electrode 81. The upper electrode 82 of the gate pad forms a boundary with the passivation layer 50 in the first contact hole 51.

The data pad 90 is connected to a data driver (not shown) to supply a data signal to the data line 30. The data pad 90 is formed on the inner surface of the data pad lower electrode 91, the second contact hole 52 penetrating the gate insulating layer 25 and the passivation layer 50, and the second contact hole 52. The data pad upper electrode 92 is connected to the data pad lower electrode 91. The data pad upper electrode 92 is bordered with the passivation layer 50 in the second contact hole 52. Since the data pad lower electrode 91 is made of the same metal on the same plane as the gate pad lower electrode 81, the vertical structures of the data pad 90 and the gate pad 80 are identically formed. The formation of the data pad 90 in the same structure as the gate pad 80 is to deviate from the general data pad structure which is susceptible to corrosion in the three mask structure including the lift-off process. A typical data pad structure is one in which the data bottom electrode extends from the data line and is made of the same metal layer as the data line. Accordingly, the data pad lower electrode 91 having the same vertical structure as the gate pad 80 is connected to the data line 30 through the first and second link electrodes 94 and 97 and the third contact hole 95. do.

The first link electrode 94 extends from the data pad lower electrode 91.

The second link electrode 97 extends from the data pad upper electrode 92, overlaps a portion of the data line 30, and penetrates the gate insulating layer 25 and the passivation layer 50 to pass through the data line 30. And the data line 30 and the first link electrode 94 through the third contact hole 95 exposing the first link electrode 94.

As described above, the data pad lower electrode 92 is connected to the data line 30 through the first and second link electrodes 94 and 97 and the third contact hole 95.

Meanwhile, the interface between the gate pad lower electrode 81 and the data pad lower electrode 91 and the passivation layer 50 exposed by the first and second contact holes 51 and 52, in particular, the pad lower electrode 81 and 91. An etching gas used to form the first and second contact holes 51 and 52 may remain at the boundary surface of the long side direction L of the cross-section. The remaining etching gas becomes a problem because it corrodes the pad lower electrodes 81 and 91 as shown in A. FIG.

Hereinafter, a method of manufacturing a thin film transistor substrate using a conventional three mask process will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 3A, the gate electrode 20 and the gate pad lower electrode 81 connected to the gate line 20, the gate line 20, and data on the lower substrate through the first mask process may be used. A first conductive pattern group including the pad lower electrode 91 and the first link electrode 94 connected to the data pad lower electrode 91 is formed.

Referring to the formation of the first conductive pattern group in more detail, the gate metal layer is formed on the lower substrate 10 through a deposition method such as a sputtering method.

Thereafter, the photoresist is entirely coated on the gate metal layer, and then the gate metal layer is patterned through a photolithography process and an etching process using a first mask, thereby forming the gate line 20 and the gate line 20 on the lower substrate 10. ) And a first conductive electrode including a gate electrode 22 and a gate pad lower electrode 81 connected to each other, and a first link electrode 94 connected to the data pad lower electrode 91 and the data pad lower electrode 91. A pattern group is formed. An aluminum metal material such as Al, AlNd, or the like is used as the gate metal for forming the first conductive pattern group.

As described above, after the first conductive pattern group is formed on the lower substrate 10, the active layer 34 forming a channel on the gate insulating layer 25 through a second mask process and the ohmic contact formed thereon. A second conductive pattern group including the semiconductor pattern 37 including the layer 35, the source electrode 32, the drain electrode 33, the data line 30, and the storage electrode 65 is formed.

A process of forming the semiconductor pattern 37 and the second conductive pattern group will be described in more detail. As shown in FIG. 3B, the gate insulating layer is deposited on the lower substrate on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. 25, the amorphous silicon layer 34a, the amorphous silicon layer 35a doped with impurities (n + or p +) and the data metal layer 31 are sequentially formed.

As the gate insulating layer 25, an inorganic insulating material such as silicon oxide (SiO _X ), silicon nitride (SiN _X ), or the like is used. As the data metal layer 31, a metal, for example, Mo, Cu-based, Al-based, Cr-based, or the like, in which exposed portions may be etched together during the etching of the protective film 50 in a subsequent process, may be used. .

Thereafter, the photoresist is entirely coated on the data metal layer 31, and then the photoresist, which is entirely coated, is exposed and developed in a photolithography process using the second mask 7, which is a diffraction exposure mask, thereby as shown in FIG. 3B. A photoresist pattern 1 having a step is formed on the metal layer 31.

The diffraction exposure mask 7 includes a transparent quartz substrate 11, a blocking layer 13 formed of a metal layer such as Cr, CrOx or the like, and a slit 15 for diffraction exposure. The blocking layer 13 is positioned in a region where the semiconductor pattern and the source / drain electrodes are to be formed to block ultraviolet rays, thereby leaving the first photoresist pattern 1a after development. The diffraction exposure slit 15 is positioned in a region where a channel of the thin film transistor is to be formed to diffract ultraviolet rays, thereby leaving a second photoresist pattern 1b thinner than the first photoresist pattern 1a after development.

Subsequently, the data metal layer 31 is patterned by an etching process using the photoresist pattern 1 having a step, thereby forming a second conductive pattern group except for the source electrode 32 and the drain electrode 33 as shown in FIG. 3C. do. In this case, the source electrode 32 and the drain electrode 33 of the second conductive pattern group are formed of a source / drain pattern 17 having an integrated structure.

Thereafter, the n + amorphous silicon layer 35a and the amorphous silicon layer 34a exposed as the data metal layer 31 is removed by the etching process are sequentially removed through dry etching.

As described above, after the n + amorphous silicon layer 35a and the amorphous silicon layer 34a that are exposed using the photoresist pattern 1 are sequentially removed, the second electrode except for the source electrode 32 and the drain electrode 33 is removed. The semiconductor pattern 37 under the conductive pattern group and the source / drain pattern 17 is formed.

Then, by ashing the photoresist pattern 1 through an ashing process using an oxygen (O ₂ ) plasma, as shown in FIG. 3D, the first photoresist pattern 1b is thinned, and 2 photoresist pattern 1a is removed.

The source / drain pattern 17 and the second conductive pattern group exposed by the removal of the second photoresist pattern 1a by an etching process using the first photoresist pattern 1b, and the ohmic contact layer below By removing 35, the source electrode 32 and the drain electrode 33 are separated as shown in FIG. 3E, and the active layer 34 is exposed. Accordingly, a channel formed of the active layer 34 is formed between the source electrode 32 and the drain electrode 33. At this time, both sides of the second conductive pattern group except for the source / drain pattern 17 and the source electrode 32 and the drain electrode 33 are etched once more along the ashed first photoresist pattern 1a. The drain pattern 17 and the semiconductor pattern 37, the second conductive pattern group excluding the source electrode 32 and the drain electrode 33, and the semiconductor pattern 37 have steps in the form of steps.

Then, the first photoresist pattern 1a remaining on the second conductive pattern group in the strip process is removed as shown in FIG. 3F.

As described above, after the semiconductor pattern 37 and the second conductive pattern group are formed on the gate insulating layer 25, the semiconductor pattern 37 and the third mask process may include a lift-off process. The passivation film 50 and the third conductive pattern group are formed on the gate insulating layer 25 on which the second conductive pattern group is formed.

A process of forming the passivation layer 50 and the third conductive pattern group will be described in more detail as shown in FIG. 3G. 50) is deposited on the front side. As the protective film 50, an inorganic insulating material such as the gate insulating film 25 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Subsequently, after the photoresist is entirely deposited on the passivation layer 50, a photolithography process using a third mask is performed to form the photoresist pattern 9 for forming the first to third contact holes and the pixel hole. .

After the photoresist pattern 9 is formed on the passivation layer 50 as described above, as shown in FIG. 3H, the passivation layer 50 and the gate insulating layer 25 exposed by the photoresist pattern 9 are removed. By sequentially removing through dry etching, the first to third contact holes 51, 52, and 95 and the pixel holes 61 are formed.

In this case, not only the protective film 50 and the gate insulating film 25 but also the side surfaces of the drain electrode 33 and the storage electrode 65 exposed by the removal of the protective film 50 are removed. SF6 is used as an etching gas for removing the protective film 50 and the gate insulating film 25, and Cl gas is used as an etching gas for removing the drain electrode 33 and the storage electrode 65. As described above, by over-etching not only the passivation layer 50 and the gate insulating layer 25 but also the drain electrode 33 and the storage electrode 65 using a mixed gas containing SF 6 gas and Cl gas. The edge portion is formed to protrude more than the edge portions of the passivation layer 50, the drain electrode 33, the storage electrode 65, and the gate insulating layer 25. This form is intended to allow a large number of strippers to penetrate the boundary between the photoresist pattern 9 and the protective film 50. When the stripper penetrates a lot, the photoresist pattern 9 covered with the transparent conductive film 14 may be easily separated from the protective film 50 in a subsequent process.

Meanwhile, as described above, the interface between the gate pad lower electrode 81, the data pad lower electrode 91, and the passivation layer 50 exposed by the first and third contact holes 51, 52, and 53 is particularly shown in FIG. 1. In connection with this, a large amount of etching gas including Cl gas remains on the boundary surface in the long side direction L of the pad lower electrodes 81 and 91. This Cl gas is a Group 7 element on the periodic table and has a high electron affinity, which results in good reactivity with hydrogen ions. Accordingly, Cl gas reacts with the hydrogen ions contained in the water vapor (H ₂ O) generated in the water vapor (H ₂ O) or a subsequent process present in the chamber to produce the HCl. Since HCl has a property of corroding metal, damage (A) is caused to the pad lower electrodes 81 and 91. In particular, when the pad lower electrodes 81 and 91 are made of an aluminum (Al) -based metal, the aluminum-based metal is more problematic since the corrosiveness caused by HCl is very strong.

Meanwhile, the pixel hole 61 passes through the passivation layer 50 and the gate insulating layer 25 formed in the pixel area to expose the lower substrate 10.

The first contact hole 51 passes through the passivation layer 50 and the gate insulating layer 25 to expose the gate pad lower electrode 81, and the second contact hole 52 forms the passivation layer 50 and the gate. The data pad lower electrode 91 is exposed through the insulating layer 25, and the third contact hole 95 is exposed through the passivation layer 50 and the gate insulating layer 25 to expose the first link electrode 94.

After forming the first to third contact holes 51, 52, and 95 and the pixel hole 61, as shown in FIG. 3I, the lower substrate on which the photoresist pattern 9 is formed using a sputtering method or the like. The transparent conductive film 14 is deposited on the entire surface. Materials of the transparent conductive film 14 include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (Indium zinc oxide) : IZO) is used.

At this time, the transparent conductive layer 14 is opened at the edges of the passivation layer 50 and the photoresist pattern 9 due to the overetching described above.

Thereafter, the photoresist pattern 9 formed on the passivation layer 50 and the transparent conductive layer 14 formed on the photoresist pattern 9 are removed through a lift-off process, as shown in FIG. 3J. A third conductive pattern group including the electrode 60, the gate pad upper electrode 82, and the data pad upper electrode 92 is formed.

In this case, the pixel electrode 60 is formed bordering with the passivation layer 50 patterned in the pixel hole 61 and connected to the side surface of the drain electrode 32.

The gate pad upper electrode 82 forms a lateral boundary with the passivation layer 50 and the gate insulating layer 25 patterned in the first contact hole 51 and is connected to the gate pad lower electrode 81.

In addition, the data pad upper electrode 92 forms a side boundary with the passivation layer 50 and the gate insulating layer 25 patterned in the second contact hole 52 and is connected to the data pad lower electrode 65 side by side.

When the above process is completed, the auto probe inspection is performed as shown in FIG. 4. Referring to FIG. 4, the auto probe test is a test for checking disconnection failure and short failure of each wiring.

In the above-described auto probe inspection, the padding upper electrodes 82 and 92 and the lower electrodes 81 and 91 may be damaged by the impregnation of the auto probe inspection needle 40. Accordingly, each of the pad portions 81 and 91, which should be opaque on a plane due to each of the pad portion lower electrodes 81 and 82 formed of an opaque metal, is transparent due to the damage of the lower electrodes 81 and 82 described above. The surface of the substrate 10 is made irregular. The irregular defective portion B is recognized as a poor appearance product during the external appearance inspection, thereby lowering the manufacturing yield of the thin film transistor substrate.

Accordingly, it is an object of the present invention to provide a thin film transistor substrate of a liquid crystal display device and a method of manufacturing the liquid crystal display device capable of stabilizing the manufacturing process of the liquid crystal display device including a lift-off process.

In order to achieve the above object, a thin film transistor substrate according to a first embodiment of the present invention includes a gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A gate pad lower electrode extending from the gate line to apply a gate signal to the gate line; An electrode hole exposing the substrate through the gate pad lower electrode at a center portion of the gate pad lower electrode; A passivation layer covering the gate insulating layer, the data line and the electrode hole; A contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a part of the electrode hole and exposing a part of the lower electrode of the gate pad; And a gate pad upper electrode formed in the contact hole and connected to the gate pad lower electrode.

The gate pad upper electrode is formed with the gate pad lower electrode exposed through the long side surface of the electrode hole and at least one of a gate insulating film or a protective film interposed therebetween.

A thin film transistor substrate according to a second embodiment of the present invention includes a gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A data pad lower electrode configured to apply a data signal to the data line; An electrode hole exposing the substrate through the lower data pad electrode at a central portion of the lower data pad electrode; A passivation layer covering the substrate, the gate insulating layer, and the data line; A contact hole penetrating the passivation layer and the gate insulating layer to overlap a portion of the electrode hole and expose a portion of the lower electrode of the data pad; And a data pad upper electrode formed in the contact hole and connected to the data pad lower electrode.

The data pad upper electrode is formed with the data pad lower electrode exposed through the long side surface of the electrode hole and at least one of a gate insulation and a protective layer therebetween.

The data pad upper electrode is formed on the same plane as the gate line.

A first link electrode connected to the data pad lower electrode; A contact hole penetrating the gate insulating layer and the passivation layer to expose the data line and the first link electrode; And a second link electrode covering the data line exposed by the contact hole and the first link electrode.

A thin film transistor substrate according to a third embodiment of the present invention includes a gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A gate pad lower electrode extending from the gate line to apply a gate signal to the gate line; A data pad lower electrode configured to apply a data signal to the data line; A first electrode hole penetrating the gate pad lower electrode at the center portion of the gate pad lower electrode to expose the substrate; A second electrode hole penetrating the data pad lower electrode at the center of the data pad lower electrode to expose the substrate; A passivation layer covering the gate insulating layer and the data line; A first contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the first electrode hole and exposing a part of the gate pad lower electrode; A second contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the second electrode hole and exposing a portion of the lower electrode of the data pad; A gate pad upper electrode formed in the first contact hole and connected to the gate pad lower electrode; And a data pad upper electrode formed in the second contact hole and connected to the data pad lower electrode.

The gate pad upper electrode is formed with the gate pad lower electrode exposed through the long side surface of the first electrode hole and at least one of a gate insulating film or a protective film interposed therebetween.

The data pad upper electrode is formed with the data pad lower electrode exposed through the long side surface of the second electrode hole and at least one of a gate insulating film and a protective film interposed therebetween.

The data pad lower electrode is formed on the same plane as the gate pad lower electrode.

A first link electrode connected to the data pad lower electrode; A third contact hole penetrating the gate insulating layer and the passivation layer to expose the data line and the first link electrode; And a second link electrode covering the data line exposed by the third contact hole and the first link electrode.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention includes a gate line, a first conductive pattern group including a gate pad lower electrode extending from the gate line, and the gate on the substrate. Forming an electrode hole penetrating the gate pad lower electrode at the center of the pad lower electrode to expose the substrate; Forming a gate insulating film to cover the first conductive pattern group and the electrode hole; Forming a data line crossing the gate line; Forming a protective film to cover the gate insulating film and the data line; Forming a contact hole penetrating through the passivation layer and the gate insulating layer to overlap a portion of the electrode hole and expose a portion of the lower electrode of the gate pad; Forming a gate pad upper electrode connected to the gate pad lower electrode in the contact hole.

In a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention, an electrode hole exposing the substrate through a first conductive pattern group including a gate line and a data pad lower electrode on the substrate and the data pad lower electrode is exposed. Forming a; Forming a gate insulating film to cover the first conductive pattern group and the electrode hole; Forming a second conductive pattern group including a data line crossing the gate line; Forming a protective film to cover the gate insulating film and the second conductive pattern group; Forming a contact hole penetrating through the passivation layer and the gate insulating layer to overlap a portion of the electrode hole and expose a portion of the lower electrode of the data pad; And forming a data pad upper electrode connected to the data pad lower electrode in the contact hole.

A method of manufacturing a thin film transistor substrate according to a third exemplary embodiment of the present invention includes a first conductive pattern group including a gate line, a gate pad lower electrode extending from the gate line, and a data pad lower electrode on the substrate; Forming a first electrode hole penetrating the gate pad lower electrode to expose the substrate and a second electrode hole penetrating the data pad lower electrode to expose the substrate or the gate insulating layer at a lower electrode center portion; Forming a gate insulating film to cover the first conductive pattern group and the first and second electrode holes; Forming a second conductive pattern group including a data line crossing the gate line; Forming a protective film to cover the gate insulating film and the second conductive pattern group; A portion of the first contact hole through which the portion of the first electrode hole overlaps with the portion of the first electrode hole through the passivation layer and the gate insulating layer, and a portion of the second electrode hole passing through the passivation layer and the gate insulating layer; Forming a second contact hole overlapping and exposing a portion of the data pad lower electrode; Forming a gate pad upper electrode connected to the gate pad lower electrode in the first contact hole and a data pad upper electrode connected to the data pad lower electrode in the second contact hole.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

The structure and operation of the thin film transistor substrate according to the present invention will be described with reference to FIGS. 5 and 6. 5 is a plan view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 6 is a thin film cut along the lines VV, VIV, VIII, VIII, and VIII of FIG. 5. A cross section of a transistor substrate.

5 and 6, a thin film transistor substrate according to an exemplary embodiment of the present invention includes a data line 130 that defines a pixel region by crossing a gate line 120 with a gate line 120 and a gate insulating layer 125 interposed therebetween. ), The pixel electrode 160, the gate line 120, and the storage electrode 165 connected to the thin film transistor 140 and the thin film transistor 140 formed at each intersection thereof and formed in the pixel hole 161 of the pixel region. And a storage capacitor 170 formed in the portion, a gate pad 180 connected to the gate line 120, and a data pad 190 connected to the data line 130.

The thin film transistor 140 may be formed to overlap the gate electrode 122 with the gate insulating layer 125 therebetween to form a channel between the source electrode 132 and the drain electrode 133. An ohmic contact layer 135 formed on the active layer 134 except for the channel part is further provided for ohmic contact between the electrode 132 and the drain electrode 133.

In this case, the semiconductor pattern 137 including the active layer 134 and the ohmic contact layer 135 is formed to overlap the data line 130, the data pad lower electrode 191, and the storage electrode 165.

The passivation 150 covers the thin film transistor 140 formed on the gate insulating layer 125, thereby protecting the active layer 134 forming the channel from moisture or scratches that may occur during subsequent processes. Do this.

The pixel electrode 160 is formed in the pixel area defined by the gate line 120 and the data line 130 intersecting each other. In this pixel area, a pixel hole 161 is formed through the passivation layer 150 and the gate insulating layer 125 to expose the lower substrate 110, and the pixel electrode 160 is formed in the pixel hole 161. In addition, the thin film transistor 140 is in side contact with the drain electrode 133.

The pixel electrode 160 charges a pixel signal supplied from the thin film transistor 140 to generate a potential difference with a common electrode formed on a color filter substrate (not shown). Due to this potential difference, the liquid crystals positioned on the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy, and the amount of light incident through the pixel electrode 160 from a light source (not shown) is controlled to be transmitted to the color filter substrate.

The storage capacitor 170 includes a gate line 120 and a storage electrode 165 overlapping the gate line 120 with the gate insulating layer 125, the active layer 134, and the ohmic contact layer 135 interposed therebetween. do. Here, the pixel electrode 160 formed in the pixel hole 161 area is connected to the side surface of the storage electrode 165. The storage capacitor 170 allows the pixel signal charged in the pixel electrode 160 to be stably maintained until the next pixel signal is charged.

The gate pad 180 is connected to a gate driver (not shown) to supply a gate signal to the gate line 120. The gate pad 180 is formed at the center of the gate pad lower electrode 181 and the gate pad lower electrode 181 extending from the gate line 120 to form inner surfaces of the lower substrate 110 and the gate pad lower electrode 181. A first contact hole 151 and a first contact hole formed to overlap the first electrode hole 201 and the first electrode hole 201 to expose the first electrode hole 201 and penetrating the passivation layer 150 and the gate insulating layer 125. The gate pad upper electrode 182 is connected to the gate pad lower electrode 181 through 151. The gate pad upper electrode 182 is integrated with the first contact hole 151.

The data pad 190 is connected to a data driver (not shown) to supply a data signal to the data line 130. The data pad 190 is formed in the center of the data pad lower electrode 191 and the data pad lower electrode 191 to expose the inner surface of the lower substrate 110 and the data pad lower electrode 191 ( The data pad lower electrode is formed to overlap the second electrode hole 202 and the second contact hole 152 and the second contact hole 152 that pass through the passivation layer 150 and the gate insulating layer 125. And a data pad upper electrode 192 connected to 191.

Since the data pad lower electrode 191 is formed of the same metal layer on the same plane as the gate pad lower electrode 181, the vertical structures of the data pad 190 and the gate pad 180 are identical. The formation of the data pad 190 in the same structure as the gate pad 180 is to deviate from the general data pad structure which is susceptible to corrosion in the three mask structure including the lift-off process. A typical data pad structure is one in which the data bottom electrode extends from the data line and is made of the same metal layer as the data line. Accordingly, the data pad lower electrode 191 having the same vertical structure as the gate pad 180 is connected to the data line 130 through the first and second link electrodes 194 and 197 and the third contact hole 195. do.

The first link electrode 194 extends from the data pad lower electrode 191.

The second link electrode 197 extends from the data pad upper electrode 192, overlaps a portion of the data pad 130, and penetrates the gate insulating layer 125 and the passivation layer 150 to pass through the data line 130. And the data line 130 and the first link electrode 194 through the third contact hole 195 exposing the first link electrode 194. As a result, the data pad lower electrode 192 is connected to the data line 130.

Meanwhile, the first contact hole 151 and the second contact hole 152 will be described in detail with reference to FIG. 7.

First, the first contact hole 151 is formed to overlap the first electrode hole 201. The long side surface of the first contact hole 151 is covered by at least one of the gate insulating layer 125 and the passivation layer 150 as shown in FIG. 6. Accordingly, the gate pad lower electrode 181 exposed by the long side surface L of the first electrode hole 201 and the gate pad upper electrode 182 formed on the long side surface of the first contact hole 151 are formed of a gate insulating film ( It is insulated by at least one of 125 and the protective film 150. However, the short side surface S of the first contact hole 151 exposes the side surface of the gate pad lower electrode 181 or is connected to the short side surface S of the first electrode hole 201 as shown in FIG. 7. A portion of the upper surface of the gate pad lower electrode 181 is exposed. Accordingly, the gate pad upper electrode 182 is connected to the gate pad lower electrode 181 exposed through the short side surface S of the first contact hole 151 and the first electrode hole 201.

The second contact hole 152 is formed to overlap the second electrode hole 202. The long side surface of the second contact hole 152 is covered by at least one of the gate insulating layer 125 and the passivation layer 150, as shown in FIG. 6. Accordingly, the data pad lower electrode 182 exposed by the long side surface L of the second electrode hole 202 and the data pad upper electrode 192 formed on the long side surface of the second contact hole 152 may be formed using a gate insulating film ( It is insulated by at least one of 125 and the protective film 150. However, the short side surface S of the second contact hole 152 may expose the side surface of the lower data pad electrode 191 or may be connected to the short side surface S of the second electrode hole 202, as shown in FIG. 7. A portion of the upper surface of the data pad lower electrode 191 is exposed. Accordingly, the data pad upper electrode 192 is connected to the data pad lower electrode 191 exposed through the short side surface S of the second contact hole 152 and the second electrode hole 202.

The long side surfaces L of the gate pad lower electrode 181 and the data pad lower electrode 191 exposed by the first and second electrode holes 201 and 202 are the first and second contact holes 151 and 152. When formed, the etching gas used to form the first and second contact holes 151 and 152 is not covered by at least one of the gate insulating layer 125 and the passivation layer 150 to form the first and second electrode holes 201,. The problem of corrosion of the pad lower electrodes 181 and 191 by remaining on the long side surface L of the gate pad lower electrode 181 and the data pad lower electrode 191 exposed by the 202 is eliminated.

Hereinafter, a method of manufacturing a thin film transistor substrate using a conventional three mask process will be described in detail with reference to the accompanying drawings.

First, as shown in FIGS. 8A, 8B, and 11, the gate electrode 122 and the gate electrode 120 connected to the gate line 120 and the gate line 120 on the lower substrate 110 through the first mask process. The first conductive pattern group and the gate pad lower electrode 181 including the pad lower electrode 181, the data pad lower electrode 191, and the first link electrode 194 connected to the data pad lower electrode 191. The data pad is disposed in the center of the first electrode hole 201 and the data pad lower electrode 191 which penetrates the gate pad lower electrode 181 to expose the inner surface of the lower substrate 110 and the gate pad lower electrode 181. A second electrode hole 202 is formed through the lower electrode 191 to expose the lower substrate 110.

Referring to the formation of the first conductive pattern group, the first electrode hole 201 and the second electrode hole 202 in more detail, the gate metal layer is formed on the lower substrate 110 through a deposition method such as a sputtering method. do.

Thereafter, the photoresist is entirely coated on the gate metal layer, and then the gate metal layer is patterned through a photolithography process and an etching process using a first mask, thereby connecting the gate line 120 and the gate line on the lower substrate 110. A gate pad lower electrode 181 connected to the gate electrode 122 and the gate line 120, and a first link electrode 194 connected to the data pad lower electrode 191 and the data pad lower electrode 191. The first conductive pattern group is formed, and the first substrate exposes the inner surface of the lower substrate 110 and the gate pad lower electrode 181 by passing through the gate pad lower electrode 181 at the center of the gate pad lower electrode 181. The second electrode hole 202 that exposes the inner surface of the lower substrate 110 and the data pad lower electrode 191 through the data pad lower electrode 191 in the center of the electrode hole 201 and the data pad lower electrode 191. ) . An aluminum metal material such as Al, AlNd, or the like is used as the gate metal for forming the first conductive pattern group.

As described above, after forming the first conductive pattern group, the first electrode hole 201, and the second electrode hole 202 on the lower substrate 110, as shown in FIGS. 9A, 9B, and 12. A semiconductor pattern 137 including an active layer 134 for forming a channel on the gate insulating layer 125 and an ohmic contact layer 135 formed thereon, and a source electrode 132 through a second mask process; A second conductive pattern group including the drain electrode 133, the data line 130, the data pad lower electrode 191, and the storage electrode 165 is formed.

A process of forming the semiconductor pattern 137 and the second conductive pattern group will be described in more detail. The PECVD process may be performed on the lower substrate on which the first conductive pattern group, the first electrode hole 201, and the second electrode hole 202 are formed. The gate insulating layer 125, the amorphous silicon layer, the amorphous silicon layer doped with the n + amorphous silicon layer, and the data metal layer are sequentially formed through a deposition method such as sputtering.

As the gate insulating layer 125, an inorganic insulating material such as silicon oxide (SiO _X ), silicon nitride (SiN _X ), or the like is used. As the data metal layer, a metal, for example, Mo, Cu, Al, Cr or the like, which may be etched together during the etching of the passivation layer 150 in the subsequent process, may be used.

Subsequently, the photoresist having a step on the data metal layer is formed by exposing the entire surface of the photoresist onto the data metal layer and then exposing and developing the photoresist applied on the data metal layer through a photolithography process using a second mask, which is a diffraction exposure mask or a transflective mask. A pattern is formed.

The diffraction exposure mask or transflective mask includes a blocking layer, a partial transmission layer, and a transmission layer. The blocking layer is positioned in a region where the semiconductor pattern and the source / drain electrodes are to be formed to block ultraviolet rays so that the first photoresist pattern remains after development. The partial transmissive layer is positioned in a region where a channel of the thin film transistor is to be formed and partially transmits ultraviolet rays, thereby leaving a second photoresist pattern thinner than the first photoresist pattern after development.

Subsequently, the data metal layer is patterned by an etching process using a photoresist pattern having a step, thereby forming a second conductive pattern group except for the source electrode 132 and the drain electrode 133. In this case, the source electrode and the drain electrode of the second conductive pattern group are formed in a source / drain pattern having an integrated structure.

Thereafter, the n + amorphous silicon layer and the amorphous silicon layer exposed as the data metal layer is removed by the etching process are sequentially removed through dry etching.

As described above, when the exposed n + amorphous silicon layer and the amorphous silicon layer are sequentially removed using the photoresist pattern, the second conductive pattern group and the source / drain pattern except for the source electrode 132 and the drain electrode 133 are sequentially removed. The semiconductor pattern 137 is patterned.

Then, the first photoresist pattern is thinned and the second photoresist pattern is removed by ashing the photoresist pattern through an ashing process using an oxygen (O ₂ ) plasma.

In addition, the source / drain pattern and the second conductive pattern group exposed by the removal of the second photoresist pattern and the ohmic contact layer 135 below are removed by an etching process using the first photoresist pattern, thereby removing the source electrode 132. ) And the drain electrode 133 are separated and the active layer 134 is exposed. Accordingly, a channel formed of the active layer 134 is formed between the source electrode 132 and the drain electrode 133. At this time, both sides of the second conductive pattern group except for the source / drain pattern and the source electrode 132 and the drain electrode 133 are etched once more along the ashed first photoresist pattern, so that the source / drain pattern and the semiconductor pattern ( The second conductive pattern group excluding the source electrode 132 and the drain electrode 133 and the semiconductor pattern 137 have steps in the form of steps.

Then, the first photoresist pattern remaining on the second conductive pattern group is removed by the stripping process.

As described above, after the semiconductor pattern 137 and the second conductive pattern group are formed on the gate insulating layer 125, a third mask process including a lift-off process is performed. As shown in FIG. 13, the passivation layer 150 including the first to third contact holes 151, 152, and 195 on the gate insulating layer 125 on which the semiconductor pattern 137 and the second conductive pattern group are formed. A third conductive pattern group including the pixel electrode 160, the gate pad upper electrode 182, the data pad upper electrode 192, and the second link electrode 197 connected to the data pad upper electrode 192 is formed. .

Referring to the formation of the passivation layer 150 and the third conductive pattern group in more detail, the passivation layer 150 is entirely deposited on the gate insulating layer 125 on which the semiconductor pattern 137 and the second conductive pattern group are formed. As the passivation layer 150, an inorganic insulating material such as the gate insulating film 125 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Thereafter, the photoresist is entirely deposited on the passivation layer 150, and then a photolithography process using a third mask is performed to form the first and second contact holes 151 and 152 and the pixel hole 161. A resist pattern is formed.

As described above, after the photoresist pattern is formed on the passivation layer 150, the passivation layer 150 and the gate insulating layer 125 exposed by the photoresist pattern are sequentially removed through dry etching to form the first to second contact holes. 152, 153, and 195 and pixel holes 161 are formed.

In this case, not only the passivation layer 150 and the gate insulating layer 125 but also the side surfaces of the drain electrode 133 and the storage electrode 165 exposed by the removal of the passivation layer 150 are removed. SF6 is used as an etching gas for removing the passivation layer 150 and the gate insulating layer 125, and Cl gas is used as an etching gas for removing the drain electrode 133 and the storage electrode 165. The edge portion of the photoresist pattern is overetched by overetching not only the passivation layer 150 and the gate insulating layer 125, but also the drain electrode 133 and the storage electrode 165 using a mixed gas including SF6 gas and Cl gas as described above. The protrusion 150 may protrude more than the edges of the drain electrode 133, the storage electrode 165, and the gate insulating layer 125. Such a shape is intended to allow a large number of strippers to penetrate into the boundary between the photoresist pattern and the passivation layer 150. When the stripper penetrates a lot, the photoresist pattern covered with the transparent conductive film may be easily separated from the protective film 150 in a subsequent process.

The pixel hole 161 passes through the passivation layer 150 and the gate insulating layer 125 formed in the pixel area to expose the lower substrate 110.

The first contact hole 151 is formed to overlap the upper portion of the first electrode hole 201. The long side surface L of the first contact hole 151 is exposed by the long side surface L of the first electrode hole 201 with at least one of the gate insulating layer 125 and the passivation layer 150 therebetween. It faces the long side surface of the gate pad lower electrode 181. In addition, the first contact hole 151 exposes a side surface S of the first electrode hole 201 to expose the side surface of the gate pad lower electrode 181 exposed through the first electrode hole 201. In this case, the first contact hole 151 may be formed longer than the first electrode hole 201 to expose a portion of the upper surface of the gate pad lower electrode 181 connected to the short side surface S of the first electrode hole 201.

The second contact hole 152 is formed to overlap the second electrode hole 202. The long side surface L of the second contact hole 152 is exposed by the long side surface L of the second electrode hole 202 with at least one of the gate insulating layer 125 and the passivation layer 150 therebetween. The long side of the data pad lower electrode 192 is faced. In addition, the second contact hole 152 exposes the side surface S of the second electrode hole 202 by exposing the short side surface S of the second electrode hole 202. In this case, the second contact hole 152 may be formed longer than the second electrode hole 202 to expose a portion of the upper surface of the data pad lower electrode 191 connected to the short side surface S of the second electrode hole 202.

The third contact hole 195 passes through the gate insulating layer 125 and the passivation layer 150 to expose the data line 130 and the first link electrode 194.

After forming the first to third contact holes 151, 152, and 195 and the pixel holes 161, a transparent conductive film is entirely deposited on the lower substrate 110 on which the photoresist pattern is formed using a sputtering method or the like. Materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). Either one is used.

In this case, the transparent conductive film is opened at the edges of the passivation layer 150 and the photoresist pattern due to the over-etching.

Subsequently, the photoresist pattern formed on the passivation layer 150 and the transparent conductive layer formed on the photoresist pattern are removed through a lift-off process to thereby remove the pixel electrode 160, the gate pad upper electrode 182, and the data pad upper electrode ( A third conductive pattern group including 192 is formed.

In this case, the pixel electrode 160 is formed bordering the patterned passivation layer 150 in the pixel hole 161 and is connected to the side surface of the drain electrode 132.

The gate pad upper electrode 182 is connected to the exposed gate pad lower electrode 181 forming a side boundary with the passivation layer 150 and the gate insulating layer 125 patterned in the first contact hole 151.

In addition, the data pad upper electrode 192 is connected to the exposed data pad lower electrode 191 in a side boundary with the passivation layer 150 and the gate insulating layer 125 patterned in the second contact hole 152.

The second link electrode 197 forms a side boundary with the passivation layer 150 and the gate insulating layer 125 patterned in the third contact hole 195, and exposes the exposed data line 130 and the first link electrode 194. ) Is connected.

When the above process is completed, the auto probe inspection is performed as shown in FIG. 14. Referring to FIG. 14, the auto probe test is a test for checking disconnection failure and short failure of each wiring.

In the above-described auto probe inspection, the padding upper electrodes 182 and 192 are badly caught by the auto probe inspection needle 140 used for the auto probe inspection, so that each pad portion upper electrode 182, 192) can be damaged. However, damage to each of the pad upper electrodes 182 and 192 formed of a transparent metal occurs in the first and second contact holes 151 and 152, and the first and second contact holes 151 and 152 are transparent. Since the external appearance of the thin film transistor including the damaged part C is transparent because the first and second electrode holes 201 and 202 exposing the lower substrate 110 surface are all transparent, they are not recognized as appearance defects during the external inspection. Yield can be improved.

In addition, the present invention is not limited to the above-described embodiment, but may include other embodiments including only one of the first electrode hole 201 and the second electrode hole 202 to achieve the object of the present invention.

As described above, the thin film transistor substrate according to the exemplary embodiment includes at least one of a first electrode hole penetrating the gate pad lower electrode and a second electrode hole penetrating the data pad lower electrode.

The long side surface of the gate pad lower electrode exposed through the first electrode hole may be covered by at least one of the gate insulating layer and the passivation layer so as not to expose the long side surface of the gate pad lower electrode when the first contact hole is formed. Since the long side surface of the gate pad lower electrode is not exposed when the first contact hole is formed, the long side surface of the gate pad lower electrode may be prevented from being corroded by the etching gas used to form the first contact hole.

In addition, the long side surface of the lower data pad electrode exposed through the second electrode hole may be covered by at least one of the gate insulating layer and the passivation layer so as not to expose the long side surface of the lower data pad electrode when the second contact hole is formed. Since the long side surface of the lower data pad electrode is not exposed when the second contact hole is formed, the long side surface of the lower data pad electrode may be prevented from being corroded by the etching gas used to form the second contact hole.

As described above, since the corrosion of the gate pad lower electrode and the data pad lower electrode generated during the manufacturing process of the thin film transistor substrate including the lift off process can be prevented, the manufacturing process of the liquid crystal display including the lift off process can be stabilized. .

The thin film transistor substrate according to the exemplary embodiment of the present invention includes at least one of a first electrode hole penetrating the gate pad lower electrode and a second electrode hole penetrating the data pad lower electrode, so that the thin film transistor substrate is formed by the probe during the auto probe inspection. Even if the pad electrode is damaged, both the damaged portion and the undamaged portion are transparent. Therefore, since the pad electrode damaged part is not recognized as a defective external appearance during the external inspection performed after the auto probe inspection, the manufacturing yield of the liquid crystal display device can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (14)

A gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A gate pad lower electrode extending from the gate line to apply a gate signal to the gate line; An electrode hole exposing the substrate through the gate pad lower electrode at a center portion of the gate pad lower electrode; A passivation layer covering the gate insulating layer, the data line and the electrode hole; A contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a part of the electrode hole and exposing a part of the lower electrode of the gate pad; And a gate pad upper electrode formed in the contact hole and connected to the gate pad lower electrode. The method of claim 1, The gate pad upper electrode is And the gate pad lower electrode exposed through the long side surface of the electrode hole and at least one of a gate insulating film and a protective film interposed therebetween. A gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A data pad lower electrode configured to apply a data signal to the data line; An electrode hole exposing the substrate through the lower data pad electrode at a central portion of the lower data pad electrode; A passivation layer covering the substrate, the gate insulating layer, and the data line; A contact hole penetrating the passivation layer and the gate insulating layer to overlap a portion of the electrode hole and expose a portion of the lower electrode of the data pad; And a data pad upper electrode formed in the contact hole and connected to the data pad lower electrode. The method of claim 3, wherein The data pad upper electrode is The thin film transistor substrate of claim 1, wherein the data pad lower electrode exposed through the long side surface of the electrode hole is formed between at least one of a gate insulating layer and a passivation layer. The method of claim 3, wherein The data pad upper electrode is And a thin film transistor substrate formed on the same plane as the gate line. 6. The method of claim 5, A first link electrode connected to the data pad lower electrode; A contact hole penetrating the gate insulating layer and the passivation layer to expose the data line and the first link electrode; And a second link electrode covering the data line and the first link electrode exposed by the contact hole. A gate line formed on the substrate; A data line crossing the gate line; A gate insulating film formed between the gate line and the data line; A gate pad lower electrode extending from the gate line to apply a gate signal to the gate line; A data pad lower electrode configured to apply a data signal to the data line; A first electrode hole penetrating the gate pad lower electrode at the center portion of the gate pad lower electrode to expose the substrate; A second electrode hole penetrating the data pad lower electrode at the center of the data pad lower electrode to expose the substrate; A passivation layer covering the gate insulating layer and the data line; A first contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the first electrode hole and exposing a part of the gate pad lower electrode; A second contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the second electrode hole and exposing a portion of the lower electrode of the data pad; A gate pad upper electrode formed in the first contact hole and connected to the gate pad lower electrode; And a data pad upper electrode formed in the second contact hole and connected to the data pad lower electrode. The method of claim 7, wherein The gate pad upper electrode is And the gate pad lower electrode exposed through the long side surface of the first electrode hole and at least one of a gate insulating film and a protective film interposed therebetween. The method of claim 7, wherein The data pad upper electrode is The thin film transistor substrate of claim 2, wherein the data pad lower electrode exposed through the long side surface of the second electrode hole is formed with at least one of a gate insulating film and a protective film interposed therebetween. The method of claim 7, wherein The lower electrode of the data pad And a thin film transistor substrate formed on the same plane as the gate pad lower electrode. 11. The method of claim 10, A first link electrode connected to the data pad lower electrode; A third contact hole penetrating the gate insulating layer and the passivation layer to expose the data line and the first link electrode; And a second link electrode covering the data line exposed by the third contact hole and the first link electrode. Forming a gate line on the substrate, a first conductive pattern group including a gate pad lower electrode extending from the gate line, and an electrode hole through the gate pad lower electrode at the center portion of the gate pad lower electrode to expose the substrate; Steps; Forming a gate insulating film to cover the first conductive pattern group and the electrode hole; Forming a data line crossing the gate line; Forming a protective film to cover the gate insulating film and the data line; Forming a contact hole penetrating through the passivation layer and the gate insulating layer and overlapping a portion of the electrode hole and exposing a portion of the gate pad lower electrode; Forming a gate pad upper electrode connected to the gate pad lower electrode in the contact hole. Forming a first conductive pattern group including a gate line and a data pad lower electrode on the substrate and an electrode hole penetrating the data pad lower electrode to expose the substrate; Forming a gate insulating film to cover the first conductive pattern group and the electrode hole; Forming a second conductive pattern group including a data line crossing the gate line; Forming a protective film to cover the gate insulating film and the second conductive pattern group; Forming a contact hole penetrating through the passivation layer and the gate insulating layer to overlap a portion of the electrode hole and expose a portion of the lower electrode of the data pad; And forming a data pad upper electrode connected to the data pad lower electrode in the contact hole. A first conductive pattern group including a gate line on the substrate, a gate pad lower electrode extending from the gate line, and a data pad lower electrode; and exposing the substrate through the gate pad lower electrode at a center portion of the gate pad lower electrode; Forming a first electrode hole to pass through the lower electrode and the second electrode hole to expose the substrate or the gate insulating layer through the data pad lower electrode; Forming a gate insulating film to cover the first conductive pattern group and the first and second electrode holes; Forming a second conductive pattern group including a data line crossing the gate line; Forming a protective film to cover the gate insulating film and the second conductive pattern group; A portion of the first contact hole through which the portion of the first electrode hole overlaps with the portion of the first electrode hole through the passivation layer and the gate insulating layer, and a portion of the second electrode hole passing through the passivation layer and the gate insulating layer; Forming a second contact hole overlapping and exposing a portion of the data pad lower electrode; Forming a gate pad upper electrode connected to the gate pad lower electrode in the first contact hole and a data pad upper electrode connected to the data pad lower electrode in the second contact hole. Method of manufacturing a substrate.

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