KR100566815B1 - Liquid Crystal Display Panel And Fabricating Method Thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a method of manufacturing the same that can reduce the number of mask processes.

A liquid crystal display panel according to the present invention comprises: a color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line which are bonded to the color filter array substrate by a real material and cross each other with a gate insulating pattern interposed therebetween, a thin film transistor formed at an intersection of the gate line and the data line, and connected to the thin film transistor. A pad connected to at least one of the pixel electrode, the gate line, and the data line and formed to include a transparent conductive film, and a protective film formed in an area overlapping the color filter array substrate to expose the transparent conductive film included in the pad, the transparency A thin film transistor array substrate formed of a front film and having a common voltage supply line for supplying a common voltage to the common electrode; And a conductive dot connected between the common electrode and the common voltage supply line between the thin film transistor array substrate and the color filter array substrate.

Description

Liquid Crystal Display Panel And Fabrication Method Thereof             

1 is a plan view showing a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line " II-II '. FIG.

3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along a line "V-V '".

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

8A to 8E are cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

9A to 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

10A through 10E are cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

11 is a plan view showing a liquid crystal display panel including a thin film transistor array substrate according to the present invention.

FIG. 12 is a cross-sectional view of the liquid crystal display panel taken along the line "XII-XII '" in FIG.

13A to 13D are cross-sectional views illustrating various shapes of the conductive portion cut along the line “XIII-XIII ′” in FIG. 11.

14A to 14C are cross-sectional views illustrating a method of manufacturing the liquid crystal display panel illustrated in FIGS. 13A and 13B.

15A to 15E are cross-sectional views illustrating a method of manufacturing the liquid crystal display panel illustrated in FIGS. 13C and 13D.

FIG. 16 is a plan view illustrating another embodiment of a liquid crystal display panel including a thin film transistor array substrate according to the present invention.

17A to 17D are cross-sectional views illustrating various types of conducting portions of the liquid crystal display panel taken along the line "VIII-VIII" in FIG. 16.

<Description of Symbols for Main Parts of Drawings>

2,102: gate line 4,104: data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 12112 gate insulating film

14,114 active layer 16,116 ohmic contact layer

18,118: protective film 20,42,56,66: contact hole

22,122: pixel electrode 28,128: storage electrode

40,140: Storage capacitor 50,150: Gate pad

52: gate pad lower electrode 54: gate pad upper electrode

60, 160: data pad 62: data pad lower electrode

64: data pad upper electrode 152: gate link

168 data link 170 transparent conductive film

172: gate metal film 300: color filter array substrate

302: thin film transistor array substrate 352: common electrode

354: actual 380: common pad

382 Supply Line 384 Silver Dot

386: laser 398: conducting portion

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel and a method of manufacturing the same that can simplify the process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a lower array substrate (thin film transistor array substrate) and an upper array substrate (color filter array substrate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The lower array substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The upper array substrate is composed of a color filter for color implementation and a black matrix for light leakage prevention, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a lower array substrate.

FIG. 1 is a plan view illustrating a lower array substrate using a conventional four mask process, and FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along line “II-II ′” in FIG. 1.

The thin film transistor array substrate illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating layer 12 interposed therebetween on a lower substrate 1, and a thin film formed at each intersection thereof. A transistor 30, a pixel electrode 22 formed in a cross-sectional pixel region, a storage capacitor 40 formed at an overlapping portion of the gate line 2 and the storage electrode 28, and a gate line 2; And a gate pad 50 connected to each other and a data pad 60 connected to the data line 4.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The thin film transistor 30 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor 30 further includes an active layer 14 overlapping with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 8. .

The active layer 14 also overlaps the data line 4, the data pad lower electrode 62, and the storage electrode 28. On the active layer 14, an ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, the drain electrode 8, the data pad lower electrode 62, and the storage electrode 28 is provided. More is formed.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 40 passing through the passivation layer 18 and is formed in the pixel region 5.

Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor 30 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the lower array substrate and the upper array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 40 includes a gate line 2, a storage electrode 28 overlapping the gate line 2, the gate insulating layer 12, the active layer 14, and the ohmic contact layer 16 therebetween. And the pixel electrode 22 connected through the storage electrode 28 and the second contact hole 42 formed in the protective film 18. The storage capacitor 40 allows the pixel signal charged in the pixel electrode 22 to remain stable until the next pixel signal is charged.

The gate pad 50 is connected to a gate driver (not shown) to supply a gate signal to the gate line 2. The gate pad 50 has a lower gate pad through a gate pad lower electrode 52 extending from the gate line 2 and a third contact hole 56 penetrating through the gate insulating layer 12 and the passivation layer 18. The gate pad upper electrode 54 is connected to the electrode 52.

The data pad 60 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through a data pad lower electrode 62 extending from the data line 4 and a fourth contact hole 66 passing through the passivation layer 18. It consists of a data pad upper electrode 64.

A method of manufacturing a thin film transistor array substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, a first conductive pattern group including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on the lower substrate 1 by using a first mask process. .

In detail, the gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a first conductive pattern group including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52. . Here, an aluminum metal or the like is used as the gate metal layer.

Referring to FIG. 3B, a gate insulating layer 12 is coated on the lower substrate 1 on which the first conductive pattern group is formed. A semiconductor pattern including an active layer 14 and an ohmic contact layer 16 on the gate insulating layer 12 using a second mask process; A second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, the data pad lower electrode 62, and the storage electrode 28 is formed.

In detail, the gate insulating layer 12, the amorphous silicon layer, the n + amorphous silicon layer, and the data metal layer are sequentially formed on the lower substrate 1 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. do. Here, as the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Subsequently, a photoresist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 4, the source electrode 8, the drain electrode 10 integrated with the source electrode 8, and the storage electrode 28 are formed. A second conductive pattern group including a is formed.

Then, the ohmic contact layer 14 and the active layer 16 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

The source / drain metal pattern and the ohmic contact layer 16 of the channel portion are etched after the photoresist pattern having a relatively low height is removed from the channel portion by an ashing process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 8 and the drain electrode 10.

Subsequently, the photoresist pattern remaining on the second conductive pattern group is removed by a stripping process.

Referring to FIG. 3C, a passivation layer 18 including first to fourth contact holes 20, 42, 56, and 66 may be formed on the gate insulating layer 12 on which the second conductive pattern group is formed by using a third mask process. ) Is formed.

In detail, the protective film 18 is entirely formed on the gate insulating film 12 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the passivation layer 18 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 20, 42, 56, and 66. The first contact hole 20 penetrates the passivation layer 18 to expose the drain electrode 10, and the second contact hole 42 penetrates the passivation layer 18 to expose the storage electrode 28. The third contact hole 56 penetrates the passivation layer 18 and the gate insulating layer 12 to expose the gate pad lower electrode 52, and the fourth contact hole 66 penetrates the passivation layer 18 to lower the data pad. The electrode 62 is exposed. Here, when a dry etching ratio metal such as molybdenum (Mo) is used as the data metal, each of the first, second, and fourth contact holes 20, 42, and 66 may have a drain electrode 10 and a storage electrode 28. As a result, the data pad lower electrode 62 penetrates to expose side surfaces thereof.

As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12, an acryl-based organic compound having a low dielectric constant, or an organic insulating material such as BCB or PFCB is used.

Referring to FIG. 3D, a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 is formed on the passivation layer 18 by using a fourth mask process. do.

In detail, the transparent conductive film is apply | coated on the protective film 18 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is etched through a photolithography process and an etching process using a fourth mask, thereby forming a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64. Is formed. The pixel electrode 22 is electrically connected to the drain electrode 10 through the first contact hole 20 and electrically connected to the storage electrode 28 through the second contact hole 42. The gate pad upper electrode 54 is electrically connected to the gate pad lower electrode 52 through the third contact hole 56. The data pad upper electrode 64 is electrically connected to the data lower electrode 62 through the fourth contact hole 66.

Herein, materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO), and indium zinc oxide (IZO). ) Is used.

As described above, the conventional thin film transistor array substrate and the method of manufacturing the same can reduce the number of manufacturing steps and reduce manufacturing costs in proportion to the case of using the 5 mask process by employing a four mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes.

In order to achieve the above object, the liquid crystal display panel according to the present invention includes a color filter array substrate having a common electrode formed on the upper substrate; A gate line and a data line which are bonded to the color filter array substrate by a real material and cross each other with a gate insulating pattern interposed therebetween, a thin film transistor formed at an intersection of the gate line and the data line, and connected to the thin film transistor. A pad connected to at least one of the pixel electrode, the gate line, and the data line and formed to include a transparent conductive film, and a protective film formed in an area overlapping the color filter array substrate to expose the transparent conductive film included in the pad, the transparency A thin film transistor array substrate formed of a front film and having a common voltage supply line for supplying a common voltage to the common electrode; And a conductive dot connected between the common electrode and the common voltage supply line between the thin film transistor array substrate and the color filter array substrate.

The liquid crystal display panel further includes an alignment mark which is used to form the conductive dot and is formed of an opaque material in a region adjacent to the common voltage supply line.

In order to achieve the above object, the liquid crystal display panel according to the present invention includes a color filter array substrate having a common electrode formed on the upper substrate; A thin film transistor array substrate bonded to the color filter array substrate by a material and formed of a transparent conductive film on a lower substrate and having a common voltage supply line for supplying a common voltage to the common electrode; And a conductive dot connected between the common electrode and the common voltage supply line between the thin film transistor array substrate and the color filter array substrate.

In order to achieve the above object, the manufacturing method of the liquid crystal display panel according to the present invention comprises the steps of providing a color filter array substrate having a common electrode formed on the upper substrate; A gate line and a data line facing the color filter array substrate and intersecting a gate insulating pattern on a lower substrate, a thin film transistor formed at an intersection of the gate line and the data line, a protective layer protecting the thin film transistor; A pad connected to at least one of the pixel electrode, the gate line, and the data line connected to the thin film transistor, the pad including the transparent conductive film, the transparent conductive film, and a common voltage supply line for supplying a common voltage to the common electrode. Preparing a thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate using a material to expose the passivation layer of the pad region including the gate pad and the data pad; Exposing the transparent conductive film in a pad region by removing the protective film using the color filter array substrate as a mask; And connecting the common voltage supply line and the conductive dot in any one of before and after the bonding step.

The method of manufacturing the liquid crystal display panel may further include forming an align mark made of an opaque material in a region adjacent to the common voltage supply line and used when the conductive dot is formed.

In order to achieve the above object, the manufacturing method of the liquid crystal display panel according to the present invention comprises the steps of providing a color filter array substrate having a common electrode formed on the upper substrate; Providing a thin film transistor array substrate facing the color filter array substrate and formed of a transparent conductive film on a lower substrate and having a common voltage supply line for supplying a common voltage to the common electrode; Bonding the thin film transistor array substrate and the color filter array substrate to each other using a material; And connecting the common voltage supply line and the conductive dot in any one of the steps before and after the bonding step.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 17D.

4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating a thin film transistor array substrate taken along the line "V-V '" in FIG. 4.

4 and 5 may include a gate line 102 and a data line 104 formed on the lower substrate 101 to intersect with the gate insulating pattern 112 interposed therebetween, and formed at each intersection thereof. The thin film transistor 130, the pixel electrode 122 formed in the pixel region 105 provided in an intersecting structure, the storage capacitor 140 formed in an overlapping portion of the pixel electrode 122 and the gate line 102, and the gate. A gate pad 150 extending at line 102 and a data pad 160 extending at data line 104.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure to define the pixel region 105.

The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode connected to the pixel electrode 122. 110). In addition, the thin film transistor 130 includes semiconductor patterns 114 and 116 that form a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating pattern 112 therebetween. do.

The gate pattern including the gate electrode 106 and the gate line 102 has a structure in which a transparent conductive film 170 and a gate metal film 172 are stacked on the transparent conductive film 170.

The semiconductor pattern includes an active layer 114 which forms a channel between the source electrode 108 and the drain electrode 110 and partially overlaps the gate pattern with the gate insulating pattern 112 therebetween. The semiconductor pattern is formed on the active layer 114 and further includes an ohmic contact layer 116 for ohmic contact with the storage electrode 128, the source electrode 108, and the drain electrode 110. The semiconductor pattern is formed to be separated between the cell and the cell to prevent signal interference between the cells by the semiconductor pattern.

The pixel electrode 122 is formed of the transparent conductive film 170 in the pixel region 105 to be directly connected to the drain electrode 110 of the thin film transistor 130.

Accordingly, a vertical electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the upper array substrate and the lower array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 105 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 140 overlaps the gate line 102 with the gate line 102, the gate insulating pattern 112, the active layer 114, and the ohmic contact layer 116 interposed therebetween, and the pixel electrode 122. The storage electrode 128 is directly connected. The storage capacitor 140 allows the pixel signal charged in the pixel electrode 122 to be stably maintained until the next pixel signal is charged.

The gate pad 150 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102 through the gate link 152. The gate pad 150 is formed in a structure in which the transparent conductive layer 170 extended from the gate link 152 connected to the gate line 102 is exposed. Here, the gate link 152 is formed of a transparent conductive film 170 and a gate metal layer 172 formed on the transparent conductive film 170.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104 through the data link 168. The data pad 160 has a structure in which the transparent conductive film 170 extended from the data link 168 connected to the data line 104 is exposed. Here, the data link 168 includes a data link lower electrode 162 made of a transparent conductive film 170; The data link upper electrode 166 is connected to the data line 104.

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the present invention.

6A and 6B, the pixel electrode 122 is formed on the lower substrate 101 by a first mask process; A gate pattern including a two-layered gate line 102, a gate electrode 106, a gate link 152, a gate pad 150, a data pad 160, and a data link lower electrode 162 is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive film 170 is a transparent conductive material such as ITO, TO, ITZO, IZO, etc., the gate metal film 172 is an aluminum (Al) -based metal, including molybdenum (AlNd), molybdenum ( Metals such as Mo, copper (Cu), chromium (Cr), tantalum (Ta), titanium (Ti) and the like are used. Subsequently, the transparent conductive film 170 and the gate metal layer 172 are patterned by a photolithography process and an etching process using a first mask to form a gate line 102, a gate electrode 106, and a gate link 152 having a two-layer structure. And a data link lower electrode 162; The gate pad 150 including the gate metal layer 172, the data pad 160, and the pixel electrode 122 are formed.

7A and 7B are plan views and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the present invention.

7A and 7B, the gate insulating pattern 112 is formed on the lower substrate 101 on which the gate pattern is formed by the second mask process; A semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed. The gate metal layer 172 included in the data pad 160, the data link lower electrode 162, the gate pad 150, and the pixel electrode 122 is removed to expose the transparent conductive layer 170. The second mask process will be described in detail with reference to FIGS. 8A to 8C as follows.

First, as shown in FIG. 8A, the gate insulating layer 111 and the first and second semiconductor layers 115 and 117 are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. . In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the material of the gate insulating layer 111, and the first semiconductor layer 115 may be formed of amorphous silicon that is not doped with impurities. As the second semiconductor layer 117, amorphous silicon doped with N-type or P-type impurities is used. Subsequently, the photoresist film 316 is entirely formed on the second semiconductor layer 117, and then the second mask 310 is aligned on the lower substrate 101. The second mask 310 includes a mask substrate 312 made of a transparent material and a blocking portion 314 formed in the blocking region S2 of the mask substrate 312. Here, the region where the mask substrate 312 is exposed becomes the exposure region S1. By exposing and developing the photoresist film 316 using the second mask 310, the photoresist pattern 318 is formed to correspond to the blocking portion 314 of the second mask 310 as shown in FIG. 8B. do. As the first and second semiconductor layers 115 and 117 and the gate insulating layer 111 are patterned by an etching process using the photoresist pattern 318, the gate line 102, the gate electrode 106, and A gate insulating pattern 112 overlapping the gate pattern including the gate link 152, and an active layer 114 and an ohmic contact layer 116 having a wider width than the gate pattern on the gate insulating pattern 112. A semiconductor pattern is formed. This is to prevent the channel characteristics when the semiconductor pattern is narrower than the width of the gate electrode 106.

Thereafter, the exposed gate metal layer 172 is removed by wet etching using the gate insulating patterns 112 and the semiconductor patterns 114 and 116 as masks. That is, the transparent conductive film 170 included in the gate metal film 172 included in the gate pad 150, the data pad 160, the data link lower electrode 162, and the pixel electrode 122 is included in the gate pad 150, the data pad lower electrode 162, and the pixel electrode 122. ) Is exposed.

9A and 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the present invention.

As shown in FIGS. 9A and 9B, the data line 104, the source electrode 108, and the drain electrode 110 are formed on the lower substrate 101 on which the gate insulating pattern 112 and the semiconductor pattern are formed by the third mask process. The data pattern including the storage electrode 128 and the data link upper electrode 166 is formed. The third mask process will be described in detail with reference to FIGS. 10A to 10E as follows.

As shown in FIG. 10A, the data metal layer 109 and the photoresist film 328 are sequentially formed on the lower substrate 101 on which the semiconductor pattern is formed by a deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, the third mask 320, which is a partial exposure mask, is aligned above the lower substrate 101. The third mask 320 includes a mask substrate 322 made of a transparent material, a blocking portion 324 formed in the blocking region S2 of the mask substrate 322, and a partial exposure region S3 of the mask substrate 322. The formed diffraction exposure part 326 (or semi-transmissive part) is provided. Here, the region where the mask substrate 322 is exposed becomes the exposure region S1. By exposing and developing the photoresist film 328 using the third mask 320, the blocking portion 324 and the diffraction exposure portion 326 of the third mask 320 are shown in FIG. 10B. A photoresist pattern 330 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 330 formed in the partial exposure area S3 has a second height lower than that of the photoresist pattern 330 having the first height formed in the blocking area S2.

The data metal layer 109 is patterned by a wet etching process using the photoresist pattern 330 as a mask, so that the storage electrode 128, the data line 104, the source electrode 108 connected to the data line 104, and the drain are formed. A data pattern including an electrode 110, a data line 104, and a data link upper electrode 166 connected to the other side is formed.

The active layer 114 and the ohmic contact layer 116 are formed along the data pattern by a dry etching process using the photoresist pattern 330 as a mask. At this time, the active layer 114 and the ohmic contact layer 116 positioned in the remaining region except for the active layer 114 and the ohmic contact layer 116 overlapping the data pattern are removed. This is to prevent a short circuit between cells due to the semiconductor pattern including the active layer 114 and the ohmic contact layer 116.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 230 having the second height in the partial exposure area S3 is removed as shown in FIG. 10C, and the blocking area S2 is removed. The photoresist pattern 330 having the first height is in a state where the height is lowered. An etching process using the photoresist pattern 330 removes the data metal layer and the ohmic contact layer 116 formed in the channel portion of the thin film transistor, that is, the drain electrode 110 and the source electrode 108. This is separated. The photoresist pattern 330 remaining on the data pattern is removed by a strip process as shown in FIG. 10D.

Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 10E. As the passivation layer 118, an inorganic insulating material such as the gate insulating pattern 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used.

FIG. 11 is a plan view illustrating a liquid crystal display panel including the lower array substrate illustrated in FIG. 5, and FIG. 12 is a cross-sectional view illustrating a liquid crystal display panel taken along the line "XII-XII '" in FIG. 11.

11 and 12 include a color filter array substrate 300 and a thin film transistor array substrate 302 bonded by a material 354.

In the color filter array substrate 300, an upper array including a black matrix, a color filter, and a common electrode 352 is formed on the upper substrate 350.

In the thin film transistor array substrate 302, a region overlapping the color filter array substrate 300 is protected by the protection pattern 304, and a gate pad 150 having a pad region overlapping with the color filter array substrate 300. The transparent conductive layer 170 included in at least one of the data pads 160 is exposed.

A conductive part 398 is formed between the upper array substrate 300 and the lower array substrate 302 to supply a common voltage to the common electrode 352 formed on the color filter array substrate.

13A and 13B, the conductive portion 398 is provided with a voltage supply line 382 formed on the lower substrate 101 and a common electrode 352 included in the upper array formed on the upper substrate 350. Silver dots 384 are provided for connecting the lines 382.

The conductive portion 398 shown in FIGS. 13C and 13D has a protection having a supply line 382 formed of a transparent conductive film on the lower substrate 101 and a contact hole 388 exposing side surfaces of the supply line 382. A pattern 304 and a silver dot 384 in side contact with the supply line 382 through the contact hole 388 are provided. The alignment mark 396 formed to facilitate the alignment of the supply line 382 and the silver dot 384 is formed of the same metal as the data line 104 and is an inner region of the actual material 354 based on the actual material 354. It is formed in and protected by the protective pattern (304).

The conductive part 398 is electrically connected to the supply line 382 and the common electrode 352 through the silver dot 384 to supply a reference voltage to the common electrode 352.

The supply line 382 supplies the reference voltage generated from the power supply unit (not shown) to the silver dot 384 through the supply pad 380. The supply line 382 and the supply pad 380 are formed of the transparent conductive film 170 to improve reliability of corrosion.

An alignment mark 396 is provided to facilitate alignment of the silver dots 384 when the silver dots 384 are formed on the supply line 382 formed of the transparent conductive film 170.

The alignment mark 396 illustrated in FIGS. 13A and 13C is formed of the same metal as the data line 104, and is formed in the inner region of the material 354 based on the material 354 to be protected by the protection pattern 304. do.

13B and 13D, the alignment mark 396 is formed of the transparent conductive film 170 and the gate metal film 172 in the same manner as the gate line 102, and the inside of the material 354 based on the material 354. It is formed in the region and is protected by the gate insulating pattern 112 and the protective pattern 304.

14A to 14C are cross-sectional views illustrating a method of manufacturing the liquid crystal display panel illustrated in FIGS. 11 and 12. Here, the liquid crystal display panel illustrated in FIG. 13A will be described as an example, but the present invention also applies to the liquid crystal display panel illustrated in FIG. 13B.

First, the upper array substrate 300 and the lower array substrate 302 are separately formed and then bonded to the material 354 as shown in FIG. 14A. In this case, a passivation layer 118 is formed on the entire lower substrate 101 to cover the thin film transistor, the pixel electrode, the gate pad, the data pad, and the conductive portion in the lower array substrate 302.

Thereafter, as shown in FIG. 14B, the protective layer 118 of the lower array substrate 302 is patterned by a pad opening process using the upper array substrate 300 as a mask, thereby forming a protective pattern 304 in the display area. The transparent conductive film 170 included in the gate pad 150, the data pad 160, the supply pad 380, and the supply line 382 in the pad region is exposed.

Then, the alignment mark 396 is used to align the silver dots 384 on the supply line 380 as shown in FIG. 14C. Accordingly, the supply line 380 and the common electrode 352 are connected to each other through the silver dot 384 to apply a common voltage to the common electrode 352.

15A to 15E are cross-sectional views illustrating a method of manufacturing the liquid crystal display panel illustrated in FIGS. 13C and 13D. Here, the liquid crystal display panel shown in FIG. 13C will be described as an example, but the present invention also applies to the liquid crystal display panel shown in FIG. 13D.

First, a silver dot on a supply line 382 formed of a transparent conductive film 170 using an alignment mark 396 on the thin film transistor array substrate 302 having the alignment mark 396 formed thereon. (384) is aligned. Then, the color filter array substrate 300 and the thin film transistor array substrate 302 are formed on the pad region including the gate pad 150, the data pad 160, and the supply pad 380 as shown in FIG. 15B. The protective film 118 is bonded by the material 354 to expose the protective film 118. Thereafter, the passivation layer 118 is etched by a pad opening process using the color filter array substrate 300 as a mask, so that the gate pad 150, the data pad 160, and the supply pad 380 are shown in FIG. 15C. A protective pattern 304 exposed by the transparent conductive film 170 is formed. Then, the laser 386, for example, as shown in FIG. 15D toward the protective pattern 304 from the bottom of the lower substrate 101 to connect the insulated supply line 382 and the silver dot 384 formed thereon. Yag laser is used to irradiate the laser light. In this case, the light emitted from the laser 386 has wavelengths of about 1064 nm, 592 nm, and 355 nm. By the laser irradiation process, as shown in FIG. 15E, a contact hole 388 penetrating through the protective pattern 304 and the supply line 382 is formed so that the silver dot 384 and the supply line 382 are laterally contacted. do. On the other hand, the laser irradiation step for contacting the silver dots 384 and the supply line 382 may be performed before or after the bonding process. That is, the laser irradiation process is performed after forming silver dots on the thin film transistor array substrate before the bonding process. Or after bonding and before or after the pad opening process.

FIG. 16 is a plan view illustrating a liquid crystal display panel including the lower array substrate illustrated in FIG. 5, and FIGS. 17A to 17D are cross-sectional views illustrating a liquid crystal display panel taken along the line “ⅩⅧ-ⅩⅧ” in FIG. 16.

The liquid crystal display panel shown in FIGS. 16 and 17 has the same components except that the alignment mark is formed on the actual outer region based on the reality as compared to the liquid crystal display panels shown in FIGS. 11 and 12. do. Accordingly, detailed description of the same components will be omitted.

The alignment mark 396 is formed in an area outside the material 354 based on the material 354 to facilitate the alignment of the silver dots 384 on the supply line 382 formed of the transparent conductive film 170. . The alignment mark 396 is formed of the same data metal as the data line 104 as shown in FIGS. 17A and 17C. Alternatively, as shown in FIGS. 17B and 17D, the transparent conductive film 170 and the gate metal film 172 are formed in the same manner as the gate line 102 and protected by the gate insulating pattern 112. Alternatively, the transparent conductive film 170 may be formed in the gate line 102. As described above, the alignment mark 396 formed on the outer region of the material 354 is protected by a gate insulating pattern when formed of a transparent conductive film resistant to corrosion and a data metal or a gate metal film resistant to corrosion.

17A and 17B, the conductive portion 398 is formed on the upper substrate 350 as well as in direct contact with the supply line and the voltage supply line 382 formed of a transparent conductive film on the lower substrate 101. The silver dot 384 is connected to the common electrode 352 included in the upper array. Alternatively, a protective pattern 304 having a supply line 382 formed of a transparent conductive film on the lower substrate 101, a contact hole 388 exposing side surfaces of the supply line 382, and a contact hole 388. A silver dot 384 in side contact with the supply line 382 is provided. The conductive part 398 is electrically connected to the supply line 382 and the common electrode 352 through the silver dot 384 to supply a reference voltage to the common electrode 352.

17A and 17B, the method of manufacturing the liquid crystal display panel illustrated in FIG. 17 is first bonded to the thin film transistor array substrate 302 and the color filter array substrate 300, followed by a gate pad 150 and a data pad by a pad opening process. The transparent conductive film 170 included in the 160, the supply pad 380, and the supply line 382 is exposed. Then, the silver dot 384 is formed using the alignment mark 396 on the exposed supply line 382.

Referring to the manufacturing method of the liquid crystal display panel shown in FIGS. 17C and 17D, first, a silver dot 384 is formed on the thin film transistor array substrate 302 using the alignment mark 396, and then the thin film transistor array substrate ( 302 and the color filter array substrate 300 are bonded to each other. Then, the transparent conductive film 170 included in the gate pad 150, the data pad 160, and the supply pad 380 is exposed by a pad opening process. After that, a protective pattern 304 positioned between the supply line 382 and the silver dot 384 and a contact hole 388 penetrating the supply line 382 are formed by a laser irradiation process. Supply line 382 and silver dot 384 are in lateral contact via 388.

Meanwhile, in the pad opening process, each pad exposed by the upper array substrate 300 is sequentially scanned using the plasma generated by the atmospheric pressure plasma generator, or the pads are collectively scanned for each pad unit, thereby providing the gate pad 150 and The transparent conductive film 170 of the data pad 160 and the supply pad 380 is exposed. Alternatively, a plurality of liquid crystal cells in which the upper array substrate 300 and the lower array substrate 302 are bonded to each other are inserted into the chamber, and then the protective layer 118 of the pad region exposed by the upper array substrate 300 is removed using atmospheric pressure plasma. By etching, the transparent conductive layer 170 of the gate pad 150, the data pad 160, and the supply pad 380 is exposed. Alternatively, the entire liquid crystal cell, to which the upper array substrate 300 and the lower array substrate 302 are bonded, is immersed in the etching liquid or only the pad region including the gate pad 150, the data pad 160, and the supply pad 380 is etched. Immersion is performed to expose the transparent conductive film 170 of the gate pad 150, the data pad 160, and the supply pad 380.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention form the pixel electrode and the gate pattern by the first mask process, the semiconductor pattern by the second mask process, and the data pattern by the third mask process. The lower array substrate is completed by forming. Here, the transparent electrode film included in the pixel electrode, the gate pad, and the data pad during the second mask process or the third mask process is exposed. In this way, by forming the lower array substrate in a three-mask process, the structure and manufacturing process can be simplified, manufacturing cost can be reduced, and manufacturing yield can be improved. In addition, since the transparent conductive film included in the pad is exposed by the pad opening process after bonding, corrosion of the pad electrode is prevented. In addition, the liquid crystal display panel and the method of manufacturing the same according to the present invention can prevent the corrosion of the supply line by forming a supply line connected to the common electrode through the silver dot with a transparent conductive film. In addition, an alignment mark is formed of an opaque material in an area adjacent to a supply line formed of a transparent conductive film to facilitate formation of silver dots on the supply line.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (25)

A color filter array substrate having a common electrode formed on the upper substrate; A gate line and a data line which are bonded to the color filter array substrate by a real material and cross each other with a gate insulating pattern interposed therebetween, a thin film transistor formed at an intersection of the gate line and the data line, and connected to the thin film transistor. A pad connected to at least one of the pixel electrode, the gate line, and the data line and formed to include a transparent conductive film, and a protective film formed in an area overlapping the color filter array substrate to expose the transparent conductive film included in the pad, the transparency A thin film transistor array substrate formed of a front film and having a common voltage supply line for supplying a common voltage to the common electrode; Conductive dots connected between the common electrode and the common voltage supply line between the thin film transistor array substrate and the color filter array substrate; And an alignment mark used to form the conductive dot and formed of an opaque material in an area adjacent to the common voltage supply line. delete The method of claim 1, And the alignment mark is formed of the same metal as the gate line including the transparent conductive film and a gate metal film formed on the transparent conductive film in the same pattern as the transparent conductive film. The method of claim 3, wherein The transparent conductive film includes at least one of ITO, TO, IZO and ITZO, The gate metal layer may include at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and tantalum (Ta). The method of claim 1, And the alignment mark is formed of the same metal as the data line. The method of claim 1, And at least one of the alignment mark and the common voltage supply line is formed in an inner region of the actual material based on the actual material. The method of claim 1, And at least one of the alignment mark and the common voltage supply line is formed in an outer region of the actual material based on the actual material. The method of claim 7, wherein And the alignment mark is protected by the gate insulating pattern. The method of claim 1, The pad A gate pad connected to the gate line and formed to expose a transparent conductive film included in the gate line; A data pad connected to the data line and formed to expose a transparent conductive film; And a common voltage supply pad connected to the common voltage supply line and formed to expose the transparent conductive film. The method of claim 9, At least one of the common voltage supply pad, the gate pad, and the data pad And a gate metal layer formed on the transparent conductive layer and at least partially exposed the transparent conductive layer on the transparent conductive layer. A color filter array substrate having a common electrode formed on the upper substrate; A thin film transistor array substrate bonded to the color filter array substrate by a material and formed of a transparent conductive film on a lower substrate and having a common voltage supply line for supplying a common voltage to the common electrode; And a conductive dot connected between the common electrode and the common voltage supply line between the thin film transistor array substrate and the color filter array substrate. Providing a color filter array substrate having a common electrode formed on the upper substrate; A gate line and a data line facing the color filter array substrate and intersecting a gate insulating pattern on a lower substrate, a thin film transistor formed at an intersection of the gate line and the data line, a protective layer protecting the thin film transistor; A pad connected to at least one of the pixel electrode, the gate line, and the data line connected to the thin film transistor, the pad including the transparent conductive film, the transparent conductive film, and a common voltage supply line for supplying a common voltage to the common electrode. Preparing a thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate using a material to expose the passivation layer of the pad region including the gate pad and the data pad; Removing the protective layer using the color filter array substrate as a mask to expose a transparent conductive film of a pad region; And connecting the common voltage supply line and the conductive dot in any one of the steps before and after the bonding step. The method of claim 12, The step of connecting the common voltage supply line and the conductive dot in any one of before and after the bonding step And forming a conductive dot on the common voltage supply line to which the transparent conductive film is exposed after exposing the transparent conductive film of the pad region. The method of claim 12, The step of connecting the common voltage supply line and the conductive dot in any one of before and after the bonding step And connecting the common voltage supply line and the conductive dot formed to be insulated by the protective film of the thin film transistor array substrate by the laser irradiation process before the bonding step. The method of claim 12, The step of connecting the common voltage supply line and the conductive dot in any one of before and after the bonding step And connecting the common voltage supply line and the conductive dot formed to be insulated by the passivation layer of the thin film transistor array substrate after the bonding step by a laser irradiation process. The method of claim 12, And forming an align mark made of an opaque material in a region adjacent to the common voltage supply line and used to form the conductive dot. The method of claim 16, The alignment mark is And a gate metal layer including the transparent conductive film and a gate metal film formed on the transparent conductive film in the same pattern as the transparent conductive film. The method of claim 17, The transparent conductive film includes at least one of ITO, TO, IZO and ITZO, The gate metal layer may include at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and tantalum (Ta). The method of claim 16, The alignment mark is formed of the same metal as the data line. The method of claim 16, At least one of the alignment mark and the common voltage supply line is formed in an inner region of the actual material based on the actual material. The method of claim 16, At least one of the alignment mark and the common voltage supply line is formed in an outer region of the actual material based on the actual material. The method of claim 21, And the alignment mark is protected by a gate insulating pattern. The method of claim 12, Preparing the thin film transistor array substrate Forming gate patterns and pixel electrodes including a gate line, a gate electrode, a gate pad, and a data pad including a transparent conductive film on the substrate; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns and the pixel electrode are formed, and exposing a transparent conductive film included in the day pad, the gate pad, and the pixel electrode; Forming a data pattern including a data line, a source electrode, and a drain electrode on the substrate on which the semiconductor pattern and the gate insulation pattern are formed; And forming a passivation layer on the substrate on which the data pattern is formed. The method of claim 23, At least one of the gate pad and the data pad And a gate metal film formed on the transparent conductive film and at least partially exposed the transparent conductive film on the transparent conductive film. Providing a color filter array substrate having a common electrode formed on the upper substrate; Providing a thin film transistor array substrate facing the color filter array substrate and formed of a transparent conductive film on a lower substrate and having a common voltage supply line for supplying a common voltage to the common electrode; Bonding the thin film transistor array substrate and the color filter array substrate to each other using a material; And connecting the common voltage supply line and the conductive dot in any one of the steps before and after the bonding step.

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