KR20050068843A - Thin film transistor substrate with color filter and method for fabricating the same - Google Patents

Abstract

The present invention provides a thin film transistor substrate on which a color filter is formed that can simplify the process while increasing the aperture ratio, and a method of manufacturing the same.

To this end, the thin film transistor substrate of the present invention comprises: a thin film transistor array including a thin film transistor connected between a gate line and a data line crossing a gate insulating film interposed therebetween to define a pixel region, and a protective film protecting them; An insulating layer formed on the thin film transistor array and having pixel holes formed in the pixel region; A dummy electrode connected to the drain electrode of the thin film transistor exposed through the pixel hole and formed on the insulating layer to cover the thin film transistor; A color filter formed in the pixel hole; And a pixel electrode formed on the color filter and connected to the dummy electrode exposed outside the color filter.

Description

Thin Film Transistor Substrate With Color Filter And Manufacturing Method Thereof {Thin Film Transistor Substrate With Color Filter And Method For Fabricating The Same}

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate having a color filter and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel (hereinafter, referred to as a liquid crystal panel) in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In general, the liquid crystal panel includes a thin film transistor substrate and a color filter substrate facing each other, a liquid crystal injected between the two substrates, and a spacer for maintaining a cell gap between the two substrates.

The thin film transistor substrate is composed of a pixel electrode formed for each liquid crystal cell region defined by the intersection of a gate line and a data line, a thin film transistor connected between the gate line and the data line and the pixel electrode, a plurality of insulating films, and an alignment film applied thereon.

The color filter substrate includes a color filter formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal in common, and an alignment layer applied thereon.

The thin film transistor substrate and the color filter substrate are bonded to each other to inject and encapsulate a liquid crystal to complete a liquid crystal panel, or to form a liquid crystal on any one of the two substrates and then attach the liquid crystal panel. At this time, the two substrates are aligned and bonded so that the color filter of the color filter substrate corresponds one-to-one with the pixel electrode of the thin film transistor substrate. However, when the alignment of the two substrates is not correct, light leakage defects occur. In order to prevent this, there is a method of forming a wide black matrix width of the color filter substrate, but this causes a decrease in the aperture ratio.

Therefore, in recent years, a color filter on thin film transistor (COT) structure for forming a color filter on a thin film transistor substrate has been proposed.

1 and 2, a COT substrate includes a thin film transistor array including a gate line 2 and a data line 4, a thin film transistor 6, and a protective film 50; The color electrodes R, G, and B formed on the thin film transistor array and the black matrix 30 and the pixel electrodes 18 overlapping the color filters R, G and B with the planarization layer 52 interposed therebetween Equipped.

The gate line 2 and the data line 4 are formed on the substrate 42 to intersect with the gate insulating layer 44 therebetween to define the pixel region.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 facing the source electrode 10. . The thin film transistor 6 includes an active layer 46 overlapping with the gate electrode 8 and the gate insulating film 44 therebetween to form a channel between the source electrode 10 and the drain electrode 12, and an active layer thereof. 46 and an ohmic contact layer 48 for reducing contact resistance between the source and drain electrodes 10, 12.

The storage upper electrode 22 overlaps the front gate line 2 and the gate insulating layer 44 to form a storage capacitor.

The passivation layer 50 is formed on the gate insulating layer 44 to cover the thin film transistor 6, the data line 4, and the storage upper electrode 22.

The R, G, and B color filters 28 are formed on the passivation layer 50 in a dot shape so as to be divided into pixel areas. In this case, the color filters 28 are formed to be spaced apart or partially overlapped so as not to overlap the gate line 2 and the data line 4.

The black matrix 30 is formed on the passivation layer 50 on which the color filter 28 is formed so as to extend to the adjacent color filter 28 along the gate line 2 and the data line 4. It is formed to overlap. The black matrix 30 prevents light leakage between the color filters 28, external light reflection, and light leakage current due to exposure of the channel portion of the thin film transistor 6 to external light.

A planarization layer 52 made of an organic insulator is formed on the color filter 28 and the black matrix 30. The planarization layer 52 compensates the level difference between the color filter 28 and the black matrix 30 to provide a flat surface, and prevents impurities from the color filter 28 and the black matrix 30 from entering the liquid crystal. do.

The pixel electrode 18 is formed independently in each pixel area so as to overlap the color filters R, G, and B on the planarization layer 52. The pixel electrode 18 is connected to the drain electrode 12 exposed through the first contact hole 24 passing through the planarization layer 52, the color filter 28, and the passivation layer 50. In addition, the pixel electrode 18 is connected to the storage upper electrode 22 exposed through the planarization layer 52, the color filter 28, and the second contact hole 26 passing through the passivation layer 50.

As described above, the conventional COT substrate has a first penetrating color filter 28 for connecting the pixel electrode 18 and the drain electrode 12 and the pixel electrode 18 and the storage upper electrode 22. And second contact holes 24 and 26. However, since the color filter 28 has a negative characteristic in which the exposed portion remains in a pattern, it is difficult to form the fine contact hole 24 in the color filter 28. As a result, when the area of the drain electrode 12 and the storage upper electrode 22 is increased along with the contact hole 24, the aperture ratio is lowered.

In addition, since the first and second contact holes 24 must pass through the planarization layer 52, the color filter 28, and the passivation layer 50 of different materials, the first and second contact holes 24 must be formed by different mask processes. Specifically, the first and second contact holes 24 may include at least a mask process for patterning the passivation layer 50, a mask process for patterning the color filter 28, and a mask process for patterning the planarization layer 52. It is formed only by performing three mask processes. As a result, the number of processes increases, leading to lower productivity and higher manufacturing costs.

In addition, in the conventional COT substrate, in order to prevent light leakage, a decrease in the aperture ratio is caused by the black matrix overlapping the peripheral portion of the pixel electrode.

Accordingly, an object of the present invention is to provide a COT substrate and a method of manufacturing the pixel electrode which can be connected to the drain electrode and the storage upper electrode without penetrating the color filter.

Another object of the present invention is to provide a COT substrate and a method of manufacturing the same, which can prevent the reduction of the aperture ratio due to the black matrix.

It is still another object of the present invention to provide a COT substrate and a method of manufacturing the same, which can simplify the process.

In order to achieve the above object, a COT substrate according to an embodiment of the present invention includes a thin film transistor connected between a gate line and a data line crossing the gate insulating film to define a pixel region, and a protective film for protecting them. A thin film transistor array; An insulating layer formed on the thin film transistor array and having pixel holes formed in the pixel region; A dummy electrode connected to the drain electrode of the thin film transistor exposed through the pixel hole and formed on the insulating layer to cover the thin film transistor; A color filter formed in the pixel hole; And a pixel electrode formed on the color filter and connected to the dummy electrode exposed outside the color filter.

The COT substrate includes: a first storage upper electrode overlapping the gate line with the gate insulating layer interposed therebetween to form a storage capacitor, and partially exposed through the pixel hole; And a second storage upper electrode formed on the insulating layer while being connected to the exposed first storage upper electrode and connected to the pixel electrode.

In addition, the COT substrate of the present invention includes a gate pad lower electrode extending from the gate line; A first contact hole penetrating the gate insulating layer, the protective layer, and the insulating layer stacked on the gate pad lower electrode; A first gate pad upper electrode connected to the gate pad lower electrode through the first contact hole; And a second gate pad upper electrode formed to overlap the first gate pad upper electrode.

In addition, the COT substrate of the present invention includes a data pad lower electrode extending from the data line; A contact hole penetrating through the passivation layer and the insulating layer stacked on the data pad lower electrode; A first data pad upper electrode connected to the data pad lower electrode exposed through the contact hole; And a second data pad upper electrode formed to overlap the first data pad upper electrode.

The pixel hole is formed through the insulating film and the protective film gate insulating film in the pixel area.

In addition, the COT substrate of the present invention further includes a second dummy electrode formed to overlap both sides of the data line on the insulating layer while surrounding the edge portion of the pixel hole.

The second dummy electrode is formed integrally with the drain electrode and the first storage upper electrode.

The color filter is formed such that both sides thereof are spaced apart from the data line and overlap both sides of the second dummy electrode.

The color filter is formed such that at least one of the gate line and the data line overlaps with a peripheral portion thereof.

The pixel electrode is formed to cover the color filter, the dummy electrode, and the second storage upper electrode.

Each of the second gate upper electrode and the second data upper electrode is formed to cover each of the first data upper electrode and the second data upper electrode.

Each of the dummy electrode, the second storage upper electrode, the first gate pad upper electrode, the first data pad upper electrode, and the second dummy electrode is a low reflection metal of Mo, Cr, CrOx / Mo, CrOx / Cr, and MoOx / Mo. It is formed of at least one.

The insulating film is formed of an organic insulator.

A method of manufacturing a COT substrate according to the present invention includes forming a thin film transistor array including a thin film transistor connected between a gate line and a data line crossing a gate insulating film interposed therebetween to define a pixel region, and a protective film protecting them. Wow; After applying an insulating film on the thin film transistor array, forming a pixel hole penetrating the insulating film, the protective film, and the gate insulating film in the pixel region; Forming a dummy electrode on the insulating layer to be connected to the drain electrode of the thin film transistor exposed through the pixel hole and cover the thin film transistor; Forming a color filter in the pixel hole; Forming a pixel electrode on the color filter so as to be connected to the dummy electrode exposed outside the color filter.

In addition, the manufacturing method of the present invention comprises the steps of: forming a first storage upper electrode overlapping the gate line with the gate insulating layer interposed therebetween to form a storage capacitor and exposing a portion through the pixel hole; The method may further include forming a second storage upper electrode connected to the pixel electrode while being connected to the exposed first storage upper electrode.

In addition, the manufacturing method of the present invention comprises the steps of forming a gate pad lower electrode extending from the gate line; Forming a first contact hole penetrating the gate insulating layer, the protective layer, and the insulating layer on the gate pad lower electrode; Forming a first gate pad upper electrode connected to the gate pad lower electrode through the first contact hole; The method may further include forming a second gate pad upper electrode formed to overlap the first gate pad upper electrode.

In addition, the manufacturing method of the present invention comprises the steps of forming a data pad lower electrode extending from the data line; Forming a contact hole penetrating the passivation layer and the insulating layer on the lower electrode of the data pad; Forming a first data pad upper electrode connected to the data pad lower electrode exposed through the contact hole; The method may further include forming a second data pad upper electrode formed to overlap the first data pad upper electrode.

In addition, the manufacturing method of the present invention further includes forming a second dummy electrode on the insulating layer to overlap the both sides of the data line while surrounding the edge portion of the pixel hole.

According to another aspect of the present invention, there is provided a method of manufacturing a COT substrate, including: forming a gate metal pattern including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; Forming a gate insulating film on the substrate on which the gate metal pattern is formed; Forming a semiconductor pattern on a predetermined region of the gate insulating film; A data line intersecting the gate line to define a pixel region on the gate insulating layer on which the semiconductor pattern is formed, a source electrode and a data pad lower electrode connected to the data line, and opposite the source electrode and the semiconductor pattern; Forming a source / drain metal pattern comprising a drain electrode and a first storage upper electrode overlapping the front gate line; Forming a protective film on the gate insulating film on which the source / drain metal pattern is formed; A pixel hole exposing a portion of the substrate, the drain electrode and the first storage upper electrode in the pixel area after the insulating layer is formed on the passivation layer, and a first electrode exposing the gate pad lower electrode and the data pad lower electrode, respectively; Forming a second contact hole; A dummy electrode connected to each of the exposed drain electrode, the first storage upper electrode, the gate pad lower electrode, and the data pad lower electrode, a second storage upper electrode, a first gate pad upper electrode, and a first data pad upper electrode. Forming a dummy conductive pattern; Forming a color filter in the pixel hole; A pixel electrode connected to the dummy electrode and a second storage upper electrode while covering the color filter, a second gate pad upper electrode and a second data pad connected to the first gate pad upper electrode and the first data pad upper electrode, respectively. Forming a transparent conductive pattern including an upper electrode.

The forming of the dummy conductive pattern may include forming a second dummy electrode integrated with the dummy electrode and the second storage upper electrode while overlapping both sides of the data line on the insulating layer while surrounding the edge portion of the pixel hole. Additionally included.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 11.

3 is a plan view showing a portion of a COT substrate according to an embodiment of the present invention, Figure 4 is a cut along the lines II-II ', III-III', IV-IV 'shown in Figure 3 It is sectional drawing.

The COT substrate shown in FIGS. 3 and 4 is largely divided into a display area DA and a non-display area NDA.

The display area DA may include a gate and data lines 102 and 104 defining a pixel area, a thin film transistor 6 connected to the gate and data lines 102 and 104, and a pixel hole for forming a color filter 150. The organic film 166 and the thin film transistor 106 provided with the 165 are formed on the dummy electrode 116 to cover, the color filter 150 formed in the pixel hole 165, and the color filter 150 to form the dummy electrode 116. The pixel electrode 118 connected to the thin film transistor 106 is provided. In addition, the display area DA further includes first and second storage upper electrodes 122 and 124 overlapping the gate line 102 and connected to the pixel electrode 118.

The gate line 102 and the data line 104 are formed on the substrate 160 to intersect with the gate insulating layer 162 therebetween to define a pixel area.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 112 facing the source electrode 110. . The thin film transistor 106 includes an active layer 114 overlapping with the gate electrode 108 and the gate insulating layer 144 therebetween to form a channel between the source electrode 110 and the drain electrode 112, and an active layer thereof. An ohmic contact layer 163 is provided to reduce contact resistance between the 114 and the source and drain electrodes 110 and 112.

The first storage upper electrode 122 is overlapped with the front gate line 102 and the gate insulating layer 144 therebetween to form a storage capacitor.

The organic layer 166 is formed on the passivation layer 150, and provides a pixel hole 165 in which the color filter 150 is to be formed in the pixel region. Since the pixel hole 165 penetrates through the passivation layer 164 and the gate insulating layer 162 under the organic layer 166, a portion of the drain electrode 112 and the first storage upper electrode 122 may be formed in the pixel area. Expose

The dummy electrode 116 is connected to the drain electrode 112 exposed through the pixel hole 165 while covering the thin film transistor 106 on the organic layer 166. The second storage upper electrode 124 is also connected to the storage upper electrode 122 exposed through the pixel hole 165 while covering the first storage upper electrode 122 on the organic layer 166. In this case, the dummy electrode 166 is wider than the thin film transistor 106 to surround the drain electrode 112 exposed through the pixel hole 165 and to prevent the channel portion of the thin film transistor 106 from being exposed to external light. It is formed by the area. The second storage upper electrode 124 is also formed to have a larger area than the first storage upper electrode 122 to surround the first storage upper electrode 122 exposed through the pixel hole 165.

The R, G, and B color filters 150 are formed in a dot shape in each of the pixel holes 165. The color filter 150 is formed to be spaced apart from the adjacent color filter 150 while its periphery is formed to overlap the gate line 102 and the data line 104. In addition, the color filter 150 is formed to expose a portion of the dummy electrode 116 and the second storage upper electrode 124. For example, the color filter 150 exposes the overlapping portion of the dummy electrode 116 with the thin film transistor 106 and exposes the overlapping portion of the second storage upper electrode 124 with the gate line 102. To be.

The pixel electrode 118 is formed independently on each of the R, G, and B color filters 150. In addition, the pixel electrode 118 may have a drain electrode 112 and a first storage upper portion of the thin film transistor 106 through each of the dummy electrode 116 and the second storage upper electrode 124 exposed through the color filter 150. It is connected to the electrode 122. Accordingly, the pixel electrode 118 is connected to the drain electrode 112 and the first storage upper electrode 122 without forming a contact hole penetrating the color filter 150.

The non-display area NDA of the COT substrate includes a gate pad 126 connected to the gate line 102 and a data pad 136 connected to the data line 104.

The gate pad 126 may include a gate pad lower electrode 128 extending from the gate line 102 and a first contact hole penetrating through the gate insulating layer 162, the protective layer 164, and the organic layer 166 stacked thereon. The first and second gate pad upper electrodes 132 and 134 having a dual structure connected to the gate pad lower electrode 128 through the 130 are provided. Here, the second gate pad upper electrode 134 is formed to have a larger area to surround the first gate pad upper electrode 132.

The data pad 136 stores data through the data pad lower electrode 138 extending from the data line 104, the passivation layer 164 stacked thereon, and the second contact hole 140 passing through the organic layer 166. The first and second data pad upper electrodes 142 and 144 having a dual structure connected to the pad lower electrode 138 are provided. Here, the second data pad upper electrode 144 is formed to have a larger area to surround the first data pad upper electrode 142.

As described above, the COT substrate according to the present invention includes the dummy electrode 116 and the second storage upper electrode 124 so that the pixel electrode 118 can drain the pixel electrode 118 without forming a contact hole penetrating the color filter 150. 112 and the first storage upper electrode 122. In addition, the peripheral part of the color filter 150 overlaps with the peripheral part of the gate line 102 and the data line 104, and the dummy electrode 116 blocks the channel part of the thin film transistor 106 from external light to separate the black matrix. There is no need. Therefore, the COT substrate according to the present invention can prevent the reduction of the aperture ratio due to the contact hole in the color filter and the black matrix. The COT substrate according to the present invention having these characteristics is formed through the following manufacturing method.

5A to 9B illustrate plan views and cross-sectional views for sequentially describing a method of manufacturing a COT substrate according to an exemplary embodiment of the present invention.

5A and 5B, a thin film transistor array including a passivation layer 164 is formed on a substrate 160, and an organic layer including pixel holes 165 and contact holes 130 and 140 is formed on the thin film transistor array. A film 166 is formed. Specifically, the thin film transistor array and the organic film 166 are sequentially formed as shown in FIGS. 6A to 6E.

Referring to FIG. 6A, a gate metal pattern including a gate line 102, a gate electrode 108, and a gate pad lower electrode 128 is formed on a substrate 160 through a first mask process.

Specifically, the gate metal layer is formed on the substrate 160 through a deposition method such as a sputtering method. Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) are used as the gate metal layer. The gate metal layer is patterned by a photolithography process and an etching process using a first mask. As a result, a gate metal pattern including the gate line 102, the gate electrode 108 protruding from the gate line 102, and the gate pad lower electrode 128 extending from the gate line 102 is formed.

Referring to FIG. 6B, a gate insulating layer 162 is formed on a substrate 160 on which a gate metal pattern is formed, and a semiconductor pattern including an active layer 114 and an ohmic contact layer 163 is formed thereon by a second mask process. Is formed.

The gate insulating layer 162 is formed on the substrate 160 on which the gate metal pattern is formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating film 162, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

 A semiconductor layer, that is, an amorphous silicon layer and an n + amorphous silicon layer, is deposited on the gate insulating layer 162 through a deposition method such as PECVD or sputtering. The semiconductor layer is patterned by a photolithography process and an etching process using a second mask. As a result, a semiconductor pattern including the active layer 114 and the ohmic contact layer 163 overlapping the gate electrode 108 is formed.

Referring to FIG. 6C, the data line 104, the source and drain electrodes 110 and 112, the first storage upper electrode 122, and the data pad bottom are formed on the gate insulating layer 162 on which the semiconductor pattern is formed by a third mask process. A source / drain metal pattern is formed that includes the electrode 138.

Specifically, a source / drain metal layer is formed on the gate insulating layer 162 on which the semiconductor pattern is formed through a deposition method such as PECVD or sputtering. As the source / drain metal layer, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) and the like are used. The source / drain metal layer is patterned by a photolithography process and an etching process using a third mask. Accordingly, the data line 104 intersects the gate line 102, the source electrode 110 protruding from the data line 104, the drain electrode 112 facing the source electrode 110, and the front gate line 102. ), A source / drain metal pattern including a first storage upper electrode 122 and a data pad lower electrode 138 extending from the data line 104 is formed. The ohmic contact layer 148 exposed between the source electrode 112 and the drain electrode 114 is removed as a mask to expose the active layer 146.

Meanwhile, the above-described semiconductor pattern and the source / drain metal pattern may be formed in one mask process when using a partially transmissive (diffractive exposure or semitransmissive) mask.

Referring to FIG. 6D, a passivation layer 164 is formed on the gate insulating layer 162 on which the source / drain metal pattern is formed, and the organic layer 166 is stacked on the gate layer 162 by a fourth mask process.

Specifically, the passivation layer 164 is formed on the gate insulating layer 162 on which the source / drain metal pattern is formed by a deposition method such as PECVD, sputtering, etc. As the material of the passivation layer 164, an inorganic insulating layer such as the gate insulating layer 162 is formed. A substance or an organic insulating substance is used.

The organic insulating layer 166 is formed on the passivation layer 164 by a spin coating method or a spinless coating method. The organic insulating layer 166 is patterned by a photolithography process and an etching process using a fourth mask. Accordingly, a pixel hole 165 in which the color filter 150 is to be formed is formed in the pixel area, and the first and second contact holes 130 and 140 to expose the gate and data pad lower electrodes 128 and 138, respectively. Is formed.

Referring to FIG. 6E, the passivation layer 164 and the gate insulation layer 162 below are etched using the organic insulation layer 166 as a mask. Accordingly, the pixel hole 165 formed to penetrate the organic insulating layer 166 penetrates to the passivation layer 164 and the gate insulating layer 162, thereby exposing a part of the drain electrode 112 and the first storage upper electrode 122. To be. In addition, the first contact hole 130 formed to penetrate the organic insulating layer 166 passes through the passivation layer 164 and the gate insulating layer 162, and the second contact hole 140 extends through the passivation layer 164. Each of the electrode 128 and the data pad lower electrode 138 is exposed.

7A and 7B, a dummy electrode 116, a second storage upper electrode 124, a first gate pad upper electrode 132, and a first data pad upper portion are formed on the organic insulating layer 166 by a fifth mask process. A dummy conductive pattern including the electrode 142 is formed.

Specifically, a dummy conductive layer is formed on the substrate 160 on which the organic insulating layer 166 is formed through a deposition method such as PECVD or sputtering. As the dummy conductive layer, a conductive material having a low reflection property is used to prevent reflection of external light except for an aluminum (Al) -based metal having a property of being corroded by galvanic phenomenon with a transparent conductive layer to be formed thereon. . For example, as the dummy conductive layer, a single metal layer such as Mo, Cr, or the like, or a double metal layer such as CrOx / Mo, CrOx / Cr, MoOx / Mo, or the like is used. The dummy conductive layer is patterned by a photolithography process and an etching process using a fifth mask. Accordingly, the pixel hole 165 covers the thin film transistor 106 while covering the dummy electrode 116 and the first storage upper electrode 122 connected to the drain electrode 112 exposed through the pixel hole 165. The second storage upper electrode 124 connected to the first storage upper electrode 122 exposed through the first gate pad upper electrode connected to the gate pad lower electrode 128 exposed through the first contact hole 130. A dummy conductive pattern including an electrode 132 and a first data pad upper electrode 142 connected to the data pad lower electrode 138 exposed through the second contact hole 140 is formed.

8A and 8B, R, G, and B color filters 150 are sequentially formed in each of the pixel holes 165 through the sixth to eighth mask processes.

Specifically, an R color filter 150 is formed in the pixel hole 165 by applying a photoresist in which a red pigment is dispersed on the substrate 160 on which the dummy conductive pattern is formed and developing in a photolithography process using a sixth mask. do. Then, the G and B color filters 150 are sequentially formed in the pixel holes 165 by repeating the seventh and eighth mask processes as described above. In this case, the dummy conductive pattern can prevent the gate metal pattern and the source / drain metal pattern from being damaged by the alkaline developer used in the photolithography process.

After the color filter 150 is formed, the residue of the color filter existing on the surface of the dummy electrode pattern may be removed by a front ashing process or a process of dry etching the exposed surface of the dummy electrode pattern. . Accordingly, poor contact between the dummy electrode pattern and the transparent conductive pattern to be formed thereon due to the residue of the color filter can be prevented.

9A and 9B, a transparent conductive pattern including the pixel electrode 118, the second gate pad upper electrode 134, and the second data pad upper electrode 144 is formed in a ninth mask process.

Specifically, a transparent conductive film is formed on the substrate 160 on which the color filter 150 is formed through a deposition method such as PECVD or sputtering. Indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used as the transparent conductive film. The transparent conductive film is patterned by a photolithography process and an etching process using a ninth mask. Accordingly, the pixel electrode 118 connected to the dummy electrode 116 and the second storage upper electrode 124 exposed while overlapping the color filter 150, and the second gate connected to the first gate pad upper electrode 132. A transparent conductive pattern including a gate pad upper electrode 134 and a second data pad upper electrode 144 connected to the first data pad upper electrode 142 is formed. Accordingly, the pixel electrode 118 is connected to the drain electrode 112 and the first storage upper electrode 122 through the dummy electrode 116 and the second storage upper electrode 124. Here, the pixel electrode 118 is formed to completely cover the color filter 150, the dummy electrode 116, and the second storage upper electrode 124, so that the pixel electrode 118, the dummy electrode 116, and the second storage upper part are covered. The contact characteristic of the electrode 124 can be improved. In addition, the second gate and data pad upper electrodes 134 and 144 may also be formed to completely cover the first gate and the data pad upper electrodes 132 and 142, respectively.

10 and 11 are a plan view and a cross-sectional view showing a COT substrate according to another embodiment of the present invention.

The COT substrates shown in FIGS. 10 and 11 are further provided with a second dummy electrode 170 overlapping both sides of the data line 104 as compared to the COT substrates shown in FIGS. 3 and 4. Since the same components are provided, the description of the above components will be omitted.

The second dummy electrode 170 surrounds the edge portion of the pixel hole 165, that is, the edge portion of the gate insulating layer 162, the passivation layer 164, and the organic insulating layer 166 on which the pixel hole 165 is formed, and then the organic insulating layer. 166 is formed to overlap both sides of the data line 104 above. The second dummy electrode 170 is integrally formed with the dummy electrode 116 overlapping the thin film transistor 106 and the second storage upper electrode 124 overlapping the first storage upper electrode 122. In other words, the second dummy electrode 170 together with the dummy electrode 116, the second storage upper electrode 122, the first gate and the data upper electrodes 132 and 142 in the above-described fifth mask process may be dummy conductive. It is formed into a pattern.

Accordingly, when both sides of the color filter 150 do not overlap both sides of the data line 104, the second dummy electrode 170 may leak light through the color filter 150 and the data line 104. Can be prevented. In this case, the distance between the adjacent color filters 150 may be increased with the data line 104 interposed therebetween, thereby increasing the patterning margin of the color filters 150. In addition, the gap between the pixel electrodes 118 formed to cover the color filter 150 also increases, thereby preventing short defects between adjacent pixel electrodes 118.

As described above, the COT substrate and the method of manufacturing the same according to the present invention include a dummy electrode and a second storage upper electrode so that the pixel electrode can be connected to the drain electrode and the first storage upper electrode without forming a contact hole through the color filter. You can connect. Accordingly, it is possible to prevent the reduction of the aperture ratio due to the contact hole penetrating the color filter.

In addition, the COT substrate and the method of manufacturing the same according to the present invention require a separate black matrix because the peripheral part of the color filter overlaps the peripheral part of the gate line and the data line, and a dummy electrode having low reflection characteristics is formed to cover the thin film transistor. There will be no. Alternatively, when the periphery of the color filter does not overlap with the periphery of the data line, the second dummy electrode overlapping with the periphery of the data line is further formed to eliminate the need for a separate black matrix. Accordingly, it is possible to prevent the reduction of the aperture ratio due to the black matrix.

In addition, the COT substrate and the method of manufacturing the same according to the present invention include a first gate and a data pad upper electrode together with the dummy electrode and the first storage upper electrode, so that the gate metal pattern and the source / drain metal pattern during the color filter process are reduced. It can be prevented from being exposed to damage by the alkaline developer of the color filter.

In addition, the COT substrate and the method for manufacturing the same according to the present invention can prevent the poor contact between the dummy conductive pattern and the transparent conductive pattern to be formed thereon by removing the residue of the color filter existing on the dummy conductive pattern after the color filter is formed. do. Furthermore, since the transparent conductive pattern is formed to completely cover the dummy conductive pattern, it is possible to further improve the contact characteristics between the dummy conductive pattern and the transparent conductive pattern.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view partially showing a thin film transistor substrate having a conventional color filter;

FIG. 2 is a cross-sectional view of the thin film transistor substrate of FIG. 2 taken along the line II ′. FIG.

3 is a plan view partially showing a thin film transistor substrate having a color filter according to an embodiment of the present invention;

4 is a cross-sectional view of the thin film transistor substrate of FIG. 3 taken along lines II-II ', III-III', and IV-IV '.

5A and 5B are plan and cross-sectional views illustrating a structure formed from a thin film transistor substrate having a color filter to an organic insulating layer according to an exemplary embodiment of the present invention.

6A through 6C are cross-sectional views illustrating a process of forming the organic insulating film illustrated in FIG. 5B in stages.

7A and 7B are plan and cross-sectional views illustrating a structure formed from a thin film transistor substrate having a color filter to a dummy electrode pattern according to an exemplary embodiment of the present invention.

8A and 8B are plan and cross-sectional views illustrating a structure formed from a thin film transistor substrate having a color filter to a color filter according to an exemplary embodiment of the present invention.

9A and 9B are plan and cross-sectional views illustrating a structure formed up to a transparent electrode pattern in a thin film transistor substrate having a color filter according to an exemplary embodiment of the present invention.

10 is a plan view partially showing a thin film transistor substrate having a color filter according to another embodiment of the present invention.

FIG. 11 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 10 taken along lines II-II ', III-III', and IV-IV '.

<Description of Symbols for Main Parts of Drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

24, 26, 130, 140: contact hole 18, 118: pixel electrode

22, 122: storage upper electrode 30: black matrix

42, 160: substrate 44, 162: gate insulating film

46, 114: active layer 48, 163: ohmic contact layer

50, 164: first protective film 52: planarization layer

28, 150 color filter 116 dummy electrode

124: second storage upper electrode 126: gate pad

128: gate pad lower electrode 132: first gate pad upper electrode

134: second gate pad upper electrode 136: data pad

138: data pad lower electrode 142: first data pad upper electrode

144: second data pad upper electrode 165: pixel hole

166: organic insulating film 170: second dummy electrode

Claims (20)

A thin film transistor array including a thin film transistor connected between a gate line and a data line crossing the gate insulating film to define a pixel region, and a protective film protecting them; An insulating layer formed on the thin film transistor array and having pixel holes formed in the pixel region; A dummy electrode connected to the drain electrode of the thin film transistor exposed through the pixel hole and formed on the insulating layer to cover the thin film transistor; A color filter formed in the pixel hole; And a pixel electrode formed on the color filter and connected to the dummy electrode exposed outside the color filter. The method of claim 1, A first storage upper electrode overlapping the gate line with the gate insulating layer interposed therebetween to form a storage capacitor, and having a portion exposed through the pixel hole; And a second storage upper electrode formed on the insulating layer while being connected to the exposed first storage upper electrode, the second storage upper electrode connected to the pixel electrode. The method of claim 1, A gate pad lower electrode extending from the gate line; A first contact hole penetrating the gate insulating layer, the protective layer, and the insulating layer stacked on the gate pad lower electrode; A first gate pad upper electrode connected to the gate pad lower electrode through the first contact hole; And a second gate pad upper electrode formed to overlap the first gate pad upper electrode. The method of claim 1, A data pad lower electrode extending from the data line; A contact hole penetrating through the passivation layer and the insulating layer stacked on the data pad lower electrode; A first data pad upper electrode connected to the data pad lower electrode exposed through the contact hole; And a second data pad upper electrode formed to overlap the first data pad upper electrode. The method according to any one of claims 1 to 4, And the pixel hole is formed through the insulating film and the passivation film gate insulating film in the pixel region. The method of claim 5, And a second dummy electrode formed on the insulating layer to overlap an edge portion of the pixel hole and overlapping both sides of the data line. The method of claim 6, And the second dummy electrode is integrally formed with the drain electrode and the first storage upper electrode. The method of claim 6, The color filter is a thin film transistor substrate, characterized in that both sides thereof are spaced apart from the data line and overlapping both sides of the second dummy electrode. The method of claim 5, And the color filter is formed such that at least one of the gate line and the data line and a peripheral portion thereof overlap each other. The method of claim 2, And the pixel electrode is formed to cover the color filter, the dummy electrode, and the second storage upper electrode. The method according to any one of claims 3 and 4, And the second gate upper electrode and each of the second data upper electrodes are formed to cover each of the first data upper electrode and the second data upper electrode. The method of claim 6, Each of the dummy electrode, the second storage upper electrode, the first gate pad upper electrode, the first data pad upper electrode, and the second dummy electrode A thin film transistor substrate having a color filter, wherein the color filter is formed of at least one of Mo, Cr, CrOx / Mo, CrOx / Cr, and MoOx / Mo, which are low reflection metals. The method of claim 1, The insulating film is a thin film transistor substrate having a color filter, characterized in that formed of an organic insulator. Forming a thin film transistor array including a thin film transistor connected between a gate line and a data line crossing the gate insulating film between the gate lines and the data lines, and a protective film for protecting them; After applying an insulating film on the thin film transistor array, forming a pixel hole penetrating the insulating film, the protective film, and the gate insulating film in the pixel region; Forming a dummy electrode on the insulating layer to be connected to the drain electrode of the thin film transistor exposed through the pixel hole and cover the thin film transistor; Forming a color filter in the pixel hole; And forming a pixel electrode on the color filter so as to be connected to the dummy electrode exposed outside the color filter. The method of claim 14, Forming a first storage upper electrode overlapping the gate line with the gate insulating layer interposed therebetween to form a storage capacitor and exposing a portion of the first storage electrode through the pixel hole; And forming a second storage upper electrode connected to the pixel electrode while being in contact with the exposed first storage upper electrode, wherein the color filter is formed on the thin film transistor substrate. The method of claim 14, Forming a gate pad lower electrode extending from the gate line; Forming a first contact hole penetrating the gate insulating layer, the protective layer, and the insulating layer on the gate pad lower electrode; Forming a first gate pad upper electrode connected to the gate pad lower electrode through the first contact hole; And forming a second gate pad upper electrode formed so as to overlap with the first gate pad upper electrode. The method of claim 14, Forming a data pad lower electrode extending from the data line; Forming a contact hole penetrating the passivation layer and the insulating layer on the lower electrode of the data pad; Forming a first data pad upper electrode connected to the data pad lower electrode exposed through the contact hole; And forming a second data pad upper electrode formed to overlap the first data pad upper electrode. The method according to any one of claims 14 to 17, And forming a second dummy electrode on the insulating layer so as to overlap an edge portion of the pixel hole so as to overlap both sides of the data line. Forming a gate metal pattern on the substrate, the gate metal pattern including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; Forming a gate insulating film on the substrate on which the gate metal pattern is formed; Forming a semiconductor pattern on a predetermined region of the gate insulating film; A data line intersecting the gate line to define a pixel region on the gate insulating layer on which the semiconductor pattern is formed, a source electrode and a data pad lower electrode connected to the data line, and opposite the source electrode and the semiconductor pattern; Forming a source / drain metal pattern comprising a drain electrode and a first storage upper electrode overlapping the front gate line; Forming a protective film on the gate insulating film on which the source / drain metal pattern is formed; A pixel hole exposing a portion of the substrate, the drain electrode and the first storage upper electrode in the pixel area after the insulating layer is formed on the passivation layer, and a first electrode exposing the gate pad lower electrode and the data pad lower electrode, respectively; Forming a second contact hole; A dummy electrode connected to each of the exposed drain electrode, the first storage upper electrode, the gate pad lower electrode, and the data pad lower electrode, a second storage upper electrode, a first gate pad upper electrode, and a first data pad upper electrode. Forming a dummy conductive pattern; Forming a color filter in the pixel hole; A pixel electrode connected to the dummy electrode and a second storage upper electrode while covering the color filter, a second gate pad upper electrode and a second data pad connected to the first gate pad upper electrode and the first data pad upper electrode, respectively. A method of manufacturing a thin film transistor substrate with a color filter, comprising the step of forming a transparent conductive pattern including an upper electrode. The method of claim 19, Forming the dummy conductive pattern And forming a second dummy electrode integrated with both of the dummy electrode and the second storage upper electrode while overlapping both sides of the data line on the insulating layer while covering an edge of the pixel hole. A method of manufacturing a thin film transistor substrate on which a filter is formed.