KR100603458B1 - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display panel capable of reducing the number of mask processes and a manufacturing method thereof.

A liquid crystal display panel according to the present invention includes: a color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line which are opposed to the color filter array substrate and intersect the lower substrate with a gate insulation pattern therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, A thin film transistor array substrate having a pad formed to include a transparent conductive film and connected to at least one of the gate line and the data line and a protective film formed in a region overlapping the color filter array substrate to expose a transparent conductive film included in the pad, and; A conductive dot formed between the thin film transistor array substrate and the color filter array substrate to supply a common voltage to the common electrode; A TFT array substrate, a color filter array substrate, and a body formed to surround the conductive dots. Wherein the gate line and the gate electrode of the thin film transistor include a transparent conductive film and a gate metal film stacked thereon, and the pixel electrode includes a transparent conductive film.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display panel,             

1 is a plan view showing a conventional thin film transistor array substrate;

Fig. 2 is a cross-sectional view of the thin film transistor array substrate shown in Fig. 1 cut along the line "II-II ".

FIGS. 3A to 3D are cross-sectional views illustrating steps of a method of manufacturing the thin film transistor array substrate shown in FIG. 2. FIG.

4 is a plan view showing a thin film transistor array substrate according to an embodiment of the present invention.

5 is a cross-sectional view of the thin film transistor array substrate shown in Fig. 4 cut along the line "V-V '".

6A and 6B are a plan view and a cross-sectional view for illustrating a first mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

7A and 7B are a plan view and a cross-sectional view for explaining a second mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

8A to 8E are cross-sectional views for explaining a second mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

FIGS. 9A and 9B are a plan view and a cross-sectional view for explaining a third mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention; FIGS.

10A to 10E are cross-sectional views for explaining the third masking process of the manufacturing method of the present invention.

11 is a plan view showing a liquid crystal display panel including a thin film transistor array substrate according to the present invention.

12 is a sectional view showing a liquid crystal display panel taken along the line "XII-XII" in Fig.

13A to 13C are cross-sectional views showing a conductive portion taken along the line "XIII-XIII" in Fig.

14A to 14C are cross-sectional views showing a method of manufacturing the liquid crystal display panel shown in Fig.

Description of the Related Art

2,102: gate line 4,104: data line

6,106: gate electrode 8,108: source electrode

10, 110: drain electrode 12, 112:

14,114: active layer 16,116: ohmic contact layer

18, 118: protective film 20, 42, 56, 66: contact hole

22,122: pixel electrodes 28 and 128: storage electrodes

40,140: Storage capacitor 50,150: Gate pad

52: gate pad lower electrode 54: gate pad upper electrode

60,160: Data pad 62: Data pad bottom electrode

64: Data pad upper electrode 152: Gate link

168: Data link 170: Transparency

172: gate metal film 300: color filter array substrate

302: thin film transistor array substrate 352: common electrode

354: Reality 380: Common pad

382: supply line 384: silver dot

386: Laser 398:

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel and a manufacturing method thereof that can simplify a process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In such a liquid crystal display device, the liquid crystal is driven by an electric field formed between the pixel electrode and the common electrode arranged opposite to the upper and lower substrates.

The liquid crystal display device includes a lower array substrate (thin film transistor array substrate) and an upper array substrate (color filter array substrate) bonded together facing each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap Respectively.

The lower array substrate is composed of a plurality of signal lines and thin film transistors, and an alignment film applied thereon for liquid crystal alignment. The upper array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, since the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, the manufacturing process is complicated, which is an important cause of an increase in manufacturing cost of a liquid crystal panel. To solve this problem, the thin film transistor array substrate is being developed to reduce the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist peeling process, and an inspection process. Accordingly, in recent years, a four-mask process in which one mask process is reduced in the five-mask process, which is the standard mask process of the lower array substrate, is emerging.

FIG. 1 is a plan view showing a lower array substrate using a conventional 4-mask process, and FIG. 2 is a sectional view showing a lower array substrate taken along lines "I-I" "and II- to be.

The lower array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed on the lower substrate 1 so as to cross each other with the gate insulating film 12 therebetween, and a thin film transistor A storage capacitor 40 formed on the overlapping portion of the gate line 2 and the storage electrode 28 and the gate line 2, A connected gate pad 50, and a data pad 60 connected to the data line 4. [

A gate line 2 for supplying a gate signal and a data line 4 for supplying a data signal are formed in an intersecting structure to define a pixel region 5.

The thin film transistor 30 causes the pixel signal of the data line 4 to be charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. The thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22 10). The thin film transistor 30 further includes an active layer 14 which overlaps the gate electrode 6 and the gate insulating film 12 and forms a channel between the source electrode 8 and the drain electrode 8 .

The active layer 14 is formed so as to overlap the data line 4, the data pad lower electrode 62, and the storage electrode 28. An ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, the drain electrode 8, the data pad lower electrode 62 and the storage electrode 28 is formed on the active layer 14 Lt; / RTI >

The pixel electrode 22 is formed in the pixel region 5 by being connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 40 penetrating the protective film 18.

Thus, an electric field is formed between the pixel electrode 22 to which the pixel signal is supplied through the thin film transistor 30 and the common electrode (not shown) to which the reference voltage is supplied. These electric fields cause liquid crystal molecules between the lower array substrate and the upper array substrate to rotate due to dielectric anisotropy. In addition, the light transmittance of the pixel region 5 varies depending on the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The storage capacitor 40 includes a gate line 2, a storage electrode 28 overlapping the gate line 2 with the gate insulating film 12, the active layer 14, and the ohmic contact layer 16, And a pixel electrode 22 connected to the storage electrode 28 through a second contact hole 42 formed in the protective film 18. [ The storage capacitor 40 allows the pixel signal charged in the pixel electrode 22 to be stably maintained until the next pixel signal is charged.

The gate pad 50 is connected to a gate driver (not shown) and supplies a gate signal to the gate line 2. The gate pad 50 is connected to the gate pad lower electrode 52 through the third contact hole 56 penetrating the gate insulating film 12 and the protective film 18 and the gate pad lower electrode 52 extending from the gate line 2, And a gate pad upper electrode 54 connected to the gate pad 52.

The data pad 60 is connected to a data driver (not shown) and supplies a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through a data pad lower electrode 62 extending from the data line 4 and a fourth contact hole 66 penetrating the protective film 18 And a data pad upper electrode 64.

The manufacturing method of the thin film transistor array substrate having such a structure is as shown in FIGS. 3A to 3D in detail using the four mask process.

Referring to FIG. 3A, a first conductive pattern group including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on a lower substrate 1 using a first mask process .

In detail, a gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Then, a gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a first conductive pattern group including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52 . Here, as the gate metal layer, an aluminum-based metal or the like is used.

Referring to FIG. 3B, the gate insulating layer 12 is coated on the lower substrate 1 on which the first conductive pattern group is formed. And a semiconductor pattern including an active layer (14) and an ohmic contact layer (16) on the gate insulating film (12) using a second mask process; A second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, the data pad lower electrode 62, and the storage electrode 28 is formed.

In detail, a gate insulating film 12, an amorphous silicon layer, an n + amorphous silicon layer, and a data metal layer are sequentially formed on a lower substrate 1 on which a first group of conductive patterns is formed by a deposition method such as PECVD or sputtering do. Here, as the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Then, a photoresist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than the other source / drain pattern portions.

Then, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern to form the data line 4, the source electrode 8, the drain electrode 10 integrated with the source electrode 8, the storage electrode 28, A second conductive pattern group is formed.

Then, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern, whereby the ohmic contact layer 14 and the active layer 16 are formed.

After the photoresist pattern having a relatively low height is removed in the channel portion by the ashing process, the source / drain metal pattern and the ohmic contact layer 16 of the channel portion are etched by the dry etching process. Thus, the active layer 14 of the channel portion is exposed and the source electrode 8 and the drain electrode 10 are separated.

Then, the photoresist pattern remaining on the second conductive pattern group is removed by the strip process.

Referring to FIG. 3C, on the gate insulating film 12 on which the second conductive pattern group is formed, a protective film 18 (including first through fourth contact holes 20, 42, 56, and 66) Is formed.

In detail, the protective film 18 is formed on the gate insulating film 12 on which the second conductive pattern group is formed by a vapor deposition method such as PECVD. Then, the protective film 18 is patterned by a photolithography process and an etching process using a third mask, thereby forming the first to fourth contact holes 20, 42, 56, and 66. The first contact hole 20 penetrates the protective film 18 to expose the drain electrode 10 and the second contact hole 42 penetrates the protective film 18 to expose the storage electrode 28. The third contact hole 56 exposes the gate pad lower electrode 52 through the protective film 18 and the gate insulating film 12 and the fourth contact hole 66 penetrates the protective film 18, Thereby exposing the electrode 62. The first, second and fourth contact holes 20, 42 and 66 are connected to the drain electrode 10 and the storage electrode 28, respectively, when a metal having a large dry etch rate such as molybdenum (Mo) And the data pad lower electrode 62 to expose their side surfaces.

As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12, an acryl based organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB is used.

3D, a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 is formed on the protective film 18 using a fourth mask process do.

In detail, a transparent conductive film is coated on the protective film 18 by a vapor deposition method such as sputtering. Then, the transparent conductive film is patterned through the photolithography process and the etching process using the fourth mask to form the third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 . The pixel electrode 22 is electrically connected to the drain electrode 10 through the first contact hole 20 and electrically connected to the storage electrode 28 through the second contact hole 42. The gate pad upper electrode 54 is electrically connected to the gate pad lower electrode 52 through the third contact hole 56. The data pad upper electrode 64 is electrically connected to the data lower electrode 62 through the fourth contact hole 66.

Herein, as the material of the transparent conductive film, indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO) and indium zinc oxide (IZO) Is used.

As described above, the conventional thin film transistor array substrate and the manufacturing method thereof can reduce the number of manufacturing processes and reduce the manufacturing cost in proportion to the number of manufacturing processes by using the four mask process. However, since the 4-mask process still has a complicated manufacturing process and thus has limitations in cost reduction, it is required to further simplify the manufacturing process and further reduce manufacturing cost.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a manufacturing method thereof that can reduce the number of mask processes.

According to an aspect of the present invention, there is provided a liquid crystal display panel comprising: a color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line which are opposed to the color filter array substrate and intersect the lower substrate with a gate insulation pattern therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, A thin film transistor array substrate having a pad formed to include a transparent conductive film and connected to at least one of the gate line and the data line and a protective film formed in a region overlapping the color filter array substrate to expose a transparent conductive film included in the pad, and; A conductive dot formed between the thin film transistor array substrate and the color filter array substrate to supply a common voltage to the common electrode; A TFT array substrate, a color filter array substrate, and a body formed to surround the conductive dots.
Wherein the gate line and the gate electrode of the thin film transistor include a transparent conductive film and a gate metal film stacked thereon, and the pixel electrode includes a transparent conductive film.
A method of manufacturing a liquid crystal display panel according to the present invention includes: providing a color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line which are opposed to the color filter array substrate and intersect the lower substrate with a gate insulating pattern therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a protective film for protecting the thin film transistor, Providing a thin film transistor array substrate having a pixel electrode connected to the thin film transistor, a pad connected to at least one of the gate line and the data line and including a transparent conductive film, and a conductive dot for supplying a common voltage to the common electrode Wow; Combining the thin film transistor array substrate and the color filter array substrate using a material so as to expose a pad region including the gate pad and the data pad, and wrapping the conductive dot using the material; And exposing the transparent conductive film in the pad region using the color filter array substrate as a mask.

According to an aspect of the present invention, there is provided a liquid crystal display panel comprising: a color filter array substrate having a common electrode formed on an upper substrate; A thin film transistor array substrate facing the color filter array substrate; A conductive dot formed between the thin film transistor array substrate and the color filter array substrate to supply a driving voltage to the common electrode; The TFT array substrate includes a TFT array substrate and a color filter array substrate. The TFT array substrate and the TFT array substrate are formed to surround the conductive dots.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display panel, including: providing a color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line which are opposed to the color filter array substrate and intersect the lower substrate with a gate insulation pattern therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a protection film for protecting the thin film transistor, A thin film transistor array substrate having a pixel electrode connected to a thin film transistor, a pad connected to at least any one of the gate line and the data line and including a transparent conductive film, and a conductive dot for supplying a common voltage to the common electrode ; Combining the thin film transistor array substrate and the color filter array substrate using a material so as to expose a pad region including the gate pad and the data pad, and wrapping the conductive dot using the material; And exposing the transparent conductive film of the pad region using the color filter array substrate as a mask.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display panel, including: providing a color filter array substrate having a common electrode formed on an upper substrate; forming a thin film transistor array substrate facing the color filter array substrate The thin film transistor array substrate and the color filter array substrate are electrically connected to each other using a substance formed between the thin film transistor array substrate and the color filter array substrate to surround conductive dots for applying a common voltage to the common electrode, And a step of joining together.

Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 14C.

FIG. 4 is a plan view showing a thin film transistor array substrate of a liquid crystal display panel according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view showing a thin film transistor array substrate taken along a line "V-V '" in FIG.

The thin film transistor array substrate shown in FIGS. 4 and 5 includes a gate line 102 and a data line 104 formed on the lower substrate 101 so as to cross each other with a gate insulating pattern 112 sandwiched therebetween, A thin film transistor 130, a pixel electrode 122 formed in the pixel region 105 provided in an intersecting structure thereof, a storage capacitor 140 formed in the overlapping portion of the pixel electrode 122 and the gate line 102, A gate pad 150 extending in line 102 and a data pad 160 extending in the data line 104.

A gate line 102 for supplying a gate signal and a data line 104 for supplying a data signal are formed in an intersecting structure to define a pixel region 105.

The thin film transistor 130 causes the pixel signal of the data line 104 to be charged and held in the pixel electrode 122 in response to the gate signal of the gate line 102. The thin film transistor 130 includes a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode (not shown) connected to the pixel electrode 122 110). The thin film transistor 130 includes semiconductor patterns 114 and 116 which form a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating pattern 112 do.

The gate pattern including the gate electrode 106 and the gate line 102 is formed in a structure in which a transparent conductive film 170 and a gate metal film 172 are stacked on the transparent conductive film 170. [

The semiconductor pattern has an active layer 114 formed to form a channel between the source electrode 108 and the drain electrode 110 and partially overlapping the gate pattern with the gate insulating pattern 112 interposed therebetween. The semiconductor pattern is formed on the active layer 114 and further includes an ohmic contact layer 116 for ohmic contact with the storage electrode 128, the source electrode 108, and the drain electrode 110. Such a semiconductor pattern is formed between the cell and the cell so as to prevent signal interference between the cells due to the semiconductor pattern.

The pixel electrode 122 is formed as a transparent conductive film 170 in the pixel region 105 and is directly connected to the drain electrode 110 of the thin film transistor 130.

Accordingly, a vertical electric field is formed between the pixel electrode 122 to which the pixel signal is supplied through the thin film transistor 130 and the common electrode (not shown) to which the reference voltage is supplied. These electric fields cause liquid crystal molecules between the upper array substrate and the lower array substrate to rotate due to dielectric anisotropy. The light transmittance of the pixel region 105 varies depending on the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The storage capacitor 140 overlaps the gate line 102, the gate line 102, the gate insulating pattern 112, the active layer 114, and the ohmic contact layer 116, And a storage electrode 128 directly connected thereto. The storage capacitor 140 causes the pixel signal charged in the pixel electrode 122 to be stably maintained until the next pixel signal is charged.

The gate pad 150 is connected to a gate driver (not shown) to supply the gate signal generated in the gate driver to the gate line 102 via the gate link 152. [ The gate pad 150 is formed in such a structure that the transparent conductive film 170 extending from the gate link 152 connected to the gate line 102 is exposed. Here, the gate link 152 is formed of a transparent conductive film 170 and a gate metal layer 172 formed on the transparent conductive film 170.

The data pad 160 is connected to a data driver (not shown) and supplies the data signal generated in the data driver to the data line 104 via the data link 168. The data pad 160 is formed in such a structure that the transparent conductive film 170 stretched from the data link 168 connected to the data line 104 is exposed. Here, the data link 168 includes a data link lower electrode 162 made of a transparent conductive film 170; And a data link upper electrode 166 connected to the data line 104.

6A and 6B are a plan view and a cross-sectional view for illustrating a first mask process in a method of manufacturing a thin film transistor array substrate according to the present invention.

6A and 6B, a pixel electrode 122 is formed on the lower substrate 101 by a first mask process; A gate pattern including a gate line 102, a gate electrode 106, a gate link 152, a gate pad 150, a data pad 160, and a data link lower electrode 162 of a two-layer structure is formed.

To this end, a transparent conductive film 170 and a gate metal film 172 are sequentially formed on a lower substrate 101 through a deposition method such as sputtering. The transparent conductive film 170 may be made of a transparent conductive material such as ITO, TO, ITZO or IZO and the gate metal film 172 may be formed of an aluminum (Al) based metal including aluminum / neodymium (AlNd) Mo), copper (Cu), chromium (Cr), tantalum (Ta), titanium (Ti) The transparent conductive film 170 and the gate metal layer 172 are patterned by a photolithography process and an etching process using a first mask to form a gate line 102, a gate electrode 106, a gate line 152, And a data link lower electrode (162); A gate pad 150, a data pad 160, and a pixel electrode 122 including a gate metal film 172 are formed.

7A and 7B are a plan view and a cross-sectional view for illustrating a second mask process in the method of manufacturing a thin film transistor array substrate according to the present invention.

As shown in FIGS. 7A and 7B, a gate insulating pattern 112 is formed on a lower substrate 101 on which a gate pattern is formed by a second mask process; A semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed. The transparent conductive film 170 is exposed by removing the gate metal film 172 included in the data pad 160, the data link lower electrode 162, the gate pad 150 and the pixel electrode 122. The second mask process will now be described in detail with reference to FIGS. 8A to 8C.

First, a gate insulating film 111 and first and second semiconductor layers 115 and 117 are sequentially formed on a lower substrate 101 on which a gate pattern is formed through a deposition method such as PECVD and sputtering as shown in FIG. 8A . As the material of the gate insulating film 111, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the first semiconductor layer 115, amorphous silicon not doped with impurities is used, As the second semiconductor layer 117, amorphous silicon doped with an N-type or P-type impurity is used. Next, a photoresist film 316 is formed on the second semiconductor layer 117, and then the second mask 310 is aligned on the lower substrate 101. The second mask 310 includes a mask substrate 312 made of a transparent material and a blocking portion 314 formed in the blocking region S2 of the mask substrate 312. [ Here, the exposed region of the mask substrate 312 becomes the exposure region S1. A photoresist pattern 318 is formed corresponding to the blocking portion 314 of the second mask 310 as shown in FIG. 8B by exposing and developing the photoresist film 316 using the second mask 310, do. The first and second semiconductor layers 115 and 117 and the gate insulating film 111 are patterned by the etching process using the photoresist pattern 318 to form the gate line 102 and the gate electrode 106, A gate insulating pattern 112 overlapped with a gate pattern including a gate link 152 and an active layer 114 and an ohmic contact layer 116 which are wider than a gate pattern on the gate insulating pattern 112 A semiconductor pattern is formed. This is because the channel characteristics are degraded when the width of the semiconductor pattern is narrower than the width of the gate electrode 106, thereby preventing this.

Then, the exposed gate metal film 172 is removed by wet etching using the gate insulating pattern 112 and the semiconductor patterns 114 and 116 as masks. That is, the gate metal layer 172 included in the gate pad 150, the data pad 160, the data link lower electrode 162, and the pixel electrode 122 is removed to form a transparent conductive film 170 ) Is exposed.

9A and 9B are a plan view and a cross-sectional view for explaining a third mask process in the manufacturing method of the thin film transistor array substrate according to the present invention.

9A and 9B, a data line 104, a source electrode 108, and a drain electrode 110 are formed on a lower substrate 101 on which a gate insulating pattern 112 and a semiconductor pattern are formed by a third mask process. A storage electrode 128, and a data link upper electrode 166 are formed. The third mask process will be described in detail with reference to FIGS. 10A to 10E.

A data metal layer 109 and a photoresist film 328 are sequentially formed on a lower substrate 101 on which a semiconductor pattern is formed, as shown in FIG. 10A, by a vapor deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, a third mask 320, which is a partial exposure mask, is aligned on top of the lower substrate 101. The third mask 320 includes a mask substrate 322 made of a transparent material, a blocking portion 324 formed in the blocking region S2 of the mask substrate 322, And a diffraction exposure portion 326 (or a semi-transmissive portion) formed thereon. Here, the exposed region of the mask substrate 322 becomes the exposure region S1. The photoresist film 328 using the third mask 320 is exposed and developed to correspond to the blocking portion 324 and the diffraction exposure portion 326 of the third mask 320 as shown in FIG. A photoresist pattern 330 having a step in the blocking region S2 and the partial exposure region S3 is formed. That is, the photoresist pattern 330 formed in the partial exposure region S3 has a second height lower than the photoresist pattern 330 having the first height formed in the blocking region S2.

The data metal layer 109 is patterned by the wet etching process using the photoresist pattern 330 as a mask to form the source electrode 108 and the drain electrode 108 connected to the storage electrode 128, the data line 104, the data line 104, A data pattern including the electrode 110, the data line 104 and the data link upper electrode 166 connected to the other side is formed.

In the dry etching process using the photoresist pattern 330 as a mask, the active layer 114 and the ohmic contact layer 116 are formed along the data pattern. At this time, the active layer 114 and the ohmic contact layer 116 located in the remaining regions other than the active layer 114 and the ohmic contact layer 116 overlapping the data pattern are removed. This is to prevent a short circuit between cells due to the semiconductor pattern including the active layer 114 and the ohmic contact layer 116. [

The photoresist pattern 230 having the second height in the partial exposure region S3 is removed as shown in FIG. 10C by an ashing process using an oxygen (O ₂ ) plasma, The height of the photoresist pattern 330 having the first height is lowered. The data metal layer and the ohmic contact layer 116 formed on the channel region of the thin film transistor are removed by the etching process using the photoresist pattern 330 to form the drain electrode 110 and the source electrode 108, Respectively. Then, the photoresist pattern 330 remaining on the data pattern is removed by a strip process as shown in FIG. 10D.

Then, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 10E. As the protective film 118, an inorganic insulating material such as the gate insulating pattern 112, an acryl based organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB is used.

FIG. 11 is a plan view showing a liquid crystal display panel including the lower array substrate shown in FIG. 5, and FIG. 12 is a sectional view showing a liquid crystal display panel taken along the line "XII-XII '" in FIG.

The liquid crystal display panel shown in Figs. 11 and 12 includes an upper array substrate 300 and a lower array substrate 302, and a substance 354 for attaching the upper array substrate 302 and the lower array substrate 304 to each other do.

The upper array substrate 300 is formed on the upper substrate 350 with an upper array including a black matrix, a color filter, and a common electrode 352.

The lower array substrate 302 is protected by the protection pattern 304 in a region overlapping with the upper array substrate 300 and the gate pad 150 and the data pad The transparent conductive film 170 included in at least one of the transparent conductive films 170 and 160 is exposed.

The liquid crystal display panel according to the present invention further includes a conductive portion 398 formed between the upper array substrate 300 and the lower array substrate 302 as shown in FIGS. 13A to 13C.

The conduction unit 398 includes a supply line 382 formed on the lower substrate 101, a common electrode 352 included in the upper array formed on the upper substrate 350, a supply line 382, And a silver dot 384 for connecting the light emitting diodes 352 and 352. The conduction unit 398 electrically connects the supply line 382 and the common electrode 352 via the silver dot 384 to supply the reference voltage to the common electrode 352.

The supply line 382 supplies the reference voltage generated from the power supply (not shown) to the silver dot 384 through the supply pad 380. [ The silver dot 384 is laterally in contact with the supply line 382 through the contact hole 388 penetrating the supply line 382 with at least one of the protective pattern 304 and the gate insulation pattern 112. The contact hole 388 uses a laser to remove the supply line 382 and a portion of the protective pattern 304 and the gate insulating pattern 112.

On the other hand, the supply line 382 is formed of a metal included in at least one of the gate pattern and the data pattern.

13A, the supply pad 380 is formed on the transparent conductive film 170, the transparent conductive film 170 thereof, and the supply line 382 is formed on the transparent conductive film 170. The supply line 380 is formed of the data metal included in the data pattern, And a gate metal film 172 overlapped with the gate electrode film 382.

When the supply line 382 is formed of the transparent conductive film 170 and the gate metal film 172 included in the gate pattern as shown in FIG. 13B, the supply pad 380 is electrically connected to the transparent conductive film 170 are extended to expose the transparent conductive film 170. In this case, a gate insulation pattern 112 for protecting the supply line 382 is formed on the supply line 382.

When the supply line 382 is formed of the transparent conductive film 170 included in the gate pattern as shown in FIG. 13C, the supply pad 380 is formed so that the transparent conductive film 170 of the supply line 382 is extended, So that the entire film 170 is exposed.

The substance 354 is formed between the upper array substrate 300 and the lower array substrate 302 and is formed so as to surround them and to enclose the conductive parts 398. By forming the conduction unit 398 so as to surround the conduction unit 354, the conduction unit 398 is positioned adjacent to the display region inside the frame 354 to prevent the liquid crystal from being contaminated by the silver dot 384 The conductive portion 398 is positioned adjacent to the pad region outside the substance 354 to prevent the supply line 382 from being exposed to the atmosphere and oxidized by the pad opening process.

14A to 14C are cross-sectional views illustrating a method of manufacturing a liquid crystal display panel according to the present invention. Here, the liquid crystal display panel shown in Fig. 13A is described as an example, but it is also applied to the liquid crystal display panel shown in Figs. 13B and 13C.

First, the upper array substrate 300 and the lower array substrate 302 are separately formed and then joined together as shown in FIG. 14A. At this time, a protection film 118 is formed on the entire surface of the lower substrate 101 so as to cover the thin film transistor, the pixel electrode, the gate pad, the data pad, and the conduction part in the lower array substrate 302. In addition, the substance 354 includes a pad region in which a gate pad and a data pad are formed; And is formed between the other regions except for the pad region, and is formed to surround the conductive portion 398.

14b from the backside of the lower substrate 101 to the protective layer 118 to connect the supply line 382 and the silver dot 384 to the laser 386, Laser light is irradiated using a laser. At this time, the light emitted from the laser 385 has wavelengths of about 1064 nm, 592 nm, and 355 nm. The laser 386 forms a contact hole 388 penetrating the supply line 382 and at least one of the protective film 118 and the gate insulating pattern 112 to form the silver dot 384 and the supply line 382, Is contacted with this side surface. The laser irradiation process for contacting the silver dot 384 with the supply line 382 may be performed before the pad opening process or after the pad opening process.

14C, the protective layer 118 of the lower array substrate 302 is patterned by a pad opening process using the upper array substrate 300 as a mask, thereby forming a protective pattern 304 in the display region At least one of the gate pad 150 and the data pad 160 of the pad region and the transparent conductive film 170 included in the supply pad 380 are exposed.

Meanwhile, in the pad opening process, the pads exposed by the upper array substrate 300 are sequentially scanned by using the plasma generated by the atmospheric pressure plasma generating unit, or are sequentially scanned by the pad units, The transparent conductive film 170 of the data pad 160 and the supply pad 380 is exposed. Or a plurality of liquid crystal cells in which the upper array substrate 300 and the lower array substrate 302 are bonded together is inserted into the chamber and then the protective film 118 of the pad region exposed by the upper array substrate 300 is vacuum- And exposes the transparent conductive film 170 of the gate pad 150 and the data pad 160 and the supply pad 380 by etching. Or the entire liquid crystal cell in which the upper array substrate 300 and the lower array substrate 302 are bonded is immersed in the etching solution or only the pad region including the gate pad 150 and the data pad 160 and the supply pad 380, To expose the transparent conductive film 170 of the gate pad 150 and the data pad 160 and the supply pad 380.

As described above, in the liquid crystal display panel and the manufacturing method thereof according to the present invention, a pixel electrode and a gate pattern are formed by a first mask process, a semiconductor pattern is formed by a second mask process, and a data pattern is formed by a third mask process Thereby completing the lower array substrate. Here, the driving electrode including at least one of the pixel electrode and the common electrode is exposed to the transparent conductive film included therein during the second mask process or the third mask process. By forming the lower array substrate by the 3-mask process, the structure and manufacturing process can be simplified, manufacturing cost can be reduced, and manufacturing yield can be improved. In addition, corrosion of the pad electrode is prevented by exposing the transparent conductive film included in the pad by the pad opening process after the cementation. In addition, the liquid crystal display panel and the method of manufacturing the same according to the present invention are formed so as to actually enclose a conductive portion for applying a driving voltage to the common electrode. Accordingly, it is possible to prevent corrosion of the conductive part by the pad opening step and to prevent contamination of the liquid crystal by the conductive part.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (22)

A color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line which are opposed to the color filter array substrate and intersect the lower substrate with a gate insulation pattern therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, A thin film transistor array substrate having a pad connected to at least one of the gate line and the data line and including a transparent conductive film and a protective film formed in a region overlapping the color filter array substrate and exposing a transparent conductive film included in the pad, ; A conductive dot formed between the thin film transistor array substrate and the color filter array substrate to supply a common voltage to the common electrode; A plurality of thin film transistor array substrates and a color filter array substrate; And a supply line formed on the thin film transistor array substrate and supplying the common voltage to the conductive dots; Wherein the gate line and the gate electrode of the thin film transistor include a transparent conductive film and a gate metal film stacked thereon, the pixel electrode including a transparent conductive film, Wherein the liquid crystal display panel is in contact with a supply line. delete delete The method according to claim 1, Wherein the supply line is formed of at least one metal included in the gate line. The method according to claim 1, Wherein the supply line is formed of a transparent conductive film. The method according to claim 1, Wherein the supply line is formed of a transparent conductive film, and a gate metal film formed to overlap with the transparent conductive film. The method according to claim 1, Wherein the supply line is formed of the same metal as the data line. The method according to claim 1, The pad A gate pad connected to the gate line and configured to expose a transparent conductive film included in the gate line, And a data pad connected to the data line and configured to expose a transparent conductive film. 9. The method of claim 8, Wherein at least one of the gate pad and the data pad And a gate metal film formed on the transparent conductive film to expose the transparent conductive film at least partially on the transparent conductive film. 10. The method according to claim 6 or 9, Wherein the gate metal film comprises at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and tantalum (Ta). delete Providing a color filter array substrate having a common electrode formed on an upper substrate; A gate line and a data line intersecting the color filter array substrate on the lower substrate with a gate insulating pattern interposed therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a protective film for protecting the thin film transistor, A pixel electrode connected to the thin film transistor, a pad connected to at least one of the gate line and the data line and including a transparent conductive film, conductive dots for supplying a common voltage to the common electrode, And a contact hole passing through at least one of a gate insulating pattern and a protective film formed on the supply line and formed on the supply line; Combining the thin film transistor array substrate and the color filter array substrate using a material so as to expose a pad region including the gate pad and the data pad, and wrapping the conductive dot using the material; And exposing the transparent conductive film of the pad region using the color filter array substrate as a mask; Wherein the gate line and the gate electrode of the thin film transistor include a transparent conductive film and a gate metal film stacked thereon, and the pixel electrode includes a transparent conductive film. 13. The method of claim 12, The step of providing the thin film transistor array substrate A gate electrode connected to the gate line, a gate pad connected to the gate line via a gate link, and a data pad connected to the data line via a data link, Forming the pixel electrode with the gate pattern including the transparent conductive film; Forming a semiconductor pattern and a gate insulating pattern on the substrate on which the gate patterns and the pixel electrode are formed, and exposing the transparent conductive film included in the data pad, the gate pad, and the pixel electrode; Forming a data pattern including the data line, the source electrode of the thin film transistor, and the drain electrode of the thin film transistor on the substrate on which the semiconductor pattern and the gate insulating pattern are formed; And forming a protective film on the substrate on which the data pattern is formed. delete delete 13. The method of claim 12, Forming a contact hole through at least one of the supply line, the gate insulating pattern formed on the supply line, and the protective film And forming a contact hole through the supply line, a gate insulating pattern formed on the supply line, and a protective film by irradiating laser to the contact hole. 13. The method of claim 12, Wherein the supply line is formed of at least one metal included in the gate line. 18. The method of claim 17, Wherein the supply line is formed of a transparent conductive film. 18. The method of claim 17, Wherein the supply line is formed of a transparent conductive film and a gate metal film formed to overlap with the transparent conductive film. 13. The method of claim 12, Wherein the supply line is formed of the same metal as the data line. 20. The method of claim 19, Wherein the gate metal film comprises at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and tantalum (Ta). delete

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