KR100600088B1 - Liquid crystal display apparatus of horizontal electronic field applying type and fabricating method thereof - Google Patents

Abstract

The present invention relates to a horizontal field application type liquid crystal display device and a method of manufacturing the same that can reduce the number of structures and mask processes.

The horizontal field application type liquid crystal display device according to the present invention comprises a gate line, a common line formed in parallel with the gate line, a data line crossing the gate line, the common line, and a gate insulating film interposed therebetween to determine a pixel region; A thin film transistor formed at an intersection of the gate line and the data line, a common electrode formed in the pixel region and connected to the common line, and connected to the thin film transistor to form a horizontal electric field in the pixel region And a pixel electrode made of the same material as the data line; A gate pad formed of at least one conductive layer included in the gate line, a data pad formed of at least one conductive layer included in the data line, a common pad formed of at least one conductive layer included in the common line, and A lower plate including a protective layer exposing the gate pad, the data pad, and the common pad; An upper plate bonded to the lower plate to fill the liquid crystal therebetween; And a conductive film connected to the exposed pads of the lower plate.

Description

Horizontal field-applied liquid crystal display device and manufacturing method therefor {LIQUID CRYSTAL DISPLAY APPARATUS OF HORIZONTAL ELECTRONIC FIELD APPLYING TYPE AND FABRICATING METHOD THEREOF}             

1 is a plan view showing a thin film transistor array substrate of a conventional horizontal field application liquid crystal display device.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate in a horizontal field application liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along a line II-II '. FIG.

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

8A through 8E are cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

9A to 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

10 is a cross-sectional view of pads having a first structure in a thin film transistor array substrate according to an embodiment of the present invention.

11 is a cross-sectional view of pads having a second structure in a thin film transistor array substrate according to an embodiment of the present invention.

12 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the liquid crystal display shown in FIG. 12 taken along the line II-II ';

<Description of Symbols for Main Parts of Drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10 source electrode 12, 112 drain electrode

13, 27, 33, 39: contact hole 14, 114: pixel electrode

16, 116: common line 18, 118: common electrode

20, 120: storage capacitor 22, 122: storage upper electrode

24, 124: gate pad 26: gate pad lower electrode

28: gate pad upper electrode 30, 130: data pad

32: data pad lower electrode 34: data pad upper electrode

36, 136: common pad 38: common pad lower electrode

40: common pad upper electrode 42, 142: first gate metal layer

44, 144: second gate metal layer 45, 145: substrate

46, 146: gate insulating film 48, 148: active layer

50, 150: ohmic contact layer 52, 152: protective film

147: amorphous silicon layer 149: n + amorphous silicon layer

154: first source / drain metal layer 156: second source / drain metal layer

127, 133, 139: contact hole 160: second mask

162: mask substrate 164: blocking portion

166: diffraction exposure portion 168: photoresist pattern

174: Gate TCP 176: Data TCP

172: base film 174, 176, 178: TCP pad

182: ACF 200: upper substrate

202: color filter array 204: sealing material

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using a horizontal electric field, and more particularly, to a horizontal field application type liquid crystal display device and a method of manufacturing the same, which can simplify a structure and a process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are roughly classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field for driving the liquid crystal.

In the vertical field applying liquid crystal display, a liquid crystal of TN (Twisted Nemastic) mode is driven by a vertical electric field formed between a pixel electrode and a common electrode disposed to face the upper and lower substrates. The vertical field application type liquid crystal display device has an advantage of having a large aperture ratio while having a narrow viewing angle of about 90 degrees.

In the horizontal field application type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. Such a horizontal field application liquid crystal display device has an advantage that a viewing angle is about 160 degrees. Hereinafter, the horizontal field application liquid crystal display will be described in detail.

The horizontal field application type liquid crystal display device includes a thin film transistor array substrate (bottom plate) and a color filter array substrate (top plate) bonded to each other, a spacer for keeping a cell gap constant between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The thin film transistor array substrate is composed of a plurality of signal wirings and thin film transistors for forming a horizontal electric field in pixels, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a thin film transistor array substrate.

FIG. 1 is a plan view illustrating a thin film transistor array substrate of a horizontal field application type liquid crystal display device using a conventional four mask process, and FIG. 2 is cut along the line II ′ of the thin film transistor array substrate of FIG. 1. It is sectional drawing.

The thin film transistor array substrate illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect a gate insulating layer 46 therebetween on a lower substrate 45, and a thin film formed at each intersection thereof. The transistor 6 includes a pixel electrode 14 and a common electrode 18 formed to form a horizontal electric field in a pixel region provided in a cross structure thereof, and a common line 16 connected to the common electrode 18. 1 and 2 may include a storage capacitor 20 formed at an overlapping portion of the pixel electrode 14 and the common electrode line 16, and a gate pad connected to the gate line 2. 24, a data pad 33 connected to the data line 4, and a common pad 36 connected to the common line 16 are further provided.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The common line 16 for supplying a reference voltage for driving the liquid crystal is formed in parallel with the gate line 2 with the pixel region 5 therebetween.

The thin film transistor 6 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 14 in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 further includes an active layer 48 that overlaps with the gate electrode 8 and the gate insulating layer 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12. .

The active layer 48 is also formed to overlap the data line 4, the data pad lower electrode 32, and the storage upper electrode 22. The ohmic contact layer 50 for ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 32, and the storage upper electrode 22 is disposed on the active layer 48. This is further formed.

The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 13 passing through the passivation layer 52 and is formed in the pixel region 5. In particular, the pixel electrode 14 is connected to the drain electrode 12 and has a first horizontal portion 14A formed in parallel with the adjacent gate line 2 and a second horizontal portion 14B formed so as to overlap the common line 16. ) And a pinker portion 14C formed side by side between the first and second horizontal portions 14A and 14B.

The common electrode 18 is connected to the common line 16 and is formed in the pixel region 5. In particular, the common electrode 18 is formed in the pixel region 5 to be parallel to the finger portion 14C of the pixel electrode 14.

Accordingly, a horizontal electric field is formed between the pixel electrode 14 supplied with the pixel signal through the thin film transistor 6 and the common electrode 18 supplied with the reference voltage through the common line 16. In particular, a horizontal electric field is formed between the finger portion 14C of the pixel electrode 14 and the common electrode 18. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 20 includes a common line 16 and a storage upper electrode 22 overlapping the common line 16 with the gate insulating layer 46, the active layer 48, and the ohmic contact layer 50 interposed therebetween. And the pixel electrode 14 connected through the storage upper electrode 22 and the second contact hole 21 formed in the passivation layer 50. The storage capacitor 20 allows the pixel signal charged in the pixel electrode 14 to be stably maintained until the next pixel signal is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad 24. The gate pad 24 includes a gate pad lower electrode 26 extending from the gate line 2 and a third gate hole 27 passing through the gate insulating layer 46 and the passivation layer 52. 26 and a gate pad upper electrode 28 connected thereto.

The data line 4 is connected to a data driver (not shown) through the data pad 30. The data pad 30 is connected to the data pad lower electrode 32 through the data pad lower electrode 32 extending from the data line 4 and the fourth contact hole 33 penetrating through the passivation layer 52. It consists of the pad upper electrode 34.

The common line 16 receives a reference voltage from an external reference voltage source (not shown) through the common pad 36. The common pad 36 includes a common pad lower electrode 38 extending from the common line 16, and a fifth contact hole 33 penetrating through the gate insulating layer 46 and the passivation layer 52. And a common pad upper electrode 40 connected with 38).

A method of manufacturing a thin film transistor array substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, the gate line 2, the gate electrode 8, the gate pad lower electrode 26, the common line 16, and the common electrode 18 are formed on the lower substrate 45 using the first mask process. ), A first conductive pattern group including the common pad lower electrode 38 is formed.

In detail, the first metal layer 42 and the second metal layer 44 are sequentially deposited on the lower substrate 45 through a deposition method such as a sputtering method, thereby forming a gate metal layer having a dual structure. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate line 2, a gate electrode 8, a gate pad lower electrode 26, a common line 16, and a common electrode 18. ), A first conductive pattern group including the common pad lower electrode 38 is formed. Here, an aluminum metal or the like is used as the first metal layer 42, and a metal such as chromium (Cr) or molybdenum (Mo) is used as the second metal layer 44.

Referring to FIG. 3B, a gate insulating layer 46 is coated on the lower substrate 45 on which the first conductive pattern group is formed. A semiconductor pattern including an active layer 48 and an ohmic contact layer 50 on the gate insulating layer 46 using a second mask process; A second conductive pattern group including a data line 4, a source electrode 10, a drain electrode 12, a data pad lower electrode 32, and a storage upper electrode 22 is formed.

In detail, the gate insulating layer 46, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 45 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. do. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 46. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Subsequently, a photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern so that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage upper electrode 22 are formed. The second conductive pattern group including () is formed.

Then, the ohmic contact layer 50 and the active layer 48 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

In addition, after the photoresist pattern having a relatively low height is removed from the channel part by an ashing process, the source / drain metal pattern and the ohmic contact layer 50 of the channel part are etched by a dry etching process. Accordingly, the active layer 48 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12.

Subsequently, the photoresist pattern remaining on the second conductive pattern group is removed by a stripping process.

Referring to FIG. 3C, a passivation layer including first to fifth contact holes 13, 21, 27, 33, and 39 on the gate insulating layer 46 on which the second conductive pattern group is formed by using a third mask process. 52 is formed.

In detail, the protective film 52 is entirely formed on the gate insulating film 46 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the passivation layer 52 is patterned by a photolithography process and an etching process using a third mask to form first to fifth contact holes 13, 21, 27, 33, and 39. The first contact hole 13 penetrates the passivation layer 52 to expose the drain electrode 12, and the second contact hole 21 penetrates the passivation layer 52 to expose the storage upper electrode 22. The third contact hole 27 penetrates the passivation layer 52 and the gate insulating layer 46 to expose the gate pad lower electrode 26, and the fourth contact hole 33 penetrates the passivation layer 52 to lower the data pad. The electrode 32 is exposed, and the fifth contact hole 39 passes through the passivation layer 52 and the gate insulating layer 46 to expose the common pad lower electrode 38. Here, when a dry etch ratio metal such as molybdenum (Mo) is used as the source / drain metal, each of the first, second, and fourth contact holes 12, 21, and 33 may have a drain electrode 12 and a storage upper electrode. (22) penetrates to the data pad lower electrode 32 to expose their sides.

As the material of the protective film 52, an inorganic insulating material such as the gate insulating film 46 or an acrylic insulating material having a low dielectric constant, an organic insulating material such as BCB or PFCB or the like is used.

Referring to FIG. 3D, the passivation layer 52 includes the pixel electrode 14, the gate pad upper electrode 28, the data pad upper electrode 34, and the common pad upper electrode 40 on the passivation layer 52. A third conductive pattern group is formed.

In detail, the transparent conductive film is apply | coated on the protective film 52 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is etched through a photolithography process and an etching process using a fourth mask, thereby forming the pixel electrode 14, the gate pad upper electrode 28, the data pad upper electrode 34, and the common pad upper electrode 40. A third conductive pattern group including the third conductive pattern group is formed, and the pixel electrode 14 is electrically connected to the drain electrode 12 through the first contact hole 13 and the storage upper electrode (via the second contact hole 21). And the gate pad upper electrode 28 is electrically connected to the gate pad lower electrode 26 through the third contact hole 37. The data pad upper electrode 34 is the fourth contact hole. The common pad upper electrode 40 is electrically connected to the common pad lower electrode 38 through the fifth contact hole 39 through 33.

Here, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or the like is used as a material of the transparent conductive film.

As described above, the conventional horizontal field-applied thin film transistor array substrate and the manufacturing method thereof employ a four mask process, thereby reducing the number of manufacturing steps and reducing the manufacturing cost in proportion to the five mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

Accordingly, an object of the present invention is to provide a horizontal field application type liquid crystal display device and a method of manufacturing the same that can reduce the number of structures and mask processes.

In order to achieve the above object, a horizontal field application type liquid crystal display device according to an embodiment of the present invention, a gate line, a common line formed in parallel with the gate line; A data line crossing the gate line and the common line and having a gate insulating layer interposed therebetween to determine a pixel region, a thin film transistor formed at an intersection of the gate line and the data line, and formed in the pixel region and connected to the common line Connected to the thin film transistor, a pixel electrode formed to form a horizontal electric field with the common electrode in the pixel region, a gate pad formed of at least one conductive layer included in the gate line, and the data line. A lower plate including a data pad formed of at least one conductive layer included therein, a common pad formed of at least one conductive layer included in the common line, and a passivation layer exposing the gate pad, the data pad, and the common pad; ; An upper plate bonded to the lower plate to fill the liquid crystal therebetween; And a conductive film connected to the exposed pads of the lower plate.

The gate line and the common line may include a main conductive layer and an auxiliary conductive layer for preventing disconnection of the main conductive layer.

The gate pad and the common pad may include the main conductive layer and the auxiliary conductive layer, and have a structure in which the auxiliary conductive layer is exposed.

The gate pad and the common pad may include the auxiliary conductive layer.

The data line has a main conductive layer and an auxiliary conductive layer for preventing disconnection of the main conductive layer.

The data pad includes the main conductive layer and the auxiliary conductive layer, and has a structure in which the auxiliary conductive layer is exposed.

The data pad includes the auxiliary conductive layer.

The main conductive layer is a low resistance metal and includes at least one metal of aluminum-based metal, copper, molybdenum, chromium, and tungsten, and the auxiliary conductive layer includes titanium.

The thin film transistor may include a gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor layer overlapping the gate electrode and the gate insulating layer therebetween and forming a channel portion between the source electrode and the drain electrode.

The drain electrode and the pixel electrode may be configured of the same conductive layer.

And, the present invention and the storage lower electrode consisting of a portion of the common line; And a storage capacitor formed on the gate insulating layer to overlap the lower storage lower electrode and having a storage upper electrode formed of the same conductive layer as the pixel electrode.

The semiconductor layer may be formed on the gate insulating layer along the data line, the source electrode, the drain electrode, the pixel electrode, and the storage upper electrode.

A method for manufacturing a horizontal field application type liquid crystal display device according to the present invention includes a thin film transistor formed at an intersection of a gate line and a data line, a pixel electrode connected to the thin film transistor, a common electrode forming a horizontal electric field with the pixel electrode; A gate pad including a common line connected to the common electrode, the gate pad formed of at least one conductive layer included in the gate line, a data pad formed of at least one conductive layer included in the data line, and included in the common line Providing a lower plate having a structure in which a common pad formed of at least one conductive layer is exposed through a protective film; Preparing an upper plate to be opposite to the lower plate; Bonding the lower plate and the upper plate; And connecting a conductive film to the exposed gate pad, the data pad, and the common pad.

The preparing of the lower plate may include forming a gate line, a gate electrode of the thin film transistor connected to the gate line, the common line parallel to the gate line, the common electrode, the gate pad, and the common pad on a substrate. Forming a first conductive pattern group comprising a; Forming a gate insulating film on the substrate on which the first conductive pattern groups are formed; A semiconductor layer in a predetermined region of the gate insulating film; The data line, the source electrode of the thin film transistor connected to the data line, the drain electrode of the thin film transistor facing the source electrode, the pixel electrode connected to the drain electrode and parallel to the common electrode, and the data pad. Forming a second conductive pattern group comprising a; And forming a passivation layer exposing the gate pad, the data pad, and the common pad on the gate insulating layer on which the semiconductor layer and the second conductive pattern group are stacked.

The first conductive pattern group may be formed in a double layer structure of a main conductive layer and an auxiliary conductive layer for preventing disconnection of the main conductive layer.

The forming of the passivation layer may include exposing an auxiliary conductive layer of the gate pad and the common pad.

The forming of the passivation layer may include forming a contact hole through the passivation layer and the gate insulating layer to expose the auxiliary conductive layer.

The forming of the passivation layer may include forming a contact hole through the passivation layer, the gate insulating layer, and the main metal layer to expose the auxiliary conductive layer.

The second conductive pattern group may be formed in a double layer structure of a main conductive layer and an auxiliary conductive layer for preventing disconnection of the main conductive layer.

The forming of the passivation layer may include exposing the auxiliary conductive layer of the data pad.

The forming of the passivation layer may include forming a contact hole penetrating the passivation layer to expose the auxiliary conductive layer.

The forming of the passivation layer may include forming a contact hole penetrating the passivation layer and the main metal layer to expose the auxiliary conductive layer.

The main conductive layer is a low resistance metal and includes at least one metal of aluminum-based metal, copper, molybdenum, chromium, and tungsten, and the auxiliary conductive layer includes titanium.

The forming of the second conductive pattern group may further include forming a storage upper electrode overlapping the common line and the gate insulating layer therebetween.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 9C.

4 is a plan view illustrating a thin film transistor array substrate of a horizontal field application type liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 5 is cut along the line II-II ′ of the thin film transistor array substrate of FIG. 4. It is sectional drawing.

The thin film transistor array substrate illustrated in FIGS. 4 and 5 includes a gate line 102 and a data line 104 formed to intersect on a lower substrate 145 with a gate insulating layer 146 therebetween, and a thin film formed at each intersection thereof. A transistor 106, a pixel electrode 114 and a common electrode 118 formed to form a horizontal electric field in a pixel region provided in an intersecting structure thereof, and a common line 116 connected to the common electrode 118 are provided. 4 and 5, the thin film transistor array substrate includes a storage capacitor 120 formed at an overlapping portion of the storage upper electrode 122 and the common electrode line 116, and a gate pad extending from the gate line 102. 124, a data pad 130 extending from the data line 104, and a common pad 136 extending from the common line 116.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure to define the pixel region 105.

The common line 116 for supplying a reference voltage for driving the liquid crystal is formed in parallel with the gate line 102 with the pixel region 105 therebetween.

The thin film transistor 106 keeps the pixel signal of the data line 104 charged and held in the pixel electrode 114 in response to the gate signal of the gate line 102. To this end, the thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode included in the data line 104, and a drain electrode 112 connected to the pixel electrode 114. Equipped. In addition, the thin film transistor 106 further includes an active layer 148 that overlaps the gate electrode 108 and the gate insulating layer 146, and forms a channel between the source electrode and the drain electrode 112.

In addition, the active layer 148 overlaps the data line 114, the data pad 130, and the storage upper electrode 122. An ohmic contact layer 150 for ohmic contact with the data line 14, the drain electrode 112, the data pad 130, and the storage upper electrode 122 is further formed on the active layer 148.

The pixel electrode 114 is integrated with the drain electrode 112 of the thin film transistor 106 and integrated with the storage upper electrode 122 to be formed in the pixel region 105. In particular, the pixel electrode 114 may include a first horizontal portion 114A extending parallel to the gate line 102 adjacent to the drain electrode 112, and a pinker portion extending in the vertical direction from the first horizontal portion 114A. 114B).

The common electrode 118 is connected to the common line 116 and is formed in the pixel region 105. In particular, the common electrode 118 is formed to be parallel to the finger portion 114B of the pixel electrode 114 in the pixel region 105.

Accordingly, a horizontal electric field is formed between the pixel electrode 114 supplied with the pixel signal through the thin film transistor 106 and the common electrode 118 supplied with the reference voltage through the common line 116. In particular, a horizontal electric field is formed between the finger portion 114C of the pixel electrode 114 and the common electrode 118. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 105 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 120 overlaps the common line 116, the common line 116, the gate insulating layer 146, the active layer 148, and the ohmic contact layer 150, and overlaps the pixel electrode 114. It consists of an integrated storage upper electrode 122. The storage capacitor 120 allows the pixel signal charged in the pixel electrode 114 to be stably maintained until the next pixel signal is charged.

The gate line 102 is connected to a gate driver (not shown) mounted on a tape carrier package (hereinafter, referred to as TCP) through the gate pad 124. The gate pad 124 extends from the gate line 102 and is exposed through the first contact hole 127 penetrating the gate insulating layer 146 and the passivation layer 152. The gate pad 124 has a structure in which a metal layer having relatively high strength and corrosion resistance, such as titanium (Ti) and tungsten (W), included in the gate line 102 is exposed. Accordingly, even when the process of attaching the gate pad 124 and the TCP is repeated, the disconnection failure of the gate pad 124 can be prevented.

The common line 116 receives a reference voltage from an external reference voltage source (not shown) through TCP attached to the common pad 136. The common pad 136 extends from the common line 116 and is exposed through the third contact hole 139 passing through the gate insulating layer 146 and the passivation layer 152. The common pad 136 has a structure in which a metal layer having relatively high strength and corrosion resistance, such as titanium (Ti) and tungsten (W), is exposed like the gate pad 124. Accordingly, even when the process of attaching the common pad 136 and the TCP is repeated, the disconnection failure of the common pad 136 can be prevented.

In detail, the gate line 102, the gate electrode 108, the common line 116, and the common electrode 118 have a double metal layer structure in which the first and second metal layers 142 and 144 are stacked. One of these metal layers is made of a metal having relatively high strength and corrosion resistance, such as titanium (Ti), tungsten (W), and the like. The other metal layer is made of a low resistance metal such as aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), or the like, which is used as a general gate metal.

Here, when the metal having high strength and corrosion resistance is used as the first metal layer 142, the gate pad 124 and the common pad 138 have the upper second metal layer 144 removed and the lower first metal layer 142. You will have this exposed structure. On the other hand, when a metal having high strength and corrosion resistance is used as the second metal layer 144, the gate pad 124 and the common pad 138 have a structure in which the second metal layer 144 is exposed.

The data line 104 is connected to a data driver (not shown) mounted in TCP through the data pad 130. The data pad 130 extends from the data line 104 and is exposed through the second contact hole 133 penetrating the passivation layer 152. The data pad 130 has a structure in which a metal layer having relatively high strength and corrosion resistance, such as titanium (Ti) and tungsten (W), included in the data line 104 is exposed. Accordingly, even when the process of attaching the data pad 130 and the TCP is repeated, a disconnection failure of the data pad 130 can be prevented.

In detail, the data line 104, the drain electrode 112, the pixel electrode 114, and the storage upper electrode 122 have a double metal layer structure in which the first and second metal layers 154 and 156 are stacked. One of these metal layers is made of a metal having relatively high strength and corrosion resistance, such as titanium (Ti), tungsten (W), and the like. The other metal layer is made of a low resistance metal such as aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), or the like, which is used as a general gate metal. That is, the data line 104 and the pixel electrode 114 are made of the same conductive metal.

Here, when the metal having high strength and corrosion resistance is used as the first metal layer 154, the data pad 130 has a structure in which the upper second metal layer 156 is removed and the lower first metal layer 154 is exposed. . On the other hand, when the metal having high strength and corrosion resistance is used as the second metal layer 156, the data pad 130 has a structure in which the upper second metal layer 156 is exposed.

6A and 6B are plan views and cross-sectional views illustrating a first mask process in a method of manufacturing a horizontal field applied thin film transistor array substrate according to an exemplary embodiment of the present invention.

As shown in FIGS. 6A and 6B, the gate line 102, the gate electrode 108, the gate pad 124, the common line 116, and the common electrode 118 are formed on the lower substrate 145 by the first mask process. ), A first conductive pattern group including the common pad 136 is formed.

In detail, the first gate metal layer 142 and the second gate metal layer 144 are sequentially deposited on the lower substrate 145 through a deposition method such as a sputtering method to form a gate metal layer having a dual structure. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, so that the gate line 102, the gate electrode 108, the gate pad 124, the common line 116, the common electrode 118, The first conductive pattern group including the common pad 136 is formed. Here, one gate metal layer of the first and second gate metal layers 142 and 144 is made of a metal having relatively high strength and corrosion resistance, such as titanium (Ti) and tungsten (W), and the other gate metal layer is made of aluminum. It is made of a metal such as (Al) -based metal, molybdenum (Mo), copper (Cu) and the like.

7A and 7B are plan views and cross-sectional views illustrating a second mask process in a method of manufacturing a horizontal field applied thin film transistor array substrate according to an exemplary embodiment of the present invention.

First, the gate insulating layer 146 is formed on the lower substrate 145 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating film 146, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

7A and 7B, a semiconductor pattern comprising an active layer 148 and an ohmic contact layer 150 stacked on the gate insulating layer 146 by a second mask process; A second conductive pattern group including the data line 104, the drain electrode 112, the pixel electrode 114, the data pad 130, and the storage upper electrode 122 is formed. The second mask process will be described in detail with reference to FIGS. 8A to 8E as follows.

As shown in FIG. 8A, the amorphous silicon layer 147, the n + amorphous silicon layer 149, and the first and second source / drain metal layers 154 on the gate insulating layer 146 through a deposition method such as PECVD or sputtering. 156 are sequentially formed. Here, the source / drain metal layer of one of the first and second source / drain metal layers 154 and 156 is made of a metal having relatively high strength and corrosion resistance, such as titanium (Ti), tungsten (W), and the other. The source / drain metal layer is made of a metal such as aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), or the like.

Next, a photoresist film is formed on the second source / drain metal layer 156 and then a photoresist pattern having a step using a photolithography process using the partial exposure second mask 160 as shown in FIG. 8B ( 168 is formed. The second mask 160 includes a mask substrate 162 made of a transparent material, a blocking portion 164 formed in the blocking region P2 of the mask substrate 162, and a partial exposure region P3 of the mask substrate 162. The formed diffraction exposure part 166 (or semi-transmissive part) is provided. Here, the region where the mask substrate 162 is exposed becomes the exposure region P1. By developing the photoresist film using the second mask 160, the blocking region P2 and the partial exposure region correspond to the blocking portion 164 and the diffraction exposure portion 166 (or the semi-transmissive portion) of the second mask 160. In P3, a photoresist pattern 168 having a step is formed. In detail, the photoresist pattern 168 formed in the partial exposure region P3 has a second height h2 that is lower than the first height h1 of the photoresist pattern 168 formed in the blocking region P2.

The first and second source / drain metal layers 154 and 156 are patterned by a wet etching process using the photoresist pattern 160 to connect with the data line 104 and the data line 104 as shown in FIG. 8C. The second conductive pattern group including the drain electrode 112, the pixel electrode 114, the storage upper electrode 122, and the data pad 130 is formed.

In addition, the n + amorphous silicon layer 149 and the amorphous silicon layer 147 are patterned by a dry etching process using the photoresist pattern 160 to form the ohmic contact layer 150 and the active layer 148 as the source / It is formed along the drain metal pattern. Subsequently, the photoresist pattern 168 formed at the second height h2 in the partial exposure area P3 by an ashing process using an oxygen (O ₂ ) plasma is removed as shown in FIG. 8D, and is blocked. The photoresist pattern 168 formed at the first height h1 in the region P2 is in a state where the height is lowered. In the etching process using the photoresist pattern 168, the first and second source / drain metal layers 154 and 156 formed in the channel portion of the diffraction exposure area P3, that is, the thin film transistor, are removed. For example, when molybdenum (Mo) is used as the second source / drain metal layer 156 and titanium (Ti) is used as the first source / drain metal layer 154, the second source / drain metal layer 156 may be dry etched. In the process, the first source / drain metal layer 154 is removed from the channel portion by a wet etching process. In contrast, when titanium (Ti) is used as the second source / drain metal layer 156 and molybdenum (Mo) is used as the first source / drain metal layer 154, the second source / drain metal layer 156 may be a wet etching process. The first source / drain metal layer 154 is removed from the channel portion by a dry etching process. Accordingly, the drain electrode 112 is separated from the data line 104 including the source electrode. Next, the ohmic contact layer 150 is removed from the channel portion of the thin film transistor by a dry etching process using the photoresist pattern 168 to expose the active layer 148.

As shown in FIG. 8E, the photoresist pattern 168 remaining on the second conductive pattern group is removed by a strip process.

9A and 9B are plan views and cross-sectional views illustrating a third mask process in the method of manufacturing the horizontal field applied thin film transistor array substrate according to the embodiment of the present invention.

As shown in FIGS. 9A and 9B, the first to third contact holes 127, 133, and 139 are formed on the gate insulating layer 146 in which the semiconductor pattern and the source / drain metal pattern described above are stacked in a third mask process. A protective film 152 is formed.

In detail, the passivation layer 152 is formed on the gate insulating layer 146 on which the semiconductor pattern and the source / drain metal pattern are stacked by a deposition method such as PECVD. As the material of the protective film 52, an inorganic insulating material such as the gate insulating film 46, an acryl-based organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB or the like is used. Subsequently, the passivation layer 152 is patterned by a photolithography process and an etching process using a third mask to form first to third contact holes 127, 133, and 139. The first contact hole 127 passes through the passivation layer 152 and the gate insulating layer 146 to expose the gate pad 124, and the second contact hole 133 passes through the passivation layer 152 to pass through the data pad 130. The third contact hole 139 passes through the passivation layer 152 and the gate insulating layer 146 to expose the common pad 136. The exposed gate pad 124, the data pad 130, and the common pad 136 have a metal layer exposed structure having high strength and corrosion resistance. In this case, the gate pad 124, the data pad 130, and the common pad 136 have two structures as shown in FIGS. 10 and 11.

For example, when titanium (Ti) is used as the lower first gate metal layer 142 and molybdenum (Mo) is used as the upper second gate metal layer 144, the gate pad 124 is illustrated in FIG. 10. The common pad 136 includes only the lower first gate metal layer 142. This is because the upper second gate metal layer 144 is removed in the etching process for forming the first and third contact holes 127 and 139.

On the contrary, when molybdenum (Mo) is used as the lower first gate metal layer 142 and titanium (Ti) is used as the second gate metal layer 144, as shown in FIG. 11, the gate pad 124 and the common pad ( 136 has a double metal layer structure in which the first and second gate metal layers 142 and 144 are stacked. The gate pad 124 and the common pad 136 have a structure in which the second gate metal layer 144 is exposed by the first and third contact holes 127 and 139.

In addition, when titanium (Ti) is used as the lower first source / drain metal layer 154 and molybdenum (Mo) is used as the upper second source / drain metal layer 156, as illustrated in FIG. 10, a data pad ( 130 consists only of the first source / drain metal layer 154 thereunder. This is because the upper second source / drain metal layer 156 is removed in the etching process for forming the second contact hole 133.

On the contrary, in the case where molybdenum (Mo) is used as the lower first source / drain metal layer 154 and titanium (Ti) is used as the second source / drain metal layer 156, the data pad 130 is illustrated in FIG. 11. Has a double metal layer structure in which the first and second source / drain metal layers 154 and 156 are stacked. The data pad 130 has a structure in which the second source / drain metal layer 156 is exposed by the second contact hole 133.

As described above, in the horizontal field applied thin film transistor array substrate and the method of manufacturing the same, the pixel electrode 114 is formed of the same metal as the drain electrode 112. As the gate pad 124, the data pad 130, and the common pad 136, a metal having high strength and corrosion resistance, which can prevent disconnection defects, may be used even in a TCP repeatedly attach process. Accordingly, the present invention eliminates the need for the transparent conductive film, that is, eliminates the need for the transparent conductive film deposition process and the patterning process, thereby reducing one mask process. In other words, the horizontal field applied thin film transistor array substrate according to the present invention can be formed by a three mask process.

12 and 13, the completed thin film transistor array substrate and the upper substrate 200 on which the color filter array 202 is formed in another process are prepared and bonded to each other through the sealing material 204. (Not shown) is injected to produce a liquid crystal panel. In this case, the upper substrate 200 is bonded to the pad region where the gate pad 124, the data pad 130, and the common pad 136 are formed on the thin film transistor array substrate.

Subsequently, TCP 170 and 180 in which drive ICs are mounted are attached to the pad region of the thin film transistor array substrate using an anisotrophic conductive film (ACF) 182 including conductive balls 184. Accordingly, the output pads 174, 176, and 178 formed on the TCP 170 and 180 may pass through the gate pad 124, the data pad 130, and the common pad through the conductive ball 184 of the ACF 182. 136) electrically connected to each. Specifically, the first TCP pad 174 formed on the base film 172 of the gate TCP 170 may include the gate pad 124 and the second TCP pad formed on the base film 172 of the data TCP 180. The data pad 130 and the third TCP pad 178 formed on the base film 172 of the data TCP 180 are electrically connected to the common pad 142 through the ACF 182. In this case, since the gate pad 124, the data pad 130, and the common pad 136 have a structure in which a metal layer having a high strength and corrosion resistance is exposed, the disconnection of the pad is poor even if the TCP 170 and 180 are repeatedly attached. Is prevented.

 As described above, the horizontal field application type liquid crystal display device and the manufacturing method thereof according to the present invention form a pixel electrode of the same metal as the drain electrode, and the pads are exposed to a metal having high strength and corrosion resistance so as to prevent disconnection failure. It is structured and connected to TCP through ACF. Accordingly, the horizontal field application type liquid crystal display device and the manufacturing method thereof according to the present invention do not require a transparent conductive film, that is, no need for a transparent conductive film deposition process and a patterning process can reduce one mask process.

As a result, the horizontal field-applied liquid crystal display device and the manufacturing method thereof according to the present invention can manufacture the thin film transistor array substrate using a three mask process, thereby simplifying the structure and the process of the thin film transistor array substrate, thereby reducing the manufacturing cost. In addition, the production yield can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (24)

Gate line, A common line formed in parallel with the gate line, A data line crossing the gate line and the common line with a gate insulating layer interposed therebetween to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode formed in the pixel region and connected to the common line; A pixel electrode connected to the thin film transistor and forming a horizontal electric field with the common electrode in the pixel region and made of the same conductive metal as the conductive metal forming the data line; A gate pad formed of at least one conductive layer included in the gate line; A data pad formed of at least one conductive layer included in the data line; A common pad formed of at least one conductive layer included in the common line; A lower plate including the gate pad, the data pad, and a passivation layer exposing the common pad; An upper plate bonded to the lower plate to fill the liquid crystal therebetween; And a conductive film connected to the exposed pads of the lower plate. The method of claim 1, The gate line and the common line And a subconducting layer for preventing disconnection of the subconducting layer. The method of claim 2, The gate pad and the common pad And a main conductive layer and the auxiliary conductive layer, wherein the auxiliary conductive layer is exposed. The method of claim 2, The gate pad and the common pad And the auxiliary conductive layer. The method of claim 1, The data line is And a subconducting layer for preventing disconnection of the subconducting layer. The method of claim 5, The data pad is And a main conductive layer and the auxiliary conductive layer, wherein the auxiliary conductive layer is exposed. The method of claim 5, The data pad is And the auxiliary conductive layer. The method according to claim 2 or 5, The main conductive layer is a low resistance metal and includes at least one metal of aluminum-based metal, copper, molybdenum, chromium and tungsten, And the auxiliary conductive layer comprises titanium. The method of claim 1, The thin film transistor is A gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor layer overlapping the gate electrode and the gate insulating layer therebetween and forming a channel portion between the source electrode and the drain electrode. The method of claim 9, And the drain electrode and the pixel electrode are formed of the same conductive layer. The method of claim 10, A lower storage electrode formed as part of the common line; And a storage capacitor formed on the gate insulating layer to overlap the lower storage lower electrode and having a storage upper electrode formed of the same conductive layer as the pixel electrode. The method of claim 11, And the semiconductor layer is formed on the gate insulating layer along the data line, the source electrode, the drain electrode, the pixel electrode, and the storage upper electrode. A thin film transistor formed at an intersection of a gate line and a data line, a pixel electrode connected with the thin film transistor, a common electrode forming a horizontal electric field with the pixel electrode, a common line connected with the common electrode, and the gate line A gate pad formed of at least one conductive layer included in the data pad, a data pad formed of at least one conductive layer included in the data line, and a common pad formed of at least one conductive layer included in the common line. Providing a top plate having a structure; Preparing a lower plate to be opposed to the upper plate; Bonding the upper plate and the lower plate to each other; And connecting a conductive film to the exposed gate pad, the data pad, and the common pad. The method of claim 13, Preparing the lower plate A first conductive pattern group including the gate line, a gate electrode of the thin film transistor connected to the gate line, the common line parallel to the gate line, the common electrode, the gate pad, and the common pad on a substrate; Forming a; Forming a gate insulating film on the substrate on which the first conductive pattern groups are formed; A semiconductor layer in a predetermined region of the gate insulating film; The data line, the source electrode of the thin film transistor connected to the data line, the drain electrode of the thin film transistor facing the source electrode, the pixel electrode connected to the drain electrode and parallel to the common electrode, and the data pad. Forming a second conductive pattern group comprising a; And forming a passivation layer exposing the gate pad, the data pad, and the common pad on the gate insulating layer on which the semiconductor layer and the second conductive pattern group are stacked. Method of preparation. The method of claim 14, The first conductive pattern group A method of manufacturing a horizontal field application type liquid crystal display device comprising a double layer structure of a LED conductive layer and an auxiliary conductive layer for preventing disconnection of the LED conductive layer. The method of claim 15, Forming the protective film And exposing the auxiliary conductive layers of the gate pad and the common pad. The method of claim 15, Forming the protective film And forming a contact hole penetrating the protective layer and the gate insulating layer to expose the auxiliary conductive layer. The method of claim 15, Forming the protective film And forming a contact hole penetrating the protective layer, the gate insulating layer, and the main metal layer to expose the auxiliary conductive layer. The method of claim 14, The second conductive pattern group A method of manufacturing a horizontal field application type liquid crystal display device comprising a double layer structure of a LED conductive layer and an auxiliary conductive layer for preventing disconnection of the LED conductive layer. The method of claim 19, Forming the protective film And exposing the auxiliary conductive layer of the data pad. The method of claim 19, Forming the protective film And forming a contact hole penetrating the passivation layer to expose the auxiliary conductive layer. The method of claim 19, Forming the protective film And forming a contact hole penetrating the protective film and the main metal layer to expose the auxiliary conductive layer. The method of claim 15 or 19, The main conductive layer is a low resistance metal and includes at least one metal of aluminum-based metal, copper, molybdenum, chromium and tungsten, The auxiliary conductive layer is a manufacturing method of a horizontal field application type liquid crystal display device characterized in that it comprises titanium. The method of claim 14, Forming the second conductive pattern group And forming a storage upper electrode overlapping the common line with the gate insulating layer interposed therebetween.

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