KR20060028519A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on a gate line and a gate fanout line formed on an insulating substrate, a gate insulating film formed on a gate line and a gate fanout line, a semiconductor formed on the gate insulating film, a semiconductor, and a gate insulating film. It is formed on the data line and the data fan-out line, the data line, and the data fan-out line, and has a contact hole exposing a part of the data line. A pixel electrode connected through the pixel electrode, a gate fanout protection line formed on the same layer as the pixel electrode, and overlapping the gate fanout line, and a data fanout protection line formed to overlap the data fanout line. desirable. Accordingly, the thin film transistor array panel according to the present invention forms a gate fanout protection line and a data fanout protection line, thereby preventing the gate fanout line and the data fanout line from being corroded and opened by a manufacturing process or an external environment, respectively. There is an advantage.

Fanout, Corrosion

Description

Thin film transistor display panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views taken along lines IIa-IIa 'and IIb-IIb' of FIG. 1, respectively.

FIG. 3 is a layout view of a first step of manufacturing the thin film transistor array panel for the liquid crystal display of FIGS. 1 and 2;

4A and 4B are cross-sectional views taken along the lines IIIa-IIIa 'and IIIb-IIIb' of FIG. 3, respectively.

FIG. 5 is a layout view of a thin film transistor array panel in the next step of FIG. 3;

6A and 6B are cross-sectional views taken along the lines VIa-VIa 'and Vb-Vb' of FIG. 5, respectively.

<Description of Symbols for Main Parts of Drawings>

110: substrate 121, 129: gate line

124: gate electrode 140: gate insulating film

151 and 154: semiconductors 161 and 165: ohmic contact members

171 and 179: data line 173: source electrode                 

175: drain electrode 180: protective film

181, 182, and 185: contact hole 190: pixel electrode

81, 82: contact auxiliary member

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

Such a liquid crystal display panel has a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line, the data line, and the pixel electrode are made of different conductive layers (hereinafter referred to as gate conductors, data conductors, and pixel conductors, respectively) and separated into insulating layers, which are generally arranged in order from the bottom.

 In such a thin film transistor array panel, not only an open defect of a pad portion but also a wiring open defect of a fan out part occur frequently.

The wiring open failure of the fanout part is because the wiring of the fanout part is exposed to the external environment through a hole generated due to various reasons in the protective film formed of the nitride film SiNx. That is, in case of dry etching the micro-pinhole of the nitride film deposited on the wiring of the fan-out part or the protective film, the protective film is formed through the hole of the photoresist film formed on the protective film to form a pattern on the protective film. A hole is generated in. Therefore, these holes act as an infiltration path of an etchant or moisture to cause corrosion and disconnection of the gate fanout line or the data fanout line formed under the nitride layer.

An object of the present invention is to provide a thin film transistor array panel and a method of manufacturing the same to prevent the gate fanout line or the data fanout line from corroding.

The thin film transistor array panel according to the present invention includes a gate line and a gate fanout line formed on an insulating substrate, a gate insulating film formed on the gate line and the gate fanout line, a semiconductor formed on the gate insulating film, the semiconductor and the gate. A passivation layer formed on the data line and the data fanout line formed on the insulating film, the passivation layer formed on the data line and the data fanout line, and having a contact hole for exposing a part of the data line; A pixel electrode connected to a portion of the data line through the contact hole, and formed on the same layer as the pixel electrode, and overlapping with the gate fanout protection line and the data fanout line formed to overlap the gate fanout line. Data fanout protection It is preferable to include.

The widths of the gate fanout protection line and the data fanout protection line may be larger than the widths of the gate fanout line and the data fanout line, respectively.

The gate fanout protection line and the data fanout protection line may be formed of the same material as the pixel electrode.

The gate fanout protection line and the data fanout protection line are preferably formed of IZO or ITO.

In addition, it is preferable to include an auxiliary gate fanout protection line formed on the gate insulating film and overlapping the gate fanout line and the gate fanout protection line.

The gate fan-out line is preferably connected to the gate line formed on the display portion and the extension portion of the gate line formed on the peripheral portion.

Preferably, the data fan-out line connects the data line formed on the display portion and the extension portion of the data line formed on the peripheral portion.                     

In addition, it is preferable that no signal is applied to the gate fanout protection line and the data fanout protection line.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention includes forming a gate line and a gate fanout line on an insulating substrate, forming a gate insulating film on the gate line and the gate fanout line, and forming a semiconductor on the gate insulating film. Forming a data line and a data fanout line on the semiconductor and gate insulating layer, forming a passivation layer on the data line and the data fanout line, and overlapping the pixel electrode and the gate fanout line on the passivation layer. And forming a data fanout protection line overlapping the gate fanout protection line and the data fanout line.

In addition, an auxiliary gate fanout protection line overlapping the gate fanout protection line and the gate fanout protection line may be formed on the gate insulating layer.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on top" of another part, this includes not only being another part "on top" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a thin film transistor array panel and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Specifically, as shown in FIG. 1, one embodiment includes a thin film transistor, a pixel electrode, and a signal line positioned in a display area of a thin film transistor array panel, and an extension of a fan out line and a signal line positioned in a peripheral area. 2A and 2B are cross-sectional views of lines IIa-IIa 'and IIb-IIb' of FIG. 1, respectively.

As shown in FIGS. 1 and 2B, a plurality of gate lines 121 are formed on the insulating substrate 110 to transmit a gate signal and mainly extend in a horizontal direction.

A portion of each gate line 121 forms a plurality of gate electrodes 124. In addition, each gate line 121 includes an extension 129 that is widened for connection with an external device. Most of the gate line 121 is located in the display area, but the extension 129 of the gate line 121 is located in the peripheral area.

In addition, the gate line 121 has an extension portion 129 of the gate line concentrated in a narrow area for connection with an external device (not shown). On the other hand, since the gate line 121 of the display area has to maintain an interval determined according to the pixel size, the interval between lines is larger than that of the expansion part 129 of the gate line. Therefore, between the gate line 121 of the display area and the extension portion 129 of the gate line, a gate fan-out line in which the gap between the gate lines 121 becomes wider (or narrower) in a buccal shape. 122 is present. The gate fanout lines 122 located near the center of the gate fanout lines 122 go straight without any change in direction, but the gate fanout lines 122 are located at the edges of the gate fanout lines 122. The angle of bending increases.

The gate line 121 may be formed of a single layer, or may be formed of two layers having different physical properties. The upper layer is made of a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum alloy so as to reduce the delay or voltage drop of the gate signal. In contrast, the underlayer is a material having excellent physical, chemical and electrical contact properties with other materials, especially indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten (MoW). ) Alloy], chromium (Cr), tantalum (Ta), titanium (Ti) and the like. An example of the combination of the lower layer and the upper layer is a chromium (Cr) / aluminum-neodymium (AlNd) alloy.

In addition, the side surfaces of the gate line 121 are inclined, respectively, and the inclination angle is about 30 to 80 degrees with respect to the surface of the substrate 110.

The gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the gate fan-out line 122. A plurality of semiconductors 150 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The semiconductor 150 is mainly formed on the gate electrode 124, and the semiconductor 150 covers a larger area than the gate electrode 124.                     

A plurality of island type ohmic contact members 163 and 165 made of a material such as n + hydrogenated amorphous silicon in which silicide or n-type impurities are heavily doped is formed on the semiconductor 150. The island-like ohmic contact members are divided into two and are paired with each other and positioned on the semiconductor.

Side surfaces of the semiconductor 150 and the ohmic contacts 163 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 to transmit a data voltage. Each data line 171 includes an expansion unit 179 which is extended in width for connection with an external device. Most of the data line 171 is located in the display area, but the extension 179 of the data line 171 is located in the peripheral area.

The data line 171 is densely packed in a narrow area in order to connect with an external device (not shown). On the other hand, since the data line 171 of the display area has to maintain the interval determined according to the pixel size, the interval between the lines is larger than that of the expansion unit 179 of the data line. Therefore, between the data line 171 of the display area and the expansion part 179 of the data line, a data fan-out line in which an interval between the data lines 171 becomes wider (or narrower) in the shape of a sub chatsal ( 172). The data fanout lines 172 positioned near the center of the data fanout lines 172 are almost straight without change in direction, but the data fanout lines 172 are located as the data fanout lines 172 positioned at the edges. The angle of bending increases.

A plurality of branches extending from the data line 171 toward the drain electrode 175 forms the source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the semiconductor 150, and channels of the thin film transistor include the source electrode 173 and the drain electrode ( 175 is formed in the semiconductor 150 between.

In order to prevent corrosion and disconnection of the gate fanout line 122, an auxiliary gate fanout protection line 176 is formed on the same layer as the data line 171. The auxiliary gate fanout protection line 176 overlaps the gate fanout line 122 and is formed to have a width wider than that of the gate fanout line 122. The auxiliary gate fanout protection line 176 is floating to prevent a signal from being applied. That is, the auxiliary gate fanout protection line 176 is not a signal transmission line, and prevents the gate fanout line 122 from being corroded or eroded through the penetration of an etchant or moisture from the upper portion or the pinhole of the nitride layer.

The data lines 171 and 173, the drain electrode 175, and the data fan-out line 172 may be formed as a single layer or two layers having different physical properties. The top layer is made of a low resistivity metal, such as aluminum (Al) or aluminum alloy, such as aluminum or silver, so as to reduce the delay or voltage drop of the data signal. In addition, the lower layer is a material having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum (Mo) and molybdenum alloys [eg, molybdenum-tungsten (MoW) alloys, chromium- Molybdenum (CrMo) alloy, molybdenum-titanium (MoTi) alloy, molybdenum-neodymium (MoNb), molybdenum-vanadium (MoV)], chromium (Cr), tantalum (Ta), titanium (Ti) and the like.

In addition, the side surfaces of the data line 171 are inclined, respectively, and the inclination angle is about 30 to 80 degrees with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 150 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The semiconductor 150 has a portion exposed to the source electrode 173 and the drain electrode 175.

A passivation layer 180 made of silicon nitride (SiNx), which is an inorganic material, is formed on the data line 171, the drain electrode 175, the data fanout line 172, and the exposed portion of the semiconductor 150.

The passivation layer 180 is provided with a plurality of contact holes 185 and 182 exposing the drain electrode 175 and the extension 179 of the data line 171, respectively, and the gate line 121 together with the gate insulating layer 140. A plurality of contact holes 181 are formed to expose the extension 129 of.

A plurality of pixel electrodes 190, a plurality of contact auxiliary members 81 and 82, a gate fanout protection line 192a, and a data fanout protection line 192b are formed on the passivation layer 180. The pixel electrode 190 is made of indium tin oxide (ITO) or indium zinc oxide (IZO), and the pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185, respectively. The data voltage is applied from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied generates a electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, thereby generating a liquid crystal of a liquid crystal layer (not shown) between the two electrodes. Rearrange the molecules.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the thin film transistor is turned off. In order to enhance the voltage holding capability of the liquid crystal capacitor, Other capacitors may be placed in parallel.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the extension part 129 of the gate line and the extension part 179 of the data line through contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 may serve to complement and protect the adhesion between the extension portions 129 and 179 of the gate line 121 and the data line 171 and the external device. Their application is optional. The contact auxiliary members 81 and 82 are made of indium tin oxide (ITO) or indium zinc oxide (IZO).

The gate fanout protection line 192a and the data fanout protection line 192b are both formed on the same layer as the pixel electrode 190, and the gate fanout protection line 192a overlaps the gate fanout line 122. The data fan out protection line 192b overlaps with the data fan out line 172.

The width of the gate fanout protection line 192a is greater than the width of the gate fanout line 122, and the width of the data fanout protection line 192b is greater than the width of the data fanout line 172. .

Accordingly, the gate fanout protection line 192a and the data fanout protection line 192b overlap each other to prevent moisture, and the like, from penetrating into the gate fanout line 122 and the data fanout line 172 respectively positioned below. Corrosion and erosion of the gate fanout line 122 and the data fanout line 172 are prevented.

In addition, the gate fanout protection line 192a and the data fanout protection line 192b are floated so that a signal is not applied, and it is preferable to form indium tin oxide (ITO) or indium zinc oxide (IZO).

In the related art, since the data fanout line 172 is protected only by the passivation layer 180, the data fanout line 172 has a weaker upper cross-sectional structure than the gate fanout line 122 which is protected by the gate insulating layer 140 and the passivation layer 180. Since the deposition process conditions of the passivation layer 180 are not largely related to the characteristics of the thin film transistor and thus are not formed densely than the gate insulating layer 140, the vulnerability was even greater. Therefore, the data fanout protection line 192b is necessary for further protection of the data fanout line 172.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6B and FIGS. 1 and 2.                     

3 is a layout view of a first step of manufacturing the thin film transistor array panel for the liquid crystal display of FIGS. 1 and 2, and FIGS. 4A and 4B are cross-sectional views taken along lines IIIa-IIIa 'and IIIb-IIIb' of FIG. 3, respectively. 5 is a layout view of a thin film transistor array panel in the next step of FIG. 3, and FIGS. 6A and 6B are cross-sectional views taken along lines VIa-VIa ′ and Vb-Vb ′ of FIG. 5, respectively.

First, as shown in FIGS. 3 to 4B, a gate metal film is formed on the insulating substrate 110 made of transparent glass or the like by sputtering or the like. The gate metal film may be formed of a single film or two films having different physical properties. The upper layer is formed of a low resistivity metal such as aluminum (Al) or an aluminum alloy such as an aluminum alloy so as to reduce the delay or voltage drop of the gate signal. In contrast, the underlayer is a material having excellent physical, chemical and electrical contact properties with other materials, especially indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten (MoW). ) Alloy], chromium (Cr), tantalum (Ta), titanium (Ti) and the like. An example of the combination of the lower layer and the upper layer is a chromium (Cr) / aluminum-neodymium (AlNd) alloy.

The gate metal layer is patterned to form the gate line 121 and the gate fanout line 122 including the plurality of gate electrodes 124.

Next, as shown in Figs. 5 to 6B, the gate insulating film 140 is formed. As the material of the gate insulating layer 140, silicon nitride (SiNx) is preferable, and the lamination temperature is preferably 250-500 ° C. and the thickness is about 2,000-5,000 Pa.                     

A semiconductor layer, that is, intrinsic amorphous silicon 150 and an impurity amorphous silicon layer 160, is sequentially stacked on the gate insulating layer 140.

Then, the impurity amorphous silicon layer and the intrinsic amorphous silicon layer are photo-etched to form the intrinsic semiconductor 150 and the plurality of impurity semiconductors 160.

The data metal film is formed on the gate insulating layer 140 by sputtering or the like. The data metal film may be formed as a single film or two films having different physical properties. The upper layer is formed of a low resistivity metal such as aluminum (Al) or an aluminum alloy such as an aluminum alloy so as to reduce the delay or voltage drop of the gate signal. In contrast, the underlayer is a material having excellent physical, chemical and electrical contact properties with other materials, especially indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten (MoW). ) Alloy], chromium (Cr), tantalum (Ta), titanium (Ti) and the like. An example of the combination of the lower layer and the upper layer is a chromium (Cr) / aluminum-neodymium (AlNd) alloy.

The data metal film is patterned to form data lines 171 and 173, a drain electrode 175, and a data fan-out line 172. That is, the metal film is patterned by wet etching or dry etching to form a plurality of data lines 171 and a plurality of drain electrodes 175 including the plurality of source electrodes 173, respectively, and the extension portion 179 of the data line. A data fanout line 172 is formed between the data lines 171.                     

At this time, the auxiliary gate fanout protection line 176 is formed on the same layer as the data line 171 to prevent corrosion and disconnection of the gate fanout line 122 in a subsequent process.

The auxiliary gate fanout protection line 176 overlaps the gate fanout line 122 and is formed to have a width wider than that of the gate fanout line 122. The auxiliary gate fanout protection line 176 is not a signal transmission line because the auxiliary gate fanout protection line 176 is formed to float so that a signal is not applied. The auxiliary fan fanout protection line 176 is a gate fanout line 122 through the penetration of an etchant or moisture or a pinhole of a nitride layer in a subsequent process. ) To prevent corrosion or erosion.

Subsequently, the plurality of ohmic contacts 160 may be completed by removing portions of the impurity semiconductor 160 that are not covered by the data line 171 and the drain electrode 175, while the portions of the intrinsic semiconductor 150 thereunder. Expose In order to stabilize the surface of the exposed portion of the intrinsic semiconductor 150, oxygen plasma is preferably followed.

Next, as shown in FIGS. 1 and 2B, after the protective film 180 is laminated with a nitride film and the photosensitive film is coated thereon, the photosensitive film is irradiated with light through a photomask and then developed. Thereafter, a plurality of contact holes 182, 185, and 189 are formed through an etching step such as an ashing process.

Then, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is laminated by sputtering, and the photoresist film is coated thereon, and then developed after irradiating light to the photoresist film through a photomask. Then, the ITO or IZO is etched using the photoresist as an etch mask, and the plurality of pixel electrodes 190 connected to the drain electrode 175 through the contact holes 185 and the gate lines and the data through the contact holes 181 and 182. A plurality of contact assisting members 81 and 82 are formed to be connected to the extension portions 129 and 179 of the line, respectively. In addition, the gate fanout protection line 192a is formed to overlap the gate fanout line 122, and the data fanout protection line 192b is formed to overlap the data fanout line 172.

In this case, the width of the gate fanout protection line 192a is greater than the width of the gate fanout line 122, and the width of the data fanout protection line 192b is greater than the width of the data fanout line 172. do. In addition, the gate fanout protection line 192a and the data fanout protection line 192b may be formed to float so that a signal is not applied.

Accordingly, the gate fanout protection line 192a and the data fanout protection line 192b overlapping the gate fanout line 122 and the data fanout line 172 and positioned at the upper portion thereof may be indium tin oxide (ITO) or ITO. In the case of forming the indium zinc oxide (IZO) etching process, since the passivation layer positioned on the gate fanout line 122 and the data fanout line 172 is not exposed to the etchant, pinholes do not occur in the passivation layer 180. Thus, the etchant does not penetrate the passivation layer 180 to corrode or disconnect the gate fanout line 122 and the data fanout line 172.

Particularly, since molybdenum is a metal that is poorly chemically resistant to erosion even when exposed to deionized water (DI), the gate fanout protection line 192a and the data fan may be further formed when molybdenum is used to form a data line. Formation of the out protective line 192b is preferable.

Meanwhile, one end of the gate line 121 may be used to receive a signal transmitted from a gate driving circuit (not shown) and may have a width wider than the width of the gate line 121. The passivation layer 180 has a plurality of contact holes 181 exposing an end portion of the gate line 121, and the contact hole 81 has a plurality of contact auxiliary members contacting the end portions of the gate line 121. (81) can be formed. The contact auxiliary member 81 and the contact hole 181 are mounted on a display panel or a flexible circuit board (not shown) in the form of a chip with a gate driving circuit (not shown) for supplying a signal to the gate line 121. If necessary. On the other hand, when the gate driving circuit is made of a thin film transistor or the like directly on the substrate 110, the contact hole and the contact auxiliary member are not necessary.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

The thin film transistor array panel and the method of manufacturing the same according to the present invention form a gate fanout protection line and a data fanout protection line to prevent the gate fanout line and the data fanout line from being corroded and opened during the manufacturing process or by an external environment, respectively. The advantage is that you can.

Claims (10)

A gate line and a gate fanout line formed on the insulating substrate, A gate insulating film formed on the gate line and the gate fan-out line; A semiconductor formed on the gate insulating film, A data line and a data fan-out line formed on the semiconductor and gate insulating film; A protective film formed on the data line and the data fan-out line and having a contact hole exposing a portion of the data line; A pixel electrode formed on the passivation layer and connected to a part of the exposed data line through the contact hole; A gate fanout protection line formed on the same layer as the pixel electrode and overlapping the gate fanout line, and a data fanout protection line overlapping the data fanout line. Thin film transistor array panel comprising a. In claim 1, And a width of the gate fanout protection line and a data fanout protection line is greater than a width of the gate fanout line and the data fanout line, respectively. In claim 1, The gate fanout protection line and the data fanout protection line are formed of the same material as the pixel electrode. In claim 3, The gate fanout protection line and the data fanout protection line are formed of IZO or ITO. In claim 3, A thin film transistor array panel formed on the gate insulating layer and including an auxiliary gate fanout protection line overlapping the gate fanout line and the gate fanout protection line. In claim 1, And the gate fan-out line connects the gate line formed on the display unit and an extension of the gate line formed on the peripheral portion. In claim 1, And the data fan-out line connects the data line formed on the display unit and an extension of the data line formed on the peripheral portion. In claim 1, And a signal is not applied to the gate fanout protection line and the data fanout protection line. Forming a gate line and a gate fanout line on the insulating substrate, Forming a gate insulating film on the gate line and the gate fan-out line; Forming a semiconductor on the gate insulating film, Forming a data line and a data fanout line on the semiconductor and gate insulating layer; Forming a passivation layer on the data line and the data fan-out line; Forming a pixel electrode, a gate fanout protection line overlapping the gate fanout line, and a data fanout protection line overlapping the data fanout line on the passivation layer; Method of manufacturing a thin film transistor array panel comprising a. In claim 9, And an auxiliary gate fanout protection line overlapping the gate fanout protection line and the gate fanout protection line, over the gate insulating film.

Images