JPH0855994A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To form a lightly doped drain(LDD) region without forming a sidewall in a thin film transistor(TFT). CONSTITUTION:After an anode oxide 107 is formed by anode oxidation of a gate electrode 105, ion doping is performed for forming a P-type impurity region 109 and an offset region. After formation of an offset region, the anode oxide 107 is removed and negative fixed charge such as negative ion of Cl<->, etc., is introduced to a gate insulation film. As a result, hole is drawn to a surface of a practically intrinsic semiconductor surface of an offset region by Cl<-> in a gate insulation film and a practically weak P-type region (CID) 110 is formed. The CID region 110 shows an effect similar to a P-type lightly doped region and forms a practical LDD region. In the case of N-channel TFT, similar effect can be acquired by introducing positive fixed charge.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
FT). Particularly, the present invention relates to a semiconductor device used for a switching transistor of an active matrix circuit.

[0002]

2. Description of the Related Art Conventionally, it is widely known to form a thin film transistor (TFT) for the purpose of driving an active matrix type liquid crystal display device, an image sensor or the like. In particular, in recent years, crystalline silicon TFTs have been developed in place of amorphous silicon TFTs using amorphous silicon for the active layer because of the need for high-speed operation. However, when more advanced characteristics and higher durability are required, a low concentration drain (LD) used in semiconductor integrated circuit technology is required.
D) It was necessary to have a region.

For example, a crystalline silicon TFT generally has a leakage current when a reverse bias voltage (for example, a positive voltage for a P-channel TFT) is applied to the gate electrode, as compared with an amorphous silicon TFT. (Off current) is large,
Moreover, it has been observed that a phenomenon in which the reverse bias voltage increases as the absolute value of the reverse bias voltage increases, but it is known that the provision of the LDD region can significantly reduce such off current. For example, in an electro-optical device such as a liquid crystal display, when it is used as a switching transistor of an active matrix circuit, it is preferable that such an off current is small for the purpose of retaining charges.

Further, a deterioration phenomenon has been observed in which the on-current of the TFT is lowered by applying a voltage for a long time.
This will be explained by taking an N-channel TFT as an example. Since a positive voltage is applied to the gate electrode, accelerated electrons are injected into the gate insulating film, which becomes fixed charges and forms a channel formation region thereunder. The reason for this is that a P-type region is formed although it is weak. This meant that for the source / drain, a PN junction was formed, thus interrupting the current. However, by providing the LDD region, it is possible to suppress the generation of the P-type region and reduce such a deterioration phenomenon.

The conventional method of forming an LDD is performed as follows. First, low-dose ion doping is performed on the entire surface using the gate electrode as a mask to form a low-concentration impurity region. Then, a sidewall is formed adjacent to the side surface of the gate electrode. As a method for forming the side wall, an insulating film is formed on the entire surface and then anisotropic etching is performed to form the side wall. Next, high-dose ion doping is performed on the entire surface by using the side wall and the gate electrode formed previously as a mask to form a high-concentration impurity region. By doing so, L is formed in a region below the side wall formed on the side surface of the gate electrode where high dose ion doping has not been performed.
It was intended to form a DD region.

[0006]

However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular, since the device is formed on the insulating surface and reactive ion anisotropic etching cannot be sufficiently performed, a fine pattern cannot be formed, which makes it difficult to form a side wall, resulting in a decrease in yield due to overetching, and a problem of forming a side wall. There has been a problem that it is difficult to perform uniform processing. In addition, in the conventional method, when forming the LDD region, since the active layer has at least two ion doping steps, the number of steps increases, which causes a decrease in productivity. Was there. Further, an ion doping method is when compared to an ion implantation process used in the semiconductor integrated circuit process (a method of injecting a substrate by separating mass ions) is very poor controllability in the low dose region, for example, 5 × 10 ¹³ It was virtually impossible to control the dose amount of atoms / cm ³ or less.

[0007]

DISCLOSURE OF THE INVENTION The present invention proposes a method for solving the above problems in a TFT, and obtaining a thin film transistor which has substantially the same effect as LDD. That is, the present invention has at least one pair of N-type or P-type impurity regions provided in the active layer and at least one gate electrode sandwiched between the impurity regions, and at least one of the gate electrode and the gate electrode. An offset region is provided between the impurity regions, and the semiconductor device is characterized in that the gate insulating film except the lower portion of the gate electrode contains fixed charges. Here, the fixed charge is N
Positive in channel type TFT, P channel type TFT
For, use the negative one. The fixed charge is a charge that does not move under the influence of an external electric field or the like, and ions having a large ionic radius, crystal defects, dangling bonds, etc. can be fixed charges.

FIG. 5 shows the structure of the present invention and the reason why the same effects as those of the LDD can be obtained by the present invention.
Will be explained. In the present invention, for example, in the case of a P-channel type TFT, as shown in FIG. 5A, the P-type impurity region 502 is formed slightly away from the gate electrode portion. As a result, not only directly below the gate electrode portion but also in the vicinity thereof, an intrinsic region (offset region) 5
01 is formed. The offset region is a region between the gate electrode portion and the P-type region when the gate electrode portion and the P-type region are separated from each other as shown in the figure (such a state is referred to as an offset state). Is. In the present invention, the offset regions may be provided on both sides of the gate electrode portion as shown in the drawing, or may be provided on only one of them.

Next, as shown in FIG. 5B, thermal annealing in a chlorine atmosphere, plasma discharge in a chlorine atmosphere, ion doping, etc. are performed to introduce negative ions of Cl ⁻ into the gate insulating film 503. To do. Cl ^- F instead of ^-
You may use negative ions, such as. These negative ions have a fixed charge. Cl ⁻ hardly enters the portion where the gate electrode portion 504 was present by any of the methods of thermal annealing, plasma discharge, and ion doping. Thus, Cl ⁻ is introduced into the gate insulating film 503.

In the present invention, it is required to form the offset region stably. What is important in carrying out the present invention is the process of manufacturing the gate electrode. Anodization may be used to stably form the offset region. That is, after forming a gate electrode with an anodizable material, the gate electrode is energized in an electrolytic solution,
An anodic oxide is formed on at least the side surface of the gate electrode.
At this time, the anodic oxidation may be selectively performed on the side surface of the gate electrode, or may be performed on the upper surface and the side surface of the gate electrode. As a material for the gate electrode, anodizable aluminum, tantalum, titanium, a metal containing silicon as a main component, an alloy thereof, a multilayer film or the like is preferable.

Aluminum as a gate electrode,
If a porous anodic oxide is used, 3
It may be carried out using an acidic aqueous solution of -20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like. In this case, a relatively thick anodic oxide having a thickness of 0.5 μm or more can be formed at a low voltage of about 5 to 50V. The thickness of the porous anodic oxide depends on the time for which current is applied, and a longer anodic oxide gives a thicker anodic oxide. The porous anodic oxide thus obtained is also easy to etch.

Doping with P-type impurities is performed using the anodic oxide and the gate electrode thus formed as a mask. Then, as shown in FIG. 1D, the P-type region (106) and the gate electrode (105) are separated from each other, and an offset region is obtained. Then, the anodic oxide formed in the previous step is removed. If the porous anodic oxide uses aluminum as the gate electrode, a phosphoric acid-based etchant may be used as the etchant. However, the phosphoric acid type etchant also etches aluminum. To avoid this difficulty,
A non-porous anodic oxide coating may be provided between the porous anodic oxide and the gate electrode. The phosphoric acid-based etchant is
Since the etching rate of the non-porous anodic oxide is extremely slow, only the porous anodic oxide can be selectively etched.

To form the non-porous anodic oxide between the porous anodic oxide and the gate electrode, after forming the porous anodic oxide, 3 to 10% of tartaric acid, boric acid, nitric acid, etc. are contained. The current may be applied in a neutral ethylene glycol solution. In this anodizing step, the thickness of the non-porous anodic oxide obtained is determined by the maximum voltage applied between the gate electrode and the opposing electrode. In the present invention, the thickness of the non-porous anodic oxide formed for the above purpose (etching stopper) is 500 to 250.
0Å is preferred.

After etching the anodic oxide, negative ions are introduced into the gate insulating film by thermal annealing, plasma discharge, or ion doping in an atmosphere of a negative ion source (for example, an atmosphere of chlorine gas). Among them, when plasma discharge is adopted, when ECR plasma discharge is used, plasma damage to the device is
It is preferable because it is smaller than F discharge or the like. Further, it is preferable to activate the doped P-type impurities before introducing the negative ions. Further, when introducing negative ions, hydrogen may be introduced at the same time to neutralize the dangling bonds of silicon in the active layer.

It is expected that the negative ions introduced into the gate insulating film by the above-mentioned means will be released due to the subsequent processing (thermal annealing or the like) or the change of the environment.
This can be dealt with by forming a film (for example, silicon nitride) having a barrier action so as to cover the gate insulating film. Although the above example relates to the P-channel type TFT, the same can be applied to the N-channel type TFT. However, in the case of N-channel type TFT,
It is necessary to use positive fixed charges instead of negative ions.

[0016]

As described above, the offset area (5 in FIG. 5) is
01) When negative ions, which are fixed charges, are introduced into the upper gate insulating film, holes are attracted to the surface layer of the underlying semiconductor layer by the negative ions. At this time, since the impurity region 502 was originally a P-type impurity region, almost no change was observed, and the effect was remarkably exhibited in the substantially intrinsic semiconductor region which was the offset region 501, and holes were attracted. Weak P-type region 50
5 is formed. Then, the weak P-type region 505 exhibits substantially the same effect as LDD. Such a weak P-type region 505 is a charge-induced drain (charge-induced drain) in the sense of a drain induced by fixed charges.
ed-Drain, CID).

The above-mentioned effects are exhibited in the same manner even when positive fixed charges are introduced into the N-channel TFT. In that case, the positive fixed charge attracts electrons to the offset region to form a weak N-type CID.
In the present invention, the gate electrode portion (504 in FIG. 5) does not need to be entirely composed of a conductor.
An insulating coating may be provided on the surface of the conductor. This will be apparent from the reason that the gate electrode portion is mainly used in the present invention to selectively introduce positive or negative fixed charges.

The semiconductor device of the present invention has a special effect in that it contributes to the reduction of off current. Therefore,
When the present invention is applied to the switching transistor of the active matrix circuit, a great effect can be obtained.
In particular, as described in JP-A-5-335572, the advantage of using a P-channel TFT as a switching transistor of an active matrix circuit is known. This is due to the off-current of the P-channel TFT. Is smaller than that of the N-channel type TFT. When a P-channel TFT having such advantageous characteristics is used in an active matrix circuit and the present invention is applied to it, the off current can be further reduced, and the characteristics of the active matrix circuit can be improved. You can Further, it is apparent from the fact that the effect of the present invention is exactly the same as that of the conventional LDD structure in that it is effective in preventing the deterioration of the ON current.

[0019]

【Example】

[Embodiment 1] FIG. 1 shows this embodiment. First, the substrate 101
(Corning 7059, 100 mm × 100 mm) with a thickness of 1000 to 5000 Å as an underlying oxide film, for example,
A 3000 Å silicon oxide film 102 was formed by a sputtering method in an oxygen atmosphere. After that, plasma CV
An amorphous silicon film is formed by the D method or the LPCVD method to a thickness of 300 to 1
500 Å, for example, 500 Å is deposited and this is 550-
It was left to crystallize in a reducing atmosphere at 600 ° C. for 8 to 24 hours. At that time, a crystallization may be promoted by adding a trace amount of a catalyst element such as nickel that promotes crystallization. Further, this step may be performed by laser irradiation. Then, the crystallized silicon film was etched to form the island-shaped silicon film 103. This island-shaped silicon film 103 will later form an active layer of a TFT. further,
A gate insulating film 104 was formed on this. Here, a silicon oxide film having a thickness of 700 to 1500 Å, for example, 1200 Å was formed by the plasma CVD method. (Fig. 1
(A))

Then, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 1000 Å to 3 μm, for example, 6000 Å was formed by the sputtering method. Then, a thin anodic oxide film having a thickness of 100 to 400 Å was formed on the surface of the aluminum film by the anodic oxidation method. For example, as an electrolytic solution at the time of anodization, the substrate is immersed in an ethylene glycol solution of 3% tartaric acid (pH adjusted to neutral with ammonia), and an electric current is applied to the aluminum film under a constant current state of 20 mV. A voltage was applied and the voltage was raised to 12 V to carry out anodization. The obtained anodic oxide was non-porous and its thickness was less than 200Å. This thin anodic oxide is
It has the function of maintaining the adhesiveness with the photoresist in the subsequent anodic oxidation process.

Thereafter, a photoresist having a thickness of about 1 μm was formed on the aluminum film thus treated by spin coating. Then, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form the gate electrode 105. Here, a photoresist mask 106 is formed on the gate electrode 105.
Exists. (FIG. 1 (B)) Next, the substrate is immersed in a 10% oxalic acid solution for 5 to 50 V,
For example, at a constant voltage of 10 V for 10 to 500 minutes, for example 80
Minute, the gate electrode 105 is energized to perform anodic oxidation, and a porous anodic oxide 1 having a thickness of about 5000 Å
07 was formed on the side surface of the gate electrode 105. Since the photoresist mask 106 was present on the upper surface of the gate electrode 105, the anodic oxidation hardly proceeded.

Next, the mask material 106 is removed to expose the upper surface of the gate electrode, and the substrate is dipped in an ethylene glycol solution of 3% tartaric acid (neutral pH adjusted with ammonia), and an electric current is applied to this. A voltage was applied in a constant current state of 20 mV, and the voltage was raised to 100 V to carry out anodization. In this case, not only the top surface of the gate electrode,
The side surface of the gate electrode was also anodized to form a dense non-porous anodic oxide 108 having a thickness of 1400Å. (Fig. 1
(C))

Thereafter, by ion doping, boron is implanted as an impurity in the island-shaped silicon film 103 in a self-aligning manner using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask to form the P-type impurity region 109. Formed.
Here, the dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm 3.
² , acceleration voltage is 40 ~ 80kV, for example, dose amount is 1
× 10 ¹⁵ atoms / cm ² , accelerating voltage was 65 kV.
(Fig. 1 (D))

Then, the porous anodic oxide 107 was etched with a phosphoric acid-based etchant to expose the non-porous anodic oxide 108. Since the phosphoric acid-based etchant has an extremely low etching rate with respect to non-porous anodic oxide, only the porous anodic oxide can be selectively etched. Protected by etching process. Further, at this time, since the lower portion of the portion where the porous anodic oxide 107 was present was not doped with boron, an offset region was formed.

After that, a KrF excimer laser (wavelength 2
The doped impurity region was activated by irradiation with 48 nm and a pulse width of 20 nsec. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . At this time, the laser was also applied to the boundary between the impurity region and the offset region, which was effective in preventing deterioration at the boundary.

Next, 300 to 45 in a chlorine atmosphere.
Chlorination was performed by applying thermal annealing at 0 ° C.
By performing this chlorination treatment, Cl ⁻ was taken into the gate insulating film. At this time, in the offset region, which was a substantially intrinsic silicon film, Cl ⁻ taken into the gate insulating film attracted holes near the surface to form a weak P-type region 110. As a result, the weak P-type region 110 has an effect similar to that obtained by doping a low-concentration P-type impurity, and a substantial LD is obtained.
Area D was formed. (Fig. 1 (E))

Next, a silicon oxide film having a thickness of 5000 Å was formed as an interlayer insulating film 111 on the entire surface by plasma CVD. Then, the interlayer insulating film 111 and the gate insulating film 10
4 was etched to form contact holes in the source / drain regions. Then, an aluminum film having a thickness of 3000 Å to 2 μm, preferably 4000 to 8000 Å, for example, 5000 Å was formed by a sputtering method.
Then, the aluminum film is etched to form the source /
A P-channel TF having a weak P-type region that forms the drain electrode 112 and has substantially the same effect as LDD.
T was obtained. (FIG. 1F) As is clear from the drawing, the TFT of this embodiment has a very simple structure. However, it showed substantially the same characteristics as the TFT having LDD.

[Embodiment 2] FIG. 2 shows the present embodiment. In this embodiment, hydrogenation of the active layer and chlorination of the gate insulating film are performed at the same time, and further, as the interlayer insulating film is made of silicon nitride so that Cl ⁻ taken in the gate insulating film does not diffuse into the interlayer insulating film. It uses a membrane. First, the substrate 20
A silicon oxide film having a thickness of 4000 Å was formed as a base oxide film 202 on 1 (Corning 7059) by a sputtering method in an oxygen atmosphere.

After that, an amorphous silicon film is deposited to 800 Å by plasma CVD method or LPCVD method, and this is deposited to 55
It was left to crystallize in a reducing atmosphere at 0 to 600 ° C. for 8 to 24 hours. At that time, a crystallization may be promoted by adding a trace amount of a catalyst element such as nickel that promotes crystallization. Further, this step may be performed by laser irradiation. Then, the crystallized silicon film was etched to form an island-shaped silicon film 203. further,
A gate insulating film 204 was formed on this. Here, a 1500 Å-thick silicon oxide film was formed by a plasma CVD method. (Fig. 2 (A))

After that, an aluminum film having a thickness of 1000 Å to 3 μm, for example, 5000 Å, was formed by the sputtering method. Then, a thin anodic oxide film having a thickness of 100 to 400 Å was formed on the surface of the aluminum film. Then, a photoresist having a thickness of about 1 μm was formed on the aluminum film thus treated by spin coating. Then, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form the gate electrode 205. Here, the gate electrode 205
Above is a photoresist mask 206.
(FIG. 2 (B))

Next, the substrate is immersed in a 10% oxalic acid solution,
By carrying out anodization for 120 minutes at a constant voltage of 10 V, a porous anodic oxide 207 having a thickness of about 8000 Å is obtained.
Was formed on the side surface of the gate electrode 205. Gate electrode 20
Since the photoresist mask 206 was present on the upper surface of No. 5, anodic oxidation hardly proceeded. next,
The mask material 206 is removed to expose the upper surface of the gate electrode 205, and the substrate is immersed in an ethylene glycol solution of 3% tartaric acid (pH adjusted to neutral with ammonia), and a current is applied to the substrate to apply a constant current of 20 mV. Voltage is applied in the state,
The voltage was raised to 100 V to carry out anodization.
At this time, not only the upper surface of the gate electrode but also the side surface of the gate electrode is anodized, and a dense non-porous anodic oxide 208 is formed.
Was formed with a thickness of 1500Å. (Fig. 2 (C))

After that, boron is implanted in the island-shaped silicon film 203 in a self-aligned manner into the island-shaped silicon film 203 by using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask to form the P-type impurity region 209. Formed.
Here, the dose amount was 5 × 10 ¹⁵ atoms / cm ² and the acceleration voltage was 65 kV. (FIG. 2D) Then, the porous anodic oxide 207 was etched with a phosphoric acid-based etchant to expose the nonporous anodic oxide 208. At this time, since the lower portion of the portion where the porous anodic oxide 207 was present was not doped with boron, an offset region was formed.

After that, a KrF excimer laser (wavelength 2
The doped impurity region was activated by irradiation with 48 nm and a pulse width of 20 nsec. The suitable energy density of the laser is 250 to 300 mJ / cm ² . At this time, the laser was also applied to the boundary between the impurity region and the offset region, which was effective in preventing deterioration at the boundary.

Next, thermal annealing was performed at 300 to 450 ° C. in a mixed gas atmosphere of chlorine and hydrogen to simultaneously chlorinate the gate insulating film and hydrogenate the active layer. By performing this chlorination treatment, Cl ⁻ was taken into the gate insulating film 204. Also, the hydrogenation treatment improved the characteristics of the active layer. At this time, in the offset region which was a substantially intrinsic silicon film,
By Cl ⁻ taken in the gate insulating film 204,
Holes are attracted near the surface, weak P-type region 21
0 was formed. As a result, in this weak P-type region 210, an effect similar to that obtained by doping a low concentration P-type impurity was obtained, and a substantial LDD region was formed.
(Fig. 2 (E))

Next, a silicon nitride film 211 having a thickness of 300 to 1500 Å, for example, 500 Å, was formed on the entire surface by plasma CVD. Further, a silicon oxide film having a thickness of 50 is formed on the entire surface as an interlayer insulating film 212 by a plasma CVD method.
00Å formed. The silicon nitride film 211 is the gate insulating film 2
It was effective to prevent Cl ⁻ taken in 04 from separating and diffusing by the external environment such as heat and humidity. Then, the silicon nitride film 211, the interlayer insulating film 212 and the gate insulating film 204 are etched to form contact holes in the source / drain regions. Then, a 6000Å aluminum film was formed by a sputtering method. Then, the aluminum film was etched to form the source / drain electrodes 213, and a P-channel TFT having a weak P-type region, which substantially achieves the same effect as LDD, was obtained. (Fig. 2 (F))

[Embodiment 3] FIG. 3 shows the present embodiment. This embodiment relates to a CMOS type circuit constituted by a P-channel TFT having a substantial LDD and an N-channel TFT not having an LDD according to the present invention. First, a 4000 Å-thick silicon oxide film was formed as a base oxide film 302 on the substrate 301 of Corning 7059 by the plasma CVD method.

Further, an amorphous silicon film having a thickness of 500 Å was deposited by the plasma CVD method and left to stand in a reducing atmosphere at 550 to 600 ° C. for 8 to 24 hours for crystallization. At that time, a crystallization may be promoted by adding a trace amount of a catalyst element such as nickel that promotes crystallization. After crystallization, the silicon film was irradiated with KrF excimer laser light to further improve the crystallinity. The substrate temperature during laser irradiation is 150 to 250 ° C., and the energy density is 150.
A preferable condition was ˜350 mJ / cm ² . Then, the crystallized silicon film was etched to form island-shaped silicon films 303 and 304. Further, a gate insulating film 305 was formed on this. Here, plasma C
A 1000 Å thick silicon oxide film was formed by the VD method. (Fig. 3 (A))

After that, an aluminum film having a thickness of 6000Å was formed by the sputtering method. Then, anodic oxidation was performed by the same means as in Example 1. That is, first, only the gate electrode 307 of the P-channel TFT is anodized to form the porous anodic oxide 30.
8 (width 1.5 μm) was formed. Next, P channel type T
The gate electrode 307 of the FT and the gate electrode 306 of the N-channel TFT are anodized to form dense non-porous anodic oxides 309 and 310 with a thickness of 1000Å. (Fig. 3
(B))

After that, impurities were implanted into the island-shaped silicon films 303 and 304 in a self-aligned manner by using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask by the ion doping method. First, a region for forming a P-channel TFT was covered with a photoresist mask 311 and phosphorus was implanted to form an N-type impurity region 312. Here, the dose amount was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , the acceleration voltage was 60 to 90 kV, for example, the dose amount was 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 80 kV. (Fig. 3 (C))

After that, a region for forming an N-channel TFT is covered with a photoresist mask 313, and boron is implanted into a region for forming a P-channel TFT to form a P-type impurity region 314. Here, the dose amount is 1 × 10
¹³ to 8 × 10 ¹⁵ atoms / cm ^2, the accelerating voltage is 40~80k
V, for example, the dose amount was 3 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 65 kV. (FIG. 3D) Then, the porous anodic oxide 308 was etched with a phosphoric acid-based etchant to expose the nonporous anodic oxide 310.

After that, a KrF excimer laser (wavelength 2
The doped impurity region was activated by irradiation with 48 nm and a pulse width of 20 nsec. The appropriate energy density of the laser is 250 to 350 mJ / cm ² . Then, fluorine was injected into the gate insulating film by the ion doping method. At this time, the dose amount is 1 ×
10 ¹² to 1 × 10 ¹⁵ atoms / cm ² , for example, 5 × 10 ¹³
The atom / cm ² and the acceleration voltage were set to 30 kV. As a result,
F ⁻ was introduced into the gate insulating film 305. At this time,
In the offset region, which was a substantially intrinsic silicon film, F ⁻ captured in the gate insulating film 305 attracted holes near the surface to form a weak P-type region 315. As a result, this weak P-type region 31
In Example 5, the same effect as that obtained by doping a low concentration P-type impurity was obtained, and a substantial LDD region was formed. Since fluorine was hardly injected into the active layer in this doping step, the crystallinity of the active layer was hardly changed before and after the doping. (Fig. 3
(E))

Next, a silicon oxide film having a thickness of 5000 Å was formed as an interlayer insulating film 316 on the entire surface by plasma CVD. Then, the interlayer insulating film 316 and the gate insulating film 30.
5 was etched to form contact holes in the source / drain regions. Then, a 5000Å aluminum film was formed by a sputtering method, and this was etched to form source / drain electrodes 317. Through the above steps, a CMOS-type circuit including a P-channel TFT having a weak P-type region and an N-channel TFT having no LDD and having substantially the same effect as LDD was obtained. (Fig. 3 (F))

[Embodiment 4] FIG. 4 shows the present embodiment. This embodiment relates to a method for manufacturing an active matrix type liquid crystal display, and more particularly to a monolithic type active matrix circuit in which an active matrix circuit and a peripheral driving circuit for driving the same are formed on the same substrate.
P-channel TF with substantial LDD according to the invention
T is used as a switching transistor of a pixel circuit (active matrix circuit), and N-channel and P-channel TFTs having no LDD are used as peripheral drive circuits.

First, a silicon oxide film having a thickness of 4000 Å is further formed as a base oxide film 402 on the substrate 401, and a thickness of 50 Å.
Deposit 0Å amorphous silicon film and deposit it
It was left to stand in a reducing atmosphere at 0 ° C. for 8 to 24 hours for crystallization. Then, the crystallized silicon film was etched to form island-shaped silicon films 403, 404, and 405.
Further, a gate insulating film 406 of silicon oxide (thickness 1200 Å) was formed on this. (Fig. 4 (A))

Thereafter, an aluminum film having a thickness of 6000Å was formed by the sputtering method. Then, a thin anodic oxide film having a thickness of 100 to 400 Å was formed on the surface of the aluminum film. Then, anodization was performed in the same manner as in Examples 1 and 3. That is, first, the gate electrode 409 of the TFT forming the pixel circuit was anodized to form a porous anodic oxide 410 having a width of 1 μm on the side surface of the gate electrode 409. Next, the gate electrode 409 of the TFT forming the pixel circuit and the gate electrodes 407 and 408 of the TFT forming the peripheral driving circuit are anodized to form a dense non-porous anodic oxide 411, 41 having a thickness of 1500 Å.
2, 413 were formed. (Fig. 4 (B))

After that, the island-shaped silicon films 403, 404 and 405 were self-aligned with impurities by ion doping using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask. First, a region for forming a P-channel TFT was covered with a photoresist mask 414 and phosphorus was implanted to form an N-type impurity region 415. Here, the dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / c
m ² , the acceleration voltage was 60 to 90 kV, for example, the dose amount was 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 80 kV.
(Fig. 4 (C))

After that, a region for forming the N-channel type TFT was covered with a photoresist mask 416, and boron was implanted into the region for forming the P-channel type TFT to form P-type impurity regions 417 and 418. Here, the dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 40.
-80 kV, for example, a dose of 1 × 10 ¹⁵ atoms / cm
^{2. The} acceleration voltage was 65 kV. (Fig. 4 (D))

Then, the porous anodic oxide 410 was etched with a phosphoric acid-based etchant to expose the non-porous anodic oxide 413. After that, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurity regions. Laser energy density is 250-350mJ /
cm ² was suitable. Next, chlorine and hydrogen plasma treatment was performed to introduce chlorine and hydrogen into the gate insulating film 406. That is, the substrate was placed on one electrode of a parallel plate type apparatus provided in a depressurized chlorine and hydrogen atmosphere, and RF plasma (excitation frequency 13.56 MHz) was generated. During the plasma treatment, the substrate may be heated to 120 to 450 ° C. By applying this processing,
Cl ⁻ was introduced into the gate insulating film 406.

How much chlorine penetrates into the silicon oxide film when the above-described plasma treatment is applied to the crystalline silicon film and the gate insulating film (silicon oxide) formed under the same conditions as in this embodiment. Secondary ion mass spectrometry (SI
MS). The results are shown in FIG. Here, plasma treatment was performed for 1 hour. The ratio of chlorine to hydrogen is 1: 1 and the total pressure is 4 Pa, 13.56 MHz.
RF power of 150 W was input. As is clear from the obtained SIMS data, it can be seen that 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ of chlorine was introduced into the film.

Even in an actual TFT, chlorine of the same degree was introduced into the gate insulating film 406 as chlorine ions (Cl ⁻ ).
Then, in the offset region, which was a substantially intrinsic silicon film, Cl ⁻ captured in the gate insulating film 406 was used.
Causes a hole to be drawn near the surface and weak P
The mold area 419 was formed. As a result, in this weak P-type region, an effect similar to that obtained by doping a low concentration P-type impurity was obtained, and a substantial LDD region was formed. Hydrogen was also introduced at the same time, but the hydrogen ion was C
Since the ionic radius was smaller than that of l ⁻ , it penetrated to the active layer. (FIG. 4E) Next, the first interlayer insulating film 42 is formed on the entire surface.
0, a silicon nitride film having a thickness of 5000 Å is formed by the plasma CVD method, and the interlayer insulating film 420 and the gate insulating film 4 are formed.
06 was etched to form contact holes in the source / drain regions.

Then, a 5000 Å aluminum film was formed by a sputtering method, and this aluminum film was etched to form source / drain electrodes 421. Through the above steps, the peripheral drive circuit area was formed. (FIG. 4F) Further, plasma CVD is performed as the second interlayer insulating film 422.
A silicon oxide film having a thickness of 3000 Å was formed by the method, and the interlayer insulating film 420 and the gate insulating film 406 were etched to form contact holes. Then, a 500 Å ITO (indium tin oxide) film was formed by a sputtering method, and the ITO film was etched to form a pixel electrode 423. (Fig. 4 (G))

Through the above steps, the pixel circuit is formed by using the P-channel type TFT having the weak P-type region, which has substantially the same effect as the LDD which is the pixel circuit, and the monolithic active matrix circuit is obtained. I was able to. Figure 7 is, TFT manufactured by the above process (channel length: 10 [mu] m, the channel width 5 [mu] m) the drain current of (I _D), the field-effect mobility (mu _FE), the gate - leakage current between the source (I _G) Shows the gate voltage (V _G ) dependence of I _D , μ _FE , and I _G are drain voltages (V _D ) −
The values when 1 V and -14 V are also shown. As is clear from FIG. 7, the off current was reduced. On the other hand, the maximum mobility was 100 to 110 cm ² / Vs, and a high level could be maintained.

[0053]

According to the present invention, the LDD has a very simple structure, and the active layer is substantially LDDed by performing the doping step of P-type or N-type impurities substantially once.
It was possible to form a TFT having a weak positive or negative channel region with which the same effect as in (4) above can be obtained. In the example,
The manufacturing process of the P-channel type TFT has been described.
It will be apparent that the same can be applied to the channel type TFT. In the present invention, a TFT having a substantial LDD can be easily formed, and the throughput is improved. In the present invention, in addition to shortening the process, the manufacturing yield is improved by eliminating the need for low-concentration doping, which has been conventionally required and was extremely technically difficult. As described above, the present invention is industrially beneficial.

[Brief description of drawings]

1 shows the steps of Example 1. FIG.

2 shows the steps of Example 2. FIG.

FIG. 3 shows steps of Example 3.

FIG. 4 shows steps of Example 4.

FIG. 5 illustrates the structure and principle of the present invention.

FIG. 6 shows how chlorine is added to the gate insulating film in Example 4.

FIG. 7 shows the characteristics of the TFT obtained in Example 4.

[Explanation of symbols]

 101 ... Substrate 102 ... Underlayer oxide film 103 ... Island silicon film 104 ... Gate insulating film 105 ... Gate electrode 106 ... Photoresist mask 107 ... .. Porous anodic oxide 108 ... Non-porous anodic oxide 109 ... P-type impurity region 110 ... Weak P-type region 111 ... Interlayer insulating film 112 ... .Source / drain electrodes

Claims (9)

[Claims] 1. At least one set of N provided in the active layer
Type or P-type impurity region and at least one gate electrode sandwiched between the impurity regions, and an offset region is provided between the gate electrode and at least one of the impurity regions. A semiconductor device characterized in that a fixed charge is contained in a gate insulating film except a lower portion. 2. The semiconductor device according to claim 1, wherein the impurity region is P-type and the fixed charge is negative ion. 3. The semiconductor device according to claim 2, wherein the negative ions contained in the gate insulating film are Cl ⁻ . 4. A semiconductor device using the semiconductor device according to claim 1 as a switching transistor of an active matrix circuit. 5. A field effect semiconductor device, wherein the fixed charge density in the gate insulating film in the channel region is different from the fixed charge density in the insulating film in contact with the semiconductor layer in the source / drain regions. 6. A step of forming an anodic oxide on a side portion of the gate electrode, a step of introducing N-type or P-type impurities in a self-aligned manner using the anodic oxide and the gate electrode as a mask, and a side surface of the gate electrode section. 2. A method for manufacturing a semiconductor device, comprising: a step of selectively removing the anodic oxide of 1. and a step of introducing a fixed charge into a gate insulating film. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the step of introducing fixed charges into the gate insulating film is performed by plasma discharge. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the step of introducing fixed charges into the gate insulating film is performed by an ion implantation method. 9. The method for manufacturing a semiconductor device according to claim 6, wherein the step of introducing the fixed charges into the gate insulating film is performed by heat treatment in a gas atmosphere in which the fixed charges are generated.