JP2002033328A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, for which a pixel part and a driver for driving the pixel part are integrated on the same substrate. SOLUTION: For the N-channel type thin-film transistor of an inverter circuit for driving a pixel, a high resistance impurity region is overlapped with a gate electrode, deterioration by hot carriers is suppressed and an on-current is increased. For the thin-film transistor of the pixel part, the high resistance impurity region and the gate electrode are made so as not to overlap, a leakage current is suppressed and the ratio of the on-current and an off-current is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulating gate type transistor (TFT) formed on an insulating material such as glass or a material obtained by forming an insulating film such as silicon oxide on a silicon wafer, and its fabrication. About the method.
The present invention particularly relates to a TFT formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or less.
It is effective for The semiconductor device according to the present invention is used for a driving circuit such as an active matrix such as a liquid crystal display, an image sensor, or a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art Conventionally, TFs have been used for driving active matrix type liquid crystal display devices and image sensors.
It is widely known to form a T (thin film transistor). In particular, recently, because of the need for high-speed operation, a crystalline silicon TFT having higher electric field mobility has been developed instead of an amorphous silicon TFT using amorphous silicon for an active layer. However, when higher characteristics and higher durability are required, the semiconductor device has a high-resistance impurity region (high-resistance drain (HRD) or low-concentration drain (LDD)) as used in semiconductor integrated circuit technology. Was needed. However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular,
Since the element is formed on the insulating surface and the reactive ion anisotropic etching cannot be sufficiently performed, there is a great limitation that a fine pattern cannot be formed.

FIG. 6 shows a conventional HRD.
1 shows a cross-sectional view of a typical process for fabricating a. First, a base film 602 is formed over a substrate 601, and an active layer is formed using crystalline silicon 603. Then, an insulating film 604 is formed on the active layer using a material such as silicon oxide. (FIG. 6 (A))

Next, a gate electrode 605 is formed of polycrystalline silicon (doped with impurities such as phosphorus), tantalum, titanium, aluminum or the like. Further, using the gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by ion doping or the like, and a high-resistance impurity region (HRD) with a small doping amount is self-aligned.
606 and 607 are formed on the active layer 603. The active layer region under the gate electrode into which the impurity has not been introduced becomes a channel forming region. Then, the doped impurities are activated by a heat source such as a laser or a flash lamp. (FIG. 6 (B))

Next, an insulating film 608 of silicon oxide or the like is formed by means such as plasma CVD or APCVD.
(C)), and by performing anisotropic etching, a side wall 609 is formed adjacent to the side surface of the gate electrode. (FIG. 6D) Then, an impurity element is again introduced by means such as ion doping, and a sufficiently high-concentration impurity region (a low-resistance impurity region, a source region, etc.) is self-aligned using the gate electrode 605 and the side wall 609 as a mask. / Drain region) 610,
611 are formed on the active layer 603. Then, the doped impurities are activated by a heat source such as a laser or a flash lamp. (FIG. 6
(E))

Finally, an interlayer insulator 612 is formed, a contact hole is formed in the source / drain region through the interlayer insulator, and a wiring / electrode 613 connected to the source / drain is formed of a metal material such as aluminum.
614 are formed. (FIG. 6 (F))

[0007]

The above method directly follows the conventional LDD fabrication process in a semiconductor integrated circuit, and it is difficult to apply the process directly to a TFT fabrication process on a glass substrate. Alternatively, there is a step that is not preferable in terms of productivity.

First, activation of impurities by irradiation with a laser or the like is required twice. For this reason, productivity decreases. In a conventional semiconductor integrated circuit, activation of an impurity element has been performed by thermal annealing. for that reason,
The activation of the impurities was performed collectively after all the impurity introduction was completed.

However, in particular, TFTs on glass substrates
In this case, it is difficult to perform thermal annealing due to the temperature constraint of the substrate, and it is necessary to rely on laser annealing and flash lamp annealing (RTA or RTP). However, in these methods, since the irradiated surface is selectively annealed, for example, a portion below the sidewall 609 is not annealed. Therefore, annealing is required for each impurity doping.

Second, it is difficult to form a side wall. The thickness of the insulating film 608 is 0.5 to 2 μm. Usually, the thickness of the base film 602 provided on the substrate is 1000 to 3000３.
Therefore, in this etching step, the substrate is often exposed by accidentally etching the base film, and the yield is reduced. Since a substrate used for manufacturing a TFT contains many elements harmful to a silicon semiconductor, it is necessary to avoid such defects as much as possible. It is also difficult to finish the width of the side wall uniformly. This is reactive ion etching (RIE)
This is because, in the case of plasma dry etching such as described above, unlike a silicon substrate used for a semiconductor integrated circuit, delicate control of plasma is difficult because the substrate surface is insulative.

Since the drain of the high-resistance impurity region has a high resistance, it is necessary to make its width as narrow as possible. However, the above-mentioned variation makes mass production difficult. The problem was how to make the process easy to control). In addition, the conventional method requires at least two dopings, but reducing the number of dopings has also been a problem to be solved.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and further simplifies the process to form a high-resistance impurity region and a high-resistance impurity region (high-resistance drain, HRD) thus formed. A TFT having:
Here, the term “high-resistance drain (HRD)” is used to mean that although the impurity concentration is relatively high, the addition of carbon, oxygen, nitrogen, or the like results in the addition of an impurity in addition to the drain having a low impurity concentration and high resistance. It also includes a drain that prevents activation and consequently increases resistance.

[0013]

In forming a high resistance region, the present invention is characterized in that an oxide layer formed by means such as anodic oxidation of a gate electrode is positively used. In particular, the thickness of the anodic oxide can be precisely controlled, and the thickness of the anodic oxide can be as thin as 1000 mm or less.
Since it has a feature that it can be formed uniformly and widely up to a thickness of 000 mm or more, it is preferable as a material that can be substituted for the conventional side wall by anisotropic etching.

In particular, a so-called barrier type anodic oxide is not etched unless it is a hydrofluoric acid-based etchant, whereas a porous type anodic oxide is selectively etched by an etchant such as phosphoric acid. For this reason, TFT
Is characterized in that it can be treated without damaging other materials (for example, silicon and silicon oxide). Further, in both the barrier type and the porous type, the anodic oxide is extremely difficult to be etched by dry etching. In particular, the feature is that the selectivity is sufficiently large in etching with silicon oxide. The present invention is characterized in that a TFT is manufactured by the following manufacturing process. By adopting this process, the HRD can be configured more reliably and the mass productivity can be improved.

[0015]

FIG. 1 shows the basic steps of the present invention. First, a base insulating film 102 is formed on a substrate 101, and an active layer 103 is formed of a crystalline semiconductor (a semiconductor in which a crystal is mixed at least, such as a single crystal, a polycrystal, and a semi-amorphous, is called a crystalline semiconductor in the present invention). ). Then, the insulating film 104 is formed to cover the insulating film 104 by using a material such as silicon oxide, and a film is formed by using a material that can be anodized. Aluminum, tantalum, titanium, silicon, and the like, which can be anodized, are preferable as the material of the coating. In the present invention, a gate electrode having a single-layer structure using these materials alone may be used.
A gate electrode having a multilayer structure in which layers are stacked may be used. For example, it has a two-layer structure in which titanium silicide is stacked on aluminum or a two-layer structure in which aluminum is stacked on titanium nitride. The thickness of each layer may be determined by a practitioner according to the required device characteristics.

Further, a film serving as a mask in anodic oxidation is formed to cover the film, and both are simultaneously patterned and etched to form a gate electrode 105 and a mask film 106 thereon. As a material of the mask film, a photoresist used in a normal photolithography process, a photosensitive polyimide, or a material which can be etched with a normal polyimide may be used.
(Fig. 1 (A))

Next, a porous anodic oxide 107 is formed on the side surface of the gate electrode 105 by applying a current to the gate electrode 105 in an electrolytic solution. This anodizing step is performed in three steps.
The reaction is performed using an acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like of about 20%. It is desirable that the hydrogen ion concentration pH of the solution is less than 2. The optimum pH depends on the type of the electrolytic solution, but is 0.9 to 1.0 in the case of oxalic acid. In this case, 10-30
A thick anodic oxide of 0.5 μm or more can be formed at a low voltage of about V. (FIG. 1 (B))

Then, the insulating film 104 is etched by a dry etching method, a wet etching method, or the like.
This etching depth is arbitrary, and etching may be performed until the underlying active layer is exposed, or may be stopped during the etching. However, from the viewpoint of mass productivity, yield, and uniformity, it is desirable to perform etching up to the active layer. In this case, the anodic oxide 107 and the gate electrode 10
The insulating film having the original thickness is left in the insulating film (gate insulating film) below the region covered with 5. The gate electrode is mainly composed of aluminum, tantalum, and titanium.
When the insulating film 104 contains silicon oxide as a main component,
In the case of using a dry etching method, if dry etching is performed using a fluorine-based (eg, NF ₃ , SF ₆ ) etching gas, the insulating film 104 made of silicon oxide is used.
Is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 104 can be selectively etched.

In wet etching, 1
A hydrofluoric acid-based etchant such as / 100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 104 can be selectively etched. (Figure 1
(C))

Thereafter, the anodic oxide 107 is removed. As the etchant, a phosphoric acid-based solution, for example, a mixed acid of phosphoric acid, acetic acid, and nitric acid is preferable. However, for example, when a gate electrode is made of aluminum and a phosphoric acid-based etchant is used, the gate electrode is also etched at the same time. Therefore, in the present invention, by applying a current to the gate electrode in an ethylene glycol solution containing 3 to 10% of tartaric acid, boric acid, and nitric acid in the previous step, the side surface of the gate electrode and It is preferable to provide a barrier type anodic oxide 108 on the upper surface. In this anodic oxidation step, the pH of the electrolytic solution may be 2 or more, preferably 3 or more, and more preferably 6.9 to 7.1. In order to obtain such a solution, it is preferable to neutralize using an alkaline solution such as ammonia. The thickness of the anodic oxide thus obtained is determined by the magnitude of the voltage applied between the gate electrode 105 and the opposing electrode.

It should be noted that although barrier-type anodic oxidation is a later step, barrier-type anodic oxide is not formed outside the porous anodic oxide, but barrier-type anodic oxidation is performed. The object 108 is to be formed between the porous anodic oxide 107 and the gate electrode 105. In the above phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more the etching rate of the barrier anodic oxide. Therefore, since the barrier type anodic oxide 108 is not substantially etched by the phosphoric acid-based etchant, the inner gate electrode can be protected. (Fig. 1 (D), (E))

Through the above steps, it is possible to obtain a structure in which a part of the insulating film 104 (hereinafter, referred to as a gate insulating film) is selectively left under the gate electrode. Since the gate insulating film 104 ′ originally existed under the porous anodic oxide 107, not only under the gate electrode 105 and under the barrier anodic oxide 108 but also at the barrier anodic oxide 108. , And a width y thereof is characterized by being determined in a self-aligned manner. In other words, a region where the gate insulating film 104 'exists and a region where the gate insulating film 104' does not exist are formed in a self-alignment manner outside the channel formation region below the gate electrode in the active layer 103.

When ions of N-type or P-type impurities accelerated by this structure are implanted into the active layer, many ions are implanted into the region where the insulating film 104 does not exist (or is thin), and the (relatively) high ion is implanted. Concentration impurity regions (low resistance impurity regions) 110 and 113 are formed. On the other hand, in the region where the gate insulating film 104 ′ is present, ions are implanted into the gate insulating film, and only ions that have passed through the gate insulating film are implanted into the semiconductor. Low-concentration impurity regions (high-resistance impurity regions) 111;
112 is formed. Low concentration impurity regions 111, 11
The difference in impurity concentration between the second impurity region 110 and the high-concentration impurity regions 110 and 113 depends on the thickness of the insulating film 104 and the like, but is usually 0.5 to 3 digits, and the former is smaller. Further, substantially no impurity is implanted into the region below the gate electrode, and the intrinsic or substantially intrinsic state is maintained, that is, the region becomes a channel formation region. After the impurity is implanted, the impurity may be activated by irradiating it with a laser beam or a strong light equivalent thereto. However, it is needless to say that substantially one step is sufficient. (FIG. 1 (E))

As described above, the present invention is characterized in that the width of the high-resistance impurity region is controlled in a self-aligned manner by the thickness y of the anodic oxide 107. Further, the end 109 of the gate insulating film 104 ′ and the high-resistance region (HRD) 112
Can be substantially matched. In the conventional method shown in FIG. 6, it is extremely difficult to control the width of the side wall which plays such a role. However, in the present invention, the width of the anodic oxide 107 is determined by the anodic oxidation current (charge amount). Therefore, extremely delicate control is possible.

Further, as is apparent from the above-mentioned steps, even if the impurity doping step is performed substantially once, a low-resistance region and a high-resistance region can be formed. Only one process is required. Thus, in the present invention, mass productivity can be improved by reducing the steps of doping and activation. Conventionally, HRD has a problem that it is difficult to make an ohmic contact with an electrode because of its large resistance, and that the resistance lowers the drain voltage. However, on the other hand, due to the presence of the HRD, the generation of hot carriers can be suppressed and high reliability can be obtained. The present invention solves this contradictory problem at a time, and can obtain a 0.1-1 μm-wide HRD formed in a self-aligned manner and ohmic contact with the source / drain electrodes.

In the present invention, the positional relationship between the end of the gate electrode and the impurity region can be arbitrarily changed by appropriately utilizing the thickness of the anodic oxide 108 in FIG.
This example is shown in FIG. For example, in a method such as an ion doping method (also referred to as plasma doping) in which ions are implanted without being substantially separated by mass, since the angle of entry of ions varies, there is considerable spread of impurities in the lateral direction. In other words, it is expected that the spread in the horizontal direction will be as large as the addition of ions. In the following example, the active layer 4
04 is 800 mm thick.

Therefore, as shown in FIG. 4A, the thickness (for example, 800 °) of the anodic oxide 402 (corresponding to 108 in FIGS. 1 and 108) is substantially the same as that of the active layer 404 outside the metal gate electrode 401. If the thickness is almost the gate electrode 4
01 and the end 40 of the high-resistance impurity region 407.
6 do not overlap and do not separate. FIG.
The thickness of the anodic oxide 402 is, for example, 30 as shown in FIG.
In the case where the thickness is larger than 00 ° and the thickness of the active layer is 800 °, the end 405 of the gate electrode and the end 406 of the high resistance impurity region
Are offset from each other. Conversely, when the thickness of the anodic oxide 402 is reduced as shown in FIG. 4C, the gate electrode and the high-resistance impurity region overlap each other. This overlap is maximum when no anodic oxide exists around the gate electrode 401 as shown in FIG.

Generally, in an offset state, a reverse leakage current is reduced and an on / off ratio is improved. For example, a TFT (pixel TFT) used for controlling pixels of an active matrix liquid crystal display has a feature. It is suitable for applications that require low leakage current. However, the hot carriers generated at the end of the HRD are trapped by the anodic oxide,
It also has the disadvantage of deterioration.

In the overlapping state, the deterioration due to the hot carrier trap as described above is reduced, and the on-current is increased, but the leakage current is disadvantageously increased. For this reason, a TFT (driver TF) used for an application requiring a large current driving capability, for example, a peripheral circuit of a monolithic active matrix.
T) is suitable. Fig. 4 (A) shows the TFT actually used.
Which of (D) to (D) should be determined depending on the use of the TFT.

[0030]

[Embodiment 1] FIG. 1 shows this embodiment. First, a substrate (Corning 7059, 300 mm × 400 m
A silicon oxide film having a thickness of 1000 to 3000 ° was formed as a base oxide film 102 on the (m or 100 mm × 100 mm) 101. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, a film in which TEOS is decomposed and deposited by a plasma CVD method may be used.

Thereafter, an amorphous silicon film is deposited in a thickness of 300 to 5000 °, preferably 500 to 1000 ° by a plasma CVD method or an LPCVD method.
The crystals were left to stand in a reducing atmosphere at 24 ° C. for 24 hours for crystallization.
This step may be performed by laser irradiation.
Then, the silicon film crystallized in this manner was patterned to form the island-like region 103. Further, a silicon oxide film 104 having a thickness of 700 to 1500 ° was formed thereon by sputtering.

Thereafter, aluminum having a thickness of 1000 to 3 μm (1 wt% of Si or 0.1 to 0.3 wt.
% Of Sc (scandium) film was formed by electron beam evaporation or sputtering. Then, a photoresist (for example, OFPR800 / 3 manufactured by Tokyo Ohka)
0 cp) by spin coating. Before the formation of the photoresist, a thickness of 100 to 1
If an aluminum oxide film of 2,000 mm is formed on the surface, adhesion to the photoresist is good, and current leakage from the photoresist is suppressed, so that a porous anodic oxide can be formed in the subsequent anodic oxidation step. Was effective in forming only on the side surface. Thereafter, the photoresist and the aluminum film are patterned and etched together with the aluminum film to form a gate electrode 105 and a mask film 10.
6. (Fig. 1 (A))

Further, anodization is performed by passing an electric current through the electrolytic solution to a thickness of 3000 to 6000 °, for example, a thickness of 50
An anodic oxide 107 of 00 ° was formed. Anodizing is 3
Using an aqueous acidic solution such as citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
A constant current of V may be applied to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.) having a pH of 0.9 to 1.0, and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (FIG. 1 (B))

Thereafter, the silicon oxide film 104 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. For example, if CF ₄ is used as an etching gas, the anodic oxide is not etched, and only the silicon oxide film 104 is etched. Also,
The silicon oxide film 104 'under the porous anodic oxide 107 remained without being etched. (Fig. 1 (C))

Next, a current was again applied to the gate electrode in the electrolytic solution. This time, an ethylene glycol ammonia solution having a pH of 6.9 to 7.1 containing a tartar liquid of 3 to 10%, boric acid, and nitric acid was used. Solution temperature is 10 ° C
A better oxide film was obtained when the temperature was lower than the room temperature before and after. As a result, a barrier-type anodic oxide 108 was formed on the upper and side surfaces of the gate electrode. The thickness of the anodic oxide 108 was proportional to the applied voltage, and an applied voltage of 150 V formed an anodic oxide of 2000 °. The thickness of the anodic oxide 108 is shown in FIG.
Is determined by the required offset and the size of the overlap as shown in the above, but a high voltage of 250 V or more is required to obtain an anodic oxide having a thickness of 3000 mm or more, which adversely affects the characteristics of the TFT. 3000 yen
Preferably, the thickness is as follows. In this embodiment, 80 to
The voltage was increased to 150 V, and the voltage was selected according to the required thickness of the anodic oxide film 108. (Fig. 1 (D))

Thereafter, the anodic oxide 107 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 107 was etched, and the etching rate was about 600 ° / min. The gate insulating film 104 'thereunder remained as it was. Then, impurities are implanted in a self-aligned manner into the active layer 103 of the TFT by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) and the gate insulating film as a mask by an ion doping method. Source / drain region) 11
0, 113 and high resistance impurity regions 111, 112 were formed. Since phosphine (PH ₃ ) was used as the doping gas, an N-type impurity region was formed. Diborane (B ₂ H ₆ ) may be used as a doping gas to form a P-type impurity region. The dose is 5 × 10 ^{14 to} 5 ×
10 ¹⁵ cm ^-2 and the acceleration energy were 10 to 30 keV. Thereafter, a KrF excimer laser (wavelength 248 n)
m, a pulse width of 20 nsec) to activate the impurity ions introduced into the active layer.

Results of SIMS (Secondary Ion Mass Spectrometry)
According to this, the impurity concentration of the regions 110 and 113 is 1 × 10
²⁰~ 2 × 10^{twenty one}cm^-3, 1 × 1 in the regions 111 and 112
0¹⁷~ 2 × 10¹⁸cm^-3Met. In dose conversion,
The former is 5 × 10¹⁴~ 5 × 10 ^Fifteencm^-2The latter is 2 × 10
¹³~ 5 × 10¹⁴cm^-2Met. This difference is gate insulation
This is caused by the presence or absence of the film 104 '.
Generally, the impurity concentration in the low resistance irregular region is high resistance.
It is 0.5 to 3 orders of magnitude larger than that of the impurity region. (Figure 1
(E))

Finally, an interlayer insulator 114 is formed on the entire surface.
A silicon oxide film having a thickness of 3000 was formed by the CVD method. Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 115 and 116 were formed. Further, hydrogen annealing was performed at 200 to 400 ° C. Thus, the TFT was completed. (Figure 1
(F))

FIG. 5A shows an example in which a plurality of TFTs are formed on one substrate by using the method shown in FIG. In this example, three TFTs 1 to 3 were formed. TFT
1 and 2 are used as driver TFTs, and oxides 501 corresponding to the anodic oxide 108 in FIG.
The thickness of the gate electrode 502 and the high resistance region (HR) are slightly reduced to a thickness of 200 to 1000 °, for example, 500 °.
D) overlapped. In the figure, TF
Connecting the drain of T1 and the source of TFT2 to each other,
In addition, an example is shown in which the source of the TFT 1 is grounded and the drain of the TFT 2 is connected to a power source to form a CMOS inverter. There are various other circuits as the peripheral circuit, and such a CMOS circuit may be used according to the specifications of each.

On the other hand, the TFT 3 is used as a pixel TFT. The thickness of the anodic oxide 503 is increased to 2000.degree. To set an offset state (corresponding to FIG. 4B) to suppress a leak current. One of the source / drain electrodes of the TFT 3 is connected to the pixel electrode 501 of ITO. To change the thickness of the anodic oxide in this way, it is necessary to use the
What is necessary is just to separate so that the voltage of the T gate electrode can be controlled independently. Note that TFT1 and TFT3 are N-channel TFTs, and TFT2 is a P-channel TFT.

Embodiment 2 FIG. 2 shows this embodiment. First, a substrate having an insulating surface (for example, Corning 705)
9) Using the steps (A) to (C) of Example 1 on the base 201, the base oxide film 202, the island-like silicon semiconductor region (for example, crystalline silicon semiconductor) 203, the gate insulating film 204, and the aluminum film ( A gate electrode 205 having a thickness of 2000 to 1 .mu.m) and a porous anodic oxide (thickness of 3000 to 1 .mu.m, for example, 5000 .mu.m) 206 are formed on side surfaces of the gate electrode. (FIG. 2 (A)) Then, similarly to the first embodiment, the thickness of the barrier mold is 1000-2.
A 500 ° anodic oxide 207 was formed. (Figure 2
(B))

Further, using the barrier type anodic oxide film 207 as a mask, the porous anodic oxide film 206 was removed by etching. Thereafter, impurities are implanted by ion doping using the gate electrode portions (205, 207) and the gate insulating film 204 as a mask, and the low-resistance impurity region 20 is formed.
8, 211 and high-resistance impurity regions 209 and 210 were formed. The dose is 1-5 × 10 ¹⁴ cm ^-2 , and the acceleration voltage is 30
９０90 kV. Phosphorus was used as an impurity. (Figure 2
(C))

Further, a coating of an appropriate metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 212 having a thickness of 50 to 500.degree. As a result, the metal film (here, titanium film) 212 was formed in close contact with the low-resistance impurity regions 208 and 211. (Figure 2
(D))

Then, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) is irradiated to activate the doped impurities and cause a metal film (here, titanium) to react with silicon of the active layer, thereby forming a metal silicide ( Here, regions 213 and 214 of (titanium silicide) were formed.
Laser energy density is 200-400mJ / cm
² , preferably 250 to 300 mJ / cm ² . When the laser is irradiated, the substrate is 200 to 500
By heating to ℃, the peeling of the titanium film could be suppressed.

In this embodiment, an excimer laser is used as described above, but it goes without saying that another laser may be used. However, when using a laser, a pulsed laser is preferred. In the case of a continuous wave laser, the irradiation time is long, and there is a risk that an object to be irradiated is separated by expansion due to heat.

As for the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switched pulse oscillation) and its visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl, and ArF can be used. However, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

The annealing may be performed by lamp annealing by irradiation of visible light or near infrared light.
When lamp annealing is performed, the surface to be irradiated is 600
The lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the temperature becomes about 1000 ° C. Annealing with near-infrared rays (for example, 1.2 μm infrared rays) selectively absorbs near-infrared rays into silicon semiconductors and does not heat the glass substrate so much. It can be suppressed and is extremely useful.

Thereafter, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film (for example, the titanium film existing on the gate insulating film 204 and the anodic oxide film 207) other than the portion in contact with the exposed active layer remains in a metal state as it is, but can be removed by this etching. On the other hand, titanium silicides 213 and 214, which are metal silicides, are not etched and can be left. (FIG. 2 (E))

Finally, as shown in FIG. 2 (F), a silicon oxide film having a thickness of 2000-1 μm, for example 3000 μm, is formed on the entire surface as an interlayer insulator 217 by a CVD method, and contact is made with the source / drain of the TFT. A hole is formed and aluminum wiring / electrodes 218 and 219 are
It was formed to a thickness of 0-1 μm, for example, 5000 °. In the present embodiment, the portion contacted by the aluminum wiring is titanium silicide, and the stability of the interface with aluminum is better than that of silicon, so that a highly reliable contact was obtained. The aluminum electrode 21
8 and 219 and the silicide regions 213 and 214, for example, titanium nitride is further formed as a barrier metal.
Reliability can be improved. In this example, the sheet resistance in the silicide region was 10 to 50 Ω / □. On the other hand, in the high-resistance impurity regions 209 and 210, 10 to 100
kΩ / □, resulting in good frequency characteristics and
TF with little hot carrier degradation even at high drain voltage
T could be produced.

In the present embodiment, the low-resistance impurity region 211 and the metal silicide region can be substantially matched. In particular, the end 215 of the gate insulating film 204 and the high-resistance impurity region 2
10 and the boundary 216 between the low-resistance impurity region 211 and the end portion 215 and the metal silicide region 214 at the same time.
4 (A) to 4 (D) as a result of substantially matching the end portions of FIG.
It is clear that the low-resistance impurity region in the above may be replaced with a metal silicide region.

FIG. 5B shows an example in which a plurality of TFTs are formed on one substrate by using the technique shown in FIG. In this example, three TFTs 1 to 3 were formed. TFT
1 and 2 are CMOS-structured driver TFTs, here used as inverter structures.
The thickness of the oxides 505 and 506 corresponding to the anodic oxide 207 was made as thin as 200 to 1000 Å, for example, 500 Å so as to slightly overlap each other. on the other hand,
The TFT 3 is used as a pixel TFT. The thickness of the anodic oxide 503 was increased to 2000 ° to set an offset state, thereby suppressing a leak current. One of the source / drain electrodes of the TFT 3 is connected to the pixel electrode 502 of ITO. In order to change the thickness of the anodic oxide in this manner, it is sufficient to separate the anodic oxide so that the voltage of the gate electrode of each TFT can be controlled independently. Note that TFT1 and TF
T3 is an N-channel type TFT, TFT2 is a P-channel type T
FT.

In this embodiment, the step of forming a titanium film is provided after the step of ion doping, but the order may be reversed. In this case, since the titanium film covers the entire surface at the time of ion irradiation, the effect is large in preventing abnormal charging (charge-up) which has become a problem in the insulating substrate. After the ion doping, annealing may be performed by a laser or the like, and then a titanium film may be formed. Then, titanium silicide may be formed by irradiation with a laser or the like or thermal annealing.

Embodiment 3 FIG. 3 shows this embodiment. First, a base oxide film 302, an island-shaped crystalline semiconductor region such as a silicon semiconductor region 303, a gate insulating film 304, and the like are formed on a substrate (Corning 7059) 301 by using the steps (A) to (C) of the first embodiment. Aluminum film (thickness 2000mm ~
A gate electrode 305 (1 μm) and a porous anodic oxide (thickness 6000 °) 306 were formed on the side surfaces of the gate electrode 305. (FIG. 3 (A)) Then, similarly to the first embodiment, the thickness of the barrier mold is 1000-2.
A 500 ° anodic oxide 307 was formed. (FIG. 3
(B))

Further, the porous anodic oxide 306 was selectively etched to expose a part of the gate insulating film 304. Then, a suitable metal, for example, a thickness of 50
A titanium film 308 of about 500 ° was formed on the entire surface by sputtering. (FIG. 3 (C)) Then, a KrF excimer laser (wavelength 248 nm,
Irradiation was performed with a pulse width of 20 nsec) to react titanium with silicon in the active layer, thereby forming titanium silicide regions 309 and 310. Laser energy density is 200-400mJ
/ Cm ² , preferably 250 to 300 mJ / cm ² . When irradiating the laser, the substrate is 200 ~
By heating to 500 ° C., the peeling of the titanium film could be suppressed. This step may be performed by lamp annealing by irradiation with visible light or near infrared light.

Thereafter, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film (for example, the titanium film existing on the gate insulating film 304 and the anodic oxide film 307) other than the portion in contact with the exposed active layer remains in a metal state as it is, but can be removed by this etching. On the other hand, titanium silicide 3
Since 09 and 310 are not etched, they can be left. (FIG. 3 (D))

Thereafter, impurities are implanted by an ion doping method using the gate electrode portion and the gate insulating film 304 as a mask to form low-resistance impurity regions (≒ titanium silicide regions) 311, 314 and high-resistance impurity regions 312, 313.
Was formed. The dose amount was 1 to 5 × 10 ¹⁴ cm ⁻² , and the acceleration voltage was 30 to 90 kV. Phosphorus was used as an impurity. (FIG. 3 (E))

Then, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated again to activate the doped impurities. This step may be performed by lamp annealing by irradiation with visible light or near infrared light. Finally, the gate insulating film 304 is formed using the gate electrode portions (305, 307) as a mask.
Was etched. This was performed to avoid instability due to impurities doped in the gate insulating film 304. As a result, the gate insulating film 304 'remained only under the gate electrode.

Then, as shown in FIG. 3 (F), a silicon oxide film having a thickness of 600 nm is formed on the entire surface as an interlayer insulator 315 by a CVD method, contact holes are formed in the source / drain of the TFT, and an aluminum wiring is formed.・ Electrode 3
16, 317 were formed. Through the above steps, the TFT
Was completed.

[0059]

According to the present invention, a high-resistance impurity region (HRD) can be formed by substantially one doping, one laser annealing, and an activation process such as RTA. The shortening of this process enhances mass productivity, and TF
This is effective in reducing the amount of investment in the T production line.
Further, in the present invention, since the width of the HRD is formed with extremely high precision, a TFT having excellent yield and uniformity can be obtained.

In the present invention, in order to further improve the characteristics, more doping, laser annealing and RTA may be performed, and the number of times of doping, laser annealing and RTA is necessarily limited to one. Not something. It is needless to say that the TFT of the present invention is formed in the same manner when a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed, or when formed on glass or an organic resin. Are formed on the insulating surface in any case. In particular, the effect of the present invention is remarkable for an electro-optical device such as a monolithic active matrix circuit having peripheral circuits on the same substrate.

In the present invention, in addition to ion implantation or ion doping of P or N type impurities, carbon,
Oxygen and nitrogen may be added simultaneously. Thus, the reverse leakage current is reduced, and the withstand voltage is improved. For example, it is effective when used as a pixel TFT of an active matrix circuit. In this case, the thickness of the anodic oxide layer of TFT3 in FIG. 5 can be made the same as that of TFT1 and TFT2.

[Brief description of the drawings]

FIG. 1 shows a method for manufacturing a TFT according to Example 1.

FIG. 2 shows a method for manufacturing a TFT according to a second embodiment.

FIG. 3 shows a method for manufacturing a TFT according to a third embodiment.

FIG. 4 shows the relationship between offset and overlap in the present invention.

FIG. 5 shows an example of a TFT integrated circuit obtained by Examples 1 and 2.

FIG. 6 shows a method for manufacturing a TFT according to a conventional method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Insulating substrate 102 Base oxide film (silicon oxide) 103 Active layer (crystalline silicon) 104 Insulating film (silicon oxide) 104 'Gate insulating film 105 Gate electrode (aluminum) 106 Mask film (photoresist) 107 Anodic oxide (porous) Aluminum oxide) 108 anodic oxide (barrier type aluminum oxide) 109 edge of gate insulating film 110, 113 low resistance impurity region 111, 112 high resistance impurity region (HRD) 114 interlayer insulating film (silicon oxide) 115, 116 metal wiring -Electrode (aluminum) 117 Boundary between low-resistance impurity region and high-resistance impurity region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H01L 27/092 H01L 29/78 612B 29/786 613A 27/08 321D (72) Inventor Hideto Onuma Kanagawa 398 Hase, Atsugi-shi, Japan Semi-Conductor Energy Laboratory Co., Ltd. (72) Inventor Naoaki Yamaguchi 398, Hase, Atsugi-shi, Kanagawa Prefecture Inside Semi-Conductor Energy Laboratory Co., Ltd. Inside the Conductor Energy Laboratory (72) Inventor Hideki Uojichi 398 Hase, Atsugi-shi, Kanagawa Prefecture Inside Semi-Conductor Energy Laboratory Co., Ltd. (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Prefecture Half Semiconductor Energy Laboratory F-term Reference) 2H092 GA59 JA25 JA34 JA37 JA41 JA46 KA04 KA05 KA10 KA12 KA18 KB25 MA05 MA07 MA08 MA15 MA18 MA24 MA26 MA27 MA30 NA22 NA24 NA27 NA29 5F048 AB10 AC04 BA16 BB09 BC06 BE08 BG07 5F110 AA16 BB02 BB04 BB10 BB11 CC02 DD01 DD02 DD05 DD13 EE01 EE03 EE04 EE12 EE14 GG14 EE12 GG25 GG35 GG45 GG47 HJ01 HJ02 HJ04 HJ12 HJ13 HJ23 HK05 HK33 HK40 HL01 HL03 HL11 HM14 HM15 NN04 NN23 NN35 NN78 PP01 PP03 PP10 PP13 QQ11 QQ24

Claims (6)

[Claims] A semiconductor device including an inverter having an n-channel thin film transistor and a p-channel thin film transistor and a pixel portion having the thin film transistor on the same substrate, wherein the n-channel thin film transistor of the inverter circuit;
The thin film transistor of the pixel portion includes a gate electrode, a gate insulating film, and a semiconductor film provided with a channel formation region, a high-resistance impurity region, and a low-resistance impurity region. The gate electrode of the N-channel thin film transistor of the inverter Partially overlaps with the high-resistance impurity region via the gate insulating film, and a gate electrode of the thin film transistor in the pixel portion does not overlap with the high-resistance impurity region through the gate insulating film. Semiconductor device. 2. A semiconductor device comprising: an inverter having an N-channel thin film transistor and a P-channel thin film transistor; and a pixel portion having the thin film transistor on the same substrate;
The thin film transistor of the pixel portion includes a gate electrode, a gate insulating film, and a semiconductor film provided with a channel formation region, a high-resistance impurity region, and a low-resistance impurity region. The gate electrode of the N-channel thin film transistor of the inverter Partially overlaps with the high-resistance impurity region via the gate insulating film, and an end of a gate electrode of the thin film transistor in the pixel portion,
A semiconductor device, which is in agreement with an end of the high-resistance impurity region via the gate insulating film. 3. A semiconductor device comprising: an inverter having an N-channel thin film transistor and a P-channel thin film transistor; and a pixel portion having the thin film transistor on the same substrate, wherein the N-channel thin film transistor of the inverter circuit is provided.
The thin film transistor of the pixel portion includes a gate electrode, a gate insulating film, and a semiconductor film provided with a channel formation region, a high-resistance impurity region, and a low-resistance impurity region. The gate electrode of the N-channel thin film transistor of the inverter The gate electrode partially overlaps with the high-resistance impurity region via the gate insulating film, and the gate electrode of the thin film transistor in the pixel portion is offset from the high-resistance impurity region via the gate insulating film. Characteristic semiconductor device. 4. The N-channel thin film transistor of the inverter circuit, wherein the low-resistance impurity region is 1 × 10 ²⁰
Contain phosphorus in a concentration of ~2 × 10 ²¹ cm ^-3, the high-resistance impurity ^{regions, 1 × 10 17 ~2 × 10} 18 cm -3 concentration of claims 1 to 3, characterized in that it comprises a phosphorus The semiconductor device according to claim 1. 5. The thin film transistor of the pixel portion is an n-channel thin film transistor, wherein the low resistance impurity region contains phosphorus at a concentration of 1 × 10 ²⁰ to 2 × 10 ²¹ cm ⁻³ , and the high resistance impurity region Is 1 × 10 ¹⁷ to 2 × 10 ¹⁸ cm
^5. The semiconductor device according to claim 1, further comprising phosphorus at a concentration of ^-3 . 6. The transistor according to claim 1, wherein the N-channel thin film transistor and the P-channel thin film transistor of the inverter and the thin film transistor of the pixel portion have a channel formation region formed of a crystalline silicon film. 13. The semiconductor device according to item 9.