JPS5837967A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short-circuit of channel by forming the source and drain electrodes deeply in the area near to the gate electrode or shallowly in the area far from it. CONSTITUTION:The field oxide film 3, silicon oxide film 4 and gate electrode 5 are formed on the silicon substrate 1. Then, the SiO2 film is deposited. Thereafter, the SiO2 film 6 is left only at the side end part of electrode 5 by the etching. The gate oxide film 7 is formed by etching the film 4. Next, the arsenic ion is implanted to the substrate 1. At this time, since the film 7 controls the depth of implantation, the arsenic ion is implanted shallowly at the area near to the electrode 5 but deeply at the area isolated far from the electrode. Thereafter, the thermal processing for activation is carrier out in order to form the source and drain regions 8, 9.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a manufacturing method for MIB type semiconductor devices.

Conventionally, MOa type semiconductor devices have been manufactured by the method described below. First, a first conductivity type semiconductor substrate is selectively oxidized to form a field oxide film for electrically isolating a portion where an element region is to be formed. Next, after forming a silicon oxide film in the area where the element region is to be formed, a silicon oxide film is formed on the silicon oxide film. -) selectively forming electrodes;

Subsequently, the silicon oxide film is etched away using the f-) electrode as a mask to form an r-) oxide film, and after that, impurities of the second conductivity type are added using the f-) electrode and the filled oxide film as a mask. A MOB type semiconductor device is manufactured by ion-implanting and performing activation heat treatment to form source and drain regions.

In the above manufacturing method, MO
In order to miniaturize 8-type semiconductor devices, K reduces the diffusion depth of impurities in the source and drain regions and increases the channel depth.
It is necessary to prevent this. Note that the sheeting of the channel causes a decrease in threshold voltage and a decrease in drain breakdown voltage. However, if the impurity diffusion depth is made too shallow, the resistance of the source and drain regions increases as well as the contact resistance with the source and drain lead electrodes, which impedes high-speed operation of the device.

The present invention has been made to eliminate the above-mentioned drawbacks, and in the source and drain regions, ? −) Reduce the diffusion depth of impurities near the electrode.

Manufacture of a MIS type semiconductor device that prevents channel shift by increasing the diffusion depth of impurities in the region away from the r-gate electrode and reduces the resistance of the source and drain regions. It is intended to provide a method.

That is, in the first invention of the present application, a semiconductor substrate of a first conductivity type is formed on a semiconductor substrate with an insulating film interposed therebetween. -) forming an electrode, at least f-) depositing a film having selective etching properties with respect to the r-) electrode around the electrode, and anisotropically etching this film to form an r-t electrode. a step of leaving a film on the side edges; a step of etching away the insulating film using the remaining film and the r-) electrode as a mask; and after removing the remaining film, impurities of a second conductivity type are added to the substrate. The method is characterized by comprising a step of implanting ions.

Further, the second invention of the present application includes a step of forming a y-t electrode on a semiconductor substrate of a first conductivity type via an insulating film, and a selective etching property for the dirt electrode at least around the r-) electrode. a step of anisotropically etching the film to leave the film on the side edges of the r-) electrode, and then ion-implanting impurities of a second conductivity type into the substrate; The method is characterized by comprising the step of, after removing the remaining film, ion-implanting impurities of a second conductivity type into the substrate again to a shallower depth than the first ion-implantation.

Materials for the r-) electrode used in the present invention include, for example, polycrystalline silicon, aluminum, molybdenum,
Examples include high melting point metals such as tungsten, metal silicides such as molybdenum silicide, and tungsten silicide.

Examples of the coating used in the present invention include CVD
- Insulating coating such as 5io2 film, silicon nitride film, or A
Any material may be used as long as it has selective etching properties with respect to T, Kt alloys, and other metal gate electrodes.

The remaining film formed by the invention of ts1 of the present application acts as a mask when etching the insulating film on the semiconductor substrate.

After such etching, an insulating film for controlling the depth of impurity ion implantation remains around the r-) electrode.

Further, the residual film formed in the second invention of the present application serves to prevent impurity ions from being implanted into the substrate around the gate electrode during the first impurity ion implantation.

Therefore, in the second impurity ion implantation after removing the remaining film, it is possible to implant impurity ions into the substrate around the r-) electrode, so it is necessary to control the conditions for the second ion implantation. Accordingly, the depth of the impurity region formed in the substrate around the electrode can be freely adjusted.

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 (1) First, field oxidation [5] was formed on a p-type silicon substrate 1 by selective oxidation to electrically isolate a portion 2 where an element region was to be formed. Next, thermal oxidation treatment is applied,
Silicon oxide M is formed on the exposed element region formation portion 2.
After growing the silicon oxide film 4, for example, polycrystalline silicon is deposited on the entire surface and then turned to selectively form a c-to electrode 5 on the silicon oxide film 4 (as shown in FIG. 1(a)).

(11) Next, the entire surface of the C■ method is Vcsio2. After 6tllll of films were deposited (as shown in Fig. 1(b)), they were placed in a reactive ion etching atmosphere and etched with 5to2II.
Anisotropic etching should be carried out to a film thickness of 6 or slightly more.
O2e;' was left (as shown in FIG. 1 (@)), and then the silicon oxide film A was etched using the remaining SIOg' and r-) electrodes 5 as a mask. - A oxide film 7 was formed (as shown in FIG. 1(d)). .

(iii) Next, after removing the remaining 81026',
Arsenic ions were implanted into a silicon substrate 1 as an n-type impurity. At this time, the r-) oxide gv is formed wider than the width of the r-) electrode 50, and this portion suppresses the depth of ion implantation into the silicon substrate 1. -) Arsenic is introduced deeply into a portion of the silicon substrate near the electrode 5 and deeply into a portion of the silicon substrate remote from the r-meter electrode 5 (as shown in FIG. 1).

Ov) Next, activation heat treatment was performed to form r-type source and drain regions 8.9 that were shallow in the vicinity of the r-) electrode 5 and deep in the portions away from the r-) electrode 5 (see Fig. 1 (f).
). Next, according to the usual method, the entire surface is K CVD −
After depositing the 8102 film, contact holes were formed by photoetching.

Subsequently, an At electrode was formed, and an n-channel MO8 type semiconductor device was manufactured.

However, according to the present invention? -) By forming a remaining portion 81026' at the side end of the electrode 5 and etching the silicon oxide film 1 using this remaining portion 81026' and the dirt electrode 5 as a mask, the width of the r-meter electrode 5 can be increased. −)
An oxide film 7 can be formed.

As a result, after removing the remaining 8102#', a single arsenic ion implantation is performed. -) It is shallow near the electrode 5, and the search source is shallow in the part far from the r-meter electrode 5.
Drain regions 8 and 9 can be formed. Therefore, it is possible to prevent the channel from becoming distorted and to reduce the resistance of the source and drain regions. Therefore, it is possible to obtain an n-channel MO8 type semiconductor device which can prevent a decrease in threshold voltage and drain breakdown voltage due to channel sheeting and can operate at high speed.

Example 2 (1) After leaving the side end K 191026' of the r-meter electrode 5 in the same manner as in Example 1,! Arsenic was ion-implanted as a type 1 impurity into the silicon substrate at high power and dose (as shown in FIG. 2(a)).

(11) Next, after removing the remaining 5IO26', arsenic was ion-implanted again into the silicon substrate at a low power and low dose similar to the first ion implantation (see Figure 2).
b) As shown).

(++i) Next, an activation heat treatment was performed to form n1 type source and drain regions 8.9 which were shallow near the dirt electrode 5 and deep in a portion away from the dirt electrode 5 (second
Figure(,)Illustrated). Furthermore, the silicon oxide film 4 was etched using the r-) electrode 5 as a mask to form an r-) oxide film. Next, apply CVD -5jO to the entire surface according to the usual method.
A contact hole was formed by photo-etching a bale stacked with j # of two turns. Continuing to form At electrodes,
An n-channel MO8 type semiconductor device was manufactured.

According to the present invention, after the residual 8102' is formed at the side end of the date electrode 5, arsenic is ion-implanted into the silicon substrate 1 at high power and dose.
After removing 6', arsenic is ion-implanted into the silicon substrate l again at a lower power and a lower dose than the first ion implantation. -) Shallow near electrode 5, y-
Deep source and drain regions 8 and 9 can be formed in portions away from the meter electrode 5. Therefore, the channel can be prevented from becoming a sheet, and the resistance of the source and drain regions 8 and 9 can be reduced. Therefore, it is possible to obtain an n-channel MOa type semiconductor device which can prevent a decrease in threshold voltage and a decrease in drain withstand voltage due to the formation of a channel and which can operate at high speed.

Furthermore, according to the method of Example 2, Kl
'-) Without using the silicon oxide film 4 remaining around the electrode 5 as a control film for ion implantation, the remaining 810
．． The second ion implantation after removal of 6' results in r-
) To control the depth of the source and drain regions 8°9 in the silicon substrate 1 around the electrodes 5,
The depth of the source and drain regions 8 and 9 around the r-meter electrode 5 is not restricted by the thickness of the silicon oxide film 4, and shallow source and drain regions can be formed, allowing a greater degree of freedom in device design. Become.

Note that the method of the present invention is applicable to n-channel MOa as in the above embodiment.
The present invention can be applied not only to manufacturing of type semiconductor devices, but also to manufacturing of other MIS type semiconductor devices such as p-channel MO8 type semiconductor devices, 0MO8, MNOS, MAO8, etc.

As described in detail above, according to the present invention, on the surface of a semiconductor substrate, source and drain regions can be formed that are shallow near the r-) electrode and deep in a portion away from the f-) electrode, so that the device can be miniaturized. It is possible to prevent the channel from becoming sheet-like even in the case of high-speed operation, and to achieve low resistance in the source and drain regions, resulting in high reliability and high speed operation.
This makes it possible to provide an S-type semiconductor device.

[Brief explanation of the drawing]

FIG. 1(,) to (f) are MO in Example 1 of the present invention.
FIG. 2 is a process cross-sectional view showing a method for manufacturing an 8-type semiconductor device
, ) to (c) are process cross-sectional views showing a method of manufacturing a MOI9 type semiconductor device in Example 2 of the present invention. 1... Silicon substrate, 3... Field oxide film, 4
...Silicon oxide film, 5...? -) electrode, 6...
5io2 film, el, .Remaining 8102.7-r-) oxide film, 8.9...n1 type source and drain region. Idemaro's agent Patent attorney Takeshi Suzue Hikoga 1 Figure 1 A

Claims (1)

[Claims] 1 f-) on a first conductivity type semiconductor substrate via an insulating film.
A step of forming an electrode, and at least r-) electrode surrounding Kt.
a step of depositing a film having selective etching properties on the l''-upper electrode, and anisotropically etching this film to form an r-
) The process of leaving a coating on the side edges of the electrode, and the remaining coating on the edges and the -) a step of etching away the insulating film using the electrode as a mask, and a second step after removing the remaining film;
A method for manufacturing an MIS type semiconductor device, comprising the step of ion-implanting a conductive type impurity into the substrate. 2. A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via an insulating film, and at least? -) A famous process of depositing a film having selective etching properties with respect to the y-top electrode around the electrode, and anisotropic etching of this film to leave the film on the side edges of the r-top electrode. , a step of ion-implanting a second conductivity type impurity into the substrate, and a step of ion-implanting the second conductivity type impurity into the substrate again at a shallower depth than the first ion implantation after removing the residual film. A method for manufacturing an MIS type semiconductor device, characterized by comprising: