JPH07153971A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent a deterioration due to hot carriers by a method wherein a pair of low resistance impurity regions is provided outside a pair of high resistance regions, and a nitride silicon film capturing positive electric charges is formed on the high resistance region, and an oxide silicon film is formed on the film. CONSTITUTION:By an ion doping method, with the use of a gate electrode part and a gate insulation film as masks, phosphorus ions being N-type impurity ions are implanted in a self-aligned manner into an active layer of TFT to apply an acceleration voltage thereto. A pair of high resistance regions 111, 112 is formed by this applying and a pair of low-resistance regions 110, 113 is formed outside it. Next, by a plasma CVD method, a nitride silicon film 114 is formed over the entire surface and laser beams are emitted thereon to activate impurity ions. Finally, an oxide silicon film is formed as an interlayer insulator 115 to form electrodes 116, 117. Thus, effects of negative electric charges generated by hot carriers can be cancelled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an insulating material such as glass,
Alternatively, the present invention relates to an insulating gate type transistor (TFT) formed on an insulating surface such as a material obtained by forming an insulating film such as silicon oxide on a silicon wafer and used at a relatively high voltage, and a manufacturing method thereof. The present invention particularly relates to N-channel TFTs. Further, the present invention is particularly effective for a TFT formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or lower. The semiconductor device according to the present invention is used in an active matrix such as a liquid crystal display, a drive circuit such as an image sensor, or a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a TF has been used for the purpose of driving an active matrix type liquid crystal display device or an image sensor.
T (thin film transistor) is widely used. In particular,
Recently, because of the need for high-speed operation, a crystalline silicon TFT having higher electric field mobility has been developed in place of the amorphous silicon TFT using amorphous silicon in the active layer. However, when higher characteristics and durability against driving at a high voltage are required, it is necessary to have a high resistance region. Hereinafter, in the present invention, a high resistance region is referred to as a high resistance impurity region (high resistance drain (HR
D) or a low-concentration drain (LDD) as well as a portion where the gate electrode and the impurity region do not overlap each other (that is, an offset region).

[0003]

However, in such a structure, particularly in the N-channel TFT, the negative charges generated by the hot carriers are trapped in the gate insulating film on the drain side. The conductivity type of the high resistance region is weak P type, and the current between the source and the drain is blocked.

Further, the step of forming such a high resistance region must rely on a photolithography method, and it is difficult to form the high resistance region in a self-aligned manner at the end of the gate electrode. The yield and the uniformity of characteristics of the obtained TFT were not good. The present invention has been made in view of such a problem, prevents deterioration due to hot carriers, and self-aligns the high resistance region.
Formation of the TFT, that is, by forming the region without using a photolithography process, the yield and the uniformity of the characteristics of the TFT are improved.

[0005]

According to the present invention, a positive charge such as silicon nitride having a thickness of 200 to 2000 Å is formed on a high resistance region or on a gate insulating film (silicon oxide) formed on the high resistance region. A film capable of trapping (capturing) is provided.
Since positive charges will be trapped in the film,
The high resistance region thereunder becomes a weak N type or cancels out negative charges, and as a result, deterioration due to hot carriers can be suppressed. That is, a high voltage is applied between the drain and the gate, for example, +15 V is applied to the drain, and
Even when 20 V is applied, of the charges generated by impact ionization, if the silicon oxide film does not exist on the high resistance region, the negative charges are not trapped and the silicon oxide film exists. Even if the negative charges are trapped therein, the effect of the negative charges is canceled out by the presence of the coating film that traps the positive charges, and the high resistance region does not become P-type. Therefore, high reliability can be obtained.

FIG. 4 shows the positional relationship between such a film for trapping (capturing) positive charges and the gate insulating film. In the figure, 1, 11, 21, and 31 are sources, and 5, 1
5, 25 and 35 are drains. Also, 2, 4, 1
2, 14, 22, 24, 32 and 34 are high resistance regions, and 3, 13, 23 and 33 are channel forming regions.
Gate insulating films 6, 16, and 2 are formed on these semiconductor active layers.
There are 6, 36. Gate electrodes 7, 17, 27 and 37 are provided so as to cover the gate insulating film. The gate electrode is covered with anodic oxide layers 7 ', 17', 27 ', 37' on its top and side surfaces. Then, interlayer insulators 8, 18, 28, 38 are formed so as to cover these, source electrodes 9, 19, 29, 39, drain electrodes 10, 2
0, 30, and 40 are formed. The coatings 8 ', 18', 28 ', 38' for trapping positive charges are provided between the interlayer insulator and the gate electrode. Then, the following four patterns can be considered in relation to the gate insulating film.

First, as shown in FIG. 4A, a gate insulating film 6 covers the source region 1 and the drain region 5, and a film 8'is formed thereon. The second is FIG.
As shown in (B), this is an example in which the gate insulating film 16 substantially covers the high resistance regions 12 and 14 and the channel forming region 13. Third, as shown in FIG. 4C, the gate insulating film 26 substantially covers only the channel forming region 23. The fourth is a modification of FIGS. 4 (A) and 4 (B).
As shown in FIG. 4D, the gate insulating film 36 is formed thinner except for the portion below the gate electrode (that is, the portion above the channel formation region 33).

According to the present invention, when the high resistance region is formed in a self-aligning manner as described above, an oxide layer formed by means such as anodic oxidation of the gate electrode is positively used to self-align. It is characterized in that a high resistance region is formed. The thickness of anodized oxide can be precisely controlled, and the thickness of anodic oxide is wide and uniform, from thin ones of 1000 Å or less to thick ones of 5000 Å or more (for example, 1 μm). Therefore, from the viewpoint of increasing the flexibility of the width of the high resistance region and adopting the self-alignment process, it is preferable to reduce the variation in the width.

In particular, the so-called barrier type anodic oxide is not etched unless it is a hydrofluoric acid type etchant, whereas the porous type anodic oxide is selectively etched by an etchant such as phosphoric acid. Therefore, the TFT
It is characterized in that it can be processed without giving any damage (damage) to other materials constituting, for example, silicon and silicon oxide. Further, in both the barrier type and the porous type, anodic oxide is extremely difficult to be etched by dry etching. In particular, the feature is that the selection ratio is sufficiently large in etching with silicon oxide. Therefore, after forming a porous anodic oxide on at least a side surface of the gate electrode with a specific width, for example, 1 μm, the gate insulating film is etched using this porous anodic oxide as a mask, and then the porous anodic oxidation is performed. When the object is etched, a region having no gate electrode but only a gate insulating film can be formed next to the gate electrode by about 1 μm. Through such steps, the structure of FIG. 4B can be obtained.

In the case of FIG. 4B, the high resistance region 12,
14 can be doped with N-type impurities having a lower concentration than the source region 11 and the drain region 15 in one doping step. That is, in the case of an impurity ion having a specific energy, for example, a phosphorus ion of 30 keV, the impurity concentration has the highest depth of several hundred Å from the surface and generally has a Gaussian distribution. Therefore, a sufficient amount of impurities are implanted into the source region and the drain region which are not covered with the gate insulating film, whereas in the high resistance region covered with the gate insulating film 16, most of the impurities are the gate insulating film. The impurities injected into the high resistance regions 12 and 14 are stopped, and the impurities injected into the high resistance regions 12 and 14 are lower than those injected into the source and drain regions by one to two digits. When the ion energy is lowered, the amount of impurities implanted into the high resistance region becomes smaller than the amount of impurities implanted into the source region and the drain region, and the conductivity type of the channel formation region remains the same. Become. As described above, by using the gate insulating film formed in self-alignment, the high resistance region can be formed in self-alignment.

[0011]

In any case, the effect of the negative charges generated by the hot carriers can be canceled out by providing the film for trapping the positive charges such as silicon nitride on the high resistance region. First, the case of FIG. 4A will be described. In this case, negative charges are trapped by hot carrier injection in the gate insulating film (of silicon oxide) (the portion of the ellipse a of the dotted line in the figure) on the high resistance region 4 on the drain side of the gate insulating film. , The above-mentioned negative charges are canceled out because positive charges are trapped in the film 8'above. However, in order for the positive charge effect to reach the high resistance region, it is not desirable that the gate insulating film is too thick, and the thickness of the gate insulating film is preferably 500 Å or less. However, a thin film having a thickness of 500 Å or less has a drawback in that a leak current is large in a poor quality gate insulating film.

Also in the case of FIG. 4B, the effect of the negative charges trapped in the gate insulating film on the high resistance region 14 on the drain side is caused by the positive charges trapped in the film 18 ′ on the gate insulating film. Cancel. Then, as in the case of FIG. 4A, it is not desirable that the gate insulating film is too thick,
The thickness of the gate insulating film is preferably 500 Å or less.

In the case of FIG. 4C, since there is no gate insulating film on the drain side high resistance region 24 and positive charges are trapped in 28 ', the conductivity type of the high resistance region is always It is a weak N type. However, in this case the coating 2
When forming the film 8 ′, the high resistance region 2 may be formed depending on the film forming means.
2, 24 may be damaged. Generally optical CV
Although the D method and the low pressure CVD method have less damage, the former method has a drawback that the film forming rate is slow and the latter method has a disadvantage that the film forming temperature is high. However, plasma damage cannot be avoided by the plasma CVD method, which has good mass productivity and a low film formation temperature. Therefore, it must be taken into consideration that this structure may deteriorate the characteristics of the device to some extent.

In the case of FIG. 4D, since the gate insulating film on the channel forming region 33 can be made sufficiently thick, the leak current is small, and the high resistance regions 32 and 34 are small.
Is not damaged when the coating 37 'is formed. The gate insulating film 36 is preferably 500 Å or less on the high resistance region. The problem with this structure is that the technique of etching the gate insulating film to an appropriate thickness is difficult, and the mass productivity is somewhat difficult. Figure 4
In (D), the gate insulating film 36 has high resistance regions 32 and 34.
Although only the channel forming region 33 is covered, the source region 31 and the drain region 35 may be covered. Examples of the present invention will be shown below and will be described in more detail.

[0015]

【Example】

Example 1 This example is shown in FIGS. 1 and 2. Figure 1
Shows the basic steps of the present invention. First, the substrate 10
A base insulating film 102 is formed on the first layer 1. As a substrate, non-alkali glass, for example, Corning 7059 (300 m
m × 400 mm or 100 mm × 100 mm) was used. The thickness of the base insulating film 102 is 1000 to 3000
A silicon oxide film of Å was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to improve mass productivity, TEOS is used as plasma CV.
A film decomposed / deposited by the D method may be used. In addition to silicon oxide, a single layer film of aluminum nitride or a multilayer film of silicon oxide and aluminum nitride may be used as the base film. A reactive sputtering method in a nitrogen atmosphere may be used to form the aluminum nitride film.

Further, the active layer 103 is formed of a crystalline semiconductor (in the present invention, a semiconductor in which crystals are mixed, such as single crystal, polycrystal, and semi-amorphous) is called a crystalline semiconductor. Here, plasma CVD method and LPCVD
The amorphous silicon film is deposited by the method to 300 to 5000 Å, preferably 500 to 1000 Å, and this is deposited to 550 to 60 Å.
It was left to stand in a reducing atmosphere at 0 ° C. for 24 hours to be crystallized. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was patterned to form the island regions 103. Then, the insulating film 104 is formed of a material such as silicon oxide so as to cover it. The insulating film 104 has a thickness of 30 by the sputtering method.
A silicon oxide film 104 having a thickness of 0 to 1500 Å, preferably 500 Å or less was used.

Further, a film is formed by using an anodizable material. As the material of this coating, aluminum, tantalum, titanium, silicon or the like which can be anodized is preferable.
In the present invention, a single-layer structure gate electrode using these materials alone may be used, or a multi-layer structure gate electrode in which two or more layers are stacked may be used. For example, it has a two-layer structure in which titanium silicide is overlaid on aluminum and a two-layer structure in which aluminum is overlaid on titanium nitride. The thickness of each layer may be determined by a practitioner according to the required device characteristics.

Further, a film which serves as a mask in anodic oxidation is formed covering the film, and both are simultaneously patterned and etched to form a gate electrode 105 and a mask film 106 thereon. As a material for the mask film, a photoresist used in a normal photolithography process, a photosensitive polyimide, or a material that can be etched with a normal polyimide may be used.

Here, as a coating capable of anodic oxidation, aluminum having a thickness of 1000Å to 3 μm (1 wt% of S
A film of i or containing 0.1 to 0.3 wt% of Sc (scandium) was formed by an electron beam evaporation method or a sputtering method. Then, as a mask for anodization, a photoresist (for example, OFPR800 /
30 cp) was formed by spin coating. Prior to the formation of the photoresist, a highly insulating, preferably barrier type, anodic oxide film, for example, with a thickness of 1
When an aluminum oxide film of 100 to 1000 Å is formed on the surface, the adhesion to the photoresist is good, and the leakage of current from the photoresist is suppressed, so that the porous anode can be used in the subsequent anodizing step. It was effective in forming the oxide only on the side surface. Then, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form the gate electrode 105 mask film 106. (Fig. 1 (A))

Next, a current is applied to the gate electrode 105 in an electrolytic solution to form a porous anodic oxide 107 on the side surface of the gate electrode. This anodic oxidation process is 3
It is carried out using an acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc. of -20%. In this case, at a low voltage of about 10 to 30 V, 0.3 to 25 μm,
For example, a thick anodic oxide of 1.0 μm can be formed. After the anodic oxidation process, the mask film 106 is removed by etching.

In this embodiment, the thickness is 3000 Å to 2 μm,
For example, a porous anodic oxide 107 having a thickness of 5000 Å was formed. The anodic oxidation may be performed using an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like, and a constant current of 10 to 30 V may be applied to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.), and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (Fig. 1
(B))

In the present invention, before proceeding to the next step,
A barrier type anode having a high insulating property is further applied to the side surface and the upper surface of the gate electrode by applying a current in an ethylene glycol solution containing 3 to 10% tartar solution, boric acid and nitric acid. It is preferable to provide the oxide 108. In this anodic oxidation process, the thickness of the obtained anodic oxide is determined by the magnitude of the voltage applied between the gate electrode 105 and the opposing electrode.

That is, the mask was removed, and a current was applied to the gate electrode again in the electrolytic solution. In this anodic oxidation, an ethylene glycol solution containing 3 to 10% tartar solution, boric acid and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. Therefore, the barrier type anodic oxide 108 was formed on the upper surface and the side surface of the gate electrode. The thickness of the anodic oxide 108 is proportional to the applied voltage and is 200 when the applied voltage is 150V.
0Å anodized oxide was formed. The thickness of the anodic oxide 108 was determined by the required offset and the size of the overlap, but a high voltage of 250 V or more is required to obtain an anodic oxide having a thickness of 3000 Å or more.
Since it has an adverse effect on the characteristics of T, it is preferable to set the thickness to 3000 Å or less. In this example, the voltage was raised to 80 to 150 V and the voltage was selected according to the required thickness of the anodic oxide film 108. (Fig. 1 (C))

It should be noted that, although barrier type anodization is a later step, it does not mean that barrier type anodization is formed outside the porous anodization, but rather barrier type anodization. The object 108 is to be formed between the porous anodic oxide 107 and the gate electrode 105. In the phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more that of the barrier type anodic oxide. Therefore, the porous anodic oxide 10
7 etching, barrier type anodic oxide 108
Is not substantially etched by the phosphoric acid-based etchant, so that the inner aluminum gate electrode can be protected.

Then, the insulating film 104 is etched by a dry etching method, a wet etching method or the like.
This etching depth is arbitrary, and etching may be performed until the underlying active layer is exposed, or may be stopped midway. However, from the viewpoint of mass productivity, yield, and uniformity, it is desirable to etch up to the active layer. At this time, the anodic oxide 107 and the gate electrode 10
The insulating film having the original thickness is left in the insulating film (gate insulating film) below the region covered with 5. The gate electrode contains aluminum, tantalum, and titanium as main components, while
In the case where the insulating film 104 contains silicon oxide as a main component,
When the dry etching method is used, the insulating film 104 made of silicon oxide is formed by dry etching using a fluorine-based (for example, NF ₃ or SF ₆ ) etching gas.
Is etched quickly, but the etching rates of aluminum oxide, tantalum oxide, and titanium oxide are sufficiently low that the insulating film 104 can be selectively etched.

In wet etching, 1
A hydrofluoric acid-based etchant such as / 100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is etched quickly, but since the etching rates of aluminum oxide, tantalum oxide, and titanium oxide are sufficiently small, the insulating film 104 can be selectively etched.

In this embodiment, the silicon oxide film 104 is etched by the dry etching method. In this etching, even in the plasma mode of isotropic etching,
Alternatively, a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being deeply etched by sufficiently increasing the selection ratio of silicon and silicon oxide. CF ₄ was used as the etching gas. As a matter of course, the silicon oxide film 104 ′ (hereinafter, referred to as a gate insulating film) below the porous anodic oxide 107 remained without being etched. (Fig. 1
(D)) Then, the porous anodic oxide 107 is removed. As the etchant, a phosphoric acid-based solution, for example, a mixed acid of phosphoric acid, acetic acid, nitric acid, or the like is preferable. Etching rate is about 600Å
/ Min. The underlying gate insulating film 104 'remains as it is. (Fig. 1 (E))

Through the above steps, a structure in which the gate insulating film 104 'selectively remains below the gate electrode can be obtained. Since the gate insulating film 104 ′ originally exists below the porous anodic oxide 107, not only the gate electrode 105 and the barrier anodic oxide 108 but also the barrier anodic oxide 108. To y, the width y is almost constant, that is, the width y is determined in a self-aligned manner with respect to the gate electrode. In other words, the region where the gate insulating film 104 'exists and the region where it does not exist are formed in a self-aligned manner outside the channel forming region below the gate electrode in the active layer 103.

After that, the process was shifted to the process shown in FIG. First, the active layer 10 of the TFT is formed by the ion doping method.
3, N-type impurity ions, for example, phosphorus ions were implanted in a self-aligning manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as a mask. The dose amount is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atom cm ⁻² , for example, 2 × 10 ¹⁵ atom cm ⁻² , and the acceleration energy is 10 to 10.
It was set to 60 keV, for example, 40 kV. At this time, since the acceleration voltage was low, a sufficient amount of N-type impurities were implanted into the regions 110 and 113, but the gate insulating film interfered with the regions 111 and 112, and only a small amount of N-type impurities were implanted. There wasn't. Thus, due to the difference in the N-type impurity concentration and the nitrogen ion concentration, the low resistance region (source / source
Drain regions) 110, 113, high resistance regions 111, 1
12 was formed. Phosphine (PH ₃ ) was used as the doping gas. (Fig. 2 (A))

According to the result of SIMS (secondary ion mass spectrometry), the impurity concentration of the regions 110 and 113 is 1 × 10.
^{20 to} 2 × 10 ²¹ cm ⁻³ , 1 × 1 in the regions 111 and 112
It was 0 ^{17 to} 2 × 10 ¹⁸ cm ⁻³ . In dose conversion,
The former is 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 , and the latter is 2 × 10
^{It was 13 to} 5 × 10 ¹⁴ cm ^-2 . This difference is caused by the presence or absence of the gate insulating film 104 ', and generally, the impurity concentration of the low resistance impurity region is 0.5 to 3 orders of magnitude higher than that of the high resistance region.

Subsequently, a silicon nitride film 114 having a thickness of 200 to 2000 Å was formed on the entire surface by plasma CVD. This silicon nitride film was prepared by mixing silane (SiH ₄ ) and ammonia (NH ₃ ) at a ratio of 1: 5, and the substrate temperature was 250 to 40.
It was formed at 0 ° C., typically 350 ° C. In the ratio of silane to ammonia, if the amount of silane is increased, silicon becomes an excessive amount of silicon, that is, a silicon nitride film having many trap centers capable of trapping positive charges. However, the insulating property is worse than that of the silicon nitride film having a small amount of silane. That is, it is necessary to determine the ratio of silane and ammonia so as to obtain a silicon nitride film having a sufficient insulating property and having a slight excess of silicon as clusters. Specifically, considering the atomic ratio, Si / N = 10 /
It is desirable to set the ratio to be 1 to 2/1.

Further, in place of the silicon nitride film, a three-layer structure having a structure in which a silicon film excessive in silicon is sandwiched by a general silicon nitride film (shown by a composition ratio of Si ₃ N ₄ or close thereto) It is also effective to employ layers (membranes). Specifically, from the side in contact with the active layer, a general silicon nitride film having a thickness of 10 to 100Å, for example 50Å, a silicon film having an excess of 20 to 200Å, for example, 100Å, and a film having a thickness of 100 to 1000Å
For example, a structure in which a general silicon film having a thickness of 500 Å is laminated in three layers may be adopted.

This is a structure for achieving both the ability to capture positive charges and the insulating property. In this case, the insulating property is maintained by a general silicon nitride film (indicated by a composition ratio of Si ₃ N ₄ or close thereto), and the silicon film having excess silicon can obtain the ability to trap positive charges. it can.

The silicon nitride film 114 may be formed by a low pressure CVD method or may be formed by implanting nitrogen ions into the silicon film. After the silicon nitride film 114 was formed in this manner, XeF excimer laser (wavelength 355 nm, pulse width 40 nsec) was irradiated to activate the impurity ions introduced into the active layer. Since the laser light needs to pass through the silicon nitride film 114, when an ultraviolet laser such as an excimer laser is used, a laser having a long wavelength is preferable.

In this embodiment, the excimer laser is used as described above, but it goes without saying that another laser may be used. However, when using a laser, a pulsed laser is preferable. Since the irradiation time of the continuous wave laser is long, there is a risk that the object to be irradiated expands due to heat and peels off.

Regarding the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switch pulse oscillation) or visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl and ArF can be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select the laser light that passes through the underlying silicon semiconductor film.

The laser annealing described above
It may be performed by lamp annealing by irradiation with visible light or near infrared light. When performing lamp annealing,
So that the surface of the irradiated surface is about 600 to 1000 ° C,
When the temperature is 600 ° C., the lamp irradiation is performed for several minutes, and when the temperature is 1000 ° C., the lamp irradiation is performed for several tens seconds. Near-infrared (for example 1.
Annealing with (2 μm infrared rays) does not heat the glass substrate so much that near infrared rays are selectively absorbed by the silicon semiconductor, and the heating of the glass substrate can be suppressed by shortening the irradiation time once. , Very useful.

After that, hydrogen ions were doped by the ion doping method. Acceleration energy is 10-50
kV, for example, 20 kV, the dose amount is 1 × 10 ^{14 to} 5 ×
It was set to 10 ¹⁵ atoms cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² .
This was done because the silicon nitride film 114 is impermeable to hydrogen in the usual thermal annealing. It is desirable that 0.01 to 10 atomic% of hydrogen be oped to at least a region between the source / drain and the channel formation region. Also,
This hydrogen ion doping process is performed by laser annealing (or lamp annealing) the impurities introduced previously.
It is desirable to carry out after the step of.

Finally, the interlayer insulator 115 is formed on the entire surface,
A silicon oxide film having a thickness of 2000Å to 1 μ is formed by the CVD method.
m, for example 3000Å. Further, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 116 and 117 were formed. And 20
Annealing was performed at 0 to 400 ° C. in a nitrogen atmosphere.
In this step, the hydrogen atom previously introduced by the ion doping method was activated. By the above, the TFT was completed. (Fig. 2 (C))

[Embodiment 2] This embodiment is shown in FIGS. 1 and 3. The base film 102, the active layer 103, the gate insulating film 104 ′, the gate electrode 105, and the anodic oxide 108 were formed on the glass substrate 101 by the same process as in Example 1. However, in this embodiment, the thickness of the gate insulating film (silicon oxide) is 1000 to 1500Å, for example 1200Å.
And As a result, the gate leakage current is small, and
It can withstand high anodizing voltages in later processes. (Fig. 1 (E))

Then, by the ion doping method, T
Nitrogen ions were self-alignedly implanted into the active layer 103 of the FT by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) and the gate insulating film as a mask. The dose amount is 1 × 10 ^{14 to} 3 × 10 ¹⁶ atoms cm ⁻² , for example, 2 × 1
And 0 ¹⁵ atoms cm ^-2, an acceleration voltage is 50～100KV, for example, was 80 kV. In this case, since the accelerating voltage is high, the active layer region 13 without the gate insulating film 104 ′ on it is formed.
At 0 and 133, nitrogen ions permeate and the active layer regions 130 and 133 are hardly doped with nitrogen (1 × 1 according to the SIMS (secondary ion mass spectrometry) method).
It was 0 ¹⁹ cm ^-3 or less. On the other hand, in the active layer regions 131 and 132 on which the gate insulating film is present, the nitrogen concentration is maximum in this region, and therefore 5 × 10 ¹⁹ to 2 × 10 ²¹
A nitrogen concentration of atomic cm ⁻³ (depending on depth) was introduced. (Fig. 3 (A))

Subsequently, the gate insulating film 104 'was etched using the anodic oxide 108 as a mask to newly form a gate insulating film 104 ". Then, as in the first embodiment.
A silicon nitride film 124 having a thickness of 200 to 2000 Å, for example, 1000 Å, was deposited on the entire surface by the plasma CVD method. Furthermore, an N-type impurity was injected into the active layer of the TFT by the ion doping method. Dose amount is 5 × 10 ¹⁴
˜5 × 10 ¹⁵ cm ⁻² , and the acceleration voltage is 50 to 100 kV, for example, 80 kV. Phosphine (PH ₃ ) was used as the doping gas. As a result, the areas 120, 1
The same amount of N-type impurity was implanted into 21, 122 and 123 to form impurity regions. However, depending on the amount of nitrogen ions previously implanted, the regions 120, 12
3 is a low resistance region, whereas regions 121 and 122 are
Became the high resistance region. In this example, unlike the example 1, since the silicon nitride film was formed on the surface of the active silicon layer during the phosphorus ion doping, the surface could be prevented from being roughened. (Fig. 3 (B))

Then, a XeF excimer laser (wavelength 355 nm, pulse width 40 nsec) was irradiated to activate the impurity ions and nitrogen ions introduced into the active layer. According to the result of SIMS (secondary ion mass spectrometry), the concentration of phosphorus in the regions 120, 121, 122 and 123 was 1 × 10 ²⁰ to 2 × 10 ²¹ cm ⁻³ . The converted dose amount was 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 .

Then, as in Example 1, hydrogen ions were doped by the ion doping method. Finally,
As the interlayer insulator 125, a silicon oxide film having a thickness of 3000 Å was formed on the entire surface by the CVD method. Further, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 139 and 140 were formed. And 2
Annealing was performed in a nitrogen atmosphere at 00 to 400 ° C.
By the above, the TFT was completed. The present embodiment is different from the first embodiment in that the high resistance region is formed by the concentration of the added resistance material (nitrogen in this case). (Fig. 3 (C))

Using the method shown in FIGS. 1 and 3, 1
As an example of forming a plurality of TFTs on a single substrate, an active matrix electro-optical device (for example, a liquid crystal display) has a matrix region and a peripheral driving circuit for driving the same formed monolithically on the same substrate. An example is shown in FIG. In this example, three TFTs, TFT1 to TFT3, are formed. TFT 1 and 2 are driver TFTs
The thickness of the oxide corresponding to the anodic oxide 108 in FIG. 1 is 200 to 2000Å, for example, 10
00 Å, and during the ion doping, due to diffraction of impurity ions, the gate electrode and high resistance region (HR
D) was made to overlap. In the figure, the drain of the N-channel type TFT 1 and the P-channel type TFT
The drain of 2 is connected to each other by a wiring 503, and
An example is shown in which the source of FT1 is grounded and the source of TFT2 is connected to a power source to form a CMOS inverter. There are various other circuits as peripheral circuits, but according to the specifications of each, such CM
It may be an OS type circuit.

On the other hand, the TFT 3 is used as a pixel TFT, and one of the source / drain electrodes of the TFT 3 is connected to the pixel electrode 502 of ITO. Although the anodic oxide is 1000 Å as in the TFTs 1 and 2, the width y ′ of the high resistance region between the drain region and the gate electrode is 0.4 to 2 μm, for example, 0.5 μm,
Suppressed leak current. On the contrary, in TFT 1 and 2,
The width y of the high resistance region is smaller than that of the TFT 3, for example, 0.2 μm. In this way, the width of the high resistance region is T
To change by FT, the thickness of the porous anodic oxide 107 may be changed by TFT, and for that purpose, TF
It suffices that T1 and T2 and the TFT 3 can be controlled independently by using a separate gate wiring during anodization. In addition, since the width of the high resistance region is large in the pixel TFT 3, the parasitic capacitance between the gate and the drain due to the voltage application can be reduced. This is preferable for use as a pixel TFT.

Since the TFTs 1 and 3 are N-channel type, the manufacturing method of this embodiment may be used.
Since T2 is a P channel type, it is not preferable in terms of characteristics to adopt the process of this embodiment as it is. That is, in the N-channel TFT, the gate insulating film 104 ′ was etched along the gate electrode portion at the stage of shifting from FIG. 3A to FIG. In the type TFT, such a process is not performed because the silicon nitride film 501 (corresponding to the silicon nitride film 124 in FIG. 2) may come into contact with the high resistance region. , Silicon nitride film 5
01 traps positive charges, so P-channel TF
This is because in the case of T, the presence of the silicon nitride film 124 causes the high resistance region to invert to the N type, thereby hindering the current between the dose and the drain. Therefore, the P-channel type has a shape as shown in the figure.

[Embodiment 3] FIG. 5 shows an N-channel TFT.
An example of forming the is shown. First, a base oxide film 202 is formed on a substrate (for example, Corning 7059) 201 having an insulating surface by using the steps of FIGS. 1A and 1B of the first embodiment.
Island-like silicon semiconductor region (for example, crystalline silicon semiconductor having a thickness of 800 Å) 203, silicon oxide film 20 having a thickness of 1200 Å
4. A gate electrode 205 made of an aluminum film (thickness 200 nm to 1 μm) and a porous anodic oxide (thickness 3000 Å to 1 μm, for example 5000 Å) on the side surface of the gate electrode 2
06 was formed. (FIG. 5A) Then, as in the first embodiment, the thickness of the barrier mold is 1000 to 2
A 500 Å anodic oxide 207 was formed. (Fig. 5
(B))

Further, the silicon oxide film 204 was etched using the porous anodic oxide 206 as a mask to form a gate insulating film 204 '. After that, the barrier type anodic oxide film 2
Using 07 as a mask, the porous anodic oxide film 206 was removed by etching. After that, the gate electrode part (205, 20
7) and the gate insulating film 204 ′ are used as masks to perform impurity implantation by ion doping to form low resistance impurity regions 208 and 211 and high resistance impurity regions 209 and 2.
Formed 10. Dose amount is 1-5 × 10 ¹⁴ atoms c
m ⁻² , and the acceleration voltage was 30 to 90 kV. Phosphorus was used as an impurity. (Fig. 5 (C))

Further, a film of an appropriate metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium or the like, for example, a titanium film 212 having a thickness of 50 to 500 Å is formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 212 was formed in close contact with the low resistance impurity regions 208 and 211. (Fig. 5
(D))

Then, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is irradiated to activate the doped impurities, and at the same time react the metal film (titanium in this case) with silicon in the active layer to form a metal silicide ( Here, regions 213 and 214 of titanium silicide) are formed.
Laser energy density is 200-400 mJ / cm
² , preferably 250-300 mJ / cm ² . In addition, the substrate is 200 to 500 during laser irradiation.
By heating to ℃, peeling of the titanium film could be suppressed.

After that, the titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at 5: 2: 2. The titanium film (eg, the gate insulating film 204 ′ or the anodic oxide film 207) other than the portion in contact with the exposed active layer is formed.
Since the titanium film existing above) remains in the metallic state as it is, it can be removed by this etching. On the other hand, the titanium silicides 213 and 214, which are metal silicides, are not etched and can be left.

After that, the gate insulating film 204 'was etched by dry etching using the gate electrode portion as a mask to form a new gate insulating film 204 "with a shape of 200 to 500 Å left. Plasma C
A silicon nitride film 217 having a thickness of 200 to 2000Å was formed on the entire surface by the VD method. In this embodiment, unlike the second embodiment, the high resistance region 209,
Since the thin silicon oxide film remains on 210, damage during film formation can be reduced. (Fig. 5 (E))

After that, hydrogen ions were doped into the active layer by the ion doping method. Finally, Figure 5
As shown in (F), an interlayer insulator 218 is formed on the entire surface.
A silicon oxide film having a thickness of 2000Å to 1 μ is formed by the CVD method.
m, for example, 3000 Å, contact holes are formed in the source / drain of the TFT, aluminum wiring,
The electrodes 219 and 220 are 2000 Å to 1 μm, for example, 50
It was formed to a thickness of 00Å.

In the present embodiment, the portion to which the aluminum wiring contacts is titanium silicide, and the stability of the interface with aluminum is better than that of silicon, so a highly reliable contact was obtained. Further, if titanium nitride, for example, is formed as a barrier metal between the aluminum electrodes 219 and 220 and the silicide regions 213 and 214, the reliability can be further improved. In this example, the sheet resistance in the silicide region was 10 to 50 Ω / □. On the other hand, it was 10 to 500 kΩ / □ in the high resistance impurity regions 209 and 210 having the same conductivity type as the source / drain.

Further, the high resistance region is formed through the silicon oxide film,
Since it is covered with the silicon nitride film 217, it prevents mobile ions such as sodium from entering from the outside. Further, as described above, the silicon nitride film 217 traps the positive charges to cancel the effect of the negative charges trapped in the silicon oxide film thereunder.

In this embodiment, the low resistance impurity region 211 and the metal silicide region 214 could be made to substantially coincide with each other.
In particular, the edge 215 of the gate insulating film 204 ′ and the boundary 216 of the high resistance impurity region 210 and the low resistance impurity region 211 are made substantially coincident with each other, and at the same time, this end 215 and the end of the metal silicide region 214 are made substantially coincident with each other. I was able to.

As an example of forming a plurality of TFTs on one substrate by using the method shown in FIG. 5, an active matrix type electro-optical device (for example, liquid crystal display),
An example in which a matrix region and a peripheral driving circuit for driving the matrix region are formed monolithically on the same substrate is shown in FIG. 8B.
Shown in. In this example, three TFTs, TFT1 to TFT3, are formed. TFT1 and 2 are CM as driver TFT
The structure used as an OS, here used as an inverter structure, has a thickness of an oxide corresponding to the anodic oxide 207 of FIG. 2 of 200 to 2000Å, for example, 1000Å. On the other hand, the TFT 3 is used as a pixel TFT, and similarly, the thickness of the anodic oxide is 1000 Å. TF
One of the source / drain electrodes of T3 is connected to the pixel electrode 505 of ITO. Reference numeral 506 is an output terminal of the inverter, and 504 is a silicon nitride film (corresponding to 217 in FIG. 5).

Regarding the anodic oxide, the thickness of the anodic oxide was selected so that the edge of the gate electrode and the edge of the source / drain region coincided with each other in consideration of wraparound during ion implantation. One of the source / drain electrodes of the TFT3 is ITO
Of the pixel electrode 502. In the TFT 3, the width y ′ of the high resistance region is 0.4 to 5 μm, for example, 0.5 μm.
On the other hand, in the TFTs 1 and 2, the width y is shorter than that, for example, 0.2 μm. In order to change the width of the high resistance region according to the TFT, the porous anodic oxide 2
The thickness of 06 may be changed depending on the TFT, and for that purpose, the wirings at the time of anodization can be independently controlled for the TFTs 1 and 2 and the TFT 3 so that they can be controlled independently. Note that TFT1 and TFT3 are N-channel type T
The FT and TFT2 are P-channel TFTs. As described above, in the pixel-use TFT 3, since the width of the high resistance region is large, it is possible to reduce the parasitic capacitance between the gate and the drain due to the voltage application. This is preferable for use as a pixel TFT.

Although the TFTs 1 and 3 which are N-channel TFTs are manufactured by the process as shown in this embodiment, the structure of the TFT 2 which is a P-channel TFT is TF.
The difference from T1 and 3 is due to the same reason as described in Example 2. In this embodiment, the titanium film forming step is arranged after the ion doping step, but this order may be reversed. In this case, since the titanium film covers the entire surface at the time of ion irradiation, it is very effective in preventing abnormal charge (charge-up) which has been a problem in the insulating substrate. Alternatively, after the ion doping, annealing may be performed with a laser or the like, a titanium film may be formed, and then titanium silicide may be formed by irradiation with a laser or the like or thermal annealing.

[Embodiment 4] This embodiment is shown in FIG. First, the base oxide film 302, the island-shaped crystalline semiconductor region, for example, the silicon semiconductor region 303, is formed on the substrate (Corning 7059) 301 using the steps of FIGS. Silicon oxide film 304, aluminum film (thickness 2
000Å to 1 μm) and a porous anodic oxide (thickness 6000Å) 30 on the side surface of the gate electrode 305 and the gate electrode.
6. Further, a barrier type anodic oxide 307 was formed between the gate electrode 305 and the porous anodic oxide 306.
(Fig. 6 (A))

Further, using the porous anodic oxide 306 as a mask, the silicon oxide film 304 was etched to form a gate insulating film 304 '. Then, the porous anodic oxide 30
6 was etched to expose a part of the gate insulating film 304 '. Then, an appropriate metal, for example, a titanium film 308 having a thickness of 50 to 500Å is formed on the entire surface by the sputtering method. (Fig. 6 (B))

Then, by the ion doping method, T
N-type impurities were implanted into the active layer of FT. The dose amount is 5
× 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 , acceleration energy is 10
It was set to 30 keV. At this time, since the acceleration voltage was low, a sufficient amount of N-type impurities was implanted into the regions 309 and 312, but the gate insulating film interfered with the region 31.
Only a small amount of N-type impurities was injected into 0 and 311. As described above, due to the difference in N-type impurity concentration and carbon ion concentration, a low resistance region (source / drain region)
309 and 312 and high resistance regions 310 and 311 were formed. Phosphine (PH ₃ ) was used as the doping gas. (Figure 6 (D))

Then, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is irradiated to react titanium with silicon of the active layer, and titanium silicide region 313,
314 was formed and the impurities doped in the regions 310 and 311 were activated. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . Further, if the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed.
This step may be performed by lamp annealing by irradiation with visible light or near infrared light.

After that, the titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at 5: 2: 2. A titanium film (for example, a gate insulating film 304 ') other than a portion that has become titanium silicide in contact with the exposed active layer.
The titanium film existing on the anodic oxide film 307) remains in the metal state as it is, and can be removed by this etching. On the other hand, the titanium silicides 317 and 318 can be left because they are not etched. After that, the gate insulating film 304 ′ is etched by dry etching using the gate electrode portion as a mask to form a new gate insulating film 304 ″. Then, by plasma CVD, a thickness of 200 to 2000 Å is obtained. Silicon nitride film 31
5 was formed on the entire surface. (Fig. 6 (E))

After that, the active layer was doped with hydrogen ions by an ion doping method and annealed in a nitrogen atmosphere. Then, as an interlayer insulator 316, CV is formed on the entire surface.
A silicon oxide film having a thickness of 6000Å is formed by the D method, and TF
Contact holes were formed in the source / drain of T, and aluminum wiring / electrodes 317 and 318 were formed. Through the above steps, a TFT having a high resistance region was completed. (Fig. 6 (F))

FIG. 8C shows an example (cross-sectional view) in which a TFT is used in a pixel of an active matrix type liquid crystal display device by the manufacturing process shown in FIG. In the figure, a region 50
Reference numeral 7 indicates a TFT area, area 508 indicates an auxiliary capacity area for compensating for the capacity of the pixel electrode, and area 509 indicates a contact area for the wirings of the first and second layers. As is clear from the figure, T
A silicon nitride film 512 is provided so as to cover the active silicon layer of the FT and the gate electrode, and further cover the wirings 510 and 511 in the same plane as the gate electrode (these are all formed with an anodic oxide film on the surface). ing. Then, an interlayer insulator 513 is formed on the silicon nitride film.

A source electrode 516 and a drain electrode 517 of the TFT are connected to the pixel electrode 514 of ITO. The interlayer insulator 513 covering the wiring 510 is the region 5
15 is removed, and the pixel electrode 514 and the wiring 510 are removed.
However, they are opposed to each other with the anodic oxide film and the silicon nitride film 512 sandwiched therebetween to form a capacitor. In this case, since the space between the electrodes is narrow and the dielectric constants of silicon nitride and the anodic oxide film (aluminum oxide) are large, a large capacitance can be obtained in a small area. Interlayer insulator 51 on wiring 511
3 and the silicon nitride film 512 and the anodic oxide film are removed by etching to form contact holes, which are in contact with the second-layer wiring 518 which is the same as the source / drain electrodes.

[Embodiment 5] This embodiment is shown in FIG. First, a base oxide film 402, an island-shaped crystalline semiconductor region, for example, a silicon semiconductor region 403, a silicon oxide film 404, an aluminum film (thickness 20) is formed on a substrate (Corning 7059) 401.
A gate electrode 405 having a thickness of 00 Å to 1 μm was formed.
(FIG. 7 (A)) Then, a porous anodic oxide (thickness 6000Å) 406 was formed on the upper surface and the side surface of the gate electrode. The conditions for anodic oxidation were the same as the conditions for producing the anodic oxide 107 of Example 1. (FIG. 7B) Furthermore, the gate electrode 405 and the porous anodic oxide 40.
A barrier type anodic oxide 407 was formed between the layers. (Fig. 7 (C))

Then, using the porous anodic oxide 406 as a mask, N-type impurities were implanted into the active layer of the TFT by the ion doping method. The dose amount is 5 × 10 ^{14 to} 5
× 10 ¹⁵ cm ^-2 , acceleration energy is 40 to 100 keV
And Phosphine (PH
₃ ) was used. Through the above steps, low resistance regions (source / drain regions) 408 and 409 and a high resistance region (offset region, not shown) having substantially the same conductivity type as the channel formation region and less affected by the gate electrode were formed. . The width z of the offset region is anodic oxide 406 and 4
Determined by the thickness of 07. (Figure 7 (D))

Further, the porous anodic oxide 406 was removed by etching to expose the surface of the barrier type anodic oxide 407. After that, a KrF excimer laser (wavelength 35
The doped impurities were activated by irradiation with 5 nm and a pulse width of 40 nsec. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . Also, the substrate may be heated to 200 to 500 ° C. during laser irradiation. This step may be performed by lamp annealing by irradiation with visible light or near infrared light. And
A silicon nitride film 410 is formed on the entire surface by plasma CVD.
The thickness was 200 to 2000Å, for example 1000Å.
Further, hydrogen ions were implanted by an ion doping method and activated by annealing in a nitrogen atmosphere. (Fig. 7 (E))

Finally, as shown in FIG. 7F, a silicon oxide film having a thickness of 6000 Å is formed as an interlayer insulator 411 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and nitrided. Multi-layered wiring / electrodes 412, 413 of titanium and aluminum were formed. The TFT was completed by the above steps.

[0073]

According to the present invention, in an N-channel type TFT, a high resistance region (HRD), that is, a weak N-type region or an offset region is formed in a self-aligned manner, and on or in the region. By forming a film (for example, a silicon nitride film) capable of trapping positive charges on the silicon oxide film on the region, it was possible to prevent the occurrence of a parasitic channel in the high resistance region. The present invention was particularly effective in preventing a decrease in mobility when the drain voltage was several volts. Therefore, when such an N-channel TFT is used as a pixel transistor of a liquid crystal display device, it is possible to control a delicate voltage and it is preferable for reproducing a delicate halftone when an image is formed. .

It is said that the TFT of the present invention can be formed in the same manner when a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed or when it is formed on glass or an organic resin. In any case, it is characterized in that it is formed on the insulating surface. In particular, the effect of the present invention is remarkable for an electro-optical device such as a monolithic active matrix circuit having peripheral circuits on the same substrate. That is, the TFT according to the present invention has the characteristics that the reverse leakage current is low, the breakdown voltage is high, and the reliability is high (the degree of deterioration is small). This is, for example, a pixel TFT of an active matrix circuit. It is effective when used.

[Brief description of drawings]

FIG. 1 illustrates a general process of the present invention.

FIG. 2 shows a method for manufacturing a TFT according to the first embodiment.

FIG. 3 shows a method for manufacturing a TFT according to a second embodiment.

FIG. 4 illustrates the structure of the TFT of the present invention.

FIG. 5 shows a method for manufacturing a TFT according to the third embodiment.

FIG. 6 shows a method of manufacturing a TFT according to a fourth embodiment.

FIG. 7 shows a method of manufacturing a TFT according to a fifth embodiment.

FIG. 8 shows an example of an integrated circuit of TFTs obtained in Examples 1 and 3.

[Explanation of symbols]

101 Insulating Substrate 102 Base Oxide Film (Silicon Oxide) 103 Active Layer (Crystalline Silicon) 104 Insulating Film (Silicon Oxide) 104 'Gate Insulating Film 105 Gate Electrode (Aluminum) 106 Mask Film (Photoresist) 107 Anodic Oxide (Porous) Aluminum oxide) 108 Anodic oxide (barrier type aluminum oxide) 109 Edge of gate insulating film

Claims (11)

[Claims] 1. In a thin film transistor formed on an insulating surface, a gate electrode, an oxide layer obtained by oxidizing the gate electrode on a side surface and an upper surface of the gate electrode, and a channel existing under the gate electrode. A formation region, a pair of high resistance regions adjacent to the channel formation region, and a pair of low resistance impurity regions provided outside the high resistance region, and on the high resistance region, or A semiconductor device comprising: a film capable of trapping positive charges, the film being formed on silicon oxide formed on the high resistance region. 2. The semiconductor device according to claim 1, wherein the film capable of trapping positive charges is a film containing silicon nitride as a main component. 3. The semiconductor device according to claim 1, wherein the end of the low resistance impurity region is formed in a self-aligned manner so as to correspond to the end of the gate electrode. 4. The semiconductor device according to claim 1, wherein the thin film transistor is an N-channel type. 5. The semiconductor device according to claim 1, wherein the thin film transistor is provided in a pixel transistor in a matrix region of an active liquid crystal display device. 6. A thin film transistor formed on an insulating surface, wherein a gate electrode, a channel formation region existing under the gate electrode, a high resistance region adjacent to the channel formation region, and an outside of the high resistance region. And a metal silicide region provided, and a film capable of trapping positive charges formed on the high resistance region or on silicon oxide formed on the high resistance region. A semiconductor device characterized in that. 7. The semiconductor device according to claim 6, wherein the metal silicide contains titanium or nickel. 8. A first step of forming an active semiconductor layer on an insulating surface, a first insulating film on the active layer, and a film of a gate electrode material on the insulating film, and the gate electrode material. A mask film is selectively provided on the gate electrode material, and the gate electrode material is etched using the mask film.
A second step of forming a gate electrode; a third step of forming a first anodic oxide layer mainly on the side surface of the gate electrode by applying a current to the gate electrode in an electrolytic solution; A fourth step of forming a gate insulating film by etching, thinning or removing the first insulating film using the first anodic oxide layer as a mask; and removing the first anodic oxide layer. And a sixth step of forming a film that covers the gate electrode and the gate insulating film and that can capture positive charges. 9. The semiconductor device according to claim 8, wherein a barrier type second anodic oxide is formed by anodizing the gate electrode between the third step and the fourth step. Of manufacturing. 10. The method according to claim 8, wherein after the fourth step or the sixth step, an impurity exhibiting an N-type conductivity type is added, and further laser or equivalent strong light irradiation is performed. A method for manufacturing a semiconductor device, which comprises activating impurities. 11. The method according to claim 8, wherein after the fifth step or the sixth step, at least hydrogen between the source / drain region and the channel formation region of the active semiconductor layer is doped with hydrogen by ion doping. A method for manufacturing a semiconductor device, which comprises a step of annealing at 200 to 400 ° C. after adding 01 to 10 atomic%.