JPH05232515A - Semiconductor integrated circuit and its production - Google Patents

Abstract

PURPOSE:To provide the process for production which decreases mask alignment stages in the production of the integrated circuit on an insulating substrate and to enhance the reliability of the resulted integrated circuit and to improve the yield. CONSTITUTION:The surfaces of the gate electrode 106, first metallic wiring, such as wiring, etc., formed on the thin-film-like semiconductor element having multilayered wirings, such as thin-film transistors, formed on the insulating substrate 101 are anodized, by which an insulating film 109 is formed on these surfaces and an interlayer insulator is formed directly or separately thereof and thereafter, source and drain electrodes or second metallic wirings 110, 111, such as wirings, are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit formed on an insulating substrate which is excellent in reliability and mass productivity and has a high yield, and a manufacturing method thereof. The present invention, as its application field, constitutes a drive circuit such as a liquid crystal display or a thin film image sensor, or a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art Recently, it has been attempted to form a semiconductor integrated circuit on an insulating substrate such as glass or sapphire.
The reason is that the parasitic capacitance between the substrate and the wiring is reduced to improve the operation speed, and in particular, the glass material such as quartz is not limited in size like a silicon wafer, and is inexpensive, Easy separation between elements, especially CM
This is because the latch-up phenomenon, which is a problem in the OS monolithic integrated circuit, does not occur. In addition to the above reasons, in a liquid crystal display or a contact image sensor, a semiconductor element and a liquid crystal element or a photodetection element need to be integrated, so that a thin film transistor (TFT) is formed on a transparent substrate. Etc. need to be formed.

[0003]

For these reasons, thin film semiconductor devices have been formed on insulating substrates. However, since the conventional semiconductor integrated circuit on the insulating substrate uses the same manufacturing process as that of the semiconductor integrated circuit (monolithic integrated circuit) on the semiconductor substrate, the number of masks required for manufacturing is extremely large. In the conventional monolithic integrated circuit, the silicon single crystal, which is the substrate, has extremely high reliability and has almost no problem such as deformation due to heat treatment. Therefore, even in the mask alignment step, the mask is displaced for such a reason. There wasn't much.

However, a commercially available insulating substrate is less reliable than a silicon substrate, and a substrate made of a glass-based material is deformed randomly by heat treatment. There are cases where mask alignment becomes extremely difficult, such as when the masks do not match.

Further, when it is used for the purpose of a liquid crystal display or the like, it is required to form an integrated circuit in a much larger area than a conventional integrated circuit, and mask alignment becomes more difficult work. It was Therefore, it has been necessary to reduce the mask alignment process. The present invention proposes a manufacturing method which requires less mask alignment steps in manufacturing an integrated circuit on such an insulating substrate.

Another object of the present invention is to improve the reliability of the obtained integrated circuit and improve the yield. In the case of forming an integrated circuit on an insulating substrate, electrostatic breakdown of the device becomes a problem. This is because static electricity is easily generated because it is an insulating substrate, and it is difficult to remove static electricity. In particular, electrostatic breakdown between multilayer wiring is
For example, in the case of a liquid crystal display, the destruction of one location renders each row in the vertical and horizontal lines unusable, and as in the case of a semiconductor memory, for example, it cannot be compensated for by other parts, resulting in damage. Is big.

[0007]

The present invention is intended to solve the above problems by introducing a process completely different from the conventional one. That is, regarding the interlayer insulator used in the conventional integrated circuit, in the present invention, the insulator formed by oxidizing the lower wiring layer is used as all or part of the interlayer insulator. Or increase the breakdown voltage between the multi-layer wirings.

FIG. 1 shows an example of the present invention. First, a silicon oxide film 102 having a thickness of 100 to 1000 nm is formed as a passivation film on a substrate 101 having an insulating surface, and a semiconductor film is formed thereover. As the substrate having the insulating surface, a glass substrate, a substrate having an insulating film provided on a silicon wafer, a substrate having an insulating film provided on a monolithic semiconductor integrated circuit using a silicon semiconductor, or the like can be used. The passivation film has a function of preventing mobile ions such as sodium from entering the semiconductor region thereover from the substrate and deteriorating semiconductor characteristics. This passivation film may be a single-layer film or a multi-layer film of, for example, silicon nitride and silicon oxide or aluminum oxide. Furthermore, if the substrate is sufficiently pure and the number of mobile ions is sufficiently small, it is not necessary to purposely provide such a passivation film. As the semiconductor film, for example, amorphous, polycrystalline, or microcrystalline silicon may be used. The semiconductor film is etched to form the semiconductor region 103.
To form.

Further, an insulating coating is formed on it. Since this insulating film is used as a gate insulating film, one having excellent characteristics at the interface with the underlying semiconductor region and one having few defects such as a carrier trap center and an interface state should be used. Is desired. For example, EC
A silicon oxide film or the like formed by the R-CVD method is preferable. Further, it may have a structure in which a plurality of insulating coatings are stacked in multiple layers.
The thickness of this insulating film is determined in consideration of its use as a gate insulating film. Typically 50-500n
m. In this way, the structure shown in FIG. 1A is obtained.

After that, a metal film containing a metal such as aluminum as a main component is formed. That is, if aluminum containing almost no impurities or pure aluminum has insufficient strength, and for example, is weak against mechanical force such as electromigration, an alloy containing 1 to 10% of silicon added to aluminum is used. Used to form a coating. Instead of aluminum, titanium or tantalum, or titanium silicide, tantalum silicide, an aluminum compound, a titanium compound, or a tantalum compound may be used. These metals can form an oxide film of the material by an anodizing method (anodic oxidation method), and the oxide film is excellent in pressure resistance. However, it should be noted in selecting this metal that titanium oxide and tantalum oxide have a remarkably large relative dielectric constant as compared with aluminum oxide. Therefore, if these materials having a high dielectric constant are used as the interlayer insulator, the dielectric loss may increase. In addition, tantalum and titanium have a higher resistivity than aluminum, which must be considered when selecting materials. Therefore, for example, even in the case of the same first wiring, high-speed response is required, and aluminum is used in the gate wiring that requires a small electrostatic loss with the upper wiring, and a high speed response is required. Instead, it is also desirable to use tantalum or titanium for the storage capacitance wiring that is required to function as a capacitor. Of course, in that case, one extra mask is required. Now, by selectively removing the metal film formed in this way, for example, it functions as the gate electrode 106, the wiring (gate wiring) 105 extending from it, or the storage capacitor electrode, and is used separately from the gate wiring. The wiring (storage capacitor wiring) 107 is formed. The gate electrode may be a single layer of phosphorus-doped silicon or metal, or a multilayer of a phosphorus-doped silicon film and a metal film. In the case of multiple layers, the thickness of the phosphorus-doped silicon film is, for example, 20 to 500Å.

Next, an impurity is introduced into the semiconductor region by a known impurity diffusion method such as an ion implantation method or a plasma doping method to form an impurity region 108. At this time, since the gate electrode 106 functions as a mask at the time of implanting impurities, the impurity regions are formed in a self-aligned (self-aligned) manner. In this way, FIG.
Is obtained.

After forming the impurity region, the substrate is immersed in an appropriate electrolytic solution, the gate wiring and the storage capacitor wiring are connected to a power source, and anodic oxidation is performed by applying a direct current or an alternating current to the gate wiring, the gate electrode and the storage. An oxide film 109 is formed on the surface of the capacitor electrode or the like. A film of aluminum oxide is formed when aluminum is used as a material for the wiring or the like, a titanium oxide film is formed when titanium is used, and a tantalum oxide film is formed when tantalum is used. These oxide films do not consist purely of metal and oxygen, but may contain elements that make up the electrolyte or become hydrates, thus changing their physical properties. For example, when an organic acid is used as the electrolyte, the oxide film contains carbon, and when sulfuric acid is used, sulfur is contained. The use of materials containing alkali metal ions in the electrolyte should be avoided. Alkali metal ions (sodium and potassium)
The reason is that if it penetrates into the semiconductor region, it significantly damages the conductive properties of the semiconductor.

The thickness of the oxide film is determined not only by the required breakdown voltage, but also because the gate electrode recedes by this oxidation process, it is also determined in consideration of how the impurity region and the gate electrode overlap. Typically, oxide film thickness is 1
It is 0 to 1000 nm.

Further, for example, when only the gate wiring is connected to the power supply and the storage capacitance wiring is not connected, an oxide film is formed only on the gate wiring, and the storage capacitance wiring is provided with a layer other than a natural oxide film. Substantially no oxide film is formed. Alternatively, the time, current, voltage or the like for energizing each may be changed. In this way, the thickness of the oxide film formed can be changed. For example, when it is used as an interlayer insulator, it is desirable that the film thickness is large in order to reduce the capacitance between wirings. On the other hand, when it is used as an insulator for capacitors such as storage capacitors, it is desirable that it be thin. When there is a difference in such purpose, it is effective to use the above method.

After the wiring and the like are covered with the oxide film in this manner, the substrate is taken out of the solution and dried thoroughly. If necessary, the oxide film may be modified by exposing it to hot water or high temperature steam. That is, in the anodizing method, the obtained film is a porous film under the conditions aimed at obtaining a particularly thick oxide film. Although such a film is thick, it may have a problem in withstand voltage, and in a later step, the current may be short-circuited through the hole. In such a case, the oxide film may be reacted with high temperature water to form a hydrate, and the volume may be expanded to block the rough. In this way, a dense film having a good insulating property can be obtained. In any case, it is necessary to sufficiently wash and dry so that the electrolyte does not remain on the coating. In this way, FIG. 1C is obtained.

After that, a metal film is formed and patterned to form, for example, the drain wiring / electrode 110 and the source electrode 11. In particular, in a multilayer wiring such as a matrix circuit, the wiring thus formed may need to intersect with the wiring formed first. Conventionally, after forming the first wiring, an interlayer insulating material is formed with an insulating material, and then the upper wiring is formed, but in the present invention, the upper wiring is directly formed without forming the interlayer insulating material. It is possible. That is, the lower wiring is already covered with the oxide film. Therefore, as compared with the conventional method, it is possible to reduce the number of masks by one at this stage. In this way, FIG.
To get

In the present invention, the masks required to obtain FIG. 1D are three masks for forming a semiconductor region, forming a first metal wiring, and forming a second metal wiring. However, the conventional method requires four sheets for forming the semiconductor region, forming the first metal wiring, forming the source electrode of the transistor (making a hole in the interlayer insulator), and forming the second metal wiring. It was

After that, for example, as shown in FIG. 1 (E), a film of a transparent conductive material such as indium tin oxide or tin oxide is formed by, for example, a sputtering method, and this is patterned to form a liquid crystal display. When the pixel electrode is formed, the pixel of the liquid crystal display is formed. The number of masks required for the above steps is four. In Figure 2,
A state in which the pixels of the liquid crystal display thus manufactured are viewed from above is shown. The chain line a-b-c-d in the figure is
Corresponding to a-b-c-d in FIG. 1E, FIG. 1 shows an outline of a cross section at each point.

As is apparent from FIG. 1E, the end of the impurity region 108 of the thin film transistor (TFT) and the end of the gate electrode do not coincide with each other. In the figure, the gate electrode and the impurity region are drawn so as not to overlap with each other. The gap L between the gate electrode and the impurity region (this is called an offset) L is designed to be 0.2 to 0.5 μm, for example. It is also a feature of the present invention that such a thing can be done. That is, in the example of FIG. 1, since the impurities are self-aligned to form the impurity regions and then the surface of the gate electrode is oxidized, the surface of the gate electrode is retreated by this oxidation process. Therefore, it is in an offset state. By providing such an offset state, it is possible to increase the ON / OFF ratio of the drain current of the TFT and to suppress the increase in leak current that is often seen when a gate voltage of reverse polarity is applied. Obtainable.

Although FIG. 1 shows an example in which the relationship between the gate electrode and the impurity region is an offset, according to the present invention, the magnitude L of this offset can be set to an arbitrary value, and the gate electrode and the It is also possible to freely set the overlapped state in which the impurity regions overlap. That is, for example, if the ion implantation method is used as the impurity implantation method, the degree of secondary scattering of the implanted ions can be adjusted according to the magnitude of the energy of the ions. The secondary scattering of the ions causes the impurity ions to get under the gate electrode. That is, if the secondary scattering is large, the gate electrode and the impurity region are largely overlapped with each other, resulting in an overlapping state. Moreover, if the energy of the ions is reduced to suppress the secondary scattering, the overlap is suppressed.

On the other hand, in the present invention, thereafter, the gate electrode is retracted by oxidizing the gate electrode. The degree of this recession is determined by the degree of oxidation. Therefore,
By controlling the ion implantation energy and the conditions of oxidation, it is possible to realize an offset state or an overlap state with an arbitrary size.

In the figure, storage capacitor electrode / wiring 107
It is shown. This electrode / wiring opposes the transparent pixel electrode 112 through the oxide film, and is kept at the same potential as the counter electrode formed by separating the liquid crystal, so that a capacitance parallel to the capacitance of the liquid crystal pixel is obtained. Will be configured. This is because, for example, when the parasitic capacitance between the gate and the source of the thin film transistor (TFT) is large, the gate signal is turned on / off.
It is provided for the purpose of reducing the fluctuation of the potential of the liquid crystal pixel when it is turned off. In the example of FIG. 1, oxides of titanium, aluminum, tantalum, etc. serve as dielectrics, and the relative permittivity of these materials is more than twice that of silicon oxide, which is a typical insulating / dielectric material. It is possible to reduce the area of. That is, increase the area of the portion of the liquid crystal pixel that transmits light (increase the aperture ratio).
Is possible. In addition, such a storage capacity is not always necessary in a liquid crystal display.

FIG. 3 shows another example of the present invention. In the example of FIG. 1, the interlayer insulating film is only the oxide film of the lower wiring, but in that case, there is a problem in thickness, and since such an oxide has a large dielectric constant, This causes an increase in wiring capacitance. Therefore, FIG. 3 shows an example in which the interlayer insulator has two layers, the thickness thereof is increased, and the average dielectric constant is measured to reduce the inter-wiring capacitance.

As in the case of FIG. 1, the passivation film 302 is formed on the insulating substrate 301, and the semiconductor region 3 is formed.
After forming 03, a gate oxide film 304 is formed, and further, a gate wiring 305, a gate electrode 306, and a storage capacitor wiring 307 are formed, and then impurities are self-aligned by an ion implantation method to form an impurity region 308. To do. Before this ion implantation, unlike the case of FIG. 1, it is preferable to leave all the gate oxide film. Thus, FIG. 3A is obtained.

After that, as shown in FIG. 3B, the surfaces of the gate wiring 305, the gate electrode 306, and the storage capacitor wiring 307 are oxidized as needed as in the case of FIG. And
An interlayer insulator 313 is formed, and holes 314 and 315 for source and drain electrodes are formed therein. Further, a drain wiring 310 and a source electrode 311 are formed, and
(C) is obtained.

Finally, as shown in FIG. 3D, a transparent conductive electrode (pixel electrode) 312 is formed to form a pixel for a liquid crystal display. In this example, the number of masks used in all the steps is five: forming a semiconductor region, forming a gate wiring, etc., forming an interlayer insulating film, forming a drain wiring, etc., and forming a pixel electrode. Is the same as the conventional case.

However, in the present invention, for example, the intersection of the gate wiring and the drain wiring has a two-layer structure such as an oxide layer of the gate wiring and a layer of an interlayer insulating material, and in particular, it is formed by anodization. Since the formed oxide is honey and has a high withstand voltage, it is suitable for insulation separation between layers. Conventionally, since there was only one interlayer insulating layer,
There is a problem in the withstand voltage, and in particular, since there is a step at the wiring intersection, the interlayer insulator cannot cover the step, and defects such as cracks exist, leading to a short circuit with the upper wiring. There were many things. However, in the present invention, it is not necessary to consider such a defect due to the step, and this contributes to a large improvement in yield.

Although the above example has been described with respect to an example using only one conductive type thin film transistor, it goes without saying that a complementary type device in which two or more transistors are combined, that is, a so-called CMOS is also used. Can be used. FIG. 4 shows an example of a pixel of a liquid crystal display using CMOS. In the case of CMOS, one or two photolithography processes are required for one conductivity type transistor. Figure 4
Shows a process that requires five masks to form one pixel.

First, as in the above-described examples, the insulating substrate 40
A passivation film 402 is formed on the first layer 1, and semiconductor regions 403a and 403b are selectively formed. After that, a gate insulating film is formed, and a metal wiring 409 and gate electrodes 406a and 406b are formed on the gate insulating film with a material such as aluminum.

Then, the surfaces of the wiring and the electrodes are oxidized by an anodic oxidation method to an appropriate thickness. For example, wiring
When aluminum is used as the electrode material, the surface is covered with the aluminum oxide film 409. Next, if the gate insulating film is silicon oxide, for example, the substrate is lightly etched with a 1/10 HF (hydrogen fluoride) solution to selectively etch the gate insulating film. At this time, the gate wiring covered with aluminum oxide and the silicon oxide under the gate electrode are not etched.
After that, impurities are introduced into the semiconductor region by a known method. The conductivity type of the impurities at this time is, for example, n-type.

Alternatively, after the surface of the gate wiring / electrode is oxidized, impurities are introduced in the state where the gate insulating film remains, and then the gate insulating film is etched using aluminum oxide as a mask. The structure is obtained. In this way, FIG. 4A is obtained.

For example, in the example of FIG. 1 or 3, the impurity introduction is performed prior to the oxidation of the surfaces of the wiring and the electrodes, and in the example of FIG. 1, the gate insulating film is removed before the surface oxidation. As a result, the aluminum oxide remained on the surface of the wiring / electrode like a mushroom umbrella, as typically shown in FIG. 1 (C). For example, if the thickness of aluminum oxide is 500 nm, a protrusion of about 250 nm can be formed. Therefore, holes and voids may be formed under this umbrella in the subsequent wiring formation, which may cause disconnection. .. However, in the example of FIG.
Since there are few such holes and voids, there is no problem such as disconnection.

Next, the semiconductor region 403a on the left side is covered with a material 407 such as a photomask, and p-type impurities are introduced in that state. Through the above steps, the n-type impurity region 408a and the p-type impurity region 408b are obtained. In this way, FIG. 4B is obtained.

Instead of the above steps, first, the semiconductor region 4 is formed without adding impurities to any of the semiconductor regions.
03b is covered with a photoresist or the like to form a semiconductor region 40
A step of introducing an n-type impurity into only 3a, then covering the semiconductor region 403a, and introducing a p-type impurity into only the semiconductor region 403b may be adopted. However, if such a method is adopted, one more mask is required in addition to the method shown in FIG.

After that, as in the example of FIG. 1, the metal wirings / electrodes 410a and 410b, 411 are formed, and the structure shown in FIG.
A structure as shown in FIG. 4C is obtained, and a pixel electrode 412 is further formed to obtain a structure as shown in FIG.

FIG. 5 shows a top view of one pixel of the liquid crystal display device obtained through the above steps. In this example, a part of the gate wiring 405 (or the gate wiring 405 ′ adjacent to it) is made to slip under the pixel electrode 412 to form a capacitance therebetween, and the same function as the storage capacitance of FIG. 2 is obtained. I decided to have it.
The a, b and c attached to the chain line in FIG.
Corresponding to a, b and c in (D), FIG. 4 shows a cross section taken along the chain line.

The above is an example in which the CMOS structure is used as the inverter structure, but in addition to this, Japanese Patent Application Nos. 3-145642, 3-1456343, 3-145566 and 3-145, filed by the present inventors. 157502, 3-157
No. 503, No. 3-157504, No. 3-157505, No. 3-157506, No. 3-157507, etc., it is also possible to use it for the buffer structure, the transfer gate structure, or their modified structures.

The number of masks for obtaining this structure is 5 for semiconductor region formation, gate electrode / wiring formation, p-type impurity region formation, (second) metal wiring formation, and pixel electrode formation. Is. Conventionally, a total of 6 sheets for forming a semiconductor region, forming a gate electrode / wiring, forming a p-type impurity region, forming a hole for an electrode of an interlayer insulator, forming a (second) metal wiring, and forming a pixel electrode. Was needed.

FIG. 6 shows another manufacturing method using the present invention to obtain a CMOS structure. This is shown in Figure 3.
And will be more easily understood than the fabrication method shown in FIG. 5 above. In this example, the thickness of the intersection of the first wiring 605 and the second wiring 610a is determined by the anodic oxide film 6 of the metal wiring.
09 is not sufficient, and when it is considered that the capacitance between wirings becomes too large, the interlayer insulator 613 is formed separately in addition to the anodic oxide film. In that case,
Semiconductor region (603a, 603b) formation, gate wiring,
Electrode (605, 606a, 606b) formation, resist (607) formation, interlayer insulator electrode hole (614a, 6)
14b, 615) formation, second metal wiring / electrode (610
a, 610b, 611) and the pixel electrode (612) are required. This is the same as the minimum number required in the conventional manufacturing method, but the effect obtained by utilizing the present invention is that the CMOS obtained is the same as that obtained by the manufacturing method in FIG. , Substantially the same, and a high yield could be achieved.

FIG. 7 shows another example using the present invention. In the example of FIG. 1 (and FIG. 4) or FIG. 3 (and FIG. 6), the thickness of the interlayer insulator between the lower wiring and the upper wiring and the thickness of the insulator between the storage capacitor wiring and the pixel electrode are Although substantially the same, the former is preferred to be thick, while the latter is preferred to be thin. The method for solving this contradiction is the method shown in FIG.

As in the case of FIG. 1, a passivation film 702 is formed on an insulating substrate 701, and a semiconductor region 703 is formed.
Then, a gate oxide film 704 is formed, and further,
Gate wiring 705, gate electrode 706, storage capacitor wiring 7
After forming 07, the surfaces of these wirings and electrodes are anodized, and the gate insulating film is removed using the anodized film 709 as a mask. Then, impurities are implanted in a self-aligned manner by ion implantation using the gate as a mask to form impurity regions 708. The gate insulating film may be left without being removed. Thus, FIG. 7A is obtained.

After that, a pixel electrode 712 is formed as shown in FIG. Further, as shown in FIG. 7C, an interlayer insulator 713 is formed, and holes 714 for source and drain electrodes are formed in this. Further, the drain wiring 71
0 is formed to obtain FIG.

In the pixel of the liquid crystal display having such a structure, the interlayer insulating material at the intersection of the wiring is thick and the dielectric layer of the storage capacitor is thin. The masks required for the above steps are semiconductor region formation, gate wiring / electrode formation, pixel electrode formation, electrode hole formation for an interlayer insulator, and upper metal wiring formation.
It is a sheet.

However, in such a structure, the upper metal wiring (functioning as the drain wiring) is located above the pixel electrode, and as a result, when the counter electrode is provided, the drain wiring portion is not formed. A phenomenon occurs in which the electric field is large and the electric field in the pixel electrode portion is small. In normal operation, the drain wiring is in a state in which a signal can be constantly applied. Therefore, even if the area of the drain wiring is small, the voltage applied to the drain wiring is large, so that regardless of the image. It will always be in a bright or dark state and will cause serious problems to the image. In addition, since the signal of the drain wiring includes the information of other pixels, a phenomenon similar to crosstalk occurs as a result. Therefore, when adopting the structure as shown in FIG. 7, pay close attention to this point and, for example, arrange the TFT panel on the front side (since the drain wiring is always shaded and invisible, it is added to the drain wiring). The effect of the signal does not appear in the visual sense).

In the example of FIGS. 1 and 3, the pixel electrode was not flat because the storage capacitor wiring and the like exist below the pixel electrode. Therefore, the magnitude of the electric field varies within the same pixel electrode, and the brightness of each pixel may vary due to the subtle difference in the width of the wiring. For this reason,
In order to obtain pixels with less variation, it is desirable that the pixel electrode be flat and that the height of each pixel be the same. FIG. 8 shows an example of the present invention which solves such a problem.

As in the case of FIGS. 1 and 7, the insulating substrate 80 is used.
1, a passivation film 802 is formed, a semiconductor region 803 is formed, a gate oxide film 804 is formed, a gate wiring 805, a gate electrode 806, and a storage capacitor wiring 807 are further formed. The surface is anodized, and the gate insulating film is removed using the anodized film 809 as a mask. Then, impurities are self-aligned by ion implantation using the gate as a mask to form impurity regions 808. The gate insulating film may be left without being removed. Thus, FIG. 8 (A)
To get

After that, a drain wiring 810 is formed as shown in FIG. Further, as shown in FIG. 8C, a flat film 81 made of an organic material such as polyimide is used.
3 is formed, and finally, a hole 815 for a source electrode is formed to form a pixel electrode 812, and FIG. 3D is obtained.

The masks required for the above steps are semiconductor region formation, gate wiring / electrode formation, upper metal wiring formation,
There are five sheets, one for forming an electrode hole for an interlayer insulator and another for forming a pixel electrode. As described above, by using the present invention, a semiconductor device can be manufactured for a variety of purposes.

In the present invention, the anodic oxidation method may be used as a method for oxidizing the metal wiring. In this anodic oxidation method, 50 to 200 V is applied between the anode and the cathode in the electrolytic solution.
Alternatively, a higher voltage than that may be applied, and a large potential gradient of 10 MV / cm or more may occur around the metal wiring / electrode during anodization. Therefore, there is a problem to protect the gate insulating film from such a high voltage. For that purpose, it is desired that the semiconductor region has the same potential as the gate wiring / electrode.

FIG. 9 illustrates the method. First, stripe-shaped semiconductor regions 903 are formed over the insulating substrate 901. After forming a gate insulating film on the semiconductor regions, holes 9 are formed in the gate insulating film at the end of each semiconductor region.
16 is provided, and then the gate wiring / electrode 905 is formed. That is, the semiconductor region 903 and the gate wiring / electrode 9
05 is kept at the same potential through the hole 916. After that, if anodic oxidation is performed, the semiconductor region and the gate wiring /
Since an electric field is not substantially generated between the electrodes, the gate insulating film is less likely to be destroyed by being applied with an excessive voltage. This state is shown in FIG.

After completion of the anodic oxidation, impurities are introduced and the stripe-shaped semiconductor region is divided into appropriate lengths. Then, a hole 917 is formed in the anodic oxide film having a gate wiring shape, and then a drain wiring / electrode 910 is formed. In this state, the gate wiring 905 and the drain wiring 916 are kept at the same potential. As a result, dielectric breakdown caused by static electricity generated during the work can be prevented at the intersection of the gate wiring and the drain wiring. However, this process itself has nothing to do with the high voltage during anodization. afterwards,
The pixel electrode 912 may be formed, and then the peripheral metal wiring may be removed.

In the above steps, a lithographic step is required in order to form a hole for interconnection between wirings in the periphery of the substrate, but these precisions are so low that they do not pose a problem when compared with those of the pixel portion. Therefore, there is almost no decrease in yield due to the addition of these steps. Furthermore, for example, it is possible to evaporate only the oxide film on the surface with a laser, and if such a method is adopted, the process is greatly simplified.

The mask used in the method of FIG. 9 is (1)
Formation of a stripe-shaped semiconductor region, (2) opening a hole in a gate insulating film, (3) formation of a gate wiring / electrode, (4) cutting of a stripe-shaped semiconductor region, (5) hole for anodized film formation As compared with the method of FIG. 1 in which the same structure is obtained, such as after the dawn, (6) formation of drain wiring / electrode, and (7) formation of pixel electrode, more masks are required. Of these, the masks required in the steps (2) and (5) are not required to have high accuracy, and therefore, substantially five masks are required, which is one mask larger than that in FIG.

[0054]

EXAMPLE An example using the present invention will be described with reference to FIG. This example is a CM formed on an AN glass substrate.
The present invention is applied to an OS type TFT. First,
As shown in FIG. 10A, a silicon nitride film 152a having a thickness of 100 nm is formed on the AN glass substrate 151 by the low pressure CVD method. The low pressure CVD uses dichlorosilane (SiH ₂ Cl ₂ ) and ammonia as source gases,
The reaction may be performed at a pressure of 10 to 1000 Pa and a temperature of 500 to 800 ° C, preferably 550 to 750 ° C. of course,
Silane (SiH ₄ ) and trichlorosilane (SiHC
l ₃ ) may be used. Further, instead of the low pressure CVD method, a plasma CVD method, a photo CVD method, a plasma enhanced CVD method or the like may be used.

The silicon nitride film thus formed is
It has a function of preventing mobile ions (such as sodium ions) contained in the glass substrate from entering the semiconductor. Therefore, if the number of mobile ions is sufficiently small on the substrate, it is not necessary to provide the silicon nitride film. Further, the silicon nitride film may be an aluminum oxide film. To form the aluminum oxide film, trimethylaluminum (Al (CH ₃ ) ₃ ) and an oxidizing gas such as oxygen or dinitrogen monoxide (N ₂ O) may be used in the low pressure CVD method described above. .. Even if another CVD method is adopted, the same material may be used. It can also be formed by a sputtering method.

Although the figure shows that the silicon nitride film is provided only on the element formation surface on the glass substrate, if possible, the film is formed so that the entire glass substrate is covered with the silicon nitride film. It is horrible. In the subsequent anodic oxidation process, the substrate is immersed in the solution, so if there is an exposed portion of the glass, alkali ions will dissolve into the solution and adhere to the semiconductor region. This is because it is possible to invade.

Then, the silicon oxide film 152b is formed to a thickness of 70.
Only nm is formed. For this formation, ECR plasma CV
The D method or the sputtering method was suitable. A semiconductor region is formed on this silicon oxide film.
If many interface states, trap centers, and the like occur at the interface between the silicon oxide film and the semiconductor region, the conductivity of the semiconductor region cannot be controlled and the characteristics of the transistor are deteriorated. Therefore, sufficient care must be taken in forming this silicon oxide film. In particular, silicon nitride cannot be used in place of silicon oxide. That is, in many cases, the silicon nitride film itself has a property of trapping carriers inside.

According to the research conducted by the present inventors, the silicon oxide film formed by the ECR plasma CVD method or the sputtering method has a sufficiently low interface state density.
It is suitable for this purpose. Particularly, in the case of forming by sputtering, a silicon oxide bulk was used as a target, the atmosphere was a mixed atmosphere of oxygen and argon, and the oxygen concentration was 50 to 100%. Further, when forming by ECR plasma CVD, silane (SiH ₄ ) and oxygen may be used.
The density of interface states between the silicon oxide film thus formed and the semiconductor film (silicon film) formed thereafter is
It was 10 ¹¹ cm ^-2 , which was extremely excellent. Furthermore, when forming a film by a sputtering method or an ECR plasma CVD method, 1-5% of hydrogen chloride or hydrogen fluoride is mixed in the atmosphere, or
If 1 to 10% of silane containing chlorine or fluorine (for example, dichlorosilane or silicon tetrafluoride SiF ₄ ) is mixed, chlorine and fluorine are taken into the silicon oxide film and these are strongly bonded to silicon. However, the unpaired combinator of the silicon-oxygen bond is terminated, and the interface state can be further lowered. For example, it may be 5 to 9 × 10 ¹⁰ cm ⁻² .

Then, a silicon coating is formed by a low pressure CVD method to a thickness of 30 nm. 6N or more silane (SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ ) is used as the silicon source,
Impurity doping was not performed. However, particularly when used as a CMOS, if it is required that the threshold voltages of the NMOS and the PMOS are almost equal, it is necessary to contain boron in an amount of 10 ¹⁵ to 10 ¹⁶ cm ⁻³ .
A small amount of diborane (B ₂ H ₆ ) may be mixed in the raw material gas. Alternatively, a treatment equivalent to this can be performed by implanting impurity ions (for example, BF ₂ ⁺ ) into the silicon film after the film formation.

The above-described three-layer film forming apparatus is a film forming apparatus capable of continuously forming a film without exposing the substrate to the atmosphere.
It was performed by a so-called multi-chamber type film forming apparatus. Particularly in a thin film transistor, the characteristics of the interface of the semiconductor are important, so a continuous film forming method capable of preventing the interface from being contaminated is indispensable.

After that, the silicon film is patterned by a known photolithography method, and the P-channel TFT region 1 is formed.
53a and N-channel type TFT region 153b are formed. Then, it was annealed at 600 ° C. for 24 to 72 hours in a hydrogen atmosphere to be crystallized. Further, a silicon oxide film 154 serving as a gate insulating film was formed by the above-described sputtering method or ECR plasma CVD method. As with the silicon oxide film 152b described above, the interface characteristics with the semiconductor region are also important for this silicon oxide film, and therefore, careful attention must be paid to the production thereof. This silicon oxide film was formed to a thickness of 100 nm.

Thereafter, an aluminum coating film having a thickness of 0.8 to 1.0 μm was formed by the electron beam evaporation method. In addition, a sputtering method or a metal organic CVD method can be used for forming the aluminum film. And
These aluminum coatings are patterned by a known photolithography method to form the gate electrode 156a.
And 156b, and the gate wiring 155 was formed. Thus, FIG. 10A was obtained. The width of the gate electrode was 10 μm.

Then, the surface of the gate electrode / wiring is oxidized by an anodic oxidation method to a thickness of 0.3 to 0.5 μm.
m aluminum oxide film was formed. The anodic oxidation was performed by the following procedure. Here, it should be noted that the numerical values used in the following description are merely examples, and depending on the size of the element to be manufactured,
The optimum value is determined. That is, the numerical values used in the following description are not absolute. First, an ethylene glycol solution of tartaric acid having a sufficiently low alkali ion concentration was prepared. The concentration of tartaric acid is 0.1 to 10%, for example, 3%, and 1 to
Add 20%, for example 10% ammonia water to adjust the pH to 7
It was adjusted to be ± 0.5.

A platinum electrode was provided as a cathode in this solution, and the substrate was immersed in the solution. Then, the gate wiring / electrode on the substrate was connected to the positive electrode of the DC power supply device. Then, at first, the current was passed so as to be constant at 2 mA. The voltage between the anode and cathode (platinum electrode), along with the concentration of the solution,
It changes with time depending on the thickness of the oxide film formed on the gate electrode / wiring, and generally requires a higher voltage as the thickness of the oxide film increases. When the current continues to flow and the voltage reaches 150V,
The voltage was kept constant and the current continued to flow until the current reached 0.1 mA. The constant current state lasted about 50 minutes, and the constant voltage state lasted about 2 hours. Thus, the aluminum oxide film 15 having a thickness of 0.3 to 0.5 μm is formed on the surface of the gate electrode / wiring.
9 could be formed. The aluminum oxide film formed in this manner was sufficiently dense by itself, but it was held in hot water for 10 minutes in order to further increase the insulating property. By this step, a high withstand voltage film of 6 to 12 MV / cm could be formed. This state is shown in FIG.

After that, the substrate is dipped in a hydrofluoric acid solution, for example, 1/10 hydrofluoric acid, and the silicon oxide film 154 is etched to expose the surface of the semiconductor region. At this time, since aluminum oxide is insoluble in hydrofluoric acid, the silicon oxide film below the gate electrode / wiring is not removed but remains as it is. However, it should be noted that if it is left in hydrofluoric acid for a long time, the silicon oxide film under the gate electrode / wiring will also be dissolved.

Then, by a known ion implantation method, first, boron ions or boron compound ions (for example, BF) are used.
₂ ⁺ ) is injected by 10 ¹⁸ cm ^-3 . At that time, since the ions do not enter the portion below the gate electrode in the semiconductor region except for the secondary scattering of the implanted ions, that is, the impurity region can be formed in a self-aligned manner. it can. Thus, the P-type impurity region 158a
To form.

Next, as shown in FIG. 10C, phosphorus ions are implanted with the photoresist 157 covering the semiconductor region 153a and exposing only the semiconductor region 153b. The phosphorus concentration at this time is 10 ²⁰ cm ^-3 .
Then, although boron is already present in the semiconductor region 153b, since phosphorus has a higher concentration, it exhibits N-type, and an N-type impurity region 158b is obtained. As described above, the impurity element could be introduced into the semiconductor region, but in the region where such an impurity was introduced, the crystal was destroyed by the impact at the time of ion implantation, and an amorphous or microcrystalline state, Or they are in a mixed state. Since there is no suitable term to describe this state, it is described here as an amorphous state.

Next, the photoresist was removed, and laser annealing such as excimer laser or argon ion laser was performed from above to perform laser annealing. Laser annealing is performed, for example, by using a KrF excimer laser (wavelength 248 nm, pulse width 10 nse).
In the case of c), the energy density is 150 to 250 m.
One beam of J / cm ² , for example 210 mJ / cm ²
When 0 shots are added, crystallization can be almost certainly performed.
If the number of shots is less than this, the degree of crystallization will not be uniform due to uncontrollable fluctuations and variations in laser output. In addition, in this laser annealing, light rays do not enter under the gate electrode, so that the area under the gate electrode cannot be crystallized. However, if the semiconductor region is thick, the laser light wraps around due to the diffraction of light rays and crystallization progresses. The degree of wraparound of laser light is about the wavelength of the laser when the thickness of the semiconductor region is larger than the wavelength of the laser, and about the thickness of the semiconductor region when the thickness of the semiconductor region is smaller than the wavelength of the laser. is there. When the thickness of the semiconductor region is 30 nm, which is remarkably smaller than the wavelength of the laser beam (248 nm) as in this embodiment, the degree of wraparound is sufficiently smaller than the width (10 μm) of the gate electrode. .. Therefore, there is a portion where the crystallinity cannot be recovered even by this laser annealing, even though it becomes amorphous by the ion implantation. The significance of that part will be described later.

As described above, the structure of the CMOS type TFT was mostly obtained. After that, metal wiring may be formed on this TFT, but unlike the conventional TFT, it is extremely easy because the labor of forming the source and drain electrode holes can be omitted. That is, since the semiconductor region is already exposed,
An ohmic junction can be obtained only by forming a metal film of aluminum or the like on it. Therefore, for example, after forming a multilayer film of aluminum or aluminum and chromium 163 as shown in FIG. 10 as a whole, unnecessary portions are etched by a known photolithography method to form second wirings 160a and 160b, 161 or the like may be formed.

Alternatively, if the element does not require a high degree of accuracy, these wirings may be directly formed by a vacuum evaporation method or the like using a metal mask. After that, FIG.
As shown in (D), the film 162 of the pixel electrode of the liquid crystal display was selectively formed to form a liquid crystal pixel.

The number of masks used in the above steps is
Five sheets are used for forming the semiconductor region 153, forming the gate electrode / wiring, forming the photoresist 157, forming the second wiring, and forming the pixel electrode. Further, paying attention to the TFT of the present embodiment, in addition to the normal impurity region 164, there is an offset region due to a geometrical shift between the gate electrode and the impurity region, and an amorphous region between the gate electrode and the impurity region is formed. A doped region 165 is formed. As for the usefulness of providing such an amorphous portion, the inventors of the present invention filed “Insulated gate type semiconductor device and its fabrication” filed on Aug. 26, 1991 by Semiconductor Energy Laboratory Co., Ltd. The method ”is described in detail here, and is omitted here.

A polyimide film was formed as an alignment film of a liquid crystal material on the substrate manufactured by the above steps (hereinafter referred to as the first substrate). The surface of this polyimide film is treated by a known rubbing method, a transparent electrode is formed on the other second substrate, and then an alignment film is formed in the same manner as the first substrate,
Rubbed. A liquid crystal cell was produced by laminating these substrates so that the rubbing directions were parallel to each other.

After that, a nematic liquid crystal material is injected into this liquid crystal cell so that two modification numbers are arranged so that the polarization axes are crossed Nicols on both sides of this liquid crystal cell, and the rubbing direction of both substrates is 45 degrees. The liquid crystal electro-optical device was completed by pasting in the direction of the angle. This NON-TWISTED-NEMATIC
In the type liquid crystal electro-optical device, bright (white) is displayed due to the birefringence of the liquid crystal material when off, and dark (black) is displayed when on because the liquid crystal molecules stand in the direction perpendicular to the substrate. The semiconductor device of the present invention can be applied not only to the liquid crystal electro-optical device described above, but also to other types of liquid crystal electro-optical device, for example, an antiferroelectric liquid crystal electro-optical device.
Furthermore, it can be applied to other electric and electronic devices.

[0074]

According to the present invention, a TFT can be manufactured with a smaller number of masks than the conventional one. Further, according to the present invention, a more reliable TFT can be manufactured although the number of masks is the same as the conventional one. In particular, an object of the present invention is to improve the yield of TFT. In particular, the formation of the source and drain electrodes of the TFT
This is an advanced work that requires an accuracy of 1 μm or less, and the number of defective panels generated in this step was significantly larger than that in other steps.

Then, the number of defects is T
It increased as the amount of FT increased, and as the panel area increased. That is, both the drilling of the electrodes and the formation of the electrode wiring required extremely high technology. According to the present invention, for example, it is not necessary to make holes in the electrodes, so that the yield is mainly formed of the electrode wiring. For example, if the defective occurrence rates of the hole formation and the electrode wiring formation are both 20%, the quality of the good product is only 64% when these two steps are performed. Since no process is required, 80% are non-defective products.

On the other hand, especially in a liquid crystal display,
The occurrence of defects due to a short circuit between the gate wiring and the signal wiring (source and drain wiring) has been a serious problem. This was a defect directly caused by a handling problem, but indirectly, it is considered to be a defect of the interlayer insulator. That is, the silicon oxide used as an interlayer insulator cannot completely cover the undulations of the wiring, and a thick portion or a thin portion occurs in the thickness. Especially, the film is not formed on the side surface of the gate wiring which is the lower wiring. It has become thin. On the other hand, a film having a sufficient thickness was formed on the upper surface of the lower wiring. When the upper wiring was formed in this state, a short circuit was likely to occur on the side surface of the lower wiring. However, according to the present invention, since the anodized insulating film having substantially the same thickness on the side surface and the upper surface of the lower wiring can be formed, such a problem is solved. The insulating effect can be further enhanced by forming an interlayer insulating film in the conventional manner after forming the anodized insulating film.

[Brief description of drawings]

FIG. 1 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 2 shows an example of a pixel of a liquid crystal display manufactured according to the present invention.

FIG. 3 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 4 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 5 shows an example of a pixel of a liquid crystal display manufactured according to the present invention.

FIG. 6 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 7 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 8 shows an example of a manufacturing process of a TFT according to the present invention.

FIG. 9 shows an example of manufacturing a liquid crystal display panel according to the present invention.

FIG. 10 shows a manufacturing process of a TFT according to this embodiment.

[Explanation of symbols]

 101 Insulating Substrate 102 Passivation Film 103 Semiconductor Region 104 Gate Insulating Film 105 First Wiring (Gate Wiring) 106 Gate Electrode 107 First Wiring (Storage Capacitance Wiring) 108 Impurity Region 109 Anodized Insulating Film 110 Second Wiring ( Drain electrode / wiring) 111 Second wiring (source electrode / wiring) 112 Pixel electrode / wiring

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Uochi 398 Hase, Atsugi City, Kanagawa Prefecture Semiconductor Conductor Research Institute Co., Ltd.

Claims (8)

[Claims] 1. A semiconductor film formed on a substrate having an insulating surface, an insulating film formed on the semiconductor film, and a material formed on the insulating film and having an upper surface and a side surface containing a metal oxide as a main component. A thin film transistor having a covered metal gate electrode as a main component, an insulating film made of the same material as the insulating film formed on a substrate, and made of the same material as the gate electrode formed thereon, First, it has a wiring covered with a material containing a metal oxide as a main component and connected to a gate electrode, and a drain wiring formed on the material containing the metal oxide as a main component of the wiring. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the material containing aluminum oxide as a main component is formed by an anodic oxidation method. 3. The semiconductor according to claim 1, wherein the gate electrode is made of aluminum, titanium, tantalum, aluminum silicide, titanium silicide, tantalum silicide, aluminum compound, titanium compound or tantalum compound. Integrated circuit. 4. The semiconductor integrated circuit according to claim 1, wherein the substrate having the insulating surface is a glass substrate. 5. The semiconductor integrated circuit according to claim 1, wherein the substrate having the insulating surface is a substrate provided with an insulating film on a silicon wafer. 6. The semiconductor integrated circuit according to claim 1, wherein the gate electrode is composed of a silicon film or a metal multilayer. 7. The semiconductor integrated circuit according to claim 7, wherein the silicon film is mixed with phosphorus and has a thickness of 20 to 500 Å. 8. A step of selectively forming a semiconductor film on an insulating substrate, and selecting an insulating film on the semiconductor film and the insulating substrate and a first film containing a metal as a main component on the insulating film. Forming step, oxidizing the surface of the first film, and forming a second metal film on the first film.