CN100388443C - Method for fabricating a thin film semiconductor device - Google Patents
Method for fabricating a thin film semiconductor device Download PDFInfo
- Publication number
- CN100388443C CN100388443C CNB2004100082826A CN200410008282A CN100388443C CN 100388443 C CN100388443 C CN 100388443C CN B2004100082826 A CNB2004100082826 A CN B2004100082826A CN 200410008282 A CN200410008282 A CN 200410008282A CN 100388443 C CN100388443 C CN 100388443C
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- film
- interconnection
- semiconductor film
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.
Description
The present invention relates to a kind of semiconductor device or semiconductor integrated circuit on the insulating substrate of being formed on of high reliability, it also can be produced in batches with high finished product rate.The invention still further relates to the manufacture method of this semiconductor device or semiconductor integrated circuit.The present invention can be used for liquid crystal display drive circuit or film image sensor drive circuit, also can be used for three dimensional integrated circuits.
In recent years, be to reduce the parasitic capacitance between substrate and the conductive interconnection, improving operating rate, people seek on the insulating substrate made from glass or sapphire and form semiconductor integrated circuit.Especially glass material is quartzy such as using, and does not resemble silicon chip, can added limitations to the size of substrate.And glass material is cheap again, and in addition, it is easy to cause the isolation between device.Also have, under the situation of CMOS monolithic integrated circuit, the breech lock problem can not occur.Except these reasons, liquid crystal display or close touching under the type image sensor situation, the integrated device of partly leading will be with liquid crystal device (element) or light-sensitive device (element).Therefore, need be produced on thin-film transistor (TFT) on transparent plate or the substrate.
Cause thus, thin-film semiconductor device once was produced on the insulating substrate.Yet common thin-film semiconductor device is with forming semiconductor integrated circuit or the same manufacturing step of monolithic integrated circuit, be produced on the Semiconductor substrate, thereby needs considerable mask plate when making.In conventional monolithic integrated circuit, quite superior as the monocrystalline silicon reliability aspect of substrate, and be difficult to heat-treated distortion or other puzzlements.So rare aligning mistake of mask alignment technology.
Though general commercial insulating substrate is lower than silicon substrate aspect reliability.Especially, by the substrate heat treated distortion difficult to calculate that glass is made, consequently the mask of designing fails to be fit to substrate.So, mask alignment technology is difficult to carry out often.
Here the liquid crystal display device that will make or similar device need to make a kind of integrated circuit more much bigger than existing integrated circuit area, and this will be the mask alignment process complications.So a requirement that reduces mask alignment operation number of times is just arranged.
An object of the present invention is to provide a kind of on insulating substrate, to reduce mask alignment technology several times and form the method for semiconductor device or integrated circuit.
Another object of the present invention provides a kind ofly promotes that rate of finished products is improved reliability and the method that forms semiconductor device or integrated circuit.
A further object of the invention provides a kind of wherein the have semiconductor device or the integrated circuit of short loop slightly.
One integrated circuit is made on the insulating substrate, and the electrostatic breakdown of device often becomes a problem, produces on the insulating substrate because static is everlasting, and is difficult to eliminate these static.Particularly under the situation of the variant interlayer electrostatic breakdown of conductive interconnection, under the situation as liquid crystal display, partial breakdown and damaged delegation and row.But, can not compensate the function of broken parts with other parts unlike semiconductor memory.That therefore causes is very harmful.
By introducing a kind of course of processing of technology before that is different from fully, the invention solves the problem that is run into.Specifically, by adopting the oxide that forms by following conductive interconnection layer oxidation partly or entirely to replace employed interlayer insulating film in the integrated circuit of technology before, thereby reduced the number of times of mask alignment operation, or improved the voltage-resistance characteristic of numerous conductive interconnection interlayers.
Other purpose of the present invention and characteristics will be expressed by following narration.
Fig. 1 (A)-(E) is the profile according to thin-film transistor of the present invention, is used for illustrating this transistorized several successive step of manufacturing.
Fig. 2 is the graphic extension of a pixel of LCD made in accordance with the present invention.
Fig. 3 (A)-(D) is the profile according to another kind of thin-film transistor of the present invention, is used for illustrating this transistorized several successive step of manufacturing.
Fig. 4 (A)-(D) is the profile according to another thin-film transistor of the present invention, is used for illustrating the step of making this transistorized several successive.
Fig. 5 is the graphic extension according to a pixel of another kind of LCD of the present invention.
Fig. 6 (A)-(D) is the profile according to another thin-film transistor of the present invention, is used for illustrating the several successive step of carrying out this transistor manufacturing.
Fig. 7 (A)-(D) is the profile according to another thin-film transistor of the present invention, is used for illustrating the several successive step of carrying out this transistor manufacturing.
Fig. 8 (A)-(D) is the profile of another kind of thin-film transistor, is used for illustrating the several successive step of carrying out this transistor manufacturing.
Fig. 9 (A)-(B) is the graphic extension of making the several successive step of liquid display panel according to the present invention.
Figure 10 (A)-(D) is the profile according to further thin-film transistor of the present invention, is used for illustrating the step of the several successive that this transistor is made.
Referring to Fig. 1 (A)-(E), on the insulating surface of a substrate 101, at first form a silicon oxide film 102, as passivating film.The thickness of this silicon oxide film 102 is 100 to 1000nm.Form the semiconductor film on the silicon oxide film again.Passivating film plays and prevents removable ion, as sodium ion, move to the semiconductor region that is covered with from substrate, otherwise semi-conductive characteristic can worsen.This passivating film for example can comprise single or multiple lift silicon nitride, silica and aluminium oxide.When the quantity of the enough height of purity of substrate and removable ion after a little while, just needn't form this passivating film.This semiconductor film can be amorphous silicon, polysilicon or microcrystal silicon.This semiconductor film forms semiconductor district 103 through corrosion.
One dielectric film is formed on this substrate (insulating surface of substrate) and the semiconductor region 103.Because this dielectric film will be as gate insulating film, this just requires the interfacial characteristics of this film and beneath semiconductor region good, and dielectric film only contains and can form the carrier traps center and defective interface energy level on a small quantity.For example, dielectric film is preferably formed as silicon oxide film with ECR CVD method, and this dielectric film also can be made up of the overlapping multilayer insulating film of each top layer.The thickness of this dielectric film will be considered as the actual conditions of gate insulating film and be determined.Generally, thickness 50 and 500nm between.So just obtain a kind of lamination shown in Fig. 1 (A).
Then, on dielectric film, form a metal or metal silicide film, as mainly containing the film of aluminium.If this metal or metal silicide film, or by fine aluminium, or form by impure hardly aluminium, so, just can not reach enough intensity.Such lamination is as running into electromigratory mechanical force with regard to sensitive for damages, so film will be added the silicon manufacturing of 1-10% by aluminium.Titanium, tantalum or its composition can be used to substitution of Al.And oxidation film forms with these metals of anodic oxidation, and these oxidation films have good voltage-resistance characteristic.Should expect when selecting used metal that titanium oxide and tantalum oxide have the much bigger dielectric constant of ratio aluminum oxide.Therefore, if interlayer insulating film is by the made that this big dielectric constant is arranged, will produce big dielectric loss so.When the selection of material, should also be noted that titanium and tantalum have the resistivity higher than aluminium.Among conductive interconnection line first, grid interconnection (wiring) will respond at a high speed, and present less static dissipative than the conductive interconnection line on upper strata.Preferablely be, grid interconnection (wiring) are manufactured from aluminium, and when as long as interconnect when not being the electric capacity effect with the storage capacitance that responds than low velocity, available tantalum or titanium manufacturing, certainly in this case, used mask number will increase by one.In this case, the metal or the metal silicide film that have formed will be removed selectively with needle drawing, and grid interconnection 105 (wirings 105 that are connected with grid) that form a gate electrode 106 on dielectric film, extend out from gate electrode and the storage capacitance of electrode for capacitors effect interconnect 107.Used electric capacity interconnection 107 is irrelevant with these grid interconnection (wiring).Gate electrode can comprise an individual layer of the one group of material formation that is selected from aluminium, titanium, tantalum, aluminum silicide, Titanium silicide and tantalum silicide composition.The multilayer that gate electrode also can be made up of the first metal layer and one second metal level of making on described the first metal layer.Further, the multilayer that can also form by the metal film of making on the silicon fiml of mixing phosphorus and the silicon fiml of gate electrode.
Yet, adopt well-known diffuse dopants method, inject or the plasma doping method such as ion, dopant atom is injected semiconductor region, form doped region 108, dopant injection period this moment, gate electrode 106 is as sheltering.So doped region forms with an autoregistration process.Resulting lamination is shown in Fig. 1 (B).
So whole lamination is immersed in a kind of suitable electrolyte, grid are interconnected, and (wiring) interconnection is connected with power supply with storage capacitance, add a DC or AC electric current, come this interconnection of oxidation (upper surface of interconnection line and side and grid) (upper surface and side) on the surface of grid interconnection (wiring), gate electrode, storage capacitor electrode etc. to form oxide-film 109 by anode oxidation method.The conductive interconnection here is by aluminium, titanium or tantalum manufacturing, and then corresponding formation is the coating of aluminium oxide, titanium oxide or tantalum oxide.These oxidation film containing metal and oxygen, and in film, also can contain the element that constitutes electrolyte, perhaps oxide film may produce hydroxide, has therefore changed physical property.For example, organic acid is as electrolyte, so will carbon containing in this oxide-film; And sulfuric acid is with being electrolyte, meeting sulfur-bearing in the oxide-film.The material of alkali metal containing ion never can be used as electrolyte, enters semiconductor region because resemble the metal ion of sodium ion and potassium ion, will seriously worsen semi-conductive conductive characteristic.
The thickness of oxide-film is determined by the voltage-resistance value of necessity.During this oxidation step, gate electrode reduces, thereby has just determined the thickness of oxide-film, also will consider the overlapping layer between grid and doped region.The thickness of general oxide-film wants 10 to 1000nm.
Here only grid interconnection (wiring) are connected with power supply, and the storage capacitance interconnection is not attached thereto, and only go up in grid interconnection (wiring) and form an oxide-film.Except that the oxide-film that has naturally, in fact do not form oxide-film in the storage capacitance interconnection.When energizing, galvanization, making alive or other index can change between these conductive interconnections.So, just can change the thickness of the oxide-film that forms.Oxide-film is used as interlayer insulating film.For the purpose of reducing the electric capacity between conductive interconnection, will increase thickness.On the other hand, oxide-film, wishes to reduce thickness in this occasion as the insulator of storage capacitance as electric capacity.By purposes situation difference, it is effective adopting above-mentioned behave.
After the conductive interconnection quilt was coated with oxide-film, this lamination was by taking out and fine drying in the electrolyte.If necessary, lamination is exposed to the open air under hot water or vapours, to improve the quality of oxide-film.Specifically, particularly obtain the occasion of thick film with anodic oxidation, resulting rete is porous.Though this film is very thick, voltage-resistance may also be unsatisfied with.That is to say, in the follow-up step, electrical short may take place by hole.In this case, oxide-film and hot water reaction form a kind of hydroxide, thereby increase volume.Its result, blocked of hole is adopted, and like this, has obtained the superior dense film of a kind of electric insulation.Under any circumstance, clean this lamination fully, remain on the tunicle to prevent electrolyte.Then, lamination is in addition dry.Resulting lamination is illustrated among Fig. 1 (C).
The surface 109 contacted coating metal layers (film) of the top oxidation of formation and metal or metal silicide, and needle drawing then become to leak interconnection and drain 110 and source electrode 111.The drain electrode be arranged on semiconductor region 103 on drain region 108 be connected.Multilayer interconnection at matrix circuit and so on, conductive interconnection as above-mentioned formation, intersect with the conductive interconnection that forms for the first time possibly, past, after forming first conductive interconnection, form interlayer insulating film with insulating material, the upper strata conductive interconnection is formed on this interlayer insulating film, but the present invention need not to form interlayer insulating film; The upper strata conductive interconnection is formed on conductive interconnection under it because beneath interconnection coated oxide-film.So processing step and prior art compare now, mask quantity can reduce one.The lamination of gained is illustrated among Fig. 1 (D).
According to the present invention, need three mask plates for obtaining the such lamination of Fig. 1 (D).First mask be in order to forming semiconductor region, and second mask is first metal interconnected in order to form, and the 3rd mask is metal interconnected in order to form second.Need four masks in the past.Secondly at first one is used to form the semiconductor district, and one is used to form first metal interconnectedly, and the 31 is used to form the source transistor electrode, promptly forms window at interlayer insulating film, and the 41 is used to form second metal interconnected.
After this, shown in Fig. 1 (E), by sputter lining layer of transparent electric conducting material, as tin indium oxide or tin oxide.This coating needle drawing is formed the pixel capacitors of LCD.Make the pixel of LCD, four of the mask numerals that needs till this processing step like this.See that as top Fig. 2 represents a pixel by the LCD of this method manufacturing.Among this figure, chain-dotted line a-b-c-d is equivalent to the line a-b-c-d of Fig. 1 (E).Fig. 1 generally illustrates the section of these points.
From Fig. 1 (E) as can be seen, each end of thin-film transistor doped region 108 does not align with each end of gate electrode, and it is not overlapping with doped region to demonstrate this grid.Distance between grid and each doped region or transfer L are 0.2 to 0.5 μ m.This constitutes characteristics of the present invention.In more detail, the embodiment of Fig. 1 is that self aligned technology is injected dopant atom formation doped region.Oxidation gate surface then, in this oxidation step, gate surface is shunk back, so this lamination has the state of transfer.Can increase the ratio of leakage current that ON state flows through and OFF leakage current like this.The problem that the electric leakage that regular meeting runs into when also quite adding the grid voltage of an opposite polarity increases can be curbed.
In the embodiment in figure 1, grid with respect to doped region have one the skew transfer from.According to the present invention, this transfer L can be set at any required value.In other words, grid can be made with doped region overlapping.Adopt ion implantation to inject the occasion of dopant atom, can inject the rescattering degree of ion by ion energy adjustment.The rescattering meeting of ion causes the sinking of dopant ion under the grid.Here it is, if the rescattering degree is bigger, so the overlapping scope of grid and doped region is also big, if reduce ion energy, contained rescattering, so just compressed overlapping.
According to the present invention, follow the oxidation grid, thereby grid is shunk back.The degree of shrinking back depends on the degree of oxidation.Therefore, can realize the transfer and the overlap condition of desired scope by the degree of control injection energy of ions and oxidation.
Storage capacitor electrode and interconnection 107 have been expressed.These electrodes and interconnection are all at the offside from their oxidation film of transparent pixel electrode 112, and this electrode and interconnection 107 will keep the identical current potential of opposite electrode with the formation of liquid crystal offside.As a result, electric capacity is in parallel with the electric capacity of the liquid crystal pixel of formation.Parasitic capacitance between the grid source of each thin-film transistor (TFT) is all very big, and during the switch gate signal, this can reduce the potential change of liquid crystal pixel.Among the embodiment of Fig. 1, oxide titanium, aluminium or tantalum constitutes medium.The dielectric constant of these materials is typical case's insulation or more than two times of dielectric material silica at least.Therefore can dwindle the area of storage capacitance, in other words, the area of the liquid crystal pixel of printing opacity part increases, and promptly numerical aperture (aperture ratio) has increased.It should be noted that LCD does not always need such storage capacitance.
Fig. 3 represents an alternative embodiment of the invention.Among the embodiment of Fig. 1, interlayer insulating film is the oxide-film of lower floor's conductive interconnection.In this case, thickness has gone out a difficult problem, because of such oxide material has big dielectric constant, can increase the electric capacity between conductive interconnection.The interlayer insulating barrier constitutes by two layers among Fig. 3, has increased thickness, just, has reduced the average medium constant, thereby reduces the electric capacity between conductive interconnection.
Press the identical method of Fig. 1 embodiment, form a passivating film 302 on the surface of insulating substrate 301.This substrate includes the monolithic integrated circuit of a Si semiconductor.The insulating surface of substrate can be the surface that is produced on the silicon oxide film on the silicon wafer.Form semiconductor district 303, then form gate oxidation films 304.Grid interconnection (wiring) 305, gate electrode 306 and storage capacitance interconnection 307 all are formed on the insulating surface with identical materials, after this, by the autoregistration ion implantation technology, inject dopant atom, form doped region 308.This secondary ion need divest all gate oxidation films, and be different from the embodiment of Fig. 1 before injecting.Obtain a kind of lamination shown in Fig. 3 (A) by this method.
Then, shown in Fig. 3 (B), the surface (lower surface and side surface) of these grid interconnection (wirings) 305, gate electrode 306 and storage capacitance interconnection 307 all gives oxidation, with the identical method of Fig. 1 embodiment, covered with the layer 309 that comprises metal oxide or metal silicide that produces as required.In after, on oxidized surface, form interbedded insulating layer 313 again.In insulating barrier 313, form a drain electrode window 314 and a source electrode window through ray 315.In addition, form to leak interconnection (wiring) 310 and formation one source electrode 311 on the layer 309 of grating routing 305 being covered with.The lamination of gained is illustrated among Fig. 3 (C), leaks interconnection (wiring) 310 in Fig. 3 (C) lining and contacts with interlayer insulating film 313.
At last, shown in Fig. 3 (D), form transparent conductive electrode 312, perhaps the electrode of pixel.So just made each pixel of LCD.In the present embodiment, the same with common process five of the mask count that overall process is used.Here it is, and first mask is in order to form semiconductor region, and second mask is in order to form grid interconnection etc., and the 3rd mask is in order to form the window in the interlayer insulating film, and the 4th mask leaks interconnection etc. in order to form, and the 5th mask is in order to form each electrode of pixel.
Among the present invention, have in grid interconnection and the crossover sites of leaking interconnection two-layer, i.e. grid interconnection oxide layer and interlayer insulating film.Especially, the oxide layer that anodic oxidation forms not only densification but also voltage-resistance characteristic is good, is suitable for very much zone isolation.Only use one deck interlayer insulating film before, therefore on voltage-resistance characteristic, go wrong.Particularly have problems at crosspoint, the step place of each conductive interconnection.Interlayer insulating film can not cover step fully, slight crack may occur, and the result is normal to be taken place and last conductive layer short circuit.In this novel method, needn't consider the defective on this step completely, this just has very big contribution for improving rate of finished products.
The embodiment that is narrated so far only is used for a kind of thin-film transistor of conductivity types.Certainly also can be used for complementary MOS transistor.Fig. 4 illustrates an embodiment of the pixel that adopts the transistorized LCD of CMOS.Use the transistorized occasion of CMOS, one or two lithography step in making a kind of conductivity type of transistor technology, must adding.Fig. 4 represents to make the manufacturing step of 5 masks of pixel needs.
At first as the identical method of preceding embodiment, on an insulating substrate 401, form passivating film 402, form semiconductor region 403a and 403b, form gate insulating film then, on gate insulating film, form metal interconnected 409 and grid 406a, 406b with aluminium in desired portion.
Above-mentioned interconnection and electrode through anodic oxidation, are oxidized to proper depth.Here, for example they are made from aluminum, and they and surface all are covered with aluminium oxide coating 409.If gate insulating film is made up of silica, that just uses 1/10 hydrofluoric acid solution, corrodes this substrate slightly, and optionally gate insulating film is removed in corrosion.At this moment, those silica parts with having covered under the aluminium oxide grid that are positioned under the grid interconnection will can not erode.Then, dopant atom is incorporated in the semiconductor region with known method.For example, the conduction type of dopant atom is the n-type.
Use other method, after grid interconnection and the gate electrode oxidation, when this gate insulating film keeps, inject dopant atom.Corrode gate insulating film then, and with aluminium oxide as mask.The result obtains a kind of similar structure, and Here it is uses shown in Fig. 4 (A).
In the embodiment of Fig. 1 and Fig. 3, just inject dopant atom prior to conductive interconnection and electrode surface oxidation.Among the embodiment of Fig. 1, remove gate insulating film prior to surface oxidation.Therefore as canonical representation at Fig. 1 (C), the umbrella shape of aluminium oxide is partly stayed the surface of conductive interconnection and electrode.If the thickness of aluminium oxide is 500nm, produce the extension that roughly is about 250nm.In conductive interconnection formed subsequently, the umbrella shape part can produce the space, causes the problem of conductive interconnection fracture.But in the example of Fig. 4, the space of generation is less, so the problem of the fracture of can avoiding interconnecting.
Then, with material 407,, cover the semiconductor region 403a that stays such as carving the mask material earlier.In this case, inject P-type dopant atom.Obtain n-type doped region 408a and p-type doped region 408b at last, the lamination of gained is shown in Fig. 4 (B).
Except that these fabrication portion, can also implement following steps.Do not add stage of alloy at semiconductor region, at first with photoresist and so on coating semiconductor district 403b allows n-type dopant only be injected into semiconductor region 403a, then covers this semiconductor region 403a.Only p-type dopant is incorporated among the semiconductor region 403b then.But when adopting the method, compare with the method for Fig. 4, mask need have another one.
Press the identical mode of Fig. 1 embodiment subsequently, form metal interconnected and electrode 410a, 410b, 411, produce the structure of Fig. 4 (C), form a pixel capacitors 412 then, the result derives the being seen a kind of structure of Fig. 4 (D).
Fig. 5 is the top view by the pixel of a LCD of above-mentioned steps manufacturing.In the present embodiment, the part of this grid interconnection 405 or contiguous grid interconnection 405 embeds under the pixel capacitors 412.Formed an electric capacity between them, this electric capacity plays Fig. 2 storage capacitance and similarly acts on.Dotted line a, the b of Fig. 5 and c are equivalent to chain-dotted line a, b and the c of Fig. 4 (D).Fig. 4 is the sectional view that expression is made along chain-dotted line.
In the foregoing description, cmos device is taked inverter structure, this cmos device also can be envisioned for buffer structure, the transfer gate structure then record and narrate the Japanese patent application series number 145642/1991,145643/1991,145566/1991,157502/1991,157503/1991,157504/1991,157505/1991,157506/1991 that the applicant and other people propose and 157507/1991 or the improvement of these structures among.
The mask number that produces these structures is 5, first mask is used to form semiconductor region, and second mask is used to form grid and interconnection thereof, and the 3rd mask is used to form P-type doped region, it is second metal interconnected that the 4th mask is used to form, and the 5th mask is used to form pixel capacitors.Common process then needs 6 masks, first mask is used to form semiconductor region, second mask is used to form grid and interconnection thereof, the 3rd mask is used to form P-type doped region, the 4th mask is used to form the window of each electrode interlayer insulating film, it is second metal interconnected that the 5th mask is used to form, and the 6th mask is used to form pixel capacitors.
Fig. 6 illustrates the method for the manufacturing CMOS structure of another kind of novelty.Set out with the manufacture method that aforesaid Fig. 3 and 5 links mutually, will be more readily understood this new method.If 1 considers to have only metal interconnected anode oxide film 609 in the present embodiment, the cross-level thickness that is used for first interconnection, the 605 and second interconnection 610a is just thick inadequately, and the electric capacity between interconnection can be too big, so form one deck interlayer insulating film 613 additional mask.First mask is used to form semiconductor region 603a, 603b, second mask is used to form grid interconnection and gate electrode 605,606a, 606b, the 3rd mask is used to form photoresist layer 607, the 4th mask is used to form window 614a, the 614b, 615 on interlayer insulating film of each electrode, the 5th mask is used to form second metal interconnected and electrode 610a, 610b, 611, the six masks and is used to form this pixel capacitors 612.The used minimum mask piece of this mask number of modules and conventional manufacture method is the same.But, except that the CMOS structure, obtained can reach high finished product rate with the obtained same advantage of manufacture method shown in Figure 3.
Fig. 7 illustrates an alternative embodiment of the invention, in Fig. 1,3, these embodiment of 4 and 6, the thickness of the interlayer insulating film between the levels interconnection is substantially equal to the thickness of insulating barrier between storage capacitance interconnection and pixel capacitors, to increase the former thickness for well, and be excellent with the thickness that reduces the latter, the method for Fig. 7 just can satisfy the requirement of this contradiction.
The same with the method for Fig. 1 embodiment, on insulating substrate 710, form one deck passivating film 702.Form semiconductor region 703, then form gate oxidation films 704 again.After this form grid interconnection 705, grid 706 and storage capacitance 707.By the surface of these interconnection of anode oxidation method oxidation with electrode, shelter with this oxide-film 709, remove gate insulating film.Then just with grid as sheltering, inject dopant ion with the autoregistration ion implantation, like this formation zone 708 of having mixed.Gate insulating film also can stay later on.In this case, obtain a kind of structure of Fig. 7 (A) expression.
Secondly, shown in Fig. 7 (B), form the electrode 712 of a pixel.Shown in Fig. 7 (C), form interbedded insulating layer 713.On these interlayer insulating films 713, be formed for the window 714 of source, drain electrode.Form one again and leak interconnection 710, obtain the lamination shown in Fig. 7 (D).
Have in each pixel of LCD of this spline structure, the interlayer insulating film of each conductive interconnection infall is thicker, and the dielectric layer of storage capacitance interconnection is thinner.Being used to make the mask plate number of said these steps, is 5 so far.First mask is used to form semiconductor region, second mask is used to form grid interconnection and electrode thereof, the 3rd mask is used to form pixel capacitors, and the 4th mask is used to form the window on the interlayer insulating film of electrode, and the 5th mask is used to form metal interconnected.
In this structure, work the last metal interconnected pixel capacitors that is covered with of leaking the interconnection effect.The result is when forming the electrode on opposite, and the electric field that leaks interconnection is stronger, the electric field of this pixel capacitors then a little less than.Keep under the operate as normal-signal is applied to Lou in the interconnection.So even it is less to leak the area that interconnection takies, because of high voltage be added to interconnection with Louing go up the image of consideration to continue unchangeably formation becomes clear or dark condition, thereby image is subjected to very big influence.And owing to transmitted the information that the signal of this leakage interconnection comprises other pixels, a kind of phenomenon of similar cross-talk has taken place.Therefore when adopting Fig. 7 structure, for this point should be enough attention.For example need TFT (thin-film transistor) base plate is installed in the front, or on other device of expecting.Always be in shade and invisible place because leak interconnection, be added to the impression that signal on Lou interconnecting can not influence vision.
Storage capacitance interconnection among Fig. 1 and 3 embodiment leans against below the pixel capacitors, and therefore pixel capacitors out-of-flatness, and this just makes that the electric field strength in the same pixel capacitors is inhomogeneous, and the width of interconnection is also different slightly.Therefore each pixel do the same height, to reach more uniform each pixel characteristic is arranged, a kind of method of Fig. 8 explanation satisfies these requirements fully.
Press the same quadrat method of Fig. 1 and 7 embodiment, on insulating substrate 801, form passivating film 802.Form semiconductor region 803, then form gate oxidation films 804.After this form grid interconnection 805, gate electrode 806 and storage capacitance interconnection 807.The surface of these interconnection and electrode is through the anode oxidation method oxidation.Make mask with oxide-film 809, remove gate insulating film.When making mask, inject dopant ion then, and form doped region 808 with the autocollimatic ion implantation with grid.Gate oxidation films also can stay afterwards.Obtain a kind of structure shown in Fig. 8 (A) like this.
Then, shown in Fig. 8 (B), form and leak interconnection 810.By organic material, such as polyimides, form smooth coating 813, shown in Fig. 8 (C).At last, form source electrode window through ray 815 and pixel capacitors 812, the structural table of gained is shown among Fig. 8 (D).
Till said step, used mask piece number is 5, first mask is used to form semiconductor region, second mask is used to form grid interconnection and electrode thereof, the 3rd mask is used to form metal interconnected, the 4th mask is used to form the window of electrode on interlayer insulating film, and the 5th mask is used to form pixel capacitors.In this way, the present invention can make the semiconductor device that is suitable for various different purposes.
According to the present invention, anodic oxidation can be used as a kind of means and is used for oxidized metal interconnection.But this anodic oxidation in electrolyte anode and negative electrode between making alive 50 to more than the 200V.Sometimes with producing the giant electric potential gradient that surpasses 10MV/cm around the oxidized metal interconnected and electrode of anode oxidation method.Therefore must can resist such high voltage by the grill-protected dielectric film.Require semiconductor region is placed and grid interconnection and the identical current potential of electrode for this reason.
Fig. 9 illustrates a kind of method that reaches this purpose.At first on an insulating substrate 901, form the semiconductor region 903 of bar shaped.Form gate insulating film on the semiconductor region again.On each gate insulating film of holding of semiconductor region, form window 916 again.Form grid interconnection and gate electrode 905.Here it is, the current potential of semiconductor region 903 remained on the current potential identical with grid interconnection and gate electrode 905 through window 916.Use these surfaces of anode oxidation method oxidation then, can not produce electric field basically between semiconductor region and the grid interconnection/electrode like this.Therefore unlikely have an extra voltage to be applied on the gate insulating film and damage this film.This situation is seen Fig. 9 (A).
Anodic oxidation finishes, and injects dopant atom.The semiconductor region of this bar shaped is divided into suitable length.On the oxide-film that forms in the grid interconnection, make window 917.Form then and leak interconnection and drain electrode 910.This kind situation, grid interconnection 905 just remain on the identical current potential with leaking interconnection 910, and its result just can prevent that the static that produces because of work from puncturing on grid interconnection and the dielectric that leaks the infall that interconnects.Also mean, this making step, during anodic oxidation, irrelevant with the high voltage that adds.Then, after the metal interconnecting wires around removing, form pixel capacitors 912.
In the technical process on top, need lithography step to form window to connect conductive interconnection.The precision of this step far is inferior to the precision that forms the pixel step, is unlikely the reduction rate of finished products so add this lithography step.Just the oxide-film on surface evaporates with laser beam possibly.If so, this makes just extremely easy.
Press Fig. 9 method, the mask number of usefulness is 7.Here it is, first mask is used to form strip-shaped semiconductor region, second mask is used to form the window on gate insulating film, the 3rd mask is used to form grid interconnection and gate electrode, the 4th mask is used to cut apart strip-shaped semiconductor region, the 5th mask is used to form the window on oxide-film, and the 6th mask is used to form Lou interconnection and drain electrode, and the 7th mask is used to form pixel capacitors.Be the same structure of generation in this case, need more mask plate than the technical process of Fig. 1.This second and the 4th mask plate does not need high accuracy as mentioned above, and can be understood as in fact needs five mask plates.Promptly the method than Fig. 1 only needs the mask plates of Duoing.
Referring now to Figure 10,, embodiments of the invention 1 is described.Apply the present invention to make on the AN glass substrate CMOS TFT.At first press shown in Figure 10 (A), on AN glass substrate 151, form the silicon oxide film 152a of thick 100nm with the low pressure chemical vapor deposition method.In the low pressure chemical vapor deposition method, unstrpped gas adopts dichlorosilane (SiH
2Cl
2) and ammonia, air pressure is 10 to 1000pa, temperature is 500-800 ℃, with 550 to 750 ℃ for well.Certainly, silane (SiH
4) or trichlorosilane (SiHCl
3) also can use.Except that the low pressure chemical vapor deposition method, other CVD technology all can be used such as plasma CVD, the light CVD of association or plasma-enhanced CVD etc.
The silicon nitride film that this method forms can stop glass substrate to contain removable ion, as sodium ion and so on.Enter semiconductor.If therefore the quantity of removable ion is quite few on the substrate, then needn't make silicon nitride film.The also available pellumina of this silicon nitride film substitutes.Desire forms pellumina, and aforesaid low pressure chemical vapor deposition method will be used trimethyl aluminium (Al (CH
3)
3) and a kind of oxidizing gas, as oxygen or nitrous oxide (N
2O).Adopt other CVD technology, also available materials similar.Also have, silicon nitride film can form with sputtering method.
In the figure, silicon nitride film only forms on the glass substrate surface that forms device.Because following reason, best whole glass substrate is covered by within the silicon nitride film.In anodic oxidation step subsequently, this substrate will be immersed in the electrolyte.If glass substrate has exposed part, so the basic ion in the solution is dissociated by these exposed positions and adheres to or enter semiconductor region.
Then, forming thickness is the silicon oxide film 152b of 70nm.ECR plasma CVD or sputtering method all are suitable for doing this film very much.The semiconductor district just is formed on this silicon oxide film.If numerous interface energy levels and many traps center appear on the interface of silicon oxide film and semiconductor region, the conductivity of semiconductor region just can not be controlled so, and this can worsen characteristics of transistor.To give enough attentions so make silicon oxide film, should expect that silicon nitride can not replace by oxidized silicon, because silicon nitride film self is usually captured charge carrier.
Our research discloses, and the silicon oxide film that forms with ECR plasma CVD method or sputtering method has very little interface energy level density, therefore extremely is fit to this purposes.Especially, sputtering method is manufactured the occasion of silicon oxide film, and when a silica is used as target, atmosphere is the mist of oxygen and argon, and oxygen content is to form in 50～100% o'clock, by overlay film good characteristic is arranged.Produce the occasion of this film by the ECR plasma CVD method, should use silane (SiH
4) and oxygen, be about 10 by the silicon oxide film of this method formation and the semiconductor that forms subsequently by the interface energy level density between overlay film or the silicon fiml
11Cm
-2, this is a quite good density.When forming by overlay film with sputter or ECR plasma CVD method.If add 1-5% hydrogen chloride, hydrogen fluoride and so in the atmosphere, perhaps add the 1-10% silane of chloride or fluorine, such as dichlorosilane or silicon tetrafluoride (SiH
4), so, chlorine or fluorine will be introduced into silica by in the overlay film.Therefore the silicon atom of the silicon-oxygen key of the atom of this introducing and the azygous position of terminal (dangling bonds) is strong securely closes.Can further reduce interface energy level like this, for example be reduced to 5 to 9 * 10
10Cm
-2
Then, having formed thickness with the low pressure chemical vapor deposition method is that the silicon of 30nm is by overlay film.Use the silane that surpasses 6N, such as SiH
4, Si
2H
6Or Si
9H
8Do the silicon source.Mixed without dopant by overlay film.But when making CMOS, as require NMOS to equate basically, so just the diborane (B of trace with the threshold voltage of PMOS
2H
6) add in the unstrpped gas, so that its boracic density is 10
15To 10
16Cm
-3Change a kind of method dopant ion, as BF
2_ +After forming silicon fiml, inject wherein.
The all available continuous film forming multicell film forming device of these three kinds of films is made, and need not the substrate exposed to weather.Especially a kind of continuous film forming system that can protect the interface not stain concerning making thin-film transistor, is indispensable, because semi-conductive interfacial characteristics is important.
Use well-known method photoengraving pattern then, make silicon be formed a p-ditch TFT district 153a and a n-ditch TFT district 153b by overlay film.This is stacked in the nitrogen atmosphere and annealed 24 to 72 hours under 600 ℃, makes TFT district crystallization.The silicon oxide film 154 that then aforesaid sputter or ECR plasma CVD method have formed becomes gate insulating film.Be similar to above-mentioned silica by overlay film 152b, this silica is also very important by the interfacial characteristics of overlay film and semiconductor region, so want superfine heart to make this layer by overlay film, this layer is 100nm by the thickness of overlay film.
After this, forming thick through electron beam evaporation is that the aluminium of 0.8 to 1.0 μ m is by overlay film.Also available sputter of this film or metallorganic CVD method form.With known method the aluminium film is carved into figure, forms grid 156a, 156b and grid interconnection (wiring) 155.Just so, obtain a kind of lamination shown in Figure 10 (A).The width of this gate electrode is 10 μ m.
With the surface of anode oxidation method oxidation gate electrode and grid interconnection, the aluminium oxide that forms thick 0.3 to 0.5 μ m is by overlay film then.Describe hereinafter now and implement anodised method, should notice that the following value that provides only is giving an example of constituting.Best value should be by the size of devices that will make and other factors decision.Here it is, and the following numerical value that provides only is to limit scope of the present invention.Make at first that to contain basic ion concentration be 0.1 to 10%, for example 3%.With 1-20%, the ammoniacal liquor as 10% is added in the tartaric acid, and PH is transferred to 7 ± 0.5 then.
One platinum electrode is used as negative electrode and puts into this solution, more whole lamination is immersed in the solution, and on-chip grid interconnection and gate electrode are connected to the anode of DC power supply.At first, supply with the constant current of 2mA.Voltage between anode and negative electrode or the platinum electrode also changes with the concentration of solution in time, and this depends on the thickness of the oxide-film that forms in gate electrode and grid interconnection, and the thickness with oxide-film increases needs-higher voltage usually.The electric current that keeps power supply in this way: voltage is behind 150V, and voltage has just remained unchanged.After electric current is added to 0.1mA, keep the electric current of this supply, constant current state continues about 50 minutes.Pressure constant state then continues 2 hours.Formed the pellumina 159 of thickness 0.3 to 0.5 μ m on the surface of gate electrode and grid interconnection.The pellumina of this formation does not need any processing, and is just enough fine and close.For strengthening electrical isolation capabilities, will be stacked in hot bubbly water 10 minutes.By this step formed can anti-high voltage 6 to 12MV/Cm by overlay film.This information slip is shown among Figure 10 (B).
Then, lamination is immersed in the hydrofluoric acid solution hydrofluoric acid as 1/10, so that corrosion oxidation silicon fiml 154, and expose on the semiconductor region surface, because aluminium oxide is insoluble to hydrofluoric acid, those silicon oxide film parts under gate electrode and grid interconnection just can not be corroded.Stay grid interconnection (wiring) 155 and gate electrode 156a and the beneath silica 154 of 156b.The silicon oxide film that stays under this grid interconnection (wiring) 155 contains the silica identical materials that stays with gate electrode 156a and 156b, and it just is formed between substrate (insulating substrate surface) and grid interconnection (wiring) 155.But if this lamination is placed in the hydrofluoric acid for a long time, even gate electrode and grid interconnection these silicon oxide films down partly also can be dissolved fall.
Then, use known ion implantation, with 10
18Atom/Cm
3Concentration inject boron or boride, for example BF
2_ +Ion.At this moment except that the ion that is subjected to rescattering, be positioned at semiconductor portions under the grid and do not have and inject ion and enter.Be that doped region can enough self aligned technical processs form.So, just formed P-type doped region 158a.
Secondly shown in Figure 10 (C), 157 coating semiconductor district 153a with photoresist; Only expose semiconductor region 153b.With this understanding with 10
20Atom/Cm
3Concentration inject phosphonium ion.There has been the boron ion in semiconductor region 153b, but phosphonium ion will surpass the boron ion concentration.Mix so this district is the n-type, obtain n-type doped region 158b.By this method, dopant ion can inject semiconductor region.In this doped region, because the bombardment that ion injects makes distortion of lattice.Therefore this doped region is envisioned for a kind of noncrystalline state, comprises the crystallite attitude, perhaps becomes a kind of admixture of this two states.Owing to also do not find any appropriate vocabulary of describing this state, be referred to as amorphous state here.
Again secondly,, remove photoresist,, shine such as the laser emission of excimer laser or argon ion laser and to make its annealing on the lamination from a laser.Here adopting a kind of KrF excimer laser of launching laser pulse wavelength 248nm, pulse duration 10nsec, is 150 to 250mJ/Cm if energy density takes place
2, as 210mJ/Cm
2Laser emission shine for 10 times, can realize crystallization for certain so fully.Number is less than this value if shine, and because of the uncontrollable fluctuation and the variation of laser output, crystallization can be inhomogeneous, and under this laser annealing, laser emission is shone less than the part that is positioned under the grid, so these parts can not form crystallization.But thicker as semiconductor region, with the diffraction of radiation, the geometrical shadow district of lamination has been arrived in laser emission, thereby can carry out crystallization.The thickness of semiconductor region is greater than the place of laser radiation wavelength, and the range of diffraction of laser emission is about optical maser wavelength partly; The thickness of semiconductor region is less than the place of optical maser wavelength, and the scope of diffraction is approximately equal to the thickness of semiconductor region.In the present embodiment, semiconductor region thickness is 30nm, much smaller than the wavelength 248nm of laser emission.Therefore the scope of diffraction is much smaller than the width 10 μ m of gate electrode.If, can not make some regional crystallization in this district with laser annealing so produced amorphous area with the ion injection.The meaning of these parts can illustrate after a while.
With such method, can produce CMOS TFT structure haply.Just need on these TFTs, form metal interconnectedly, not resemble the TFTs of prior art, needn't form again Lou, the window of drain electrode.Therefore be easy to form that these are metal interconnected, more carefully say,, just can produce ohmic contact simply by formation aluminium or other metal film on exposed position owing to exposed these semiconductor regions.Therefore lift an example, as shown in figure 10, form layer of aluminum film or multilayer aluminium and chromium film 163 on whole surface, unwanted part is fallen with the known method photoetching corrosion, forms second conductive interconnection (wiring) 160a, 160b and 161.Interconnection (wiring) 160a is the leak routing that is connected with the drain region 158a that is located at semiconductor region 153a.Interconnection (wiring) 160a contacts with the layer that is covered with grid interconnection (wiring) 155 (oxidized surface 159 in the grid interconnection 155).
Concerning not needing high-precision device, these interconnection available metal masks directly form by vacuum evaporation or other method.So shown in Figure 10 (D), requiring to form that part of of liquid crystal pixel, form be used for doing the LCD pixel capacitors by overlay film 162.
Till the mask that is used to make described step is counted to this is five.Here it is, first mask is used to form semiconductor region 153a and 153b, and second mask forms gate electrode and grid interconnection with son, and the 3rd mask is used to form photoresist layer 157, the 4th mask is used to form second conductive interconnection, and the 5th mask is used to form pixel capacitors.This TFTs has the deviate region that overlaps generation owing to gate electrode and the geometry between the doped region up and down, also has vertical dopant district 164 in addition.The doped region 165 that between this two classes doped region, also has amorphous.Form the advantage of amorphous area, at length be described in the inventor wait on August 16th, 1991 that file an application, be entitled as in the Japanese application for a patent for invention of " insulated gate semiconductor device and manufacture method thereof ", it has transferred Japanese semiconductor energy and has tested Co., Ltd (SemiConductorEnergy Laboratory Co.Ltd), so these advantages repeat no more here.
Go up the formation polyimide film at the lamination of making by these steps (after this being called first lamination).This polyimide surface polishes with cotton.Go up the transparency electrode that forms ITD (indium tin oxide) at another lamination (after this being called second lamination).Again polyimide film is produced on this ITD electrode.Polish with cotton again on the surface of polyimides.With first and second layer stack together, make the polishing direction on first lamination parallel like this, then nematic liquid crystal is injected between first and second lamination with the polishing direction on second lamination.Nicolle (Nicol) prism that after this will have the perpendicular each other polarising sheet of a pair of polarization plane is bonded in the outside of each lamination.So just finished a kind of non-nematic liquid crystal photoelectric device that reverses.The Nicol prism that will bond like this, this direction to the absorption axes of polarising sheet becomes miter angle with the polishing direction of first and second lamination.
When turn-offing, because of this non-twisted nematic liquid crystal electro-optical device display white of birefringence.And when device was opened, nematic liquid crystal stood up and present black on lamination.
People should know, the invention is not restricted to above-mentioned non-twisted nematic liquid crystal electro-optical device, and can also be applied to other liquid crystal electro-optical.For example the present invention can be used for the anti ferroelectric liquid crystal electro-optical device.
According to the present invention, can be with being that the mask plate number that lacks is made TFTs than routine, also available mask plate number same as the prior art produces more reliable TFTs with new method.
An object of the present invention is to improve the rate of finished products, the especially TFTs that make TFTs active with manufacturing of drain electrode be a kind of work that needs precision to be higher than the advanced technology of 1 μ m.This making step can cause more underproof circuit board than other step.
Along with the increase of the TFTs quantity that encapsulates on the plate with the increase of plate area, substandard products quantity also can increase, because the formation of the formation of electrode window through ray and electrode interconnection all needs very advanced technology.The present invention has saved the formation of electrode window through ray, so rate of finished products is just only relevant with the formation of electrode interconnection.Let us is imagined, and because of window forms step and the percentage that causes substandard products because of formation electrode interconnection step, the both is 20%.Two step process like this have only 64% finished product qualified.Saved the formation step of electrode window through ray according to the present invention, then qualification rate reaches 80%.
In the LCD, because grid interconnection and holding wire produce waste product such as source and the short circuit of leaking interconnection and cause serious problem.This is because of processing problems, but can think that the problem that induced by underproof interlayer insulating film directly causes.Particularly, the interlayer insulating film that is made of silica can not cover uneven conductive interconnection fully, makes it in uneven thickness, and especially this film on the side of lower-layer gate interconnection is thinner.On the other hand, form an enough thick film at the upper surface of lower interconnection.In such cases, as formed upper layer interconnects, short circuit also always appears at the place, side of lower interconnection.But, can both in fact can form the uniform dielectric film of thickness at the side and the upper surface of lower interconnection with anodised method, so above-mentioned problem has been solved according to method of the present invention.If after this dielectric oxide film forms, form conventional interlayer dielectric, electrical insulation capability also can be strengthened so.
Claims (12)
1. method of making display comprises step:
On a substrate, form first insulating barrier that comprises silicon nitride;
On described first insulating barrier, form second insulating barrier that comprises silica;
On described second insulating barrier, form the semiconductor film that comprises non-crystalline silicon;
Make described semiconductor film crystallization; And
After described crystallisation step, form the pixel capacitors that is electrically connected with described semiconductor film,
Wherein, need not described substrate is exposed among the air and forms described first insulating barrier, described second insulating barrier and described semiconductor film.
2. the method for manufacturing display according to claim 1, wherein said first insulating barrier, described second insulating barrier and described semiconductor film are all made with chemical vapor deposition method.
3. the method for manufacturing display according to claim 1, wherein said crystallisation step carries out with method for annealing.
4. method of making display comprises step:
On a substrate, form first insulating barrier that comprises silicon nitride;
On described first insulating barrier, form second insulating barrier that comprises silica;
On described second insulating barrier, form the semiconductor film that comprises non-crystalline silicon;
Make described semiconductor film crystallization; And
After described crystallisation step, form the pixel capacitors that is electrically connected with described semiconductor film,
Wherein, described first insulating barrier, described second insulating barrier and described semiconductor film form in a multi-chamber system, so that described substrate is not exposed among the air.
5. the method for manufacturing display according to claim 4, wherein said first insulating barrier, described second insulating barrier and described semiconductor film are all made with chemical vapor deposition method.
6. the method for manufacturing display according to claim 4, wherein said crystallisation step carries out with method for annealing.
7. method of making display comprises step:
On a substrate, form first insulating barrier that comprises silicon nitride;
On described first insulating barrier, form second insulating barrier that comprises silica;
On described second insulating barrier, form the semiconductor film that comprises non-crystalline silicon;
Described semiconductor film is patterned into a plurality of semiconductor islands;
Make described a plurality of semiconductor island crystallization; And
After described crystallisation step, form the pixel capacitors that is electrically connected with described semiconductor film,
Wherein, need not described substrate is exposed among the air and forms described first insulating barrier, described second insulating barrier and described semiconductor film.
8. the method for manufacturing display according to claim 7, wherein said first insulating barrier, described second insulating barrier and described semiconductor film are all made with chemical vapor deposition method.
9. the method for manufacturing display according to claim 7, wherein said crystallisation step carries out with method for annealing.
10. method of making display comprises step:
On a substrate, form first insulating barrier that comprises silicon nitride;
On described first insulating barrier, form second insulating barrier that comprises silica;
On described second insulating barrier, form the semiconductor film that comprises non-crystalline silicon;
Described semiconductor film is patterned into a plurality of semiconductor islands;
Make described a plurality of semiconductor island crystallization; And
After described crystallisation step, form the pixel capacitors that is electrically connected with described semiconductor film,
Wherein, described first insulating barrier, described second insulating barrier and described semiconductor film form in a multi-chamber system, so that described substrate is not exposed among the air.
11. the method for manufacturing display according to claim 10, wherein said first insulating barrier, described second insulating barrier and described semiconductor film are all made with chemical vapor deposition method.
12. the method for manufacturing display according to claim 10, wherein said crystallisation step carries out with method for annealing.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP273377/1991 | 1991-09-25 | ||
| JP27337791 | 1991-09-25 | ||
| JP273377/91 | 1991-09-25 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991203895A Division CN1147004C (en) | 1991-09-25 | 1999-09-17 | Method for manufacturing thin-film transistor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510008063 Division CN1652312A (en) | 1991-09-25 | 1992-09-25 | Method for fabricating a thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1525543A CN1525543A (en) | 2004-09-01 |
| CN100388443C true CN100388443C (en) | 2008-05-14 |
Family
ID=17527054
Family Applications (8)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100082826A Expired - Lifetime CN100388443C (en) | 1991-09-25 | 1992-09-25 | Method for fabricating a thin film semiconductor device |
| CN92112490A Expired - Lifetime CN1041873C (en) | 1991-09-25 | 1992-09-25 | Semiconductor device and method for forming the same |
| CNB991203933A Expired - Lifetime CN1143395C (en) | 1991-09-25 | 1992-09-25 | Semiconductor device and its associated ICs |
| CN 200510008063 Pending CN1652312A (en) | 1991-09-25 | 1992-09-25 | Method for fabricating a thin film transistor |
| CNB2006100934562A Expired - Lifetime CN100490159C (en) | 1991-09-25 | 1992-09-25 | Method for manufacturing thin-film transistor |
| CN95119391A Expired - Fee Related CN1059518C (en) | 1991-09-25 | 1995-11-25 | Semiconductor device and its related integrated circuit |
| CN 99120390 Expired - Fee Related CN1130766C (en) | 1991-09-25 | 1999-09-17 | Process for preparing thin-film transistor |
| CNB991203895A Expired - Lifetime CN1147004C (en) | 1991-09-25 | 1999-09-17 | Method for manufacturing thin-film transistor |
Family Applications After (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN92112490A Expired - Lifetime CN1041873C (en) | 1991-09-25 | 1992-09-25 | Semiconductor device and method for forming the same |
| CNB991203933A Expired - Lifetime CN1143395C (en) | 1991-09-25 | 1992-09-25 | Semiconductor device and its associated ICs |
| CN 200510008063 Pending CN1652312A (en) | 1991-09-25 | 1992-09-25 | Method for fabricating a thin film transistor |
| CNB2006100934562A Expired - Lifetime CN100490159C (en) | 1991-09-25 | 1992-09-25 | Method for manufacturing thin-film transistor |
| CN95119391A Expired - Fee Related CN1059518C (en) | 1991-09-25 | 1995-11-25 | Semiconductor device and its related integrated circuit |
| CN 99120390 Expired - Fee Related CN1130766C (en) | 1991-09-25 | 1999-09-17 | Process for preparing thin-film transistor |
| CNB991203895A Expired - Lifetime CN1147004C (en) | 1991-09-25 | 1999-09-17 | Method for manufacturing thin-film transistor |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2781706B2 (en) |
| KR (1) | KR960010931B1 (en) |
| CN (8) | CN100388443C (en) |
| TW (1) | TW258835B (en) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719065A (en) | 1993-10-01 | 1998-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device with removable spacers |
| JP3141979B2 (en) * | 1993-10-01 | 2001-03-07 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| JPH07335904A (en) | 1994-06-14 | 1995-12-22 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor integrated circuit |
| KR100291971B1 (en) | 1993-10-26 | 2001-10-24 | 야마자끼 순페이 | Substrate processing apparatus and method and thin film semiconductor device manufacturing method |
| JP3469337B2 (en) * | 1994-12-16 | 2003-11-25 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4421632B2 (en) * | 1996-01-19 | 2010-02-24 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4859266B2 (en) * | 1999-01-05 | 2012-01-25 | エルジー ディスプレイ カンパニー リミテッド | THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, AND LIQUID CRYSTAL DISPLAY DEVICE |
| SG179310A1 (en) * | 2001-02-28 | 2012-04-27 | Semiconductor Energy Lab | Semiconductor device and manufacturing method thereof |
| US7038239B2 (en) | 2002-04-09 | 2006-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| JP3989761B2 (en) | 2002-04-09 | 2007-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor display device |
| US7256421B2 (en) | 2002-05-17 | 2007-08-14 | Semiconductor Energy Laboratory, Co., Ltd. | Display device having a structure for preventing the deterioration of a light emitting device |
| KR100459733B1 (en) * | 2002-12-30 | 2004-12-03 | 삼성전자주식회사 | Interconnections having double story capping layer and method for forming the same |
| US7973313B2 (en) * | 2003-02-24 | 2011-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Thin film integrated circuit device, IC label, container comprising the thin film integrated circuit, manufacturing method of the thin film integrated circuit device, manufacturing method of the container, and management method of product having the container |
| CN100356554C (en) * | 2004-03-16 | 2007-12-19 | 私立逢甲大学 | Integrated radiating base plate and making method thereof |
| KR101043992B1 (en) * | 2004-08-12 | 2011-06-24 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of fabricating thereof |
| KR100645718B1 (en) | 2005-04-28 | 2006-11-14 | 삼성에스디아이 주식회사 | Thin Film Transistor and Method for Fabricating the Same |
| CN101621037B (en) * | 2008-07-03 | 2011-10-05 | 中芯国际集成电路制造(上海)有限公司 | Tft sas memory unit structure |
| CN102386237A (en) * | 2011-11-23 | 2012-03-21 | 深圳市华星光电技术有限公司 | Thin-film transistor, array substrate and device and preparation method |
| ITRE20110109A1 (en) | 2011-12-07 | 2013-06-08 | Redox S R L | ENERGY SAVING COFFEE MACHINE |
| CN109216437B (en) * | 2017-06-30 | 2021-08-24 | 无锡华润上华科技有限公司 | Self-aligned manufacturing method of field plate and manufacturing method of semiconductor device |
| CN110148601B (en) * | 2019-05-31 | 2022-12-20 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611258A (en) * | 1979-07-11 | 1981-02-04 | Toray Ind Inc | Installing method for lithoprinting plate to printer drum |
| JPS56111258A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Thin film semiconductor device |
| US4470852A (en) * | 1982-09-03 | 1984-09-11 | Ncr Corporation | Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions |
| JPS6233417A (en) * | 1985-08-07 | 1987-02-13 | Nec Corp | Manufacture of semiconductor device |
| US4851363A (en) * | 1986-07-11 | 1989-07-25 | General Motors Corporation | Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses |
| US4988642A (en) * | 1988-05-25 | 1991-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method, and system |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52102690A (en) * | 1976-02-25 | 1977-08-29 | Hitachi Ltd | Semiconductor capacitance device |
| JPS625662A (en) * | 1985-07-01 | 1987-01-12 | Nec Corp | Soi type high withstand voltage ic |
| JPS62104172A (en) * | 1985-10-31 | 1987-05-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH061836B2 (en) * | 1985-10-31 | 1994-01-05 | シャープ株式会社 | Thin film transistor |
| JPS6489464A (en) * | 1987-09-30 | 1989-04-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5041888A (en) * | 1989-09-18 | 1991-08-20 | General Electric Company | Insulator structure for amorphous silicon thin-film transistors |
| JPH03165575A (en) * | 1989-11-24 | 1991-07-17 | Nec Corp | Thin film transistor and manufacture thereof |
| JP2717233B2 (en) | 1991-03-06 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device and method of manufacturing the same |
| JPH04360580A (en) * | 1991-06-07 | 1992-12-14 | Casio Comput Co Ltd | Field-effect transistor and manufacture thereof |
-
1992
- 1992-09-19 JP JP27539692A patent/JP2781706B2/en not_active Expired - Lifetime
- 1992-09-23 TW TW83100884A patent/TW258835B/zh not_active IP Right Cessation
- 1992-09-25 CN CNB2004100082826A patent/CN100388443C/en not_active Expired - Lifetime
- 1992-09-25 KR KR1019920017498A patent/KR960010931B1/en not_active IP Right Cessation
- 1992-09-25 CN CN92112490A patent/CN1041873C/en not_active Expired - Lifetime
- 1992-09-25 CN CNB991203933A patent/CN1143395C/en not_active Expired - Lifetime
- 1992-09-25 CN CN 200510008063 patent/CN1652312A/en active Pending
- 1992-09-25 CN CNB2006100934562A patent/CN100490159C/en not_active Expired - Lifetime
-
1995
- 1995-11-25 CN CN95119391A patent/CN1059518C/en not_active Expired - Fee Related
-
1999
- 1999-09-17 CN CN 99120390 patent/CN1130766C/en not_active Expired - Fee Related
- 1999-09-17 CN CNB991203895A patent/CN1147004C/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611258A (en) * | 1979-07-11 | 1981-02-04 | Toray Ind Inc | Installing method for lithoprinting plate to printer drum |
| JPS56111258A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Thin film semiconductor device |
| US4470852A (en) * | 1982-09-03 | 1984-09-11 | Ncr Corporation | Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions |
| JPS6233417A (en) * | 1985-08-07 | 1987-02-13 | Nec Corp | Manufacture of semiconductor device |
| US4851363A (en) * | 1986-07-11 | 1989-07-25 | General Motors Corporation | Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses |
| US4988642A (en) * | 1988-05-25 | 1991-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method, and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1525543A (en) | 2004-09-01 |
| CN100490159C (en) | 2009-05-20 |
| CN1652312A (en) | 2005-08-10 |
| CN1254947A (en) | 2000-05-31 |
| JPH05232515A (en) | 1993-09-10 |
| CN1135095A (en) | 1996-11-06 |
| CN1909235A (en) | 2007-02-07 |
| CN1147004C (en) | 2004-04-21 |
| JP2781706B2 (en) | 1998-07-30 |
| CN1130766C (en) | 2003-12-10 |
| TW258835B (en) | 1995-10-01 |
| CN1143395C (en) | 2004-03-24 |
| CN1041873C (en) | 1999-01-27 |
| CN1254955A (en) | 2000-05-31 |
| CN1073300A (en) | 1993-06-16 |
| CN1254951A (en) | 2000-05-31 |
| CN1059518C (en) | 2000-12-13 |
| KR960010931B1 (en) | 1996-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100388443C (en) | Method for fabricating a thin film semiconductor device | |
| US6004831A (en) | Method for fabricating a thin film semiconductor device | |
| US6462403B1 (en) | Semiconductor device comprising thin film transistors having a passivation film formed thereon | |
| JP5230909B2 (en) | Method for manufacturing thin film transistor array panel | |
| CN1122314C (en) | Thin-film semiconductor device | |
| KR19980019183A (en) | Thin-Film Transistors and Method for Manufacturing the Same (THIN-FILM TRANSISTOR AND FABRICATION METHOD THEREOF) | |
| US6831333B2 (en) | Semiconductor device and method of making thereof | |
| US5897345A (en) | Semiconductor device and process for fabricating the same | |
| JPH09232586A (en) | Method of forming substrate film | |
| JPH07169973A (en) | Thin film transistor array, its manufacture, and liquid crystal device using this | |
| JP2921816B2 (en) | Active matrix substrate and manufacturing method thereof | |
| JP3390726B2 (en) | Method for manufacturing thin film transistor | |
| JPH11283923A (en) | Manufacture of thin-film semiconductor device | |
| JPH03108319A (en) | Manufacture of semiconductor device | |
| JPH10284735A (en) | Semiconductor device | |
| JPH07153962A (en) | Liquid crystal display unit | |
| JP2004336068A (en) | Method for fabricating semiconductor circuit | |
| JPH11316557A (en) | Semiconductor device | |
| JP2004282101A (en) | Semiconductor integrated circuit | |
| JPH02303134A (en) | Manufacture of semiconductor device | |
| JPH10154819A (en) | Semiconductor device | |
| JPH07128686A (en) | Liquid crystal display device and its production | |
| JP2001057433A (en) | Manufacture for thin film transistor | |
| JPH03292773A (en) | Manufacture of thin film transistor | |
| JPH04364783A (en) | Manufacture of liquid crystal drive element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20120925 Granted publication date: 20080514 |