JPH07321329A - Method for manufacturing thin film transistor and liquid display unit - Google Patents

Abstract

PURPOSE:To reduce characteristic variations and readily expand to a large area substrate by providing a technique for forming self-adjustably an electric- field mitigation region of a thin film transistor. CONSTITUTION:Gate electrodes 14, 15 of a thin film transistor are formed out of two kinds of metal or a metal compound thin film, and the wiring width of a lower layer gate electrode 14 is finely set by etching for the wiring width of an upper layer gate electrode 15. Thereafter, with the use of the gate electrode as a mask, impurities are implanted in a self-alignment manner into source and drain regions 18 of the thin film transistor. Incidentally, the film thickness of the upper layer gate electrode 15 is controlled when implanting impurities, whereby prevention capability for implanted ions are controlled and a low concentration impurity implanted region 17 is formed upon implantation of impurities into the source and drain regions 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor and a liquid crystal display device, and more particularly to reduction of leakage current of a polycrystalline silicon thin film transistor which can be used for input / output devices such as liquid crystal display devices and image sensors.

[0002]

2. Description of the Related Art In a liquid crystal display device in which a thin film transistor is integrated and in an image sensor, there is a strong demand for cost reduction as well as a technology trend of higher density. The development of thin film transistors using crystalline silicon as an active layer has been activated. Compared with amorphous silicon thin film transistors, polycrystalline silicon thin film transistors have electron mobility of two orders of magnitude or more, and while being advantageous in that devices can be miniaturized and drive circuits can be integrated on the same substrate, the thin film transistors can be turned off during standby. There is a problem that the current is larger than that of an amorphous silicon thin film transistor. In order to solve the problem of this OFF current, an offset structure and LDD (Lightly-D
The oped-drain structure has been proposed.

FIG. 7 is a process cross-sectional view showing an example of a conventional method for manufacturing a polycrystalline silicon thin film transistor, which has an LDD structure for reducing the leak current of the thin film transistor. As shown in FIG. 7 (a), an amorphous silicon thin film is formed on a translucent substrate 11 (highly heat-resistant glass substrate) by a low pressure vapor deposition method (LPCVD method), and a thin film is formed in a nitrogen atmosphere.
The amorphous silicon thin film is crystallized by performing heat treatment at 0 ° C. to form a polycrystalline silicon thin film 12. The polycrystalline silicon thin film 12 is processed into an island shape to form a silicon oxide thin film to be the gate insulating film 13. A gate electrode 15 is formed on the silicon oxide thin film.

After the gate electrode is formed, the first impurity 71 is implanted by an ion implantation method using the gate electrode 15 as a mask to form a trace impurity implantation region (n to region) 17. First
For the impurity implantation, phosphorus (P) ions are implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹³ / cm ² .

[0005]

[Outer 1]

In the second impurity implantation, phosphorus (P) ions are implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ / cm ² . After implanting the second impurity 72, the mask of the photoresist 16 is removed,
The implanted impurities are activated. Finally, as shown in FIG. 7C, an interlayer insulating film 20 is formed, contact holes are opened, and then source / drain wirings 21 are formed to complete a thin film transistor.

[0007]

When a thin film transistor is manufactured by using the manufacturing method shown in FIG. 7, there are some problems. The first problem is that since the photoresist (doping mask) 16 that masks the trace impurity implantation region (n to region) 17 is manufactured by a photolithography process, there is variation in the n to region length between substrates or within the substrate. It exists, and the reproducibility of the transistor characteristics decreases.

[0008]

[Outside 2]

Especially when using an exposure device for a large-area substrate, the alignment accuracy is usually about 2 μm, and the positional accuracy of the photoresist (doping mask) 16 is about 2 μm. Variation occurs, which adversely affects the transistor characteristics. Further, in order to realize the LDD structure described above, two doping steps are required to form two types of impurity implantation regions of high concentration and low concentration, which complicates the manufacturing process.

It is an object of the present invention to solve the above-mentioned conventional problems and to realize it by a simple manufacturing process without causing variations in the length of a trace impurity implantation region (n to region) between substrates or within a substrate.

[0011]

The first means of a method of manufacturing a thin film transistor for achieving the above-mentioned object of the present invention is to form a semiconductor thin film containing silicon on a substrate,
Forming an insulating film on the semiconductor thin film, forming a metal or metal compound thin film on the insulating film,
A step of forming an organic thin film on the metal or metal compound thin film to form a pattern; a step of etching a metal or metal oxide thin film of a lower layer using the organic thin film to process it into a gate electrode shape; At least a step of implanting impurity ions to form source and drain regions before removing is performed.

The second means is a step of forming a semiconductor thin film containing silicon on a substrate, a step of forming an insulating film on the semiconductor thin film, and two or more kinds of metals or metal on the insulating film. The method is characterized by including at least a step of forming a gate electrode in which compound thin films are laminated, and a step of implanting impurity ions to form source and drain regions after forming the gate electrode.

Further, a third means is a step of forming a semiconductor thin film containing silicon on a substrate, a step of forming an insulating film on the semiconductor thin film, and a metal capable of being anodized as a lower layer on the insulating film. Alternatively, a gate electrode is formed by laminating a metal compound thin film and a metal or metal compound thin film that is not anodized in the lower layer anodizing electrolyte solution on the upper layer, and at least one of the upper gate electrodes is formed after impurity ion implantation at the time of forming the source and drain regions. The method further comprises at least a step of removing at least a part and then modifying at least a part of the surface of the lower gate electrode thin film into an insulating film.

Further, in the liquid crystal display device of the present invention, at least a part of the screen portion or the driving circuit portion is formed by the thin film transistor manufactured by any one of the manufacturing methods of the first, second and third thin film transistors. To be done.

[0015]

According to the manufacturing method of the present invention, when implanting impurities in the source / drain regions of a thin film transistor, a laminate of two or more kinds of thin films is processed into a shape of a gate electrode and used as a mask of a channel portion. In the step of processing the two-layer laminated thin film into the shape of the gate electrode, the lower thin film is over-etched to be thinned by a certain amount with respect to a predetermined gate line width (upper thin film pattern). After that, impurities are implanted into the source and rain regions of the thin film transistor using the laminated thin film as a mask.

Further, the lower layer thin film of the gate electrode in which the above-mentioned two types of thin films are laminated is formed of an anodizable metal or metal compound thin film. After forming the gate electrode using the gate electrode forming step, impurities are implanted into the source and drain regions of the thin film transistor using the laminated thin film as a mask. After the implantation of the impurities, the upper thin film of the gate electrode is selectively removed and the lower thin film is anodized to modify the surface of the gate electrode into an insulating film.

As described above, it is possible to form the offset or LDD region, which was conventionally performed by mask alignment, in a self-aligned manner in the etching process at the time of forming the gate electrode. As a result, the controllability of the offset or the LDD region length is improved, and the characteristic variation of the thin film transistor can be reduced. Also, as a lower layer thin film of a two-layer laminated thin film, Al
By using a system-based thin film and anodizing at least a part of the gate electrode to modify it into an insulating film, the probability of defective insulation of the thin film transistor can be greatly reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a process sectional view showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention.

As shown in FIG. 1A, a polycrystalline silicon thin film 12 is formed on a transparent substrate (glass substrate) 11 and patterned, and then a gate insulating film 13 is formed to 100 nm. Al-1% Zr (300 nm) to be the gate electrode 14 on the gate insulating film 13
To form. A polyimide thin film 51, which is an organic thin film, is formed to a thickness of 1.0 μm on the thin film of the gate electrode 14, and the polyimide thin film 51 is processed into the shape of the gate electrode 14. When the gate electrode is processed, the polyimide thin film 51 is used as a mask to be described later with reference to FIG.
As shown in, when the gate electrode 14 (Al) is etched, the gate wiring is self-aligned with the polyimide thin film 51 on one side.
1.0 μm (total 2.0 μm) thin. After that, as shown in FIG. 1B, an impurity 50 is implanted into the source / drain region 18 of the thin film transistor using the polyimide thin film and the gate electrode laminated film (51, 14) as a mask. At this time, the polyimide thin film
Since impurities are not injected into the polycrystalline silicon thin film 12 below 51, it is possible to realize the offset region 52 in which impurities are not injected in a self-aligned manner with respect to the channel region below the gate electrode 14. After implanting the impurities, the polyimide thin film 51 is removed. In this case, the polyimide thin film 51 was removed at a pressure of 300 mTorr and an RF power of 300 W by using a reactive ion etching method using an O ₂ / N ₂ mixed gas as an etching method having a large removal ability for the organic thin film.

After removing the polyimide thin film 51, as shown in FIG. 1C, an interlayer insulating film 20 having a thickness of 200 nm is formed, contact holes are opened, and the insulating film on the source / drain regions 18 is selectively removed. Finally, the source / drain wiring (Al) 21 is formed to complete the thin film transistor.

As described above, in this embodiment, the controllability of the offset is improved and the characteristic variation of the thin film transistor can be suppressed by a simple manufacturing process.

2A to 2D are process sectional views showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention.

First, as shown in FIG. 2A, a 100-nm-thick polycrystalline silicon thin film 12 is formed on a transparent substrate (glass substrate) 11. In this embodiment, as a method of manufacturing the polycrystalline silicon thin film 12, a substrate temperature of 250 ° C. is formed by a plasma CVD method.
A method of crystallizing the amorphous silicon thin film formed in 1. by irradiation with an excimer laser was used. Polycrystalline silicon thin film
By using this method for forming 12, it is possible to form a high-quality polycrystalline silicon thin film 12 at a heat resistance temperature (500 to 600 ° C.) or lower of a normal alkali-free glass substrate. After forming this polycrystalline silicon thin film 12, the polycrystalline silicon thin film 12 other than the thin film transistor forming region is removed and processed into an island shape.

Next, the substrate temperature is set to 450 by using the atmospheric pressure CVD method.
100 nm thick silicon oxide thin film to be the gate insulating film 13 at ℃
Form. After forming the gate insulating film 13, an Al alloy (Al-1% Zr) to be the gate electrode 14 is formed to 300 nm, and a Ta thin film to be the gate electrode 15 is formed to 50 nm on the gate electrode (Al alloy) 14 by the sputtering method. To do. A photoresist 16 in the shape of a gate electrode is formed on the Ta / Al alloy bilayer thin film.
Using the photoresist 16 as a mask, the upper gate electrode (Ta thin film) 15 is first processed into the shape of the gate electrode. For processing the gate electrode (Ta thin film) 15, a reactive ion etching method using SF ₆ / O ₂ gas (gas ratio 1: 0.2) was used, and etching was performed at a pressure of 200 mTorr and an RF power of 300 W. After etching the gate electrode (Ta thin film) 15, the lower layer of the gate electrode (Al alloy) 14 is processed into the shape of the gate electrode. The Al alloy thin film was etched by using a mixed solution of phosphoric acid: nitric acid: acetic acid at a liquid temperature of 60 ° C.

FIG. 3 is a characteristic diagram (a) showing the dependence of the side etching length L (vertical axis) on the etching time (horizontal axis) during Al alloy etching and an enlarged view (b) of the main part of FIG. Figure 3
As shown in (a), the side etching length L increases in proportion to the etching time. Depending on the etching time, the amount of penetration from the upper gate electrode (Ta film) 15, that is, the side etching length L is 0.5 μm to 2.5 μm. It is possible to control over a wide range up to the above.

2A, the side etching length L of the Al alloy thin film of the lower gate electrode 14 with respect to the pattern of the upper gate electrode 15 is set to 1.0 μm by using the side etching of the Al alloy thin film shown in FIG. Processed to be. Then, as shown in FIG. 2B, the impurity 10 is implanted into the source / drain regions 18 of the thin film transistor by using the ion doping method. Phosphorus was used as the impurity and was implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ / cm ² . By using the ion doping method for the impurity implantation, the ion mass separation step is not required, and the beam area can be increased and the throughput is improved as compared with the conventional ion implantation method. Further, it is possible to suppress the charge-up phenomenon when injecting into an insulating substrate such as glass.

The thin film transistor of this embodiment is characterized in that the upper and lower gate electrodes 15 and 14 are processed into the shape shown in FIG. 2 (a) and ion implantation is performed so that the offset region or LDD (Lightly -Doped-Drain) area can be formed.

That is, in the source / drain region 18 of the thin film transistor, the impurity ions are implanted into the polycrystalline silicon through the silicon oxide thin film of the gate insulating film, whereas the polycrystalline under the upper gate electrode (Ta film) 15 is formed. In the silicon thin film 12, the implanted ions are decelerated by the upper gate electrode (Ta film) 15, and the impurity implantation amount is reduced in this region as compared with the polycrystalline silicon thin film 12 in the source / drain region 18. As a result, a low concentration impurity implantation region 17 is formed between the channel region 19 and the source / drain region 18 of the thin film transistor.
Can be formed in a self-aligned manner, and LD can be
D structure can be realized.

Finally, as shown in FIG. 2 (c), atmospheric pressure CVD is performed.
The interlayer insulating film 20 is formed to a thickness of 400 nm by the method at a substrate temperature of 450 ° C. The implanted impurities are self-activated by the substrate temperature at the time of forming the interlayer insulating film. After forming the interlayer insulating film, the contact hole is opened and the source / drain wiring 21 (Al) is formed to complete the thin film transistor.

FIG. 4 is a characteristic diagram of the electric field relaxation region resistivity (vertical axis) with respect to the Ta film thickness (horizontal axis) of the upper gate electrode 15 of resistivity in the low concentration impurity implantation region 17. When the Ta film thickness is 0, it is the same as the resistivity of the polycrystalline silicon thin film in the source / drain regions, but the resistivity also increases as the Ta film thickness increases. In this structure, when the Ta film thickness is 200 nm or more, the implanted impurities do not reach the polycrystalline silicon thin film, and the resistivity becomes the same as the resistivity of the channel region. By controlling the film thickness of the upper layer thin film of the two-layer gate electrode in this way, the resistivity of the low concentration impurity implantation region can be controlled over a wide range.

The Ta film thickness of the upper gate electrode 15 is 200 nm.
With the above, an offset structure can be realized. In this example, Al-1% Zr was formed on the lower thin film of the two-layer gate electrode.
The reason why is used is that the heat resistance can be improved as compared with normal Al, and the insulation failure due to Al hillocks in the interlayer insulating film forming step can be reduced.

(Embodiment 2) FIGS. 5A to 5C are process sectional views showing a method of manufacturing a thin film transistor according to a third embodiment of the present invention. The basic manufacturing method is the same as that of the second embodiment shown in FIG. As the upper and lower gate electrodes 15 and 14 of the two layers,
The upper thin film is Ta thin film (50 nm) and the lower thin film is Al-1% Zr (30
0 nm), as shown in FIG. 3B, the lower layer thin film (Al-1% Zr) is self-aligned during etching of the lower layer thin film.
Gate wiring of 1.0μm on one side compared to the upper thin film (Ta) (total
2.0μm) Thin line. After that, impurities are implanted into the source / drain regions 18 of the thin film transistor by self-alignment using the gate electrode as a mask. At this time, the upper gate electrode
Since trace impurities are introduced into the polycrystalline silicon thin film 12 below the region where only 15 exists, as shown in FIG.
Low impurity concentration (LDD) region
(n˜region) 17 can be formed.

Next, as shown in FIG. 5B, after the impurity implantation, the upper layer gate electrode 15 is selectively removed, and the lower layer gate electrode 14 Al-1% Zr is anodized. A mixed solution of ethylene glycol and ammonium tartrate (7: 3) was used as an electrolytic solution for anodization, and the formation voltage was 140 V to form an anodized (Al ₂ O ₃ ) film 41 of 200 nm. The Ta thin film of the upper gate electrode 15 is processed into the shape of a chemical conversion mask at the time of anodic oxidation, and functions as an anodic oxidation prevention film at the electrode extraction portion. After forming the anodic oxide film, an interlayer insulating film 20 is formed to a thickness of 200 nm as shown in FIG. 5C, contact holes are opened, and the insulating film on the source / drain regions 18 is selectively removed. Finally, the source / drain wiring (Al) 21 is formed to complete the thin film transistor.

FIG. 6 shows an active matrix type liquid crystal display device as an embodiment of the liquid crystal display device of the present invention. FIG. 6A is an equivalent circuit diagram of one picture element of the liquid crystal display device. When the write signal (scan signal n) is input from the scan line Sn to the scan electrode (gate electrode) of the thin film transistor 31, the thin film transistor 31 is turned on, and the liquid crystal is charged through the data line Dn to write the image information in the liquid crystal. Be done. The auxiliary capacitance Cs is formed in parallel with the liquid crystal capacitance CLC in order to retain the image information until the next writing time. A liquid crystal display is formed by integrating the picture elements shown in FIG. 6A in a matrix.

FIG. 6B is a block diagram of an active matrix array for a liquid crystal display. Each pixel 34 is manufactured by using an n-channel thin film transistor 31, and in addition to this, a scanning line drive circuit 32 and a data line are provided. Line drive circuit 33
Is manufactured on the same substrate by a C-MOS structure in which n-channel and p-channel thin film transistors are combined. As a result, it is not necessary to mount an IC for driving a liquid crystal display, which has been conventionally required, on the outside, and it is possible to significantly reduce the cost. In this example, a thin film transistor for driving a pixel electrode or for forming a driving circuit was manufactured by using the method for manufacturing a thin film transistor according to the present invention.

As a result, the OFF current can be reduced while using the polycrystalline silicon thin film transistor having a high mobility, and the display quality is improved and the power consumption is reduced. Further, in the driving circuit portion, the electric field strength near the drain of the thin film transistor can be reduced, and the reliability can be improved. In the embodiment of the present invention, all the thin film transistors for driving the pixel electrode and the peripheral driving circuit are manufactured by using the manufacturing method according to the present invention, but this is not always necessary, and the peripheral driving circuit or the pixel electrode driving is required. The same result can be obtained by using only the thin film transistor of a part.

[0038]

As described above, by using the manufacturing method of the present invention, it becomes possible to form an LDD or an offset structure in a self-aligned manner, and an OF of a thin film transistor is formed.
At the same time as the F current is reduced, the characteristic variation due to the mask alignment variation, which has been a problem in the past, can be greatly reduced, and an LDD or an offset transistor can be realized on a large-area substrate. Further, the conventional LDD structure requires two impurity implantation steps for forming a high-concentration impurity region and a low-concentration impurity region, but by using the manufacturing method of the present invention, a high-concentration impurity region of a thin film transistor is formed. Since the low-concentration impurity region can be formed at the same time when the region is formed, the number of impurity implantation steps can be reduced and the manufacturing cost can be reduced.

Further, Al or an alloy containing Al as a main component is used as the lower layer gate electrode, and after the impurity implantation step, a part of the lower layer gate electrode is anodized to modify the surface into an insulating film, whereby an interlayer insulating film is formed. A double structure of Al ₂ O ₃ and a silicon oxide film was formed, and the probability of insulation failure between the gate electrode of the thin film transistor and the signal wiring was significantly reduced, and the yield was improved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a method of manufacturing a thin film transistor in a second embodiment of the present invention.

FIG. 3 is a characteristic diagram (a) showing the dependence of the side etching length L on the etching time during Al alloy etching and an enlarged view (b) of the main part of FIG. 2.

FIG. 4 is a characteristic diagram of the electric field characteristic region resistivity with respect to the film thickness of the upper gate electrode Ta of the resistivity in the low concentration impurity implantation region.

FIG. 5 is a process sectional view showing the method of manufacturing the thin film transistor in the third embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram (a) of one pixel of an active matrix type liquid crystal display device in one embodiment of the present invention and a configuration diagram of an active matrix array for a liquid crystal display.
It is (b).

FIG. 7 is a process cross-sectional view showing an example of a conventional method for manufacturing a polycrystalline silicon thin film transistor.

[Explanation of symbols]

10, 50, 71, 72 ... Impurities, 11 ... Translucent substrate (glass substrate), 12 ... Polycrystalline silicon thin film, 13 ... Gate insulating film, 14 ... Gate electrode (Al alloy), 15 ... Gate electrode (T
a), 16 ... Photoresist, 17 ... Low concentration impurity implantation region, 18 ... Source / drain region, 19 ... Channel region, 20 ... Interlayer insulating film, 21 ... Source / drain wiring,
31 ... Thin film transistor, 32 ... Scan line driving circuit, 33
… Data line drive circuit, 34… Picture element, CLC… Liquid crystal capacity, Cs… Additional capacity for signal holding, 41… Anodic oxidation (Al ₂
O ₃ ) film, 51 ... Polyimide thin film, 52 ... Offset area.

Claims (14)

[Claims] 1. A step of forming a semiconductor thin film containing silicon on a substrate, a step of forming an insulating film on the semiconductor thin film, a step of forming a metal or metal compound thin film on the insulating film, and the metal. Alternatively, a step of forming an organic thin film on the metal compound thin film to form a pattern, a step of etching the underlying metal or metal oxide thin film using the organic thin film to form a gate electrode shape, and removing the organic thin film A method of manufacturing a thin film transistor, which comprises at least a step of implanting impurity ions to form source and drain regions. 2. The method of manufacturing a thin film transistor according to claim 1, wherein a thin film containing aluminum as a main component is used as the metal or metal compound thin film. 3. The method of manufacturing a thin film transistor according to claim 1, wherein a polyimide thin film is used as the organic thin film. 4. The pattern size of a gate electrode formed of a metal or metal compound thin film with respect to the organic thin film is 0.5 μm.
It is made smaller than the above.
A method for manufacturing the thin film transistor described. 5. A step of forming a semiconductor thin film containing silicon on a substrate, a step of forming an insulating film on the semiconductor thin film, and a gate in which two or more kinds of metal or metal compound thin films are laminated on the insulating film. A method of manufacturing a thin film transistor comprising at least a step of forming an electrode and a step of implanting impurity ions to form source and drain regions after forming the gate electrode. 6. A step of forming a semiconductor thin film containing silicon on a substrate, a step of forming an insulating film on the semiconductor thin film, and an anodizable metal or metal compound thin film and an upper layer on the lower layer on the insulating film. The gate electrode is formed by laminating a metal or metal compound thin film that is not anodized in the anodizing electrolyte solution of the lower layer, and after removing at least a part of the upper gate electrode after impurity ion implantation at the time of forming the source and drain regions, the lower layer is formed. A method of manufacturing a thin film transistor, comprising at least a step of modifying at least a part of the surface of the gate electrode thin film into an insulating film. 7. The thin film in which two kinds of metal or metal compound thin films are laminated is used as the gate electrode, and the wiring width of the lower layer thin film is formed to be 0.5 μm or more smaller than the wiring width of the upper layer thin film. Alternatively, the method of manufacturing a thin film transistor according to Item 6. 8. The thin film in which two kinds of metal or metal compound thin films are laminated is used as the gate electrode, and the film thickness of the upper thin film is 30 nm or more and 300 nm or less. A method for manufacturing the thin film transistor described. 9. A thin film in which two kinds of metal or metal compound thin films are laminated is used as the gate electrode, and the lower thin film is formed of a thin film containing aluminum as a main component and has a film thickness of 200 n.
9. The method of manufacturing a thin film transistor according to claim 5, wherein the thickness is at least m. 10. A thin film in which two kinds of metal or metal compound thin films are laminated is used as the gate electrode, a wet etching method is used to form a pattern of the lower layer thin film, and the pattern size of the upper layer thin film is controlled by etching time. 10. The method of manufacturing a thin film transistor according to claim 5, wherein the thin film transistor is a thin film transistor. 11. The method of manufacturing a thin film transistor according to claim 6, wherein the upper layer gate electrode is used as a mask during anodic oxidation of the lower layer gate electrode. 12. The method of manufacturing a thin film transistor according to claim 1, wherein an ion doping apparatus that does not use a mass separation step of implanted ions is used for the impurity implantation. 13. The method of manufacturing a thin film transistor according to claim 1, wherein a polycrystalline silicon thin film is used as the semiconductor thin film containing silicon. 14. A liquid crystal display device in which a thin film transistor is integrated, wherein at least a part of a screen portion or a driving circuit portion is formed by the thin film transistor according to any one of claims 1 to 13. Liquid crystal display device.