JP2000031494A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To anodic-oxidate an Al gate wiring, without forming a voltage feed line for the anodic oxidation. SOLUTION: A probe of an anodic oxidating apparatus makes contact with a Ta film 104, with leaving a resist mask 106, to anodic-oxidate in an oxalic acid soln., thereby forming a porous A.O. film 108, the resist mask 106 is removed, a voltage is applied to the Ta film 104 in the oxalic acid soln. again in the anodic oxidating apparatus to anodic-oxidate them, thereby forming a barrier A.O. film 109 and TaOx film 111, wherein the Ta film 104 is not completely oxidated below the porous A.O. film 108, the porous A.O. film 108 is removed by etching, and then the remaining Ta film is thermally oxidated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device such as an insulated gate transistor having a wiring formed of an aluminum material and a method of manufacturing the same. The semiconductor device of the present invention includes not only elements such as thin film transistors and MOS transistors, but also electronic devices such as display devices and image sensors having a semiconductor circuit composed of these insulated gate transistors.

[0002]

2. Description of the Related Art Active matrix liquid crystal displays, in which a pixel matrix circuit and a driving circuit are formed by thin film transistors (hereinafter abbreviated as TFTs) formed on an insulating substrate, have received attention. Liquid crystal displays include those for projectors of about 0.5 to 2 inches and those for notebook computers of about 10 to 20 inches, and are mainly used as small to medium display displays.

[0003] One area in the development of liquid crystal displays is to increase the area. However, when the area is increased, the pixel matrix circuit serving as an image display section also has an increased area, and accordingly, the source wiring and the gate wiring arranged in a matrix become longer, and the wiring resistance increases. Further, it is necessary to make the wiring thinner for the demand for miniaturization, and the increase in the wiring resistance becomes more apparent. In addition, the source wiring and the gate wiring include:
Since a TFT is connected to each pixel and the number of pixels increases, an increase in parasitic capacitance also poses a problem. In a liquid crystal display, generally, a gate wiring and a gate electrode are integrally formed, and a delay of a gate signal becomes conspicuous as the area of the panel increases.

Therefore, a material mainly composed of aluminum having a low specific resistance is used for the gate wiring. When the gate wiring and the gate electrode are formed using a material containing aluminum as a main component, a gate delay time can be reduced and high-speed operation can be performed. Since aluminum has low heat resistance, it has been practiced to coat aluminum with an anodic oxide film to improve the heat resistance of wiring.

[0005] Conventionally, it has been attempted to reduce the off-current by making the thin film transistor an offset structure or an LDD (Light Doped Drain) structure. In Japanese Patent No. 2757915, the present applicant discloses a technique for manufacturing a thin film transistor having an LDD structure. The above publication describes a method of forming an LDD structure in a semiconductor layer in a self-aligned manner by using aluminum as a gate electrode material and anodizing the gate electrode. This method will be described with reference to FIG.

A semiconductor layer 13 made of a polycrystalline silicon film is formed on a glass substrate 10, and a gate insulating film 14 is formed on the semiconductor layer 13. Next, an aluminum film is formed and patterned using a photoresist mask 16.
A gate electrode 15 made of aluminum is formed. (FIG. 3
1 (A))

Using the gate electrode 15 as an anode, the pattern is anodized in an electrolytic solution to form a porous alumina film 17. In this state, since the surface of the gate electrode 15 is blocked by the mask 16, the porous (porous) alumina film 17 is formed only on the side surface of the gate electrode 15. (FIG. 31 (B))

After removing the photoresist mask 16,
The gate electrode 15 is anodized again to form a barrier (non-porous).
An alumina film 18 is formed. The aluminum remaining in the two anodic oxidation steps functions as the gate electrode 15 '.
(FIG. 31 (C))

Next, the gate insulating film 14 'is patterned using the alumina films 17 and 18 as a mask. (FIG. 31
(D))

Then, the porous alumina film 17 is removed. In this state, the semiconductor layer 13 is doped with an impurity imparting N-type or P-type conductivity by a plasma doping method. Doping is performed in two steps. In the first time, the acceleration is set low and the dose is increased so that the gate insulating film 14 'functions as a mask. The second time, high acceleration is applied so that impurities pass through the gate insulating film 14 ', and LD
The dose is reduced to form the D region. As a result, in the semiconductor layer 13, the channel formation region 20, the source region 21, the drain region 22, the low concentration impurity region 23,
24 are formed in a self-aligned manner. The low concentration impurity region 24 on the drain region 22 side is an LDD region. In this doping step, the regions 23 and 24 can be used as offset regions by using the gate insulating film 14 'as a mask.

However, in order to perform the anodic oxidation treatment, it is necessary to connect all the electrodes and wirings to be anodized to the voltage supply wiring for anodic oxidation. For example, when the technology disclosed in the above-mentioned patent publication is applied to an active matrix type liquid crystal panel, it is necessary to connect the gate electrodes and wirings of the thin film transistors constituting the active matrix circuit and the driver circuit to the voltage supply lines. In order to make the connection, a voltage supply wiring is formed on the substrate. Therefore, extra space is required.

At the time of anodic oxidation, each gate electrode / wiring is short-circuited by a voltage supply line. After the anodizing treatment, the voltage supply lines and unnecessary connection portions with the supply lines are removed by etching, and the gate wirings / electrodes are electrically separated. Therefore, the circuit layout must be designed in consideration of the etching process margin.

Therefore, in order to manufacture a transistor by using anodizing treatment, a space for forming a voltage supply line and an etching margin are required.
This is an obstacle to reducing the substrate area. Further, since aluminum is exposed in the cross section of the wiring, the heat resistance is reduced.

In the TFT shown in FIG. 31, the process temperature after forming the aluminum wiring is 300 to 4
Even at 50 ° C., a malfunction of the TFT was confirmed. There are various possible causes for this malfunction. In particular, most of the malfunctions of the top gate type TFT are such that protrusions such as hillocks and whiskers generated at the gate electrode penetrate the gate insulating film to reach the channel formation region, or aluminum atoms diffuse into the gate insulating film. This is due to a short circuit (short circuit) between the gate electrode and the channel caused by the operation.

At present, TFTs are required to have high mobility, and it is considered that a crystalline silicon film having higher mobility than an amorphous silicon film is used as a semiconductor layer. Conventionally, to obtain a crystalline silicon film by heat treatment, it was necessary to use a quartz substrate having a high strain point. Since a quartz substrate is expensive, a low temperature of crystallization at which a cheap glass substrate can be used is required.

Techniques for lowering the crystallization temperature are described in Japanese Patent Application Laid-Open Nos.
No. 321339. The above technique is to obtain a crystallized silicon film by introducing a trace amount of a catalytic element into an amorphous silicon film and then performing a heat treatment. As a catalyst element for promoting crystallization, Fe,
Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, C
One or plural kinds selected from u, Au and Ge are used. By using this technique, a polycrystalline silicon film can be manufactured at a process temperature at which a glass substrate can withstand.

However, the problem with this technique is that the catalytic element used for crystallization remains in the polycrystalline silicon film, which causes deterioration in the reliability and uniformity of characteristics of the TFT. In view of this, the present applicants have further developed a technique of forming a wiring using an aluminum material and then gettering a metal element in a polycrystalline silicon film (Japanese Patent Laid-Open No. 8-330602). In this technology, the source / drain regions doped with phosphorus are used as gettering sinks.
By performing the heat treatment, the catalyst element in the channel formation region is gettered to the source / drain region.

However, even if an aluminum material having low heat resistance is used for the wiring and covered with the anodic oxide film, the heating temperature for gettering has been limited to 300 to 450 ° C. At a heating temperature of 300 to 450 ° C., a long processing time is required because the temperature for sufficiently gettering the metal element in the polycrystalline silicon film is low. Therefore, diffusion of aluminum from the gate electrode and expansion of the gate wiring due to hillocks and the like easily occur.

[0019]

As described above, it is desirable to use an aluminum material for the wiring from the viewpoint of reducing the resistance of the wiring. Aluminum can be anodized,
By utilizing the anodic oxidation technology, a thin film transistor having an LDD structure or an offset structure can be manufactured in a self-aligned manner. However, since it is necessary to form a voltage supply wiring for anodic oxidation, high integration of a circuit and reduction of a substrate area are prevented.

Even if aluminum is coated with anodic oxide, the process temperature after forming the gate wiring is limited to about 400 ° C. due to low heat resistance. Also, the diffusion of aluminum from the gate wiring, the occurrence of hillocks, the gate wiring and the channel are short-circuited, the gate wiring is deformed, and the TFT malfunctions.

According to the present invention, it is possible to anodize an aluminum material without forming a voltage supply wiring for anodization. It is still another object of the present invention to prevent the diffusion of aluminum from a wiring caused by heating and the deformation of the wiring to manufacture a semiconductor element with high yield.

[0022]

Means for Solving the Problems The process leading to the present invention will be described below with reference to FIGS.

[1. Anodizing)
Using the tantalum film as an electrode, it was confirmed whether an island-shaped aluminum pattern could be anodized on the tantalum film. FIG. 22 is a cross-sectional view of the aluminum pattern for each experimental procedure.

<< Experimental Procedure >> 1737 manufactured by Cornings Incorporated
A tantalum (Ta) film 41 having a thickness of 20 nm and a thickness of 40 are formed on a glass substrate (5 inch square) 40 by sputtering.
An aluminum (Al) film 42 having a thickness of 0 nm was laminated. Then, a probe of an anodizing apparatus was connected to the aluminum film 42 to anodize the surface of the aluminum film, thereby forming a barrier type anodic oxide (Anodic Oxicide) film 44. The barrier type anodic oxide film (hereinafter referred to as barrier AO film) is alumina. (FIG. 22A)

Anodizing conditions are as follows: an ethylene glycol solution containing 3% tartaric acid is used as an electrolytic solution, and the solution temperature is set at 30.
° C, ultimate voltage 10V, voltage application time 15 minutes, supply current 1
The substrate was 0 mA / 1 substrate. This anodization step is for improving the adhesion of the resist mask 50. This anodizing step is referred to as a mask anodizing step since the barrier AO film 44 is formed on the surface of the Al film 42.

Next, a resist mask 50 is formed.
The O. film 44 and the Al film are etched to form a gate wiring pattern 43 (hereinafter referred to as a gate Al 43) made of the Al film.
) Are formed. The gate Al 43 is formed separately for each wiring, and in FIG.
43 are shown only two.

The etchant of the barrier AO film 44 is 550 g of a chromic acid solution (300 g of chromic acid and 10 liter of a mixed solution of phosphoric acid: nitric acid: acetic acid: water = 85: 5: 5: 5). Water (250 grams) was used. Here, this etchant is called a chromium mixed acid. An acid in which phosphoric acid, acetic acid, nitric acid, and water were mixed at a volume ratio of 85: 5: 5: 5 (hereinafter, this acid is referred to as an aluminum mixed acid) was used as an etchant for the Al film 42. (FIG. 22 (B))

Next, with the resist mask 50 left,
A voltage was applied to the Ta film 41 in the anodic oxidation apparatus to perform anodic oxidation. The conditions were as follows: a 3% oxalic acid aqueous solution was used as the electrolytic solution, the ultimate voltage was 8 V, the voltage application time was 40 minutes, and the supply current was 20 mA / 1 substrate. In the conventional anodic oxidation method, a porous anodic oxide (porous AO) film 44 is formed on the side surface of the aluminum pattern 43. Therefore, this anodic oxidation step is referred to as a side anodic oxidation step.
(FIG. 22 (C))

Next, after removing the resist mask 50,
A voltage is again applied to the Ta film 41 in the anodizing apparatus,
Anodization was performed. The conditions used were an ethylene glycol solution containing 3% tartaric acid as the electrolytic solution, an electrolytic solution temperature of 10 ° C., an ultimate voltage of 80 V, a voltage application time of 30 minutes, and a supply current of 30 mA / 1 substrate. According to the conventional method, tartaric acid penetrates the porous AO film 45 under this anodic oxidation condition, and the surface of the gate Al 43 is anodized to form a barrier type anodic oxide (barrier AO) film 46. For this reason, this anodic oxidation step will be referred to as a barrier anodic oxidation step. The barrier AO film 46 is made of nonporous alumina and has resistance to hydrofluoric acid. (FIG. 22 (D))

Next, the porous AO film 45 was removed by wet etching using the above-described aluminum mixed acid.
(FIG. 22E)

<< Experimental Results and Discussion >> In order to confirm whether the Ta film 41 functions as a voltage supply wiring for anodic oxidation of the Al pattern, the sheet resistance of the Ta film 41 was measured for each process.

Further, in order to examine the sectional structure of the Al gate 43, a scanning electron microscope (Scanning Electron microscope) was used.
SEM) and transmission electron microscope (Transmission Ele)
The cross-sectional structure was observed using a ctron microscope (TEM). Furthermore, energy dispersive X-ray spectroscopy (Elec
Elemental analysis of a fine region of the cross-sectional structure was performed by tron dispersion Xray spectroscopy (hereinafter, referred to as EDX).

FIGS. 23A to 23C are SEM observation photographs and correspond to the cross-sectional observation photographs of FIGS. 22B to 22D. 24 and 26A are TEM observation photographs of FIG. 22E, and FIG. 26 is a partially enlarged photograph of FIG. FIG. 25 is a schematic view of the TEM observation photograph of FIG. The reference numerals in FIG. 25 correspond to those in FIG.

The sheet resistance of the Ta film 41 was 100.1 Ω / □ cm in an initial state (before mask anodic oxidation). After the end of the side anodic oxidation step, it was 205.1 Ω / □ cm, and the sheet resistance after the end of the barrier anodic oxidation step was equal to or larger than the measurement range of the measuring apparatus. The maximum measurable value of the device is 5000 kΩ / □
cm, the sheet resistance after the barrier anodic oxidation step is considered to be at least 5000 kΩ / □ cm or more.

After completion of the side anodic oxidation step, the glass substrate 4
When 0 was observed with the naked eye, the transparency of the Ta film 41 was higher than in the initial state. From this and the sheet resistance,
It is assumed that the Ta film 41 was slightly oxidized by oxalic acid. This is because the surface of the Ta film 41 is oxidized in the side anodic oxidation step to obtain a tantalum oxide film (hereinafter referred to as TaOx) from the elemental analysis result by the EDX method as described later.
(Referred to as a film) 51 are formed. (FIG. 22 (C)
reference)

It should be noted that, from the SEM photograph of FIG.
By applying a voltage to the a film 41, a voltage can be supplied to the gate Al 43 divided into islands, and the gate Al 43 is anodized to form a porous AO (porous alumina) film. Can be confirmed.

After the barrier anodic oxidation step, the glass substrate 4
When 0 was observed with the naked eye, the exposed Ta film 41 was almost transparent. This is because tartaric acid used in the mask anodizing step also anodizes tantalum, and it is presumed that the Ta film 41 in this portion has been anodized and transformed into a TaOx film 52.

According to the SEM observation photograph of FIG.
The Ta film 41 is formed below and outside the porous AO film 45.
Is about three times as thick. This also indicates that the Ta film 41 remaining in this portion has been anodized and transformed into a TaOx film 52. From this, it can be understood that the sheet resistance value becomes extremely large. In addition,
For simplicity, in FIG. 22, the total film thickness of the TaOx films 51 and 52 is the same as the Ta film 41.

However, since tantalum oxide is an insulator, the TaOx films 51 and 52 function as wiring, but this poses a problem. In the barrier anodic oxidation step, there is no large change in the monitored current value. Therefore, even if the Ta film 41 is transformed into the TaOx film 45, the gate Al 43
It is considered that a voltage is applied to. This is TaO
Although the x film 45 has a very large sheet resistance value, it has a slight conductivity (semi-insulating property) because the oxygen content is smaller than that of Ta ₂ O ₅ (tantalum pentoxide) which is a stoichiometric ratio. It is presumed that there is. This deviation from the stoichiometric ratio is due to TaO
This is considered to be largely due to the fact that the x films 51 and 52 were formed by anodic oxidation.

The etching process of FIG. 22E uses an aluminum mixed acid. Aluminum mixed acid etches both porous alumina (porous AO film 45) and aluminum, while non-porous alumina (barrier AO film 46) is hardly etched. Therefore, in the barrier anodic oxidation process, the barrier AO
If the film 46 is not formed sufficiently, the gate Al 43 will also be removed.

According to the SEM observation photograph of FIG. 23C and the TEM observation photograph of FIG. 24, it can be confirmed that the gate Al43 remains even after the etching treatment with the mixed acid of aluminum.
Therefore, it can be inferred that the barrier AO film 46 that can withstand aluminum mixed acid is formed in the mask anodic oxidation process. FIG.
According to the TEM observation photograph, the thickness of the barrier AO film 46 is about 20 nm.

According to the above experiment, the gate Al 43 selectively formed on the glass substrate 40 was short-circuited by the Ta film 41 formed on the entire surface of the glass substrate 40.
By applying a voltage to the a film 41, the gate Al4
3 was found to be anodizable. In particular, it was found that even if the Ta film 41 was used for the voltage supply wiring for anodic oxidation using tartaric acid, the gate Al 43 formed thereon could be anodized.

Although not confirmed by the SEM observation photograph of FIG. 23, the TEM observation photograph of FIG. 24 shows that the TaOx film has three different layers 51, 52a and 53b (see FIG. 25). The composition of each layer 51, 52a, 52b is EDX
Was analyzed. In FIG. 25, P1 to P6 indicated by “*” indicate ED.
X is the measurement point.

The measurement point P1 is a portion that is not immersed in the electrolytic solution in all the anodic oxidation steps, and serves as a reference point for other measurement points. At the measurement point P1, most of the peaks were Ta, but low peaks such as C and O were also confirmed.

The measurement points P2 and P3 are portions immersed in the electrolytic solution in the porous anodic oxidation step and the barrier anodic oxidation step. At the measurement points P3 and P4, the EDX measurement results are almost the same, and Ta and O peaks appear. Since the peak of O is higher than the point P1, at the measurement points P3 and P4, Ta is anodized and tantalum oxide (Ta
Ox).

However, in the TEM photograph, since the lower layer 52b (measurement point P2) and the upper layer 51 (measurement point P3) have different contrasts, the lower layer 52b and the upper layer 5b have different contrasts.
In No. 1, the crystal structure is presumed to be different. Upper layer 51
Is a portion oxidized in the porous anodic oxidation step, which is assumed to be porous TaOx.
Is the portion oxidized in the barrier anodic oxidation step, and the upper layer 5
It is considered that the crystal structure is more dense than 1.

In the region where the porous AO film 45 was present, at the measurement point P4 near the interface of the glass substrate 40, the peak of the detected element is almost the same as the measurement point P1, so Ta is anodized in this portion. Not, T
The a layer 40 remains.

At the measurement point P5 on the surface layer 52a, Ta and O
And Al peaks were detected. O peak at point P1
Higher than. It is considered that TaOx and Al coexist in the surface layer 52a, or an alloy of Ta and Al is oxidized. The TEM photograph shows that the layer 52a has a needle shape (porous shape) and has a lower density than the layer 51.

Measurement point between measurement points P4 and P5
The EDX result at P6 is almost the same as the measurement result at point P3, and TaO oxidized in the barrier anodic oxidation step
It is considered to be x.

From the results of the above TEM observation photograph and EDX, in the region outside the porous AO film 45, the TaOx layers 5 having different densities (contrasts in the photographs are different) are shown.
It is considered that it has a two-layer structure of 1, 52b.

In the region below the porous AO film 45, T
a film 41, a TaOx layer 52a, and a TaOx layer 52b. The TaOx layer 52b has a TaOx layer containing Al.
x or an oxide of an alloy of Al and Ta.

The T of the conventional LDD structure shown in FIG.
Consider FT. Gate insulating film 1 of this TFT
4 ', the portions above the low concentration impurity regions 23 and 24 are portions where the porous alumina film 17 was present. Therefore, the wiring having a two-layer structure of Al / Ta shown in FIG.
Is applied to the gate wiring of the TFT of FIG.
The film 41 remains.

In such a case, in the ON state, Ta
Since the low-concentration impurity regions 23 and 24 are always applied by the film 41, deterioration of the TFT is accelerated. Therefore, in the present invention, after the anodic oxidation step, the low concentration impurity region 2
One of the constitutions is to thermally oxidize a portion such as the Ta film 41 remaining on 3, 24.

[2. Evaluation of blocking property of Ta layer]
Next, the blocking property of Al diffusion of the Ta layer is evaluated. A sample on which a Ta layer was formed (referred to as Sample A) and a sample on which a Ta layer was not formed (referred to as Sample B) were subjected to a heat treatment in a nitrogen atmosphere.
Ion Mass Spectroscopy S
(IMS) was evaluated.

FIG. 27 shows a sectional structure of each of the samples A and B. Sample A is a polycrystalline silicon film 61 (thickness 2) corresponding to a semiconductor layer on a Corning 1737 glass substrate 60.
00 nm), a silicon nitride oxide film 62 (120 nm) corresponding to a gate insulating film, a tantalum film 63 (20 nm) forming a gate wiring, and an aluminum film 64 (200 n).
m) are stacked.

The sample B corresponds to the sample A except that the tantalum film 63 is removed.
A polycrystalline silicon film 71 (200 nm thick) corresponding to a semiconductor layer, a silicon nitride oxide (SiON) film 72 (120 nm) corresponding to a gate insulating film, and a tantalum (Ta) film 73 (20 nm ) And an aluminum (Al) film 74 (200 nm).

The conditions of the heat treatment are as follows: nitrogen atmosphere, temperature 55
0 ° C., time 2 hours.

The SIMS measurement direction is from the glass substrates 60 and 70 to the aluminum films 64 and 74 for both samples A and B. For both samples A and B, the analysis conditions were a primary ion species O ₂ ⁺ , a primary acceleration voltage of 6.0 kV, and a sputtering rate of 0.1 kV.
6 nm / s, the measurement area was 120 μm × 192 μm, and the degree of vacuum was 3 × 10 ⁻⁷ Pa. The elements to be analyzed are Al, O, S
i and Ta.

The SIMS analysis results of Samples A and B are shown in FIG.
As shown in FIG. 28 and 29, the horizontal axis is the depth [μm], the left axis is the concentration of Al [atoms / cm ³ ], and the right axis is the secondary ion intensity of O, Si, Ta [cts / sec].
].

The quantification of the Al concentration was performed by
A SiO ₂ standard sample implanted with Al and a Si standard sample implanted with Al were used. Figure 28, the concentration profile of Al in FIG. 29 is a processing data, SiO ₂
A profile was quantified using a standard sample, a profile that connects the profile quantified using Si standard sample, SiO ₂ is in the SiON film 62 and 72
This is a profile quantified using a standard sample, and a profile quantified using a Si standard sample in the polycrystalline Si films 61 and 71. Therefore, uncertainty due to data processing remains in the profile at the SiON film / Si film interface. The background level of the Al concentration is Si
1 × 10 ¹⁶ atoms / cm ³ in the O ₂ standard sample,
It is 1 × 10 ¹⁵ atoms / cm ³ in the standard sample.

When comparing FIGS. 28 and 29, it is apparent that
It can be seen that the Ta film 63 functions as a blocking film for preventing Al diffusion. In sample B (without Ta layer), S
In both the i film (semiconductor layer) 61 and the (gate insulating film) 62, the concentration of Al is about 1 × 10 ¹⁹⁶ atoms / cm ³ .
On the other hand, in sample A (with a Ta layer), the concentration of Al
In the ON film 63, the concentration is 3 × 10 ¹⁶ atoms / cm ³ or less, and the minimum concentration is 1 × 10 ¹⁶ atoms / cm ³ which is almost the background level.
cm ³ or less. In the Si film 61, 1 × 10 ¹⁵ to 1
It is in the range of × 10 ¹⁷ atoms / cm ³ .

Further, FIG. 30 shows the results at 550 ° C. of Samples A and B.
3 shows a micrograph after the heat treatment. FIG. 30A corresponds to sample B, and FIG. FIG.
(C) and (D) show that the thickness of the Ta layer 63 in Sample A was 3
0 nm and 50 nm.

In FIG. 30A, an Al single layer (Ta layer = 0)
nm), it is confirmed that aluminum is diffused (exuded). FIG.
From (B) to (D), 20n is formed under the aluminum layer.
It can be seen that by forming a Ta layer having a thickness of at least m, the exudation of aluminum can be prevented.

As described above, the gate wiring is made of the Al layer / T
It can be seen that the two-layer structure of the a layer can prevent Al from diffusing into the semiconductor layer and the gate wiring. According to the findings of the present inventors, in order to obtain an Al blocking effect,
A Ta layer having a thickness of 1 nm or more, preferably 5 nm or more is required. Below this, no blocking effect can be expected.

The upper limit of the Ta layer is 400 nm,
Preferably, it is considered to be about 200 nm. Above this level, the total thickness of the gate electrode is reduced (to reduce steps)
Therefore, the thickness of the aluminum material layer must be reduced, and the low resistance characteristic of aluminum cannot be utilized.

From the above, the thickness of the tantalum layer is 1 to 50.
nm (preferably 1 to 20 nm, more preferably 5 to 20 nm)
20 nm).

Further, the higher the heat treatment temperature of the gate wiring, the greater the degree of diffusion of Al. Therefore, the thickness of the Ta layer may be set according to the heating temperature. For example, Ta
The minimum value of the Al concentration in the underlying insulating film (the SiON film 62 in FIG. 27) of the layer is set to 3 × 10 ¹⁶ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less. Alternatively, the lowest value of the Al concentration in the semiconductor layer is 1 × 10 ¹⁷ at.
The thickness of the Ta layer may be determined so as to be oms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

[Configuration of the Present Invention] The configuration of the present invention is based on the knowledge obtained from the above experimental results. According to the present invention, a second wiring layer is formed on a first conductive film so as to be electrically separated for each wiring, and a plurality of second wiring layers are formed by the first conductive film.
Short the wiring layer. Then, a voltage is applied to the first conductive film to anodize the second wiring layer.

In the above structure, the upper second wiring layer is mainly used as a charge passage, and its thickness is 200 to 50.
It is about 0 nm. In addition, it is preferable that the metal film forming the second wiring layer be formed of aluminum or a material containing aluminum as a main component, so that the resistance of the wiring can be reduced.

Further, a valve metal can be used as the first conductive film. The valve metal refers to a metal in which a barrier type anodic oxide film formed as an anode allows a cathode current to flow but does not allow an anode current to flow, that is, a metal exhibiting a valve action.
(Electrochemical Handbook, 4th edition; edited by The Electrochemical Society, p.370, Maruzen, 1985).

In order to obtain an aluminum blocking effect, a valve metal film having a higher melting point than aluminum is used. These include tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Z
r), titanium (Ti), chromium (Cr) and the like. As the first conductive film, an alloy containing these valve metal elements, for example, molybdenum tantalum (MoTa)
Can be used.

In particular, it has been confirmed that tantalum can be anodized in the same electrolytic solution as a thin film containing aluminum as a main component, and is suitable for the present invention. It is also possible to use molybdenum tantalum (MoTa) or tantalum nitride obtained by adding nitrogen to tantalum.

Although the thickness of the first conductive film is preferably as small as possible, it is necessary that the first conductive film has a thickness that functions as a blocking layer for preventing the constituent atoms of the second wiring layer from diffusing.
The thickness of the first conductive film is 1 nm or more, preferably 5 nm.
Thickness or more.

The upper limit of the thickness of the first conductive film is 50 nm. Preferably, it is considered to be about 30 nm. This is because the first oxide film is formed by oxidizing the first conductive film, and its thickness is about two to three times the thickness of the first conductive film. Therefore, in consideration of the throughput such as the formation of the first conductive film and the etching of the first oxide, the upper limit of the first conductive film is 50 nm, preferably 30 nm.

As described above, the thickness of the first conductive film is 1 to 50 n.
m (preferably 5 to 30 nm, more preferably 5 to 2 nm)
0 nm).

Further, the higher the heat treatment temperature of the gate wiring, the greater the degree of diffusion of Al. Therefore, the thickness of the first wiring layer may be set according to the heating temperature. For example, the base insulating film of the first wiring layer (in the case of FIG. 27, SiON
The minimum value of the Al concentration in the film 62) is 3 × 10 ¹⁶ atoms / cm ³
Or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less, or the lowest value of the Al concentration in the semiconductor layer is 1
× 10 ¹⁷ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ at
The thickness of the first wiring layer may be determined so as to be oms / cm ³ or less. Here, the Al concentration is defined by the lowest value of the SIMS data.

[0077]

DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment is an application of the present invention to a TFT. 1 and 2 are cross-sectional views of a TFT in each process. FIG. 3 is a partially enlarged view of FIGS.

First, as the substrate 100 on which the substrate 100 having an insulating surface is prepared, an insulating substrate such as a glass substrate, a quartz substrate, or a crystalline glass, and silicon oxide, silicon nitride, or silicon nitride oxide is formed on the substrate surface. The formed one can be used.

A semiconductor layer 102 made of a semiconductor material is formed on a substrate 100. Amorphous silicon,
Polycrystalline silicon, or amorphous silicon film, Si _x Ge _1-x
An amorphous silicon germanium film represented by (0 <x <1) or a film obtained by crystallizing the amorphous silicon germanium film may be used.

Next, the insulating film 10 constituting the gate insulating film
Form 3 In close contact with the insulating film 103, a laminated film of a Ta film 103 as a first conductive film and an Al film 105 containing 2 wt% of scandium and having a thickness of 40 nm as a second conductive film is formed. The second conductive film 105 is preferably made of not only pure aluminum but also an additive of several weight% of Si, Sc or the like, or an alloy with a metal such as Si to improve heat resistance. (Fig. 1 (A))

Next, a resist mask 106 is formed and A
l film 105 is patterned and Al is used as a second wiring layer.
The layer 107 is formed. The Al layer 107 constitutes the upper layer of the gate wiring. (FIG. 1 (B))

Next, while the resist mask 258 is left, the probe of the anodic oxidation device is brought into contact with the Ta film 104 to perform anodic oxidation. The conditions are as follows: a 3% aqueous solution of oxalic acid (temperature: 10 ° C.) is used as the electrolytic solution, the ultimate voltage is 8 V, the voltage application time is 40 minutes, and the supply current is 20 mA / 1 substrate. Under this anodic oxidation condition, a voltage is applied to the Al layer 107 by the Ta film, and the anodic oxide film 108 (hereinafter referred to as the AO film
8) is formed. The AO film 108 is a porous (porous) alumina film. The exposed surface of the Ta film 104 is also slightly anodized, but is omitted in the drawing. (Fig. 1 (C))

After removing the resist mask 106, a voltage was applied to the Ta film 104 again in the anodic oxidation apparatus to perform anodic oxidation. The conditions are as follows: an ethylene glycol solution containing 3% tartaric acid is used as the electrolytic solution, the electrolytic solution temperature is 10 ° C., the ultimate voltage is 80 V, the voltage application time is 30 minutes, and the supply current is 30 mA / 1 substrate.

Tartaric acid penetrates the porous AO film 108 and the surface of the Al layer 107 is anodized to form a barrier type anodic oxide film (referred to as a barrier AO film) 109. The barrier AO film 209 is a non-porous alumina film and has corrosion resistance to buffered hydrofluoric acid.

In the Ta film 104, the exposed portion and the portion where the porous AO film 108 is present are anodized to form a tantalum oxide film (hereinafter Ta).
Ox film). The remaining tantalum film (Ta layer) 104 becomes the first wiring layer (Ta layer) 110. Although the TaOx film 111 is thicker than the Ta film 104, the thickness is shown in FIG. 6 for simplicity. (Fig. 1 (D))

FIG. 3A is an enlarged sectional view of a portion surrounded by a dotted line in FIG. Porous A. is formed on the insulating film 103.
O. The region where the film 108 exists is a Ta layer 110, a Ta layer
The Ox layer 111a and the TaOx layer 111b are stacked.
Outside the AO film 108, the TaOx layer 111a,
The aOx layer 111c is laminated. TaOx film 111
In this case, the TaOx layers 111a and 111b
This is a portion oxidized in the same step as the film 109. TaOx
The layer 111a enters the lower part of the AO film 109 by about 5 to 20 nm. The TaOx layer 111b is a porous AO film 10
Since anodization was carried out in the presence of 8, it became TaOx containing Al or an oxide of an alloy of Ta and Al. Further, the TaOx layer 111c is a portion oxidized in the same step as the porous AO film 108, and is less dense than the TaOx layer 111a.

Next, using the AO films 108 and 109 as a mask, the TaOx film 111 is etched.
3 is dry-etched to form a gate insulating film 112. (Fig. 2 (A))

The porous AO film 10 is formed by using an aluminum mixed acid.
8 is removed by etching. Then, impurity ions imparting conductivity are added to the semiconductor layer 102 to form P-type or B-type source / drain regions. The addition of ions may be performed by any of ion implantation, plasma doping, and laser doping. When a CMOS circuit is formed, a region to which impurity ions are added may be selected using a resist mask.

In this step, the gate insulating film 112 and the Ta
The doping conditions, the dose, the acceleration voltage, and the like are adjusted so that the layer 110 and the TaOx layer 111 function as a translucent mask. As a result, the semiconductor layer 102 includes the barrier A.
Low-concentration impurity regions are formed in regions 117 and 118 where the gate insulating film is present, and the regions 115 and 116 where the gate insulating film 112 is not present are portions extending outside the side surfaces of the O. film 109. A source region and a drain region are formed. A region 119 below the Al layer 107 is defined as a channel formation region. (FIG. 2 (B))

FIG. 3B is an enlarged view of a portion surrounded by a dotted line in FIG. On the low-concentration impurity region 118, the gate insulating film 112, the Ta layer 110, and the TaOx layer 111
a, a TaOx layer 111c is laminated. In this structure, in the ON state, the low concentration impurity region 11 is formed by the Ta layer.
Since a voltage is applied to 7, 118, deterioration of the TFT is accelerated.

In this embodiment, the low concentration impurity region 117,
The Ta layer 110 on 118 is thermally oxidized. (Fig. 2 (C))

The thermal oxidation temperature is a temperature at which Ta is oxidized, and may be any temperature at which the Al layer can withstand.
650 ° C. The atmosphere may be an oxidizing atmosphere,
A dry oxygen atmosphere, a steam atmosphere, or a halogen-containing atmosphere such as hydrochloric acid is used. It has been confirmed that all the Ta films having a thickness of 60 nm can be thermally oxidized in a dry oxygen atmosphere at 450 ° C. Here, heat treatment is performed at 450 ° C. for 2 hours in dry oxygen.

FIG. 3C is an enlarged sectional view of a portion surrounded by a dotted line in FIG. On the low-concentration impurity region 118, the Ta layer 110 is transformed into a TaOx layer 111d by thermal oxidation. Therefore, the TaOx film 111 '
TaOx layers 111a, 11 formed by anodic oxidation
1b and a TaOx layer 111d formed by thermal oxidation.
The interface between the Ta layer 110 and the TaOx film 111 'exists below the barrier AO film 109, and the TaOx film 111' overlaps with the lower part of the barrier AO film 109 by about several tens of nm. Therefore, the Al layer 107 is composed of the Ta layer 206 ′ and the barrier AO film 109.
It is wrapped or sandwiched between.

In the conventional aluminum single-layer gate wiring, the heat resistance of the aluminum material was low, so that only a heat treatment of at most about 450 ° C. could be performed in a short time. In addition, in the conventional configuration, even if the heat treatment is performed at about 450 ° C., there is a large possibility that aluminum atoms are diffused into the gate insulating film and the semiconductor layer, which may cause deterioration and variation in TFT characteristics. it was high.

In the present invention, the Al layer 107 of the gate wiring is
By forming the structure surrounded by the a layer 110 and the barrier AO film 109, the deformation (expansion) of the Al layer 107 and A
Since the diffusion of l atoms can be prevented, the upper limit of the heating temperature after the formation of the gate wiring can be increased to about 500 to 650 ° C.

Therefore, in the thermal oxidation step of the Ta layer (first wiring layer), the activation of impurities in the source and drain regions and the recovery of the crystal structure of the semiconductor layer damaged in the doping step can be performed simultaneously. Furthermore, a gettering step can also be performed as described in the embodiment.

Next, an interlayer insulating film 1 made of a silicon oxide film
20 is formed. A contact hole is formed in the interlayer insulating film 120, and a source wiring 121 and a gate wiring 122 are formed. (FIG. 2 (D))

[0098]

Embodiment An embodiment of the present invention will be described with reference to FIGS.

[Embodiment 1] In this embodiment, the present invention is applied to a TFT.
In this example, an N-channel TFT and a P-channel TFT are formed on the same substrate to form a CMOS circuit.

FIG. 4 shows a schematic top view of a TFT. FIG.
In the figure, 201 is a gate wiring, 202 is an N-channel TFT semiconductor layer, and 203 is a P-channel TFT semiconductor layer. 204 and 205 are semiconductor layers 202 and 203
And contact portions of the source wiring, and 206 and 207 are contact portions of the semiconductor layers 202 and 203 and the drain wiring. Reference numeral 508 denotes a contact portion (gate contact portion) with an extraction wiring (not shown).

A manufacturing process of the TFT will be described with reference to FIGS. 5 and 6, the left side shows a cross-sectional view of an N-channel TFT, and the right side shows a cross-sectional view of a P-channel TFT. The cross section of each TFT is indicated by a dotted line AA ′ in FIG.
This corresponds to a cross-sectional view taken along a dotted line BB ′.

First, a glass substrate (Corning 1737; strain point = 667 ° C.) was prepared as the substrate 200, and a 200 nm-thick silicon oxide film was formed as a base film (not shown) on the surface thereof.
It was formed thick. Next, a polycrystalline silicon film (polysilicon film) is formed. First, an amorphous silicon film 251 having a thickness of 45 nm is formed by low-pressure CVD. The thickness of the amorphous silicon film 251 is 10 to 100 nm (preferably 15 to 100 nm).
(75 nm, more preferably 20 to 45 nm).
Next, a silicon oxide film is formed to a thickness of 70 n by a plasma CVD method.
Then, the openings 252a and 252b are formed by wet etching. Then, a Ni acetic acid solution is applied using a spinner, and further dried to obtain a Ni layer 2.
53 is formed. Note that the Ni layer 253 is not a complete layer. (FIG. 5 (A))

The Ni concentration of the Ni acetic acid solution is 1 to 1 in terms of weight.
20 ppm. In this embodiment, it is set to 10 ppm. In this state, the regions 251a, 251b of the amorphous silicon film 251 are formed in the openings 252a, 252b of the mask 252.
Is added to Ni.

Next, heating is performed at 550 ° C. for 6 hours in a nitrogen atmosphere. As schematically shown by arrows, the region 251a,
As Ni diffuses from 251b, crystal growth proceeds with Ni as a nucleus. That is, a crystal grows parallel to the substrate surface. The region crystallized in this manner is referred to as a “lateral growth region” here. (FIG. 5 (B))

After removing the mask 252 made of silicon oxide, the polycrystalline silicon film 252 is patterned to
A semiconductor layer 202 of a channel type TFT and a semiconductor layer 203 of a P-channel type are formed. And the semiconductor layers 202 and 20
3, a silicon nitride oxide film constituting a gate insulating film is formed to a thickness of 120 nm. Although one N-channel TFT and one P-channel TFT are shown in this embodiment, a plurality of N-channel TFTs and a plurality of P-channel TFTs are formed in accordance with the circuit configuration.
(FIG. 5 (C))

Next, a 20 nm thick tantalum film (Ta film) 256 and a 40 nm thick aluminum film (Al film) 257 containing 2 wt% scandium are formed on the substrate 200.
Are formed in a sputtering apparatus. Then, the probe P of the anodic oxidation device is brought into contact with the Al film 257, and
A thin barrier type alumina film (not shown) was formed on the surface of the film 257. This anodic oxidation step is for improving the adhesion of the resist mask. The conditions are as follows: an ethylene glycol solution containing 3% tartaric acid is used as the electrolytic solution, the electrolytic solution temperature is 30 ° C., the ultimate voltage is 10 V, the voltage application time is 15 minutes, and the supply current is 10 mA / 1 substrate.

A resist mask 258 is formed. An alumina film (not shown) is etched with chromium mixed acid, and then the Al film 257 is etched with aluminum mixed acid to form an Al layer 207 as a second wiring layer. The Al layer 207 forms an upper layer of the gate wiring 204. In FIG. 5, the Al layer 207 on the left side and the Al layer 207 on the right side are separated from each other, but are actually integrated as shown in FIG. (FIG. 5E)

FIG. 8 is a cross-sectional view of the gate wiring shown in FIG. FIG. 8B is a cross-sectional view in the channel length direction of the N-channel TFT taken along a chain line XX ′ in FIG.
FIG. 8C is a cross-sectional view taken along a dashed line YY ′ plane in FIG. 8A, and corresponds to a cross-sectional view of an N-channel TFT in a channel width direction. FIG. 9 (A) is a view similar to that of FIG. 18 (B).
It is sectional drawing cut | disconnected by the -Z 'plane. 9 and 10, the relationship among the XX ′ cross section, the YY ′ cross section, and the ZZ ′ cross section is the same as FIG. The planar shape of the Al layer 207 is similar to the gate wiring 201 in FIG. 4, but is simplified to a rectangular shape. 9 and 10, the same applies to the Al layer 207.

Next, while the resist mask 258 was left, the probe P was brought into contact with the Ta film 256 in an anodic oxidation apparatus to perform anodic oxidation. The condition is 3
% Oxalic acid aqueous solution (temperature 10 ° C.)
V, the voltage application time was 40 minutes, and the supply current was 20 mA / 1 substrate. Under these anodic oxidation conditions, a porous anodic oxide film 259 (hereinafter, porous AO film 2) is formed on the side surface of the Al layer 207.
59) is formed. The AO film 259 is a porous (porous) alumina film. The exposed surface of the Ta film 256 is also slightly oxidized, but is omitted in the figure.
(FIG. 6 (A))

After removing the resist mask 258, the probe P is again brought into contact with the Ta film 256 in the anodic oxidation apparatus to perform anodic oxidation. The conditions were as follows: using an ethylene glycol solution containing 3% tartaric acid as the electrolytic solution,
Electrolyte temperature 10 ° C, ultimate voltage 80V, voltage application time 3
0 minute, supply current 30 mA / substrate.

Tartaric acid penetrates the porous AO film 259, and the surface of the Al layer 207 is anodized to form a barrier type anodic oxide film (referred to as a barrier AO film) 209. The barrier AO film 209 is a non-porous alumina film. Further, in the Ta film 256, the exposed portion and the portion where the porous AO film 259 is present are also anodized to form a tantalum oxide film (hereinafter referred to as a TaOx film).
Transformed into 210. Remaining tantalum layer (Ta layer) 2
06 is defined as the first wiring layer. Although the TaOx film 208 is thicker than the Ta film 206, for simplicity, the thickness is shown in the drawing. (FIG. 6 (B))

FIG. 9 is a cross-sectional view of the gate wiring in the state of FIG. 6B. As shown in FIG. 9, the thickness tp of the porous AO film 259 protruding from the side surface of the barrier AO film 209 and the thickness tb of the barrier AO film 209 are all uniform around the Al layer 207.

In the anodic oxidation step of FIG.
The region where the porous AO film 259 exists in the upper portion of the a film 255 is not completely oxidized, and the Ta layer 206
Remain, and a TaOx film 208 is formed as an upper layer.
A part of the TaOx film 208 also exists below the barrier AO film 209.

Next, using the AO films 209 and 234 as a mask, the TaOx film 208 and the insulating film 207 are dry-etched to form a gate insulating film 205. Etching is C
An etching gas in which an O ₂ gas is mixed with F ₄ is used. (FIG. 6 (C))

The porous AO film 25 is formed by the mixed acid of aluminum.
9 is removed by etching. In a portion of the gate insulating film 205 extending outside the side surface of the barrier AO film 209, a Ta layer 206 is formed as a lower layer, and a TaOx film 208 is formed.
Are laminated on the upper layer. (FIG. 6 (D))

In this embodiment, since no anodic oxidation wiring is formed, a step of dividing the gate wiring for each wiring after anodic oxidation is completed is unnecessary.

Next, impurity ions imparting N-type conductivity are added to the semiconductor layers 202 and 203. In this embodiment, phosphorus ions are added to the semiconductor layers 202 and 203 by a plasma doping method. Phosphine diluted to 5% with hydrogen is used as a doping gas. Acceleration voltage of 6
It was as high as 0 to 90 keV. Dose amount is 1 × 10 ¹³ to 8 ×
It is 10 ¹⁵ atoms / cm ³ . In this step, since the acceleration voltage is high, the TaOx film 208, the Ta layer 206, the gate insulating film 20
Phosphorus ions are added through the five ends.

Next, a second doping step is performed at a low acceleration voltage of 5 to 10 keV. In this step, since the acceleration voltage is low, the gate insulating film 205 completely functions as a mask.

In this embodiment, 211, 212, 261,
In the N ⁺ type region indicated by reference numeral 262, 1 × 10 ²⁰ to 8 × 1
Phosphorus was added at a concentration of 0 ²¹ atoms / cm ³ .
The phosphorus concentration in the N − -type regions 214, 215, 265 and 266 is adjusted to be 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ . In the N-channel TFT, the N + -type regions 211 and 212 are a source region and a drain region, and the N ^-- type regions 214 and 215 are low-concentration impurities. (FIG. 7 (A))

Next, the N channel type TFT is covered with a resist mask 260, boron ions are added to the semiconductor layer 203, and the P ⁺ type regions 221 and 222 and the P ⁻ type region 22 are added.
4, 225 are formed. 5% hydrogen in doping gas
Use diborane diluted in water. The dose of boron is
The concentration of boron ions in the P ⁺ -type regions 221 and 222 is N ⁺
The concentration is set to about 1.3 to 2 times the concentration of phosphorus ions added to the mold regions 262 and 261 regions. (FIG. 7 (B))

The P ⁺ regions 221 and 222 are P-channel type T
The source region of the FT, is a drain region, P ^- type region 2
24 and 225 are low concentration impurity regions. Phosphorus ion,
The regions 213 and 223 into which boron ions have not been implanted are intrinsic or substantially intrinsic channel forming regions which later serve as carrier movement paths.

The intrinsic region refers to a region in which electrons and holes are perfectly balanced and is completely neutral, and the substantially intrinsic region is a concentration range (1 × 10 ¹⁵ to 1 × 10 ^{15) in which} a threshold value can be controlled. 1x
10 ¹⁷ atoms / cm ³ ) indicates a region containing an impurity imparting N-type or P-type, or a region where conductivity type is offset by intentionally adding an impurity of opposite conductivity type.

Next, 550 in a dry oxygen atmosphere.
Heat treatment at 2 ° C. for 2 hours. In this embodiment, the Al layer 20 is used.
7 was used as a blocking layer of aluminum atoms for a long time,
Heat treatment at 450 ° C or higher, preferably 500 to 650 ° C, can be performed. (FIG. 7 (C))

By the heat treatment in an oxidizing atmosphere,
In the heat treatment step in a dry oxygen atmosphere, the Ta layer 206 remaining in the portion of the gate insulating film 205 extending outward from the side surface of the barrier AO film 209 is oxidized. By this step, a Ta layer 206 'is defined as a first wiring layer constituting the gate wiring 201. TaOx
The layer 208 'has a portion oxidized by anodic oxidation and a portion oxidized by heat.

FIG. 10 is a cross-sectional view of the gate wiring in the state of FIG. 7C. FIG. 11 shows N in the state of FIG.
1 shows a partially enlarged view of a channel type TFT. TaOx film 20
8 'extends outside the side surface of the barrier AO film 209. The interface between the Ta layer 206 'and the TaOx film 208' exists below the barrier AO film 209, and the TaOx film 20 '
8 ′ overlaps the lower part of the barrier AO film 209 by about several tens of nm. Therefore, the Al layer 207 is composed of the Ta layer 206 'and the barrier AO.
It has a structure that is wrapped or sandwiched by the film 209.

Before heat treatment in an oxidizing atmosphere, the low-concentration impurity regions 214 and 21 are interposed via the gate insulating film 205.
5, 224, and 225 also have a Ta layer 206. When the Ta layer 206 exists on these low-concentration impurity regions, a voltage is applied to the low-concentration impurity regions by the Ta layer in the ON state, so that the TFT is easily deteriorated. Further, in the off state, the current easily leaks from the drain region. Deterioration and leakage current can be reduced by removing the Ta film remaining on the low concentration impurity region.

As a result of the heating step, Ni intentionally added for crystallization of the amorphous silicon film is added to the channel formation regions 213 and 213 as schematically shown by arrows in FIG.
23 to the respective source / drain regions 211 and 21
2, 221 and 222. This is because these regions contain a high concentration of phosphorus element, and Ni that reaches these source / drain regions is captured (gettered) there. Ni can be diffused by about 5 to 10 μm by a heat treatment at 500 to 600 ° C. for about 2 to 4 hours.

As a result, channel forming regions 213 and 22
3 can be reduced. The Ni concentration in the channel forming region is 5 × 1, which is the lower limit of SIMS detection.
It can be set to 0 ¹⁷ atoms / cm ³ or less. On the other hand, the source / drain regions 211 and 2
12, 221, and 222 have a higher Ni concentration than the channel formation regions 213 and 223.

Antimony and bismuth can be used as an impurity for imparting the N-type conductivity in addition to phosphorus.
Phosphorus has the highest gettering ability, followed by antimony.

In particular, like the P-channel type TFT source / drain regions 221 and 222, a region where both phosphorus and boron are added and the boron concentration is about 1.3 to 2 times that of phosphorus is only phosphorus. N-channel type TF
Experiments have confirmed that the gettering ability is higher than that of the T source / drain regions 211 and 212.

Further, the source / drain regions 211, 212, 221, 2
22, and low concentration impurity regions 214, 215, 224,
The phosphorus and boron added to 225 are activated. Conventionally, the low heat resistance of aluminum materials
Since only heat treatment at about 50 ° C. was performed, the activation rate of the dopant (phosphorus, boron) was low, and it was necessary to perform an activation step using an excimer laser. In this embodiment, by increasing the heating temperature to 500 ° C. or higher, the dopant can be sufficiently activated, and the resistance of the source / drain region can be further reduced only by the heat treatment.

Further, the crystallinity of the region where the crystallinity is destroyed by the ion doping step by the heat treatment is improved.

That is, in the heating step in the oxidizing atmosphere shown in FIG. 7C, 1) the Ta layer 206 remaining on the low concentration impurity region;
2) Gettering to reduce the metal element concentration in the channel formation region 3) Activation of impurities in the source and drain regions 4) Annealing to recover crystal structure damage caused by ion implantation Can be performed simultaneously.

In the conventional gate wiring consisting of a single layer of aluminum, the heat resistance of the aluminum material was low, so that only a heat treatment of at most about 450 ° C. could be performed in a short time. In addition, in the conventional configuration, even if the heat treatment is performed at about 450 ° C., there is a large possibility that aluminum atoms are diffused into the gate insulating film and the semiconductor layer, which may cause deterioration and variation in TFT characteristics. it was high.

In this embodiment, the gate wiring Al layer 207 is used.
Is a structure surrounded by a Ta layer 206 ′ and a barrier AO film 209, whereby the Al layer 207 is deformed (expanded).
In addition, since the diffusion of Al atoms can be prevented, the upper limit of the heating temperature after the formation of the gate wiring can be increased to about 500 to 650 ° C.

Next, an interlayer insulating film 2 made of a silicon oxide film
40 is formed. After forming a contact hole in the interlayer insulating film 240, a laminated film made of titanium / aluminum / titanium is formed as an electrode material and patterned to form a wiring 24.
1 to 243 were formed. Here, the N-channel TFT and the P-channel TFT are connected by the wiring 433 to form a CMOS circuit. Further, an extraction wiring 244 for the gate wiring 201 is also formed. (FIG. 7 (D))

Finally, in a hydrogen atmosphere at 350.degree.
A hydrogenation process is performed for about a time, and a hydrogen termination process is performed on the entire TFT.

FIG. 12 is a view of the semiconductor layer 202 of FIG. 7D cut in a channel width direction (a direction orthogonal to the channel length), and corresponds to a cross-sectional view of FIG. 4 cut by a dashed line CC ′. .

Conventionally, in a multilayer wiring, a step is formed on the surface of an interlayer insulating film, reflecting a lower structure. Extraction wiring 2
44 is formed in such a step portion. Conventionally, there has been a problem of disconnection of wiring at a step portion. In particular, a large amount of disconnection of the wiring occurs due to a step between the gate wiring and the gate insulating film.

In this embodiment, since the TaOx film 208 'is formed around the surface of the gate insulating film 205, the difference in height between the gate wiring 201 and the gate insulating film 205 is reduced. Step 2 due to gate insulating film
At 60, the extraction wiring 244 becomes difficult to be divided.

The gate wiring 201 and the extraction wiring 24
When a contact hole for connecting to the Ta layer 206 is formed, buffered hydrofluoric acid is used.
Can function as an etching stopper.
Over-etching of the gate insulating film 205 can be prevented.

[Embodiment 2] In this embodiment, the TFT described in Embodiment 1 is applied to an active matrix substrate. The active matrix substrate of this embodiment is used for a flat-type electro-optical device such as a liquid crystal display device and an EL display device.

This embodiment will be described with reference to FIGS. 13 to 15, the same reference numerals indicate the same components. FIG. 13 is a schematic perspective view of the active matrix substrate of this embodiment. Active matrix substrates
A pixel matrix circuit 301, a scanning line driving circuit 302, and a signal line driving circuit 303 formed over a glass substrate 300
And The scanning line driving circuit 302 and the signal line driving circuit 303 are connected to the pixel matrix circuit 301 by a scanning line 520 and a signal line 530, respectively.

The scanning lines 520 are formed for each row of the pixel matrix circuit, and the signal lines 530 are formed for each column. Near the intersection of the scanning line 520 and the signal line 530, a pixel TFT 500 connected to each wiring is formed.
The pixel TFT 500 has a pixel electrode 550 and an additional capacitor 560.
Is connected. The driving circuits 302 and 303 are
It is mainly composed of S circuits.

The active matrix substrate of the present embodiment can be easily realized by substantially the same steps as in the first embodiment. Example 1
The N-channel type TFT of the CMOS circuit,
A P-channel TFT and a pixel TFT of a pixel matrix are completed.

FIG. 14A shows a pixel matrix circuit 301.
5 is a top view of almost one pixel. FIG.
4 (B) shows a CMOS circuit forming the driving circuits 302 and 303.
It is a top view of a circuit. FIG. 15 is a cross-sectional view of the active matrix substrate.
A sectional view of the S circuit is shown. A cross-sectional view of the pixel matrix circuit 301 is a cross-sectional view taken along a dashed line AA ′ in FIG. 14A, and a cross-sectional view of the CMOS circuit is a dashed line B-A in FIG.
It is sectional drawing along B '.

The pixel TFT 500 of the pixel matrix circuit is an N-channel type TFT. On the glass substrate 300, a semiconductor layer 502 bent in a “U” shape (horse-shoe shape) is formed. A scan line 520 which is a first-layer wiring is formed to intersect with the semiconductor layer 501 with the gate insulating film 505 interposed therebetween. The scanning line 520 is a Ta layer (first wiring layer)
506, Al layer (second wiring layer) 507, TaOx film 3
20 and a barrier AO film 509.

The semiconductor layer 502 includes N ⁺ type regions 511 to 511.
513, two channel formation regions 514 and 515, and low-concentration impurity regions (N ⁻ -type regions) 516 to 519 are formed. N ⁺ type regions 511 and 512 are source / drain regions.

On the other hand, in the CMOS circuit, one gate wiring 401 intersects two semiconductor layers 402 and 403 via a gate insulating film 405. Semiconductor layer 40
2 includes a source / drain region (N ⁺ type region) 411;
412, a channel formation region 413, and low-concentration impurity regions (N ⁻ -type regions) 414 and 415 are formed. In the semiconductor layer 403, a source / drain region (P ⁺ type region)
421 and 422, a channel formation region 423, and low-concentration impurity regions (P ⁻ type regions) 424 and 425 are formed.

After doping the semiconductor layers 402, 403, and 502 with impurities, an interlayer insulating film 310 is formed over the entire surface of the substrate. On the interlayer insulating film 310, a second layer wiring
Source electrodes 431 and 432, a drain electrode 432, a signal line 530, and a drain electrode 532 are formed as electrodes.

As shown in FIG. 13B, the drain region electrode 433 of the CMOS circuit is connected to the gate wiring 4 of another TFT.
10 (first layer wiring).

As shown in FIG. 13A, in the pixel matrix circuit 301, the signal lines 530 are formed for each column, and are orthogonal to the gate lines 501 via the interlayer insulating film 320. The drain electrode 532 is a drain region 51
2 as well as an extraction electrode for connecting the pixel electrode 550 to the pixel electrode 550, and also functions as a lower electrode of an additional capacitor of a pixel portion described later. In order to increase the capacitance of the additional capacitance, the drain electrode 532 is made as wide as possible as long as the opening is not reduced.

The signal line 530 and the drain electrode 532 are formed over the gate wiring 501 and the semiconductor layer 502. Since the TaOx film 508 is formed on the gate wiring 501 to reduce the height difference, it is possible to prevent the signal line 530 and the drain electrode 532 from being cut by the step.

A first flattening film 320 is formed on the second layer wiring / electrode. In this embodiment, silicon nitride (50 nm) / silicon oxide (25 nm) / acryl
The (1 μm) stacked structure is used as the first planarization film 320. Since an organic resin film such as acrylic or polyimide is a solution-coated insulating film formed by a spin coating method, a thick film can be easily formed and a very flat surface can be obtained. Therefore, a film thickness of about 1 μm can be formed at a high throughput, and a good flat surface can be obtained.

Next, on the first planarization film 320, as a third layer wiring, a source wiring 441, a drain electrode 442, a drain wiring 443, and a black mask 541 made of a light-shielding conductive film such as titanium or chrome. Are formed. Prior to the formation of these third-layer wirings 441, 442, 541, the first flattening film 320 is etched to form a concave portion 540 on the drain electrode 532 leaving only the lowermost silicon nitride film. Is formed.

In the pixel matrix circuit 301, in the portion where the concave portion 540 is formed, the drain electrode 532 and the black mask 541 are close to each other only via the silicon nitride film. In the concave portion 540, the drain electrode electrode 53
2. Using the black mask 541 as an electrode, an additional capacitor 560 having a silicon nitride film as a dielectric is formed. Since silicon nitride has a high relative dielectric constant and a small film thickness, it is easy to secure a large capacity.

The black mask 541 is integrated with the pixel matrix circuit, and the portion where the pixel electrode 550 is not formed,
That is, it is formed so as to cover all portions that do not contribute to display. Note that as shown by a dotted line in FIG.

A second planarizing film 330 is formed on the third-layer wirings 441, 442, 541. The second flattening film 330 is formed of 1.5 μm thick acrylic. A large step is formed in the portion where the additional capacitance is formed, and such a step can be sufficiently flattened.

A contact hole is formed in the first planarization film 320 and the second planarization film 330, and a pixel electrode 550 made of a transparent conductive film (typically, ITO or tin oxide) is formed. Thus, an active matrix substrate is completed.

When the active matrix substrate of this embodiment is used for a liquid crystal display device, an alignment film (not shown) is formed to cover the entire surface of the substrate. Rubbing treatment is applied to the alignment film if necessary

When a highly reflective conductive film, typically aluminum or a material containing aluminum as a main component, is used for the pixel electrode 550, an active matrix substrate for a reflective AMLCD can be manufactured.

In FIG. 14, the pixel TFT has a double gate structure, but may have a single gate structure.
A multi-gate structure such as a triple gate structure may be used.

The structure of the active matrix substrate of the present embodiment is not limited to the structure of the present embodiment.
Since the feature of the present invention resides in the configuration of the gate wiring, the other configuration may be appropriately determined by the practitioner.

[Embodiment 3] In this embodiment, an example in which an AMLCD is configured using the active matrix substrate of Embodiment 2 will be described.

FIG. 16 shows the appearance of the AMLCD of this embodiment. In FIG. 16, the same reference numerals as those in FIG. 13 denote the same components, and the active matrix substrate is a glass substrate 300
The pixel matrix circuit 301 and the scanning line driving circuit 30
2. A signal line driving circuit 303 is formed.

Active matrix substrate and counter substrate 60
0 is pasted. Liquid crystal is sealed between the active matrix substrate and the counter substrate 600. However, the active matrix substrate is exposed on only one side, and an FPC (flexible print circuit) 610 is connected to the active matrix substrate. External signals and power are transmitted to circuits 301 to 303 by FPC 610.

The opposing substrate 600 has an I
A transparent conductive film such as a TO film is formed. The transparent conductive film is a counter electrode to the pixel electrode of the pixel matrix circuit 301, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. Further, an alignment film and a color filter are formed on the counter substrate 600 if necessary.

Using the surface on which the FPC 610 is mounted, I
C chips 611 and 612 are attached. These IC chips include video signal processing circuits, timing pulse generation circuits, gamma correction circuits, memory circuits, arithmetic circuits, etc.
Various circuits are formed on a silicon substrate. In FIG. 16A, two are attached, but one may be attached, or three or more may be attached.

Also, a configuration as shown in FIG. 16B can be adopted. In FIG. 16B, the same portions as those in FIG. 16A are denoted by the same reference numerals. Here, the IC shown in FIG.
An example in which signal processing performed by a chip is performed by a logic circuit 620 formed using TFTs on the same substrate is shown. In this case, the logic circuit 620 is configured based on a CMOS circuit similarly to the drive circuits 302 and 303.

In the AMLCD of this embodiment, a black mask is provided on the active matrix substrate (BM on).
TFT) is employed, but in addition, a configuration in which a black mask is provided on the opposite side is also possible.

A color display may be performed using a color filter, or a liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like.
It is good also as composition not using a color filter.

Further, a configuration using a microlens array may be employed as in the technique described in Japanese Patent Application Laid-Open No. 8-15686.

[Embodiment 4] This embodiment is an example in which the present invention is applied to an inverted stagger type TFT. This embodiment is a modification of the gate interconnection forming method of the first embodiment. A manufacturing process of the TFT of this embodiment will be described with reference to cross-sectional views shown in FIGS. In this embodiment, the N-channel TFT
And a CMOS circuit including P-channel TFTs.
17, a cross section of an N-channel TFT is shown on the left side, and a P-channel type cross section is shown on the right side.

First, a 1737 glass substrate (strain point = 667 ° C.) manufactured by Cornings is prepared as the substrate 700. Next, a 20 nm-thick tantalum film (Ta) is formed on the substrate 700.
A film 531 and an aluminum film (Al film) containing scandium with a thickness of 40 nm and containing 2 wt% of scandium were laminated by a sputtering apparatus. Then, a probe of an anodizing apparatus was brought into contact with the Al film to form a thin barrier AO film (not shown) on the surface of the Al film. This anodic oxidation step is for improving the adhesion of the resist mask. The conditions were as follows: an ethylene glycol solution containing 3% tartaric acid was used as the electrolytic solution, the electrolytic solution temperature was 30 ° C., the ultimate voltage was 10 V, the voltage application time was 15 minutes, and the supply current was 10 mA / 1 substrate.

Next, a resist mask is formed. Then, the barrier AO film (not shown) is etched with a chromium mixed acid,
Next, the Al film was etched with an aluminum mixed acid to form an aluminum layer (Al layer) 702 as a second wiring layer.
The Al layer 702 forms the upper layer of the gate wiring. In FIG. 17, the Al layer 702 on the left side and the Al layer 702 on the right side are separated from each other, but they are actually integrated and constitute one gate wiring of the CMOSTFT. (FIG. 17A)

In the anodic oxidation apparatus, the probe P was brought into contact with the Ta film 731 again, and a voltage was applied to perform anodic oxidation. The conditions were as follows: an ethylene glycol solution containing 3% tartaric acid was used as the electrolytic solution;
° C, ultimate voltage 80V, voltage application time 30 minutes, supply current 3
0 mA / 1 substrate. The surface of the Al layer 702 is anodized to form a barrier AO film 704. Also, the Ta film 7
At 31, the exposed part is anodized,
Tantalum oxide film (hereinafter referred to as TaOx film) 510
Metamorphosis. The remaining tantalum layer (Ta layer) 701 is defined as a first wiring layer. (FIG. 17B)

The thickness of the TaOx film 703 is actually about two to three times the thickness of the Ta film 731.
17 and 18 show the same thickness. Further, since the anodic oxidation of the barrier AO film 704 is started at the same time,
The interface between the TaOx film 703 and the Ta layer 701 is a barrier AO
It will be present under the film 704. In this embodiment, Ta
The interface between the layer 701 and the TaOx film 703 is
Is located outside the interface between the barrier AO film 704 and
As described above, the effect of preventing Al from diffusing from the Al layer 702 is high.

Next, TEOS and oxygen are mixed on the entire surface of the substrate and used as a source gas.
A 5-nm-thick silicon nitride oxide film is formed as the gate insulating film 705.

In this embodiment, the TaOx layer 703 is left without being etched for each wiring. Since the entire surface of the glass substrate 700 is covered with the TaOx film 703, diffusion of mobile ions such as sodium from the glass substrate into the semiconductor layer can be prevented. Further, the step of etching the TaOx film 703 is omitted, so that the step can be simplified.

In this embodiment, the T of other gate wirings
Since the a-layers are connected by the TaOx film 703, it is very important that the Ta film does not remain in a portion not functioning as a gate wiring. Porous as in Example 1.
Since the TaOx film 703 is not formed in the presence of AO, it is predicted that there is no remaining Ta film. However, Ta
When an unnecessary Ta film is expected to remain, for example, when the film is thick or when the processing time of the anodic oxidation step is short,
After the anodizing step, thermal oxidation at about 400 to 550 ° C. in an oxygen atmosphere may be added. Even if this thermal oxidation step is added, the throughput is better than when the etching step is performed.

Next, TFT semiconductor layers 706 and 707 are formed on the gate insulating film 705. In this embodiment, a polycrystalline silicon film in which amorphous silicon is crystallized is used for a semiconductor layer. An amorphous silicon film 732 having a thickness of 500 nm was formed by a plasma CVD method using silane as a source gas. Then, a Ni acetic acid solution is applied using a spinner and further dried to form a Ni layer 733. In addition,
The Ni layer 733 is not a complete layer. N
The Ni concentration of the i-acetic acid solution was 5 ppm in terms of weight. (FIG. 17C)

Next, heating is performed at 550 ° C. for 6 hours in a nitrogen atmosphere. In the amorphous silicon film 732, crystal growth proceeds from a portion in contact with the Ni layer 733, and the amorphous silicon film 732 is modified into a polycrystalline silicon film. That is, in this embodiment, the amorphous silicon film 73 is used.
Crystals grow from 2 toward the substrate surface. This crystallization is called “vertical growth” as opposed to “lateral growth”.

The obtained polycrystalline silicon film is patterned to form a semiconductor layer 706 of an N-channel TFT and a semiconductor layer 707 of a P-channel type. (FIG. 17D)

Next, covering the semiconductor layers 706 and 707,
Silicon oxide film (preferably with a thickness of 100 to 300 nm,
In this embodiment, the film thickness was set to 150 nm).
Patterning was performed to form a channel stopper 708 for protecting the channel formation region.

[0185] Source / drain regions are formed by adding impurity ions to the semiconductor layers 706 and 707. Here, a plasma doping method is used. First, the semiconductor layers 706 and 7
07, phosphorus ions are added, and then the semiconductor layer 706 is covered with boron ions, and boron ions are added. Since the channel stopper 708 functions as a doping mask, an N-type source region 710, an N-type drain region 711, and a channel formation region 712 are formed in the semiconductor layer 706 in a self-aligned manner. In the semiconductor layer 707, a P-type source region 713, a P-type drain region 714, and a channel formation region 715 are formed in a self-aligned manner (FIG. 18A).

The source / drain regions 710, 71
The phosphorus concentration of 1,713,714 is 1 × 10 ²⁰ to 8 × 10
It should be ²¹ atoms / cm ³ . The boron concentration of the P-type source / drain regions 713 and 714 is set to be about 1.3 to 2 times the concentration of phosphorus ions added to the regions. This is because the source / drain regions 710, 711, 71
3, 714 as a Ni gettering sink.

Next, heat treatment is performed at 550 ° C. for 2 hours in a nitrogen atmosphere. As a result of this heat treatment, Ni in the channel formation regions 712 and 714 is reduced as shown by arrows in the drawing to the source / drain regions 710, 711 and 713.
It diffuses to 714 where it is captured. By setting the gettering atmosphere to a halogen-added atmosphere such as hydrochloric acid, Ni can be vaporized as a halide, so that the gettering effect is increased.

By this heat treatment for gettering, Ni in the channel forming regions 712 and 714 diffuses into the source / drain regions as schematically shown by arrows, where they are captured (gettered). . As a result, the Ni concentration in the channel formation regions 712 and 714 can be reduced. The Ni concentration in the channel formation region is SIM
The detection limit of S can be set to 5 × 10 ¹⁷ atoms / cm ³ or less. On the other hand, source / drain regions 710 and 7
Since 11, 713 and 714 are used for gettering sinks, the Ni concentration is higher than that of the channel formation regions 712 and 715. (FIG. 18 (B))

Next, an interlayer insulating film 7 made of a silicon oxide film
20 is formed. After forming a contact hole in the interlayer insulating film 720, a laminated film made of titanium / aluminum / titanium is formed as an electrode material and patterned to form a wiring 72.
1 to 723 were formed. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 722 to form a CMOS circuit. Finally, a hydrogenation process is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to perform a hydrogen termination process on the entire TFT (FIG. 18D).

The structure of the inverted staggered TFT is not limited to this embodiment, but may be a channel etch type.

[Embodiment 5] This embodiment is an example in which the TFT of Embodiment 4 is applied to an active matrix substrate. In FIG. 19, in FIG.
801, a P-channel TFT 802 is a CMOS circuit 80
3. This embodiment can be easily realized by substantially the same steps as in the fourth embodiment.

First, according to the process of the fourth embodiment, an N-channel TFT 801, a P-channel TFT 802, a pixel T
FT804 is completed. N-channel TFT 801, P
The channel type TFT 802 is a CMOS circuit 803 forming a driving circuit for driving a pixel matrix circuit. 83
Numeral 0 denotes a wiring for taking out a gate wiring of the pixel TFT 802. 850 is an interlayer insulating film, and 860 is a pixel electrode.

The gate wiring of each of the TFTs 802, 805, and 806 is composed of Ta layers 811, 821 and Al layers 812, 822.
Each of the Ta layer and the Al layer has its own anodic oxide film, a TaOx film 813 and a barrier AO film 81.
4,824.

When the gate wiring has a two-layer structure, the Ta layer 811 can be used as an etching stopper when a contact hole for connecting the extraction wiring 830 and the gate wiring is formed.

In this embodiment, since the surface of the glass substrate 800 is covered with the TaOx film 813, it is possible to prevent mobile ions such as sodium from diffusing from the glass substrate into the AMLCD substrate. Further, the step of etching the TaOx film 813 is omitted, so that the step can be simplified.

Since the TaOx film 813 is transparent to visible light, the TaOx film 813 can be used as a transmission type AMLCD substrate even if the TaOx film 813 is left on the entire surface of the substrate as in this embodiment.

[Embodiment 6] The structure of the present invention is not limited to a TFT, and a MOSFET formed by using a silicon substrate.
It is also possible to apply to. The present invention uses MOS
FIG. 20 shows an example in which the present invention is applied to an FET.

In FIG. 20, reference numeral 901 denotes a silicon substrate;
902 is a field oxide film, 903 is a source region, 90
4 is a drain region, and 905 is a pair of LDD regions.
906, a gate insulating film; 920, an interlayer insulating film;
Reference numeral 21 denotes a source wiring, and 9822 denotes a drain wiring.

The gate wiring structure is almost the same as the structure described in the first embodiment. The gate wiring comprises a Ta layer 911, an Al layer 912, a TaOx film 913, and a barrier AO film 914. The difference between the present embodiment and the first embodiment is that the thermal oxidation process is omitted and the Ta layer is left on the LDD region 905 via the gate insulating film 906.

By doing so, Inverse T
(Inverted T-shaped) LDD structure can be used, and an increase in ON current is observed. In the case of this embodiment, the LDD region 90
5 has a lower concentration than the conventional LDD.

[Embodiment 7] In Embodiments 1 to 6, the first wiring layer of the gate wiring was formed of a Ta film. However, instead of the Ta film, a Ta film containing nitrogen (N) and a tantalum nitride (here, In this case, a TaNy film is used.)

In the fifth embodiment, the Ta layer is the
Although it is electrically connected to 0, the resistance can be reduced by using a TaNy film as the Ta film. This is because the TaNy film is less likely to be oxidized than the Ta film, and when a contact hole for an extraction wiring is opened,
It is considered that a natural oxide film is hardly formed in the aNy film.

Further, by adding nitrogen, Ta
It is also considered that a state in which the resistance is lower than that results in a stable crystal structure. Two crystal structures of Ta are known: a stable cubic crystal with low resistance (α-Ta or bcc-Ta) and a high-resistance and metastable tetragonal crystal (β-Ta). Ta
When a film is formed, generally, at room temperature, β-Ta grows preferentially at a thickness of 1 μm or less, and α-Ta hardly grows. Growth of α-Ta preferentially 1
One method is to add nitrogen during film formation.
Since the nitrogen-added Ta film (TaNy) is cubic and stable,
It is known that the similarity between α-Ta and the crystal structure is very high.

To form a TaNy film, a sputtering method is used. Conditions are Ta target, back pressure 4.0 × 10 ^-4 P
a, sputtering pressure 4.0 × 10 ⁻¹ Pa, sputtering current 4
A, the flow rate of argon gas is 50 sccm, and the flow rate of nitrogen gas is 2 sccm. The thickness is set to 20 nm. The resistivity of the TaNy film was 30 to 50 μΩcm, and the sheet resistance value calculated from the resistivity was 15 to 25Ω / □ when the film thickness was 20 nm. The resistivity of the TaNy film can be controlled by the flow rate of nitrogen gas during film formation.

This embodiment is different from Embodiments 1 to 6 in that Ta
The film is replaced with a TaNy film, and the others are the same. The anodic oxidation of the TaNy film is possible under the same conditions as the Ta film, and the formed anodic oxide is a tantalum oxide film containing nitrogen. Further, the Ta film is not only a single layer of TaNy film but also, for example, Ta film / TaNy film or T
a film laminated from the lower layer in the order of aNy film / Ta film;
It is also possible to use a three-layer film of a y film / Ta film / TaNy film. By forming a TaNy film as a base and then forming a Ta film, α-Ta having low resistivity can be easily grown.

[Embodiment 8] The TFT of the present invention was manufactured by using AML.
The present invention can be applied to various other electro-optical devices and semiconductor circuits other than the CD.

An electro-optical device other than AMLCD is E
Examples include an L (electroluminescence) display device and an image sensor.

The semiconductor circuit includes an arithmetic processing circuit such as a microprocessor constituted by an IC chip, and a high-frequency module (MMIC) for handling input / output signals of a portable device.
Etc.).

As described above, the present invention can be applied to all semiconductor devices functioning with circuits constituted by insulating gate type TFTs.

Embodiment 9 The AM shown in Embodiments 2 and 5
LCDs are used as displays for various electronic devices. Note that an electronic device described in this embodiment is defined as a product equipped with an active matrix liquid crystal display device.

Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, and the like). Is mentioned. One example of them is shown in FIG.

FIG. 21 (A) shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and the like.

FIG. 21B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, operation switches 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102, the audio input unit 2103, and the image receiving unit 2106.

FIG. 21C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to an image receiving unit 220.
3. Applicable to the display device 2205 and the like.

FIG. 21D shows a head mounted display, which comprises a main body 2301, a display device 2302, and a band 2303. The present invention can be applied to the display device 2302.

FIG. 21E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 21F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. In addition, the present invention can be used for an electronic bulletin board, a display for advertising, and the like.

[0219]

According to the present invention, since the wiring can be anodized without forming the voltage supply wiring for anodic oxidation, the space for forming the voltage supply wiring can be provided while the wiring has heat resistance. Also, the circuit can be designed without considering an etching margin for dividing the voltage supply wiring. Therefore, high integration of a circuit and reduction of a substrate area are promoted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 3 is a partially enlarged view of FIGS. 1 and 2;

FIG. 4 is a plan view of the CMOS circuit according to the first embodiment.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 8 is a cross-sectional view of a gate wiring.

FIG. 9 is a cross-sectional view of a gate wiring.

FIG. 10 is a cross-sectional view of a gate wiring.

FIG. 11 is a partially enlarged sectional view of a TFT.

FIG. 12 is a cross-sectional view of a TFT in a channel width direction.

FIG. 13 is an external perspective view of an active matrix substrate according to a second embodiment.

FIG. 14 is a top view of a pixel matrix circuit and a CMOS circuit.

FIG. 15 is a cross-sectional view of an active matrix substrate.

FIG. 16 is a perspective view of an AMLCD according to a third embodiment.

FIG. 17 is a cross-sectional view illustrating a manufacturing process of a TFT of Example 4.

FIG. 18 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 19 is a sectional view of an active matrix substrate according to a fifth embodiment.

FIG. 20 is a sectional view of a MOSFET according to a sixth embodiment.

FIG. 21 is a configuration diagram of an electronic device using the semiconductor device of Embodiment 9;

FIG. 22 is a sectional view of an aluminum pattern showing a procedure of an anodizing step.

FIG. 23 is an SEM photograph observing a cross-sectional structure of an aluminum pattern.

FIG. 24 is a TEM observation photograph showing a cross-sectional structure of an aluminum pattern.

FIG. 25 is a schematic diagram of the TEM observation photograph of FIG. 24.

FIG. 26 is a partially enlarged photograph of FIG. 24;

FIG. 27 is a cross-sectional view of SIMS measurement samples A and B.

FIG. 28 shows SIMS data of Sample A.

FIG. 29 shows SIMS data of Sample B.

FIG. 30 is an optical micrograph of Samples A and B after heat treatment.

FIG. 31 is a cross-sectional view showing a step of manufacturing a TFT using a conventional anodic oxidation step.

[Explanation of symbols]

 Reference Signs List 200 substrate 201 gate wiring 206 tantalum layer (first wiring layer) 207 aluminum layer (second wiring layer) 208 tantalum oxide film (TaOx film) 209 barrier alumina (A.O.) film

Claims (19)

[Claims] 1. A semiconductor device having a plurality of insulated gate transistors, wherein a gate wiring of the insulated gate transistor is formed by a second conductive film on a first wiring layer made of a first conductive film. A first oxide film formed by oxidizing the first wiring layer; and a second oxidation film formed by oxidizing the second wiring layer. And a lower portion of the second wiring layer is in contact with only the first wiring layer, and a lower portion of the second oxide film is formed of the first wiring layer and the first wiring layer. At least one semiconductor layer of the insulated gate transistor in contact with an oxide film contains a catalytic element that promotes crystallization of silicon; the concentration of the catalytic element is higher in the source region and the drain than in the channel formation region. A semiconductor device, wherein the region is higher. 2. The method according to claim 1, wherein the catalyst element is Fe, Co, Ni, Ru, Rh, P
A semiconductor device comprising at least one element selected from d, Os, Ir, Pt, Cu, Au, and Ge. 3. The semiconductor device according to claim 1, wherein an impurity imparting N-type conductivity is added to the source region and the drain region. 4. The semiconductor device according to claim 1, wherein the source region and the drain region of at least one of the semiconductor layers include an impurity imparting an N-type conductivity and a P-type conductivity. A semiconductor device to which an impurity to be added is added. 5. The semiconductor device according to claim 1, wherein the first conductive film has a thickness of 1 to 50 nm. 6. The semiconductor device according to claim 1, wherein the first conductive film is a valve metal film. 7. The method according to claim 1, wherein the first conductive film is made of a material mainly composed of one of Ta, Nb, Hf, Ti, and Cr. Alternatively, a semiconductor device formed of an alloy containing these metal elements. 8. The semiconductor device according to claim 1, wherein the first conductive film is made of tantalum or a material containing tantalum as a main component. 9. The semiconductor device according to claim 1, wherein the second conductive film is made of aluminum or a material containing aluminum as a main component. 10. A method for manufacturing a semiconductor device including a plurality of wirings having a stacked structure in which a second wiring layer is stacked on a first wiring layer, wherein a first conductive film is formed on an insulating surface. Forming a second conductive film in contact with the first conductive film; patterning the second conductive film to selectively form the second wiring layer for each of the wirings Forming, anodizing the second wiring layer by applying a voltage to the first conductive film, and thermally oxidizing the first conductive film. Of manufacturing a semiconductor device. 11. A method for manufacturing a semiconductor device provided with a wiring having a stacked structure in which a second wiring layer is stacked on a first wiring layer, wherein a step of forming a first conductive film on an insulating surface is performed. A, a step B of forming a second conductive film in contact with the first conductive film, and patterning the second conductive film to form a second wiring layer on the first conductive film. A step C of selectively forming a first conductive film; and a step D of applying an voltage to the first conductive film to anodize the second wiring layer and anodize the first conductive film. A method for manufacturing a semiconductor device, comprising: a step E of selectively removing an anodic oxide film of the first conductive film; and a step F of thermally oxidizing the remaining first conductive film. 12. A method for manufacturing a semiconductor device including a gate wiring having a stacked structure in which a second wiring layer is stacked on a first wiring layer, wherein a plurality of semiconductor layers are formed on an insulating surface. A step A, a step B of forming an insulating film in close contact with the semiconductor layer, a step C of forming a first conductive film on the insulating film, and the second step of forming a second conductive film on the first conductive film. A step D of forming a conductive film, a step E of patterning the second conductive film, and a step E of forming the second wiring layer crossing the semiconductor layer with the insulating film interposed therebetween; Applying a voltage to the conductive film to anodize the second wiring layer to form a first anodic oxide film covering a side surface of the second wiring layer; By applying a voltage to the conductive film, the second wiring layer is anodized and the second wiring layer is anodized. Forming a second anodic oxide film covering the surface of the first wiring layer and selectively anodic oxidizing the first conductive film to form a third anodic oxide film; A step G of defining a layer; a step H of patterning the insulating film and the third anodic oxide film using the first and second anodic oxide films as masks; A step I of removing a film, and adding an impurity to a semiconductor layer using the insulating film, the second and third anodic oxide films as masks, to form a source region, a drain region, and a channel formation region in the semiconductor layer. A forming step J; and a step K of heat-treating the first wiring layer in an oxidizing atmosphere.
And a method for manufacturing a semiconductor device. 13. The step A according to claim 12, wherein: a step of forming an amorphous semiconductor film in contact with the insulating surface; a step of contacting a catalyst element with the amorphous semiconductor film; A semiconductor device comprising: a step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film; and a step of patterning the crystalline semiconductor thin film in an island shape to form the semiconductor layer. Method of manufacturing. 14. The method according to claim 13, wherein the catalyst element is Fe, Co, Ni, Ru, Rh, P
A method for manufacturing a semiconductor device, comprising using at least one element selected from d, Os, Ir, Pt, Cu, Au, and Ge. 15. The method for manufacturing a semiconductor device according to claim 13, wherein an impurity imparting N-type conductivity is added to the source region and the drain region. . 16. The process J according to claim 13, wherein in at least one of the semiconductor layers, the source region and the drain region have an impurity imparting a P-type conductivity and N. A method for manufacturing a semiconductor device, comprising adding an impurity imparting a conductivity type of a mold and an impurity imparting a conductivity type of a P type. 17. The method for manufacturing a semiconductor device according to claim 13, wherein the thickness of the first conductive film is 1 to 50 nm. 18. The material according to claim 13, wherein the first conductive film is mainly made of a metal element selected from the group consisting of Ta, Nb, Hf, Ti, and Cr. A method for manufacturing a semiconductor device, which is formed using an alloy containing a metal element. 19. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive film is formed using aluminum or a material containing aluminum as a main component.