JPH11261075A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for realizing a TFT whose gate electrode is formed of aluminum material as well as keeping it high in yield. SOLUTION: A gate electrode is formed of a laminated film composed of a tantalum layer 110 and an aluminum layer 105, and then an active layer is doped with phosphorus and subjected to a thermal treatment carried out at temperatures of 450 to 700 deg.C for gettering impurity elements (mainly nicked). In this structure, the tantalum layer 110 serves as a stopper, and aluminum atoms can be prevented from penetrating into a gate insulating film even in a temperature range of 450 to 700 deg.C. The edge of the tantalum layer 110 becomes a tantalum oxide 112 and has an effect to lessen damage inflicted on a gate insulating film due to implantation of ions when an LDD region is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique relating to a structure of a thin film transistor (hereinafter abbreviated as TFT) using a semiconductor thin film and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display device (hereinafter, referred to as A) in which a pixel matrix circuit and a driving circuit are constituted by TFTs formed on an insulating substrate.
MLCD) is gaining attention.

As an insulating substrate, it is desired to use an inexpensive glass substrate rather than an expensive substrate such as a quartz substrate from an industrial point of view.

Such AMLCDs range from projectors of about 0.5 to 2 inches to notebook computers of about 10 to 20 inches, and are mainly used as small to medium display displays.

When the size of the AMLCD is increased, the area of a pixel matrix circuit serving as an image display section increases, and the length of a source wiring, a gate wiring, and the like increases. Further, since it is necessary to narrow the wiring width for miniaturization, an increase in wiring resistance has become a problem. Further, a TFT such as a source wiring and a gate wiring is connected to each pixel for each pixel, and a large parasitic capacitance is connected thereto.
Therefore, since the gate wiring and the gate electrode are generally formed at the same time, the delay of the gate signal has been a problem with the increase in the area of the panel.

For this reason, the use of aluminum or a material containing aluminum as a main component (hereinafter abbreviated as aluminum material) for the wiring is considered promising. Aluminum materials have the advantage of low resistance, but have the disadvantage of low heat resistance.

Further, it is considered that a crystalline silicon film having higher mobility than an amorphous silicon film is used as an active layer of a TFT. Conventionally, to obtain a crystalline silicon film by heat treatment, it was necessary to use a quartz substrate having a high strain point.

Therefore, the present applicants have introduced a technique of obtaining a crystallized silicon film by introducing a trace amount of a metal element into the amorphous silicon film and then performing a heat treatment (Japanese Patent Laid-Open No. 6-23205).
No. 9, JP-A-7-321339). Metal elements that promote crystallization include Fe, Co,
Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, A
One or more types selected from u are used. By using this technique, a crystalline silicon film can be manufactured by a process (a low-temperature process) at a temperature that the glass substrate can withstand.

However, the problem with this technique is that the metal element used for crystallization remains in the crystalline silicon film, which has an adverse effect on the element characteristics (particularly reliability, uniformity, etc.) of the TFT. Was. Then, the present applicants further formed a technique of forming a wiring using an aluminum material and then gettering a metal element in a crystalline silicon film (Japanese Patent Application No. 8-330).
602) was also developed.

However, in the above gettering technique, since the aluminum material having low heat resistance is used for the wiring, the heat treatment is limited to a temperature range (about 300 to 450 ° C.).

The above temperature range is low as a temperature at which the metal element in the crystalline silicon film is sufficiently gettered, so that a long processing time is required. However, since the heat resistance of the aluminum material is low, a long time is required. Time heating was avoided. In addition, even in a heat treatment in a temperature range (about 300 to 450 ° C.), aluminum atoms diffuse into the gate insulating film and reach the channel formation region, thereby causing a malfunction of the TFT or a TF.
This caused a decrease in T characteristics.

Similarly, even in the heat treatment in the above temperature range, protrusions such as hillocks and whiskers generated from the aluminum material by the heat treatment penetrate through the gate insulating film to reach the channel formation region, and the operation of the TFT is reduced. Had a defect.

In addition, similarly, even in the heat treatment in the above temperature range, a pinhole exists in the gate insulating film, and aluminum atoms flow into the pinhole during the heat treatment and enter the channel formation region. Had reached it.

As described above, various factors can be considered as a factor of an operation failure of a TFT (using an aluminum material as a wiring), and a short circuit (a gate electrode / channel formation region) is mainly caused by a heat treatment (300 ° C. or more). (Short circuit) is likely to occur.

[0015]

An object of the present invention is to provide a technique for realizing a TFT using an aluminum material as a gate electrode at a high yield.

Therefore, an object is to provide a technique for preventing a short circuit between a gate electrode and an active layer (particularly, a channel formation region). Another object is to provide a method for manufacturing a TFT in which aluminum atoms are not diffused into a gate insulating film in a case where heat treatment is performed after formation of a wiring using an aluminum material.

[0017]

According to a first aspect of the invention disclosed in this specification, a plurality of TFTs formed on the same substrate are provided.
A semiconductor device including a semiconductor circuit having
FT includes a gate electrode formed by stacking a valve metal layer and a material layer mainly containing aluminum or aluminum; a gate insulating film in contact with the gate electrode; a channel formation region in contact with the gate insulating film; A high-resistance region in contact with the formation region, and a source region or a drain region in contact with the high-resistance region, wherein the source region or the drain region contains a metal element that promotes crystallization of silicon at a high concentration. And the high resistance region contains the metal element at a low concentration.

The gist of the present invention is to prevent the intrusion of aluminum atoms into the gate insulating film by using a tantalum / aluminum laminated film (tantalum is a lower layer) for a gate electrode which is conventionally formed only of an aluminum material. It is in. That is, a tantalum layer provided as a lower layer is used as a blocking layer for aluminum atoms having low heat resistance. With such a configuration, it is possible to perform a heat treatment at 300 ° C. or higher, preferably 450 ° C. or higher after the wiring is formed.

Therefore, according to the present invention, after the wiring is formed, the source region or the drain region is doped with
It is characterized by performing a heat treatment at 50 ° C. or higher to reduce metal elements in the crystalline silicon film. Thus, the concentration of the metal element in the channel formation region is 1 × 10 ¹⁷ atom
s / cm ³ , typically undetectable level of SIMS,
It is estimated that it has been reduced to about 1 × 10 ¹⁵ atoms / cm ³ . On the other hand, the concentration of the metal element in the source region or the drain region is 5 × 10 ¹⁸ atoms / cm ³ or more, typically 1 × 10 ¹⁹ atoms / cm ³ or more. In addition, other Group 15 elements such as arsenic and antimony can be used in addition to the phosphorus element, but the phosphorus element has the highest gettering effect. It is desirable to use nickel as a metal element that promotes crystallization.

As the blocking layer other than the above-mentioned tantalum, a metal film or an alloy film mainly containing a metal element having higher heat resistance (melting point, etc.) than aluminum, or an inorganic film (silicon nitride film, silicon nitride oxide film, oxide film) (A silicon film) can be used. In addition, it is also possible to use those laminated films. Preferably, niobium (Nb), hafnium (Hf), zirconium (Zr), titanium (Ti), or the like, which is called a valve metal, is used. Tantalum is one of the valve metals.

The thickness of the tantalum layer must be large enough to function as a barrier against the movement of aluminum atoms. The present inventors conducted an experiment on the film thickness, and the experimental results are shown in FIG. FIG. 19 is a photomicrograph showing a state after a process at 550 ° C. for 2 hours after forming a wiring using an aluminum layer.
Note that the test was performed both when a silicon film formed by a low-pressure CVD method was used as an active layer and when a silicon film formed by a plasma CVD method was used as an active layer.

Aluminum single layer (Tantalum layer = 0 nm)
In FIG. 19A of [Conventional configuration], it was confirmed that aluminum was diffused (bleeding). In addition, aluminum laminated (Tantalum layer = 20
19 (b) and (c), it was confirmed that aluminum was not diffused and a sufficient blocking effect was obtained. According to the findings of the present inventors, a tantalum layer having a thickness of 1 nm or more, preferably 5 nm or more is required. Below this, no blocking effect can be expected.

The upper limit is 400 nm, preferably 20 nm.
We think it is about 0nm. Above this, the thickness of the aluminum material layer must be reduced in order to reduce the total thickness of the gate electrode (to reduce the level difference), making it impossible to take advantage of the low resistance characteristic of aluminum.

From the above, the thickness of the tantalum layer is 1 to 400.
nm (preferably 1 to 200 nm, more preferably 5 to 50 n
It can be said that it is preferable to select from the range of m).

The valve metal layer such as a tantalum layer is characterized in that it can be easily anodized with the same electrolytic solution as the aluminum layer, and the form of formation of the anodized layer (such as the direction in which the oxide layer is formed). It is a material suitable for use in the present invention because it is close to that of an aluminum film.
In addition, when the stacked gate electrodes are configured to be covered with the respective anodic oxide films, the insulation properties are improved and the heat resistance is improved.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein a metal element for promoting crystallization of silicon is provided. A first step of forming an active layer using a crystalline silicon film including silicon, a second step of forming a gate insulating film, and a tantalum layer and a material layer containing aluminum or aluminum as a main component are sequentially stacked and formed. A third step of forming a gate electrode, a fourth step of selectively anodizing the aluminum or the material layer containing aluminum as a main component to form a porous alumina layer, and a second anodization. At the same time as forming the nonporous alumina layer on the surface of the aluminum or aluminum-based material layer, all or one of the tantalum layers located under the porous alumina layer A fifth step of transforming a portion into a tantalum oxide layer; and a sixth step of doping a region to be a source or drain region of a TFT with a phosphorus element.
And a seventh step of performing a heat treatment to getter the metal element.

In the above structure, the heat treatment in the seventh step is performed at 450 to 700 ° C.

According to a third aspect of the invention, there is provided a method of manufacturing a semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein a metal element for promoting crystallization of silicon is provided. A first step of forming an active layer using a crystalline silicon film including silicon, a second step of forming a gate insulating film, and a tantalum layer and a material layer containing aluminum or aluminum as a main component are sequentially stacked and formed. A third step of forming a gate electrode, and a fourth step of selectively performing first anodic oxidation on the aluminum or the material layer containing aluminum as a main component to form a porous alumina layer,
A second anodic oxidation is performed to form a nonporous alumina layer on the surface of the aluminum or the material layer containing aluminum as a main component, and at the same time, a part of the tantalum layer located below the porous alumina layer. A fifth step of transforming into a tantalum oxide layer, a sixth step of removing the porous alumina layer, and a third anodic oxidation are performed, so that the surface of the aluminum or the material layer containing aluminum as a main component is not formed. Forming a porous alumina layer and simultaneously transforming the entire tantalum layer located under the porous alumina layer into a tantalum oxide layer; and forming the gate electrode, the tantalum oxide layer, and the gate insulating film. An eighth step of doping with a phosphorus element as a mask and a ninth step of performing a heat treatment to getter the metal element. The features.

The above structure is characterized in that a step of etching a gate insulating film using the non-porous alumina layer and the porous alumina layer as a mask is provided.

In the above structure, the fourth step is performed in a solution containing oxalic acid as a main component.

The above structure is characterized in that the fifth step is performed in a solution containing tartaric acid as a main component.

The above structure is characterized in that the heat treatment in the ninth step is performed at 450 to 700 ° C.

According to a fourth aspect of the present invention, there is provided a semiconductor device including a semiconductor circuit having a plurality of N-channel TFTs and a plurality of P-channel TFTs formed on the same substrate, TFT and the P-channel TFT
FT includes a gate electrode formed by stacking a valve metal layer and a material layer mainly containing aluminum or aluminum; a gate insulating film in contact with the gate electrode; a channel formation region in contact with the gate insulating film; A source region or a drain region that is in contact with the formation region; and a source or drain region that is in contact with the high resistance region. The source or drain region of the N-channel TFT and the P-channel TFT contains a phosphorus element. The semiconductor device is characterized in that a source region or a drain region of the P-channel TFT contains an impurity imparting P-type conductivity at a higher concentration than the concentration of the phosphorus element. .

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a semiconductor circuit including a plurality of N-channel TFTs and a plurality of P-channel TFTs formed on the same substrate. A first step of forming an active layer using a crystalline silicon film using a metal element that promotes crystallization of silicon, a second step of forming a gate insulating film, and a valve metal layer. A third step of forming a gate electrode in which aluminum or a material layer containing aluminum as a main component is sequentially formed and forming a gate electrode by selectively anodizing the aluminum or the material layer containing aluminum as a main component; A fourth step of forming an alumina layer, and simultaneously forming a nonporous alumina layer on the surface of the aluminum or aluminum-based material layer by anodic oxidation again, A fifth step of transforming all or a part of the valve metal layer located under the porous alumina layer into an anodized layer, and a source region or a drain region of the N-channel TFT and the P-channel TFT. A sixth step of doping a region to be doped with a phosphorus element, a seventh step of performing a heat treatment to getter the metal element, and forming a region to be a source region or a drain region of the P-channel type TFT in a P-type TFT. A sixth step of doping an impurity imparting mold conductivity with a higher concentration than the concentration of the phosphorus element.

According to a sixth aspect of the invention, there is provided a semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein the TFTs are made of aluminum or a material mainly containing aluminum. A gate electrode comprising a layer, a blocking layer in contact with the gate electrode, a gate insulating film in contact with the blocking layer, a channel forming region in contact with the gate insulating film, a high resistance region in contact with the channel forming region, and A source region or a drain region that is in contact with a resistance region, wherein the source region or the drain region contains a metal element that promotes crystallization of silicon at a high concentration, and the high resistance region includes the metal element. Is a low concentration semiconductor device.

In the sixth structure, the blocking layer is a silicon nitride oxide film, a silicon nitride film, a silicon oxide film, or a laminate thereof.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1A is an example of a cross-sectional view of a TFT along a channel forming region direction (a direction in which carriers move) using the present invention. Although FIG. 1 shows only one TFT, a semiconductor circuit including a plurality of TFTs is formed on the substrate 101. Note that an interlayer insulating film and source / drain electrodes covering the gate electrode are omitted.

In FIG. 1A, reference numeral 101 denotes a substrate, 10
Reference numeral 2 denotes a base film (insulating silicon film). When a base film is provided, glass (including crystallized glass), a silicon wafer, ceramics, quartz, or the like can be used for the substrate 101. When quartz is used, the base film may not be provided.

The active layer of the TFT is obtained by patterning a semiconductor thin film (typically, a polycrystalline polysilicon film) in an island shape. In the present invention, any type of semiconductor thin film may be used as the active layer. In particular, a technique of crystallizing using a metal element (typically, nickel element) that promotes crystallization (Japanese Patent Application Laid-Open No. 6-232059) JP-A-7-321
A remarkable effect can be obtained when a crystalline silicon film utilizing the method described in U.S. Pat.

A gate electrode is arranged on the active layer via a gate insulating film 104. The gate electrode is formed by stacking an aluminum layer 105 and a valve metal layer (typically a tantalum layer), and a TFT having a small signal delay is realized by utilizing the low resistance of the aluminum material. In the present invention, since the valve metal layer functions as a blocking layer, heat treatment at 300 ° C. or higher, preferably 450 ° C. or higher has become possible.

FIG. 1B is an enlarged view of a region surrounded by a dotted line indicated by reference numeral 106. As shown in FIG. 1B, the active layer 103 includes a channel formation region 107 and an LDD.
(Lightly Doped Drain) region 108, drain (or source) region 109, and channel formation region 10
The gate insulating film 104 is provided on the gate insulating film 7 and the LDD region 108. Strictly speaking, the channel forming region and the LDD
An offset region is formed between the regions, but if the width is small, the offset effect is hardly obtained. In addition,
In this specification, a low-concentration impurity region (including an LDD region) and an offset region are referred to as a high-resistance region.

In the present invention, in a structure in which a high resistance region such as an LDD region or an offset region is arranged adjacent to a channel forming region, a phosphorus element is typically added to a source region and a drain region (at least one region). Doping and gettering site. Then, heat treatment is performed typically at 300 to 700 ° C., preferably 450 to 600 ° C., so that the metal element concentration in the channel formation region and the high-resistance region is reduced, typically by SIMS (secondary ion analysis method). To 1 × 10 ¹⁶ atoms / cm ³ or less, preferably by SIMS to 1 × 10 ¹⁸ atoms / cm ³ or less. The dose of phosphorus is 1 × 10 ¹³ io
If it is ns / cm ² or more, the metal element concentration (typically nickel) can be reduced to 1 × 10 ¹⁸ atoms / cm ³ or less.

When the above heat treatment is performed, the metal element concentrations in the high resistance region and the channel formation region are lower than those in the source region and the drain region. FIG. 18 shows the concentration distribution of the metal element concentration in the crystalline silicon film after the heat treatment and the concentration distribution of the phosphorus element in the crystalline silicon film.

The higher the temperature of the heat treatment, the better the gettering effect is obtained, and the longer the treatment time, the better. However, in consideration of the object of the present invention of utilizing a low-temperature process, the upper limit temperature is desirably 700 ° C., and in consideration of the throughput of the manufacturing process, the upper limit time is 24 hours (preferably 1 to 12 hours, typically 1 to 12 hours. Is preferably 2 to 8 hours).

When a P-channel TFT (PTFT) is manufactured, the source and drain regions of the PTFT are doped with a phosphorus element, and P-type conductivity is imparted at a concentration exceeding the concentration of the phosphorus element. An impurity (typically, B (boron)) is doped.

The gate insulating film 104 is a silicon oxide film,
Silicon nitride film, silicon nitride oxide film (represented by SiO _x N _y )
Alternatively, it is composed of a laminated film thereof.

In particular, since a silicon nitride film has a high ion blocking effect, it is effective to use it as a part of a gate insulating film. Further, a silicon nitride oxide film has both physical properties of a silicon oxide film and a silicon nitride film, and thus is suitable as a gate insulating film.

The laminated structure is not limited to two layers, but may be a plurality of layers. For example, a stacked film (called an ONO film) having a three-layer structure of silicon oxide / silicon nitride / silicon oxide is suitable as the gate insulating film of the present invention because of its high reliability.

The gate electrode is laminated in the order of a valve metal layer (tantalum layer) 110 and an aluminum layer 105.
By the anodic oxidation treatment, a part of the aluminum layer 105 becomes a nonporous alumina layer 111, and a part of the valve metal layer (tantalum layer) 110 becomes an anodic oxide layer (tantalum oxide layer) 112 of the valve metal layer.

In the above anodic oxidation, only the tantalum layer which does not overlap with the aluminum layer 105 and the nonporous alumina layer 111 is anodized, and as shown in FIG.
An anodized layer (tantalum oxide layer) of a valve metal layer is formed so as to project outside the aluminum layer 105.

When forming the source / drain regions, an anodic oxide layer (tantalum oxide layer) of a valve metal layer is used.
The LDD region 108 can be formed by intentionally lowering the impurity concentration thereunder using the mask 112 as a mask. Therefore, the drain (or source) region 109 and the LD
Junction with D region 108 (source or drain junction)
Is defined in a self-aligned manner by the ends (protruding ends) of the anodized layer (tantalum oxide layer) of the valve metal layer.

The configuration of the present invention having the above configuration will be described in detail with reference to the following embodiments.

[0053]

[Embodiment 1] A manufacturing process of a TFT utilizing the present invention will be described with reference to FIGS. In this embodiment, an example in which an N-channel TFT (NTFT) is manufactured is described. In addition, the present invention has a feature from the formation of the gate electrode to the formation of the source region and the drain region,
For other parts, a known technique can be used. Therefore, the present invention is not limited to the manufacturing process of this embodiment.

First, a glass substrate (Corning 1737; strain point = 667 ° C.) is prepared as the substrate 201, and a silicon oxide (silicon oxide) film is formed thereon as the base film 202.
It was formed to a thickness of nm. Then, an active layer 203 having a thickness of 45 nm was formed thereon by a known means. The thickness of the active layer 203 is 10 to 100 nm (preferably 15 to 75 nm, more preferably
20-45 nm). (Fig. 2 (A))

The active layer 203 is formed by a technique for obtaining a crystalline silicon film using a metal element which promotes crystallization of silicon (Japanese Patent Laid-Open No.
A polycrystalline silicon film (polysilicon film) using JP-A No. 232059 and JP-A-7-321339) was used. In this example, nickel was used as a metal element for promoting crystallization.

When the state shown in FIG. 2A was obtained, a gate insulating film 204 made of a silicon nitride oxide film was formed, and a tantalum layer 205 having a thickness of 50 nm and an aluminum layer 206 having a thickness of 350 nm were sequentially formed. In this embodiment, an aluminum layer containing 2 wt% of scandium was used as the aluminum layer 206.

The tantalum layer 205 and the aluminum layer 206 may be formed by a vapor phase method (typically, a sputtering method). (Fig. 2 (B))

Next, the tantalum layer 205 and the aluminum layer 206 were etched by a dry etching method or a wet etching method to form a laminated pattern 207 serving as a prototype of a gate electrode after the etching.

As an etching gas for dry etching, a chlorine-based gas can be used for etching an aluminum layer, and a fluorine-based gas can be used for etching a tantalum layer. It has been confirmed that when the tantalum layer is as thin as about 50 nm, the aluminum layer and the tantalum layer can be collectively etched with a chlorine-based gas. (Fig. 2 (C))

Further, a resist mask (not shown) is used for patterning the laminated pattern 207. However, if the surface of the aluminum layer is covered with a thin anodic oxide film before forming the resist mask, the adhesion is improved. improves.

Next, an anodic oxidation treatment with a reaching voltage of 8 V was performed in a 3% oxalic acid aqueous solution while leaving the resist mask,
A porous alumina layer 208 having a thickness of 600 to 800 nm was formed. In this solution, the tantalum layer remained without being anodized, and only the aluminum layer was selectively anodized.
(FIG. 2 (D))

Further, after removing a resist mask (not shown), an anodic oxidation treatment was performed at an ultimate voltage of 80 V in an ethylene glycol solution containing 3% tartaric acid. In this treatment, both the aluminum and tantalum layers were anodized. (FIG. 2 (E))

Only the portion of the tantalum layer 205 that is in contact with the porous alumina layer 208 was anodized to form a tantalum oxide layer 209. This is because only that portion contacts the electrolytic solution that has permeated the inside of the porous alumina layer 208.

On the surface of the aluminum layer 206 (inside of the porous alumina layer), a nonporous alumina layer 210 having a thickness of 100 to 120 nm was formed. The thickness of the nonporous alumina layer 210 is determined by the ultimate voltage.

Here, SE showing the state shown in FIG.
An M photograph is shown in FIG. FIG. 16A is a SEM photograph of a sample obtained by experimentally reproducing the structure of FIG. 2E at a magnification of 40,000, and shows a state near the porous alumina layer.

FIG. 16A is a schematic diagram of FIG.
(B). In FIG. 16B, reference numeral 10 denotes a base made of a silicon oxide film, 11 denotes a tantalum layer, 12 denotes an aluminum layer, 13 denotes a tantalum oxide layer, 14 denotes a nonporous alumina layer, and 15 denotes a porous alumina layer. .

As shown in FIG. 16 (B), the surface of the aluminum layer 12 is covered with a nonporous alumina layer 14, and a porous alumina layer 15 is formed outside thereof. Then, the end of the tantalum layer 11 (below the porous alumina layer)
Has a tantalum oxide layer 13 formed thereon. This tantalum oxide layer serves to protect the LDD region obtained in a later step.

As can be seen from the photograph shown in FIG. 16A, when the tantalum layer is transformed into a tantalum oxide layer by anodic oxidation, the volume expands about twice and the film thickness becomes 2 to 4 times. (Typically three times).

After such a structure was obtained, the gate insulating film 204 was etched by dry etching using the gate electrode and the porous alumina layer as a mask. As an etching gas, CHF ₃ gas was used at a flow rate of 55 sccm, and the pressure was 55 mTorr and the supply power was 800 W.

In this step, the gate insulating film 204 was etched in a self-aligned manner, and was processed into an island-like pattern as shown by 211. At this time, the end portion (GI end portion) 212 of the gate insulating film remains in such a manner as to protrude outside the gate electrode. Further, the active layer which will later become the source / drain region is exposed.

After this etching step was completed, the porous alumina layer 208 used as a mask was removed using an aluminum mixed acid (mixed solution of phosphoric acid, acetic acid, nitric acid and water) solution kept at 45 ° C.

At this time, since the selectivity between the porous alumina layer 208 and the tantalum oxide layer 209 is large, the tantalum oxide layer 209 is not etched. This is apparent from the SEM photograph shown in FIG.

The SEM photograph shown in FIG. 17 is shown in FIG.
3 shows a state in which only the porous alumina layer 15 has been removed from the state shown in FIG. From this photograph, it can be confirmed that the tantalum oxide layer remains in the shape of the eaves.

When the state shown in FIG. 3A is obtained,
The first impurity ion implantation step was performed by an ion implantation method or a plasma doping method.
In this embodiment, an N-channel TFT (NT
In this example, P (phosphorus) was used as an impurity ion for imparting N-type conductivity. In any case, the doping step is not particularly limited as long as it is a method of ionizing an impurity element imparting N-type conductivity and electrically implanting it. First, the first test was performed by increasing the acceleration voltage to 60 to 90 keV. The dose is 1 × 10 ¹³
What is necessary is just to set to about 8 × 10 ¹⁵ atoms / cm ³ . (FIG. 3
(B))

In this step, since the acceleration voltage is high, impurity ions are implanted through the tantalum oxide layer 209 and the GI end 212. That is, the impurity was also added below the region covered by the GI end and the like.

In this step, the GI end 212
Impurities implanted below will determine the impurity concentration of the LDD region later. Therefore, it is necessary for a practitioner to set an optimal dose amount at the time of ion implantation so that the LDD region contains a desired concentration of impurities. In this embodiment, the source region and the drain region contain 1 × 10 ²⁰ to 8 × 1 phosphorus.
It was implanted at about 0 ²¹ atoms / cm ³ . GI end 212
The lower portion was adjusted so that an impurity element (phosphorus) was added at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ .

By performing the impurity ion implantation process as described above, low concentration impurity regions 213 and 214 are formed. The dose of the phosphorus element was determined under the condition that the region to be doped was a source and a drain region. Further, it is preferable that the doping concentration is performed under a condition that is higher than the concentration of the metal element (typically, nickel) after gettering. By doing so, gettering of the metal element can be performed more effectively in a later step.

At this time, since the tantalum oxide layer 209 exists on the GI end portion 212, there is an advantage that damage during ion implantation does not directly reach the gate insulating film. That is, generation of unnecessary trap levels in the gate insulating film can be suppressed.

Next, a second ion implantation step was performed at an acceleration voltage as low as 5 to 10 keV. In this step, the acceleration voltage is low, so that the GI end 212 completely functions as a mask (Japanese Patent Application Laid-Open No. Hei 7-135318 because a tantalum oxide layer is also present).
The mask effect is improved as compared with the technology described in Japanese Patent Application Publication No.

Therefore, in this step, impurity ions are added only to the regions (source region or drain region) indicated by 215 and 216. In this embodiment, 1 × 10 ²⁰ to 1 ×
It was adjusted so that phosphorus was added at a concentration of 10 ²¹ atoms / cm ³ .

At the same time, the impurity region formed in the first ion implantation step remains below the GI end 212 and becomes the LDD region 217. Therefore, the junction between the source or drain regions 215 and 216 and the LDD region 217 is defined by the GI end (the end of the tantalum oxide layer).

Further, regions 21 where no impurities were implanted in the first and second impurity ion implantation steps
Numeral 8 becomes an intrinsic or substantially intrinsic channel forming region which later becomes a carrier movement path.

Note that intrinsic refers to a completely neutral region where electrons and holes are perfectly balanced, and a substantially intrinsic region refers to a concentration range (1 × 10 ¹⁵ to 1 × 10
¹⁷ atoms / cm ³ ) indicates a region containing an impurity imparting N-type or P-type, or a region where the conductivity type is offset by intentionally adding an impurity of the opposite conductivity type.

After the step of implanting ions into the source and drain regions is completed as described above, a heat treatment is performed in an inert gas atmosphere.

In the prior art (a single layer of aluminum material), the heat resistance of the aluminum material was low,
Only a heat treatment of about 450 ° C. could be performed. In addition, in the conventional configuration, even if the heat treatment is performed at about 450 ° C., there is a large possibility that aluminum atoms are diffused into the gate insulating film and the active layer, which may lead to deterioration and variation in TFT characteristics. it was high.

On the other hand, in this embodiment, since the tantalum layer provided as the lower layer is used as a blocking layer for aluminum atoms which has low heat resistance and easily diffuses, it is used for a long time and at 450 ° C. or more, preferably 500 to 650. It became possible to carry out a heat treatment at ℃. In this embodiment,
Heat treatment was performed at 550 ° C. for 2 hours in a nitrogen atmosphere. (FIG. 4 (A))

By the above-mentioned heating step, the metal element is changed as shown in FIG.
In the process of diffusion in the direction indicated by the arrow in (A), gettering is performed on the phosphorus element. 219 is a source region containing a high concentration of a metal element, and 220 is a drain region containing a high concentration of a metal element. As a result, the metal element concentrations in the channel formation region and the high resistance region could be reduced. The conventional temperature range (300 to 450 ° C.) was insufficient for gettering.

When nickel is used as a metal element that promotes crystallization, phosphorus and nickel are converted to NiP, NiP ₂ ,
It is in the form of various compounds such as NiP ₃ . Further, since the bonding state is extremely stable, in this embodiment, nickel was used as a metal element for promoting crystallization, and phosphorus was used as an element for gettering. FIG. 18 shows the distribution of nickel and phosphorus after the heat treatment.

In the heat treatment step, the region 2 where the crystallinity has been destroyed by the accelerated implantation of impurity ions.
Improvement of the crystallinity of 15, 216, 217 proceeds. This largely relates to the concentration of the nickel element in the regions 215, 216, and 217. That is, in the regions 219 and 220 where the nickel element is concentrated, the crystallization by the action of the nickel element is strongly promoted, and the damage of the crystal structure caused by the doping of the phosphorus element is recovered.

In addition, at the same time as the gettering in the heat treatment, the activation of the impurities in the source region 219 and the drain region 220 is performed. Conventionally, since the heat resistance of the aluminum material was low, only the heat treatment at about 450 ° C. was performed, so that the activation rate of the dopant (phosphorus) was low.

Conventionally, another step (laser annealing, strong light annealing, etc.) has been added and performed as a step of recovering damage to the crystal structure caused by ion implantation and a step of activating impurities. Note that, in this embodiment as well, laser annealing or high-light annealing of front or rear surface irradiation may be performed simultaneously with the heat treatment. Alternatively, as another step, laser annealing of high-side or low-side irradiation, high-temperature annealing, or the like may be added to obtain a better active layer.

That is, in the heating step after doping in the present embodiment, 1) gettering treatment for reducing the metal element concentration in the channel formation region and high resistance region 2) activation treatment for impurities in the source and drain regions 3) ions Annealing is performed simultaneously to recover damage to the crystal structure caused by the implantation.

Next, an interlayer insulating film 221 is formed. As the interlayer insulating film 221, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, an organic resin film, or a stacked film thereof can be used. Note that examples of the organic resin film include polyimide, polyamide, polyimide amide, and acrylic.

After the interlayer insulating film 221 is formed, contact holes are formed and the source electrode 222 and the drain electrode 2 are formed.
23 are formed. In this embodiment, a laminated conductive layer made of titanium / aluminum / titanium is used as these electrode materials.

Lastly, a hydrogenation process is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to perform a hydrogen termination process on the entire TFT. Thus, a TFT having a structure as shown in FIG. 4C is completed. In the TFT thus manufactured, since a tantalum layer exists between the gate electrode and the gate insulating film, diffusion of aluminum atoms and the like can be prevented by heat treatment during the manufacturing.

Therefore, TFTs can be manufactured with a very high yield, and a high non-defective rate can be secured even in the case of manufacturing an AMLCD in which one million or more TFTs are manufactured on the same substrate. Accordingly, it is possible to reduce the manufacturing cost of the liquid crystal module and a product (electronic device) equipped with the liquid crystal module.

[Embodiment 2] In Embodiment 1, the case of manufacturing an NTFT has been described as an example.
Needless to say, it can be applied to An example of a manufacturing process and conditions of a P-channel TFT (PTFT) is briefly described below.

First, a source and a source into which phosphorus ions have been implanted.
Impurity ion (bore) for imparting P-type conductivity to the rain region
Ron) is injected. 5% with hydrogen as doping gas
Use diborane diluted in water. Acceleration voltage is 60 to 90
kV, dose amount is 1 × 10¹³~ 8 × 10^Fifteenatoms / cm
^Three And In addition, it was implanted into the source and drain regions.
From the maximum value of boron concentration to the maximum value of phosphorus ion concentration
3 × 10 ¹⁹~ 3 × 10^{twenty one}atoms / cm^Three When
It is important to adjust the dose so that this
As a result, the conductivity types of the source and drain regions are inverted and the P-type
Impurity region can be formed. In addition, LDD area
The step of inverting the conductivity type of the region may be performed.

Further, if a known CMOS technology is used, N
It is also easy to construct a CMOS circuit in which a TFT and a PTFT are complementarily combined.

In this embodiment, FIG. 5 shows an example in which an active matrix substrate in which a driving circuit formed of a CMOS circuit and a pixel matrix circuit formed of an NTFT are formed on the same substrate.

In FIG. 5, NTFT 501, PTFT
Reference numeral 502 denotes a CMOS circuit 503. As described above, if the known CMOS technology is used, it can be easily realized in substantially the same steps as in the first embodiment.

The pixel TFT (NTFT in this embodiment) 504 constituting the pixel matrix circuit can be realized by adding a few steps to the manufacturing steps described in the first embodiment.

First, according to the steps of Embodiment 1, FIG.
To get the structure. Next, as shown in FIG.
0 is formed. In this embodiment, a stacked structure of silicon nitride (50 nm) / silicon oxide (25 nm) / acryl (1 μm) is used as a first planarization film.

The organic resin film such as acryl or polyimide is a solution-coated insulating film formed by spin coating, so that a thick film can be easily formed and a very flat surface can be obtained. Therefore, a film thickness of about 1 μm can be formed at a high throughput, and a good flat surface can be obtained.

Next, a black mask 51 made of a light-shielding conductive film is formed on the first flattening film 50. Further, prior to forming the black mask 51, the first planarizing film 5 is formed.
0 is etched to form a concave portion leaving only the lowermost silicon nitride film.

By doing so, the drain electrode and the black mask are close to each other via the silicon nitride film only in the portion where the concave portion is formed, and the storage capacitor 52 is formed there.
Since silicon nitride has a high relative dielectric constant and a small film thickness, it is easy to secure a large capacity.

When the auxiliary capacitance 52 is formed at the same time when the black mask 51 is formed, the second planarizing film 53 is formed.
Is formed of 1.5 μm thick acrylic. Although a large step is formed in the portion where the auxiliary capacitance 52 is formed, such a step can be sufficiently flattened.

Finally, contact holes are formed in the first flattening film 50 and the second flattening film 53, and a pixel electrode 54 made of a transparent conductive film (typically, ITO) is formed. Thus, a pixel TFT 504 as shown in FIG. 5 can be manufactured.

When a highly reflective conductive film, typically aluminum or a material containing aluminum as a main component, is used for the pixel electrode, an active matrix substrate for a reflective AMLCD can be manufactured.

In FIG. 5, the gate electrode of the pixel TFT has a double gate structure, but may have a single gate structure or a multi-gate structure such as a triple gate structure.

Further, the structure of the active matrix substrate is not limited to the structure of this embodiment. Since the feature of the present invention lies in the configuration of the gate electrode, the other configuration may be appropriately determined by the practitioner.

[Embodiment 3] In this embodiment, an example in which an LDD region is formed in a step different from that of the embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. Note that the configuration of the present embodiment can be used for the configuration of the second embodiment.

First, according to the same steps as in the first embodiment, FIG.
(D) state is obtained. Then, the porous alumina layer 20
8 is selectively removed to obtain the state shown in FIG. In this state, the tantalum oxide layer 209 is exposed.

Next, a step of implanting impurity ions with a high acceleration voltage is performed. This step is a step for forming a later LDD region as described in the first embodiment. Therefore, the impurity concentration of the low concentration impurity regions 601 and 602 is 1 × 10 ¹⁷ to
Adjust so as to be about 1 × 10 ¹⁸ atoms / cm ³ .

The process shown in FIG. 3B and the process shown in FIG. 6B described in the first embodiment are different only in the presence or absence of the gate insulating film on the source / drain regions. In the case of this embodiment, impurity ions are implanted into all the active layers by through doping via a gate insulating film.

The advantages of the through doping are that the process can be shortened (the step of etching the gate insulating film can be omitted) and the active layer is not directly damaged by ion implantation.

Next, as shown in FIG. 6C, a step of implanting impurity ions with a low acceleration voltage is performed. In this step, since the region where the tantalum oxide layer 609 exists functions as a mask, the low concentration impurity region described above remains below the region.

As a result, the source region 603, the drain region 604, the LDD region 605, and the channel formation region 606
Is formed. Also in this case, since the tantalum oxide layer 209 is present on the LDD region 605, damage to the GI at the time of ion implantation is reduced in that portion.

Thereafter, the heat treatment (5) was performed in the same manner as in Example 1.
(50 ° C., 2 hours), the effects of reducing the metal element in the channel formation region and the high resistance region, activating the dopant, and recovering the crystal structure can be simultaneously obtained. (FIG. 6 (D))

Then, similarly to the first embodiment, the interlayer insulating film 60 is formed.
7, a source electrode 608 and a drain electrode 609 are formed, and finally a hydrogenation step is performed to complete a TFT as shown in FIG.

[Embodiment 4] In this embodiment, an example in which an offset region is provided instead of the LDD region in Embodiment 1 will be described with reference to FIG.

First, according to the steps of Embodiment 1, FIG.
To get the same state. Then, the first impurity ion implantation step shown in the first embodiment is not performed, but the ion implantation step using a low acceleration voltage as described with reference to FIG.
(FIG. 7 (A))

In this implantation step, since the tantalum oxide layer and the gate insulating film function as a mask, 1 × 10 ²⁰ to
A source region 701 and a drain region 702 containing an impurity (phosphorus) at a concentration of 1 × 10 ²¹ atoms / cm ³ are formed.

The region denoted by reference numeral 603 maintains an intrinsic or substantially intrinsic state because no impurity (phosphorus) ions are added, and functions as a mere high-resistance region because no gate voltage is applied. Such a region 703
Is called an offset area.

While the LDD regions described in the first to third embodiments are effective in alleviating the electric field at the drain junction, the offset regions are rather effective in reducing the off current (current flowing when the TFT is off) or the leak current. is there.

Also in this case, the tantalum oxide layer 209 has the effect of reducing the damage to the gate insulating film during ion implantation.

After the step of implanting ions into the source and drain regions is completed as described above, a heat treatment is performed in an inert gas atmosphere as in the first embodiment. In this embodiment, the heat treatment was performed at a temperature of 600 ° C. for 12 hours. Through this heating step, the metal element is diffused in the direction indicated by the arrow in FIG. 7B and is gettered by phosphorus using 703 and 704 as gettering sites. As a result, the metal element concentrations in the channel formation region and the high resistance region could be reduced.

Thereafter, the interlayer insulating film 7 is formed in the same manner as in the first embodiment.
07, a source electrode 708 and a drain electrode 709, and finally a hydrogenation step is performed to complete the TFT.
(FIG. 7 (C))

In addition, in this embodiment, since the impurity ion implantation step is performed only once, the throughput can be improved. Also, the throughput can be improved by performing the ion implantation step with a high acceleration voltage instead of the ion implantation step with a low acceleration voltage in the present embodiment. Note that the dose of the impurity ions is adjusted so as to function as a source region and a drain region.

Further, the gate insulating film may be left on the entire surface of the active layer, and a through-doping of phosphorus may be performed once to form a source region and a drain region, and a heat treatment may be performed.

It is easy to apply this embodiment to the configuration of the second embodiment.

[Embodiment 5] In this embodiment, an example in which a TFT is formed in a step different from that of the embodiment 1 will be described with reference to FIGS.
Explanation will be made using 0. It should be noted that the configuration of the present embodiment is changed to Embodiment 2
And the configuration of the fourth embodiment.

First, the steps up to the state shown in FIG. 2D are the same as those of the first embodiment, so that the description thereof is omitted. Note that FIG. 2D corresponds to FIG. Then, the insulating film 204 is selectively removed to obtain the state of FIG. In this state, the active layer 2 not in contact with the gate insulating film 811
The area 03 is exposed.

Next, an anodic oxidation treatment is performed in an ethylene glycol solution containing 3% tartaric acid at an ultimate voltage of 10 to 20 V. In this process, both the aluminum layer and the tantalum layer are anodized, and a thin anodic oxide film is formed.
(FIG. 9A)

In the tantalum layer 205, only a portion in contact with the porous alumina layer 208 is anodized to form a thin tantalum oxide layer 809a.

On the surface of the aluminum layer 206 (on the inside of the porous alumina layer), a thin nonporous alumina layer 810a having a thickness of 10 to 30 nm is formed. The thickness of the nonporous alumina layer 810a is determined by the ultimate voltage.

Then, the porous alumina layer 208 is selectively removed to obtain the state shown in FIG. In this state, the tantalum layer is exposed.

Next, the anodic oxidation treatment is performed again at an ultimate voltage of 80 V in an ethylene glycol solution containing 3% tartaric acid. In this process, both the aluminum layer and the tantalum layer are anodized, and the thick anodic oxide films 810b and 810b are formed.
9b is formed. (FIG. 9 (C))

As described above, in this embodiment, the anodic oxidation is performed three times. However, at the time of performing the third anodic oxidation, the tantalum layer is exposed and easily transformed into a tantalum oxide layer. It is characterized in that the thickness is increased to about 4 times (typically 3 times).

As such a configuration, it is preferable that the tantalum layer existing above the LDD region later is completely transformed into a tantalum oxide layer (809b) so that the TFT operates normally.

Next, as shown in FIG. 9D, a step of implanting impurity ions with a high acceleration voltage is performed. This step is a step for forming a later LDD region as described in the first embodiment. Therefore, the impurity (phosphorus element) concentration of the low concentration impurity regions 813 and 814 is 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ^3.
Adjust to the extent.

Next, as shown in FIG. 9E, a step of implanting impurity ions at a low acceleration voltage is performed. In this embodiment, 1 ×
Adjustment was made so that phosphorus was added to the source region or the drain region at a concentration of 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In this step, the region where the tantalum oxide layer 809b exists functions as a mask, so that the low-concentration impurity region described above remains below the region.

As a result, the source region 815, the drain region 816, the LDD region 817, and the channel formation region 818
Is formed. In this case as well, since the tantalum oxide layer 809b exists on the LDD region 817, damage to the GI at the time of ion implantation is reduced in that portion. Note that the same concentration distribution as in FIG. 18 was obtained.

Thereafter, the heat treatment (5) was performed in the same manner as in Example 1.
(50 ° C., 2 hours) to perform activation and recovery of the crystal structure simultaneously with gettering. (FIG. 10A) 81
Reference numeral 9 denotes a source region containing a high-concentration metal element, and 820 denotes a drain region containing a high-concentration metal element.

Then, as in the first embodiment, the interlayer insulating film 82
1. A source electrode 822 and a drain electrode 823 are formed, and a hydrogenation step is finally performed to complete a TFT as shown in FIG.

As another structure, a source region and a drain region are formed while leaving a gate insulating film on the entire surface of the active layer.
A configuration in which a step of performing a heat treatment may be performed may be employed.

[Embodiment 6] This embodiment shows an example in which a quartz substrate is used and a crystalline silicon film is formed on the substrate by using the technique disclosed in Japanese Patent Application Laid-Open No. 8-335152. In the above publication, gettering is performed at the stage of obtaining a crystalline silicon film.

In the above publication, even in a manufacturing method using a quartz substrate having a high strain point, after forming a wiring using an aluminum material, the method is limited to a heat treatment at a temperature in consideration of the heat resistance of the aluminum material. In contrast, by adopting the structure of the present invention (aluminum material / tantalum layer),
After the wiring is formed, 450 ° C to 700 ° C, preferably 600 ° C
It has become possible to perform a degree of heat treatment.

In this embodiment, gettering has already been performed in the process of forming the crystalline silicon film. However, after the wiring is formed, the impurity activation heat treatment is performed on the source region and the drain region doped with the phosphorus element. (About 600 ° C.) for several hours (2 to 3 hours).

By doing so, the activation of impurities and the
The crystal structure was recovered, and a TFT with higher uniformity was obtained. The second gettering was performed simultaneously with the activation of the impurities and the recovery of the crystal structure.

Thereafter, as in the first embodiment, an interlayer insulating film,
A TFT is completed by forming a source electrode and a drain electrode and finally performing a hydrogenation step.

It is to be noted that the configuration of the present embodiment can be used for the configuration of the second embodiment.

As another structure, a source region and a drain region are formed while leaving a gate insulating film on the entire surface of the active layer.
A configuration in which a step of performing a heat treatment may be performed may be employed.

[Embodiment 7] In this embodiment, a wiring having the two-layer gate electrode structure (aluminum material layer / tantalum layer) shown in each of the above embodiments is formed, and phosphorus is doped.
FIG. 11 shows an example in which a silicide layer is formed after a step of adding heat treatment (typically, FIG. 4A). The following briefly describes a manufacturing method.

First, a source region and a drain region are obtained in the same manner as in the above embodiments. Next, a metal film that reacts with silicon with silicide is formed. As this metal film, 5
Any metal film that undergoes a silicide reaction at a heating temperature of about 00 to 600 ° C. may be used, for example, Ta, Cr, Mn, Nb, M
Any one of the metal films of o and Ti can be used. The metal film is in contact with only the source region and the drain region in the active layer.

By the heat treatment (450 to 700 ° C.),
The silicon in contact with the metal film reacts to form silicide layers 232 and 233. Note that all of the source region and the drain region may be silicided.

Then, the unreacted metal film is removed by etching. At this time, the gate insulating film is protected by the anodic oxide film. Note that the heat treatment may be performed by heating in an electric furnace or RTA using an infrared lamp. In this embodiment, by providing the silicide layer, the sheet resistance of the source region and the drain region can be reduced.

Thereafter, as in the first embodiment, an interlayer insulating film,
A TFT is completed by forming a source electrode and a drain electrode and finally performing a hydrogenation step.

As another structure, a metal film may be formed immediately after doping with phosphorus, and heat treatment at 450 ° C. to 700 ° C. may be performed. In this case, the gettering of phosphorus and silicidation are performed simultaneously, and the process can be shortened.

[Embodiment 8] In this embodiment, the wiring having the two-layer gate electrode structure (aluminum material layer / tantalum layer) shown in each of the above embodiments was formed, doped with phosphorus, and subjected to heat treatment. After the process, a method for forming a contact with a lead wiring will be described.

In the conventional gate electrode structure (a single layer of an aluminum material), an aluminum mixed acid (phosphoric acid, acetic acid, nitric acid, and water: 85: 5:
An acid obtained by mixing a chromic acid solution with an acid mixed at a ratio of 5: 5 (hereinafter referred to as a chromium mixed acid) is used. When a chromium mixed acid was used, the selectivity with respect to the silicon oxide film constituting the base film could not be obtained, and the base film was etched.
The chromium mixed acid refers to a chromic acid solution (300 g of chromic acid, 150 g of water) with respect to 10 liters of the above aluminum mixed acid.
Is mixed with 550 g).

In the present embodiment, a contact hole was formed by using the tantalum layer 205 as an etching stopper by employing a two-layer gate electrode structure as shown in FIG. Then, a lead wiring 224 is formed,
Good contact with the tantalum layer exposed at the bottom of the contact hole could be obtained. FIG. 12 shows an example in which a contact hole is formed on the active layer.
The contact is not particularly limited as long as it is a contact between the layered gate wiring and the lead wiring.

[Embodiment 9] In each of the above embodiments, an example was shown in which a tantalum layer was used as a lower blocking layer in the gate electrode. However, in this embodiment, a blocking effect of the tantalum layer was used instead of the tantalum layer. A high silicon nitride film was used. FIG. 13 shows the structure of this embodiment.

In the case where a silicon nitride film is used, stress is easily generated at the interface between the silicon nitride film and the aluminum layer. Therefore, when the silicon nitride oxide film 231 is formed at the interface between the silicon nitride film 230 and the aluminum layer. Good.

In this embodiment, the silicon nitride film 230 having a thickness of 5 to 30 nm and the silicon nitride oxide film 23 having a thickness of 1 to 10 nm
1 was provided.

After obtaining the laminated film, an interlayer insulating film, a source electrode, and a drain electrode are formed in the same manner as in the above embodiments, and finally, a hydrogenation step is performed to complete the TFT.

[Embodiment 10] In this embodiment, Embodiments 1 to 9 will be described.
An example in which an AMLCD is configured using the TFT configuration shown in FIG. FIG. 14 shows the appearance of the AMLCD of this embodiment.

In FIG. 14A, reference numeral 901 denotes an active matrix substrate, and a pixel matrix circuit 902,
A source side drive circuit 903 and a gate side drive circuit 904 are formed. It is preferable that the drive circuit be formed of a CMOS circuit in which an N-type TFT and a P-type TFT are complementarily combined. 905 is a counter substrate.

In the AMLCD shown in FIG. 14A, an active matrix substrate 901 and a counter substrate 905 are bonded together with their end faces aligned. However, only a part of the counter substrate 905 is removed, and an FPC (flexible print circuit) 906 is connected to the exposed active matrix substrate. The FPC 906 transmits an external signal to the inside of the circuit.

Further, IC chips 907 and 908 are mounted using the surface on which the FPC 906 is mounted.
These IC chips are configured by forming various circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 14A, two are attached, but one or more may be attached.

Further, a configuration as shown in FIG. 14B can be adopted. In FIG. 14B, the same portions as those in FIG. 14A are denoted by the same reference numerals. Here, FIG. 14A illustrates an example in which signal processing performed by an IC chip is performed by a logic circuit 909 formed using TFTs over the same substrate. In this case, the logic circuit 909 is also connected to the drive circuit 9.
Like the circuits 03 and 904, a CMOS circuit is basically used.

In the AMLCD of this embodiment, a black mask is provided on the active matrix substrate (BM0).
n TFT), but a black mask may be provided on the opposite side in addition to the TFT.

A color display may be performed using a color filter, or a liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like.
It is good also as composition not using a color filter.

As in the technique described in Japanese Patent Application Laid-Open No. 8-15686, a configuration using a microlens array may be adopted.

[Embodiment 11] The construction of the present invention is similar to that of AML.
The present invention can be applied to various other electro-optical devices and semiconductor circuits other than the CD.

As an electro-optical device other than the AMLCD, E
Examples include an L (electroluminescence) display device and an image sensor.

As the semiconductor circuit, an arithmetic processing circuit such as a microprocessor constituted by an IC chip, and a high-frequency module (MMIC) for handling input / output signals of a portable device are used.
Etc.).

As described above, the present invention can be applied to all semiconductor devices functioning with circuits constituted by insulating gate type TFTs.

[Embodiment 12] AML shown in Embodiment 10
CDs are used as displays for various electronic devices. Note that an electronic device described in this embodiment is defined as a product equipped with an active matrix liquid crystal display device.

Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head-mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, and the like). Is mentioned. One example is shown in FIG.

FIG. 15A shows a portable telephone, and the main body 20 is provided.
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and the like.

FIG. 15B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, operation switches 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102, the sound input unit 2103, and the image receiving unit 2106.

FIG. 15C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention is applied to the image receiving section 220.
3. Applicable to the display device 2205 and the like.

FIG. 15D shows a head mounted display, which comprises a main body 2301, a display device 2302, and a band 2303. The present invention can be applied to the display device 2302.

FIG. 15E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 15F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. In addition, the present invention can be used for an electronic bulletin board, a display for advertising, and the like.

[0188]

According to the present invention, defects such as a short circuit between the gate electrode and the active layer can be prevented even in a TFT using aluminum or a material mainly containing aluminum as the gate electrode. . In particular, diffusion of aluminum atoms from the gate electrode was prevented, and deterioration in TFT characteristics was suppressed.

In addition, since the LDD region and the offset region can be formed without giving unnecessary damage to the gate insulating film, the long-term reliability of the TFT is improved.

After forming a wiring using an aluminum material,
A method for manufacturing a TFT in which heat treatment is performed at a temperature (approximately 600 ° C.) at which gettering can be sufficiently performed and a metal element in a crystalline silicon film is gettered without being limited by a processing time can be obtained. At the same time, activation of the dopant and recovery of damage to the crystal structure can be achieved. This heat treatment improves the uniformity of element characteristics.

Further, since the nickel element is fixed to the source region and the drain region which do not affect the operation of the TFT, high characteristics can be stably obtained. Also,
Even when a large number of TFTs are manufactured at the same time, variations in characteristics can be reduced.

In the heating step after doping (typically 450 to 700 ° C.) in the case of the structure of the present invention, 1) gettering treatment for reducing the metal element concentration in the channel formation region and high resistance region 2) source And an impurity activation process in the drain region 3) An annealing process for recovering crystal structure damage caused during ion implantation is performed simultaneously.

As a result, the following effects can be obtained: (1) a significant simplification of the process; (2) an improvement in breakdown voltage and leakage current characteristics; (2) an improvement in reliability;

As described above, according to the present invention, a highly reliable TFT can be manufactured with a high yield, an electro-optical device functioning with a semiconductor circuit including such a TFT, and a semiconductor circuit and an electro-optical device having such a function. The yield of electronic equipment equipped with the device is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration near a gate electrode of a TFT.

FIG. 2 illustrates a manufacturing process of a TFT.

FIG. 3 illustrates a manufacturing process of a TFT.

FIG. 4 is a diagram showing a manufacturing process of a TFT.

FIG. 5 is a diagram showing a configuration of an active matrix substrate.

FIG. 6 is a diagram showing a manufacturing process of a TFT in Example 3.

FIG. 7 is a view showing a manufacturing process of a TFT in Example 4.

FIG. 8 is a view showing a manufacturing process of a TFT in Example 5.

FIG. 9 is a view showing a manufacturing process of a TFT in Example 5.

FIG. 10 is a view showing a manufacturing process of a TFT in Example 5.

FIG. 11 is a diagram showing a structure of a TFT according to a seventh embodiment.

FIG. 12 is a diagram showing a structure of a TFT according to an eighth embodiment.

FIG. 13 is a diagram showing a structure of a TFT according to a ninth embodiment.

FIG. 14 is a diagram showing a configuration of an AMLCD.

FIG. 15 illustrates a structure of an electronic device.

FIG. 16 is an SEM photograph showing a structure near a gate electrode.

FIG. 17 is an SEM photograph showing a structure near a gate electrode.

FIG. 18 is a diagram showing a concentration distribution of nickel and phosphorus in an active layer of a TFT.

FIG. 19 is a micrograph showing a diffusion state of aluminum in heat treatment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Substrate 102 Base film 104 Gate insulating film 105 Aluminum layer 106 Enlarged region 107 Channel formation region 108 LDD region 109 Drain region (or source region) 110 Valve metal layer (tantalum layer) 111 Nonporous alumina layer 112 Valve metal layer Anodized layer (tantalum oxide layer)

Claims (15)

[Claims] 1. A semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein the TFT is formed by stacking a valve metal layer and aluminum or a material layer containing aluminum as a main component. A gate insulating film in contact with the gate electrode, a channel forming region in contact with the gate insulating film, a high-resistance region in contact with the channel forming region, and a source region or a drain region in contact with the high-resistance region. Wherein the source region or the drain region contains a metal element which promotes crystallization of silicon at a high concentration, and the high resistance region contains the metal element at a low concentration. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the source region or the drain region is doped with a phosphorus element. 3. The semiconductor device according to claim 1, wherein the valve metal layer is made of tantalum or a material layer containing tantalum as a main component, and has a thickness of 1 to 200 nm. 4. The semiconductor device according to claim 1, wherein the metal element that promotes crystallization of silicon is nickel. 5. A method for manufacturing a semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein the active layer is formed using a crystalline silicon film containing a metal element which promotes crystallization of silicon. A second step of forming a gate insulating film; and a third step of forming a gate electrode in which a valve metal layer and a material layer containing aluminum or aluminum as a main component are sequentially laminated. A fourth step of selectively anodizing the aluminum or the material layer containing aluminum as a main component to form a porous alumina layer; and subjecting the aluminum or aluminum to the main component by re-anodization. At the same time as forming the nonporous alumina layer on the surface of the material layer, all or part of the valve metal layer located below the porous alumina layer is transformed into an anodized layer. A fifth step of doping a region to be a source or drain region of the TFT with a phosphorus element, and a seventh step of performing a heat treatment to getter the metal element. A method for manufacturing a semiconductor device, comprising: 6. The method for manufacturing a semiconductor device according to claim 5, wherein the heat treatment in the seventh step is performed at 450 to 700 ° C. 7. A method for manufacturing a semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein the active layer is formed using a crystalline silicon film containing a metal element that promotes silicon crystallization. A second step of forming a gate insulating film; and a third step of forming a gate electrode in which a valve metal layer and a material layer containing aluminum or aluminum as a main component are sequentially laminated. Performing a first anodizing process selectively on only the aluminum or the material layer containing aluminum as a main component to form a porous alumina layer; and performing a second anodizing process, At the same time as forming a non-porous alumina layer on the surface of aluminum or a material layer containing aluminum as a main component, a part of the valve metal layer located under the porous alumina layer is turned into an anodized layer. A fifth step of metamorphosis and a sixth step of removing the porous alumina layer
Performing a third anodic oxidation to form a nonporous alumina layer on the surface of the aluminum or the material layer containing aluminum as a main component, and at the same time, a valve metal positioned below the porous alumina layer. A seventh step of transforming all of the layers into an anodic oxide layer, an eighth step of doping a phosphorus element using the gate electrode, the anodic oxide layer and the gate insulating film as a mask, And a ninth step of gettering. 8. The semiconductor device according to claim 5, further comprising a step of etching a gate insulating film using the non-porous alumina layer and the porous alumina layer as a mask. Method of manufacturing. 9. The method according to claim 5, wherein the fourth step is performed in a solution containing oxalic acid as a main component. 10. The method for manufacturing a semiconductor device according to claim 5, wherein the fifth step is performed in a solution containing tartaric acid as a main component. 11. The heat treatment according to claim 7, wherein the heat treatment in the ninth step is 450 to 700.
A method for manufacturing a semiconductor device, characterized in that the method is performed at ° C. 12. A semiconductor device including a semiconductor circuit having a plurality of N-channel TFTs and a plurality of P-channel TFTs formed on the same substrate, wherein the N-channel TFT and the P-channel TFT are:
A gate electrode formed by stacking a valve metal layer and a material layer containing aluminum or aluminum as a main component; a gate insulating film in contact with the gate electrode; a channel formation region in contact with the gate insulating film; and a channel formation region. An N-channel TFT having a high-resistance region in contact with the source region or a drain region in contact with the high-resistance region;
And the source region or the drain region of the P-channel TFT contains a phosphorus element, and the source region or the drain region of the P-channel TFT contains an impurity imparting P-type conductivity with the phosphorus element. A semiconductor device which is contained at a higher concentration than the concentration. 13. A method for manufacturing a semiconductor device including a semiconductor circuit having a plurality of N-channel TFTs and a plurality of P-channel TFTs formed on the same substrate, wherein a metal element for promoting crystallization of silicon is provided. A first step of forming an active layer using a crystalline silicon film including silicon, a second step of forming a gate insulating film, and a valve metal layer and a material layer containing aluminum or aluminum as a main component are sequentially laminated A third step of forming a formed gate electrode, a fourth step of selectively anodizing the aluminum or the material layer containing aluminum as a main component to form a porous alumina layer, and anodizing again Forming a nonporous alumina layer on the surface of the aluminum or the material layer containing aluminum as a main component, and at the same time, a valve metal located below the porous alumina layer. A fifth step of transforming all or a part of the metal layer into an anodized layer; and a sixth step of doping a region to be a source region or a drain region of the N-channel TFT and the P-channel TFT with a phosphorus element. And a seventh step of performing heat treatment to getter the metal element, and doping an impurity imparting P-type conductivity to a region to be a source region or a drain region of the P-channel TFT. A sixth step performed at a higher concentration than the concentration of the phosphorus element. 14. A semiconductor device including a semiconductor circuit having a plurality of TFTs formed on the same substrate, wherein the TFT comprises: a gate electrode made of aluminum or a material layer containing aluminum as a main component; A blocking layer in contact with the gate insulating film in contact with the blocking layer, a channel forming region in contact with the gate insulating film, a high-resistance region in contact with the channel forming region, and a source or drain region in contact with the high-resistance region. Having a high concentration of a metal element that promotes crystallization of silicon in the source region or the drain region, and a low concentration of the metal element in the high resistance region. Characteristic semiconductor device. 15. The semiconductor device according to claim 14, wherein said blocking layer is a silicon nitride oxide film, a silicon nitride film, a silicon oxide film, or a laminate thereof.