JP4562868B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a transistor, a diode, a resistance element, or the like using a semiconductor having a crystal structure (hereinafter referred to as a crystalline semiconductor), a method for manufacturing the semiconductor device, and addition of impurities to the semiconductor device. The present invention relates to an impurity addition apparatus for forming a region.
[0002]
[Prior art]
When producing an impurity added region such as a source / drain region or an LDD region which is a constituent element of a MOS transistor, a method of activating the impurity by adding an impurity by some method and then performing a heat treatment is adopted. .
[0003]
As a method for adding impurities, an ion implantation method or an ion doping method is used. The ion implantation method is a technology in which elements such as boron (B) and phosphorus (P) are ionized into a semiconductor such as silicon, and only necessary ions are accelerated by an electric field and implanted by an electric field. This is a technique in which ions are accelerated by an electric field without being analyzed. Ion implantation and ion doping destroy the crystal structure when impurities are added.
[0004]
Impurity addition conditions such as the amount and location of impurities in the impurity addition method affect the properties of the semiconductor device. For example, in a MOS transistor, if the amount of impurities is small, the sheet resistance of the impurity added region increases, and the on-current of the MOS transistor decreases.
[0005]
As an impurity addition condition, for example, Japanese Patent Application Laid-Open No. 10-256557 states that it is important to lower the sheet resistance after the heat treatment so that the crystal is partially left in the lowermost layer of the active layer. In Japanese Patent Application Laid-Open No. 10-256557, ideal impurity addition conditions are given, but the validity thereof can only be determined by electrical measurement after wiring formation.
[0006]
[Problems to be solved by the invention]
In order to solve such problems, it is an object to provide a technology capable of predicting the sheet resistance of a region to which an impurity is added at an early stage of manufacturing a semiconductor device and confirming the validity of the impurity addition condition. And
[0007]
[Means for Solving the Problems]
After adding an impurity to the crystalline semiconductor and before activation, a Raman scattered light spectrum of the added region is measured. If crystals remain in the crystalline semiconductor, a peak peculiar to the crystals can be confirmed. It was found that there was a correlation between the peak position and the sheet resistance after activation. Therefore, the sheet resistance of the impurity added region can be predicted from the peak position using the correlation.
[0008]
Further, if the sheet resistance after activation can be predicted before activation by using the correlation after the addition of impurities, impurities can be additionally added when the sheet resistance after activation is inappropriate.
[0009]
Combining the impurity adding device and the Raman scattered light spectrum measuring device, there is a device capable of performing Raman scattered light spectrum measurement after adding the impurity, predicting the sheet resistance from the correlation, and re-adding the impurity if necessary. it can.
[0010]
Examples of the method for adding impurities include an ion implantation method and an ion doping method. The ion implantation method is a technique in which an element such as boron (B) or phosphorus (P) is extracted as an ion into a semiconductor such as silicon, and then only the necessary ions are accelerated and implanted by an electric field. The doping method is a technique in which ions are accelerated by an electric field without mass spectrometry. The ion implantation method and the ion doping method destroy crystallinity when impurities are added.
[0011]
Here, the activation includes heat treatment, rapid thermal annealing, laser activation, and the like. For example, in ion implantation, many of the impurities after implantation cannot be substituted at lattice positions in the crystal and exist as interstitial atoms as defects. Activation replaces these impurities with substitution positions in the crystal lattice, making them act electrically as acceptors or donors. At this time, the crystallinity destroyed by ion implantation can be recovered to some extent.
[0012]
A crystalline semiconductor is a semiconductor having a crystal structure at least in part, for example, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor in which crystal and amorphous are mixed. However, the peak must be confirmed by Raman scattering light spectrum measurement. Impurities are Group 13 or Group 15 elements such as boron (B) and phosphorus (P), which are added to a semiconductor such as silicon to constitute an impurity semiconductor.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
For example, impurities are added to crystalline silicon by an ion doping method. After that, when the Raman scattered light spectrum was measured using a 514.5 nm laser, 500 cm − ¹ To 520.6cm ¹ A peak can be confirmed in the range (FIG. 1). It was found that there was a correlation between the peak position and the sheet resistance after activation. FIG. 2 shows the relationship between the peak position and the sheet resistance after thermal activation at 850 ° C. for 30 minutes. Using this correlation, the sheet resistance after activation can be predicted before activation.
[0014]
According to FIG. 2, when the sheet resistance of the impurity added region is desired to be 1 kΩ / □ or less, the peak of the Raman scattered light spectrum is 515.5 cm −. ¹ Must be: If the peak of the Raman scattered light spectrum is 515.5 cm ¹ If this is the case, impurities are further added. Once again, the Raman scattered light spectrum was measured and the peak was 515.5 cm ¹ If it is below, the sheet resistance after activation will be 1 kΩ / □ or less.
[0015]
Therefore, a means for adding an impurity element to a semiconductor by an ion implantation method or an ion doping method and a means for measuring a Raman scattered light spectrum are combined, and in one case or in a plurality of cases, addition of impurities, It is possible to form an impurity addition apparatus that performs Raman scattering spectrum measurement, predicts sheet resistance from the correlation, judges the appropriateness of the process, and adds impurities if necessary.
[0016]
Here, the impurity is an element of Group 13 or Group 15 such as boron (B) or phosphorus (P), and is added to a semiconductor such as silicon to constitute an impurity semiconductor. Crystalline silicon is silicon having crystallinity at least partially, for example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, or silicon in which crystal and amorphous are mixed. However, in the Raman scattering light spectrum measurement, when using a laser with a wavelength of 514.5 nm, ¹ To 520.6cm ¹ The peak must be able to be confirmed.
[0017]
Ion doping is a technique in which an element such as boron (B) or phosphorus (P) is extracted as an ion into a semiconductor such as silicon and then accelerated by an electric field. Ion doping destroys crystallinity when impurities are added.
[0018]
Here, a case where a Raman scattered light spectrum is measured using a laser having a wavelength of 514.5 nm is shown, but data can be obtained by using another wavelength such as 488.0 nm. Further, as an example, the thermal activation is performed at 850 ° C. for 30 minutes, but this step may be rapid thermal annealing, laser activation, etc. In the case of thermal activation, it can be performed at 400 ° C. to 1400 ° C. However, the data needs to be retaken.
[0019]
【Example】
[Example 1]
An embodiment in which a display device is manufactured from a crystalline semiconductor film by applying the impurity doping method of the present invention to the formation of the source / drain regions of a MOS transistor will be described. Here, a method for simultaneously manufacturing a pixel TFT and a storage capacitor in a pixel region and a TFT of a driver circuit provided around the pixel region will be described with reference to the drawings.
[0020]
In FIG. 3A, a substrate 301 includes polyethylene terephthalate (PET), polyethylene, in addition to a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass. A plastic substrate having no optical anisotropy such as naphthalate (PEN) or polyethersulfone (PES) can be used. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, an insulating film 302 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 301 where a TFT is to be formed in order to prevent impurity diffusion from the substrate 301. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film formed from O is formed to a thickness of 10 to 100 nm to form the insulating film 302.
[0021]
The silicon oxynitride film is formed using a parallel plate type plasma CVD method. The silicon oxynitride film is SiH _Four 16.91 Pa · l / sec, NH _Three 169.1 Pa · l / sec, N ₂ O was introduced into the reaction chamber as 33.82 Pa · l / sec, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency is 60 MHz.
[0022]
Next, a semiconductor film 303 having an amorphous structure with a thickness of 10 to 100 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon film is formed to a thickness of 55 nm by plasma CVD. In addition, the insulating film 302 and the amorphous silicon film 303 can be formed continuously. For example, after forming a silicon oxynitride film as described above, the reaction gas is changed to SiH. _Four , N ₂ O, H ₂ To SiH _Four And H ₂ Or SiH _Four By switching only to this, it can be formed continuously without being exposed to the air atmosphere. As a result, contamination at this interface can be prevented, and variations in characteristics of TFTs to be manufactured and fluctuations in threshold voltage can be reduced.
[0023]
The crystallization step shown in FIG. 3B is performed by a laser crystallization method. Gas lasers typified by pulsed excimer lasers, YAG lasers, YVO _Four A solid laser typified by a laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is condensed into a linear shape, a rectangular shape, or a rectangular shape by an optical system and irradiated onto a semiconductor film. The laser irradiation conditions for the amorphous semiconductor film are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200 to 300 mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is 80 to 98%.
[0024]
The crystalline semiconductor film 305 manufactured by this laser crystallization method has a polycrystalline structure in which a plurality of crystal grains are aggregated.
[0025]
Then, as shown in FIG. 3C, a resist pattern is formed by a light exposure process, the crystalline semiconductor film 305 is divided into islands by dry etching, and island-like semiconductor films 306 to 309 are formed. CF for dry etching _Four And O ₂ The mixed gas is used. The gate insulating film 310 is formed of an insulating film containing silicon with a thickness of 40 to 200 nm by using a plasma CVD method or a sputtering method. SiH by plasma CVD _Four And N ₂ A silicon oxynitride film manufactured from a mixed gas of O is a material suitable as a gate insulating film, and is formed to a thickness of 80 nm to be a gate insulating film. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS and O2 are formed by plasma CVD. ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0026]
Then, a first conductive film 311 and a second conductive film 312 for forming a gate electrode are formed over the gate insulating film 310. The gate electrode of the TFT shown in this embodiment is formed in a two-layer structure, and the first conductive film 311 is formed of a tantalum nitride (referred to as TaN in this specification) film with a thickness of 50 to 100 nm. The conductive film 312 is formed with a tungsten (W) film to a thickness of 100 to 300 nm.
[0027]
The TaN film is an excellent material with high thermal stability, considering that heat treatment is performed in a later process. The W film is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. A W target having a purity of 99.9999% is used, and a W film is formed with sufficient consideration to prevent impurities from entering the gas phase during film formation, so that the resistivity is 9 to 20 μΩ · cm. Can be realized.
[0028]
Next, as shown in FIG. 4A, a resist mask 313 is formed and a first etching process is performed. An etching method is not limited, but an ICP (Inductively Coupled Plasma) etching apparatus is preferably used. CF for etching gas _Four And Cl ₂ Etching is performed by generating plasma by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 0.5 to 2 Pa, preferably 1 Pa. 100 W RF (13.56 MHz) electric power is also applied to the substrate side (sample stage), and a negative self-bias voltage is substantially applied. CF _Four And Cl ₂ When W is mixed, the W film and the Ta film can be etched at the same rate.
[0029]
In the first etching treatment, the end portions of the first conductive layer and the second conductive layer are processed so as to have a tapered shape. The angle of the tapered portion is 15 to 45 °. However, in order to perform etching without leaving a residue on the gate insulating film, it is preferable to perform an overetching process that increases the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 314 to 318 (first conductive layers 314 a to 318 a and second conductive layers 314 b to 318 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form.
[0030]
Next, a second etching process is performed as shown in FIG. Using ICP etching equipment, CF as etching gas _Four And Cl ₂ And O ₂ And 500 W of RF power (13.56 MHz) is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage) so that the self-bias voltage is lower than that in the first etching process. Under such conditions, the W film is anisotropically etched, and the TaN film is anisotropically etched at a slower etching rate to form second shape conductive layers 319 to 323 (first conductive layers 319a to 323a). And second conductive layers 319b to 323b) are formed. Reference numeral 324 denotes a gate insulating film, and a region that is not covered with the second shape conductive layers 319 to 323 is formed as a thinned region by etching about 40 to 80 nm by the first etching process and the second etching process. The
[0031]
The impurity regions of the n-channel TFT and the p-channel TFT are formed in a self-aligned manner using the second shape conductive layer. Two types of impurity regions having different concentrations are formed in the n-channel TFT. FIG. 4C illustrates a first impurity region 325 which overlaps with the first conductive layers 319 a to 323 a by adding an impurity element imparting n-type conductivity in the first doping process (conditions of high acceleration voltage and low dose). The process of forming -328 is shown. In this case, second impurity regions 329 to 332 are formed outside the first impurity regions 325 to 328. The doping process is performed by an ion doping method, an ion implantation method, or the like. The impurity element imparting n-type is an element belonging to Group 15 of the periodic table, and typically phosphorus (P) or arsenic (As) is used. The concentration of the impurity element to be added is 2 × 10 in the first impurity region. ¹⁶ ~ 1x10 ¹⁸ / Cm ^Three To be. In the second impurity region, 1 × 10 ¹⁷ ~ 5x10 ¹⁸ / Cm ^Three To be.
[0032]
Next, a resist mask 333 is formed as shown in FIG. This mask is formed to determine the source and drain regions of the pixel TFT and the n-channel TFT of the sampling circuit in the driving circuit. The second doping process is performed in order to form the third impurity region 334 in the n-channel TFT of the driver circuit. The concentration of the impurity element imparting n-type added to the third impurity region 334 is 5 × 10 5. ¹⁷ ~ 5x10 ¹⁹ / Cm ^Three To be. Further, a third doping process is performed, and an impurity element imparting n-type conductivity is 1 × 10 5. ²⁰ ~ 1x10 ^{twenty one} / Cm ^Three Fourth impurity regions 335 to 337 to be added at a concentration are formed.
[0033]
The Raman scattered light spectrum of the fourth impurity regions 335 to 337 is measured. When the Raman scattered light spectrum is measured using a laser with a wavelength of 514.5 nm, ¹ To 520.6cm ¹ It is confirmed that a peak is formed in the range (FIG. 1). In this embodiment, since the impurity is activated by heat treatment at 500 ° C. for 1 hour, data on the relationship between the peak position and the sheet resistance when heat treatment is performed at 500 ° C. for 1 hour is obtained in advance. Impurities are added several times as necessary so that the peak position where the sheet resistance is set to the target value is obtained.
[0034]
In the present embodiment, a case where a Raman scattered light spectrum is measured using a laser having a wavelength of 514.5 nm is shown, but data can be obtained by using another wavelength such as 488.0 nm. The same applies to the second impurity-added regions 329 to 332. The first impurity regions 325 to 328 and the third impurity added region 334 can be similarly achieved by measuring the Raman scattered light spectrum from the back surface of the substrate.
[0035]
As shown in FIG. 5B, the impurity region for the p-channel TFT is formed by forming a resist mask 338 so as to protect the region where the n-channel TFT is formed, and performing a fourth doping process. Fifth impurity regions 339 and 340 to which an impurity element imparting p-type conductivity is added are formed. The impurity element imparting p-type is an element belonging to Group 13 of the periodic table, and typically boron (B) is used.
[0036]
Also for the fifth impurity regions 339 and 340, data on the relationship between the peak position and the sheet resistance when heat-treated at 500 ° C. for 1 hour is acquired in advance, and Raman scattering is performed in the same manner as the fourth impurity-added region. Measure the light spectrum and add impurities as many times as necessary to achieve the target sheet resistance.
[0037]
As shown in FIG. 5C, a first interlayer insulating film 341 is formed over the gate electrode and the gate insulating film. The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the first interlayer insulating film 341 is formed of an inorganic insulating material, and 5 to 30 atomic%, preferably 15 to 25 atomic% of hydrogen is contained in the film. The thickness of the first interlayer insulating film 341 is 100 to 200 nm. When a silicon oxide film is used, TEOS and O2 are formed by plasma CVD. ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² It is formed by discharging with. When using a silicon oxynitride film, SiH is formed by plasma CVD. _Four , N ₂ O, NH _Three Silicon oxynitride film manufactured from SiH or SiH _Four , N ₂ A silicon oxynitride film formed from O may be used. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm. ² Can be formed. SiH _Four , N ₂ O, H ₂ Alternatively, a silicon oxynitride silicon film manufactured from the above may be used. Similarly, the silicon nitride film is made of SiH by plasma CVD. _Four , NH _Three It is possible to make from.
[0038]
Thereafter, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed. This step may be performed by heat treatment using a furnace annealing furnace or by laser annealing. When the heat treatment is performed, the oxygen concentration is 400 ppm to 700 ° C., typically 400 ° C. to 550 ° C. in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. Heat treatment for 1 hour is performed. By this heat treatment, hydrogen contained in the first interlayer insulating film 341 is diffused into the semiconductor film, and hydrogenation can be performed at the same time. In the case where a plastic substrate having a low heat resistant temperature is used as the substrate 301, it is preferable to apply a laser annealing method.
[0039]
Alternatively, after the heat treatment, the semiconductor film may be hydrogenated by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. In any case, the purpose of hydrogenation is in the semiconductor film. ¹⁶ -10 ¹⁸ / Cm ^Three The dangling bond is compensated with hydrogen to reduce its density. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0040]
The second interlayer insulating film 342 is formed using an organic insulating material with an average film thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 300 ° C. using a clean oven. When acrylic is used, a two-component one is used. After mixing the main material and the curing agent, the whole surface of the substrate is applied using a spinner, and then preheating is performed on a hot plate at 80 ° C. for 60 seconds. Further, it can be formed by baking at 250 ° C. for 60 minutes using a clean oven.
[0041]
Thus, the surface can be satisfactorily flattened by forming the interlayer insulating film with an organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, it needs to be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the protective insulating film 341 as in this embodiment.
[0042]
Thereafter, a resist mask having a predetermined pattern is formed by an optical exposure process, and contact holes reaching the source region or the drain region formed in each semiconductor film are formed. Contact holes are formed by dry etching. In this case, CF is used as an etching gas. _Four , O ₂ , The second interlayer insulating film 342 made of an organic resin material is etched using a mixed gas of He, and then the etching gas is changed to CF. _Four , O ₂ The first interlayer insulating film 341 is etched as follows. Further, in order to increase the selectivity with the island-shaped semiconductor film, the etching gas is changed to CHF. _Three The contact hole can be satisfactorily formed by switching to 1 and etching the gate insulating film.
[0043]
Then, a conductive metal film is formed by sputtering or vacuum vapor deposition, a resist mask having a predetermined pattern is formed by a light exposure process, and source wirings and drain wirings 343 to 349 are formed by etching. 350 formed simultaneously functions as a pixel electrode. Although not shown, in this embodiment, this electrode is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with the semiconductor film forming the source or drain region of the island-like semiconductor film, and the Ti film Overlaid on top, aluminum (Al) is formed to a thickness of 300 to 400 nm to form a wiring.
[0044]
When a heat treatment (sintering) is performed at 300 to 450 ° C. for 1 to 12 hours in this state, good ohmic contact can be obtained. If this heat treatment is performed in a hydrogen atmosphere, it can also serve as a hydrogenation treatment (FIG. 5C).
[0045]
In this manner, a substrate in which the TFT of the driving circuit and the pixel TFT of the pixel region are integrally formed by using six photomasks can be completed. In the driver circuit 356, a first p-channel TFT 351, a first n-channel TFT 352, a second n-channel TFT 353, and a pixel TFT 354 and a storage capacitor 355 are formed in the pixel region 357. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0046]
The first p-channel TFT 351 of the driver circuit 356 is formed with a single drain structure having a channel formation region 358 and source or drain regions 359 and 360 each including a fifth impurity region. However, the source or drain region 359 is formed so as to overlap with the first conductive layer 319a.
[0047]
The first n-channel TFT 352 includes a channel formation region 361, a third impurity region 362 that overlaps with the second conductive layer 320a that is a gate electrode, and a fourth impurity region 363 that is formed outside the gate electrode. Yes. The third impurity region 362 is an LDD (Lightly Doped Drain) region, and the fourth impurity region 363 is a region functioning as a source region or a drain region. In particular, the third impurity region 362 is an LDD region overlapping with the gate electrode (such an LDD region is expressed as Lov), and is also called a GOLD (Gate Overlapped Drain) structure. As a result, TFT deterioration due to the hot carrier effect can be prevented, and extremely stable operation can be obtained even when a high voltage of 10 V or higher is applied.
[0048]
The second n-channel TFT 353 includes a channel formation region 364, a first impurity region 365 overlapping the second conductive layer 321a which is a gate electrode, a second impurity region 366 formed outside the gate electrode, 4 impurity regions 367. The first impurity region 365 is Lov and prevents TFT deterioration due to the hot carrier effect. The second impurity region 366 is an LDD region that does not overlap with the gate electrode (such an LDD region is expressed as Loff), and has an effect of reducing off-state current.
[0049]
The pixel TFT 354 includes a channel formation region 368, a first impurity region 369, a second impurity region 370, and a fourth impurity region 371. Although FIG. 5C illustrates the pixel TFT 354 with a double gate structure, a single gate structure may be used, or a multi-gate structure with a plurality of gate electrodes may be used. Further, a storage capacitor 355 is formed from the capacitor wiring 323, an insulating film made of the same material as the gate insulating film, and semiconductor films 374 and 375 (an impurity element imparting n-type conductivity is added to 375). Yes.
[0050]
An impurity element imparting n-type conductivity is added to the first impurity region to the fourth impurity region. The first impurity region has 2 × 10 ¹⁶ ~ 1x10 ¹⁸ / Cm ^Three In the second impurity region, 1 × 10 ¹⁷ ~ 5x10 ¹⁸ / Cm ^Three In the third impurity region, 5 × 10 ¹⁷ ~ 5x10 ¹⁹ / Cm ^Three In the fourth impurity region, 1 × 10 ²⁰ ~ 1x10 ^{twenty one} / Cm ^Three Impurity elements are added at a concentration of. An impurity element imparting p-type conductivity is added to the fifth impurity region, and the impurity element is added at a concentration 1.5 to 3 times that of the fourth impurity region.
[0051]
The first impurity region and the third impurity region are Lov, and the length in the channel length direction is 0.5 to 3 μm, preferably 0.5 to 1.5 μm. The reason why the concentration of the impurity element added in the two impurity regions is different is that the former is formed at the lowest possible concentration in consideration of the reduction of off-current, while the latter is to increase the current driving capability. This is derived from the importance of on-current. The second impurity region is Loff and is formed with a length in the channel length direction of 0.5 to 3 μm, preferably 1.0 to 1.5 μm.
[0052]
The first p-channel TFT 351 and the first n-channel TFT 352 form a shift register circuit, a buffer circuit, or the like. The second n-channel TFT 353 is applied to a sampling circuit. As described above, the structure of the TFT can be optimized in accordance with the specifications required for each circuit formed on the active matrix substrate, and the operation performance and reliability can be improved.
[0053]
FIG. 6 is a top view showing almost one pixel of the pixel portion. A cross section AA ′ shown in the drawing corresponds to the cross sectional view of the pixel portion shown in FIG. The gate electrode 322 of the pixel TFT 354 intersects with the island-like semiconductor film 309 under the gate insulating film (not shown). Although not shown, a source region, a drain region, and an LDD region are formed in the island-shaped semiconductor film 309. Reference numeral 372 denotes a contact portion between the source wiring 349 and the source region, and 373 denotes a contact portion between the pixel electrode 350 and the drain region. The storage capacitor 355 is formed in a region where the capacitor wiring 323 overlaps with the semiconductor film extending from the drain region of the pixel TFT 354 and the gate insulating film. The structure shown here is an active matrix substrate in which the pixel electrode 350 is formed of the same material as the source wiring and the drain wiring, that is, applicable to a reflective display device.
[0054]
[Example 2]
The active matrix substrate manufactured in Embodiment 1 can be applied to a reflective display device. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided in each pixel of the pixel portion may be formed using a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device is described with reference to FIGS.
[0055]
The active matrix substrate is manufactured in the same manner as in Example 1. However, before the source wiring and the drain wiring are formed, a transparent conductive film is formed over the second interlayer insulating film 342, and the pixel electrode 376 is formed. Thereafter, a source wiring 377 and a drain wiring 378 are formed. The drain wiring 378 overlaps with the pixel electrode 376 to form a contact portion. As an example of the source wiring and the drain wiring, a Ti film is formed with a thickness of 50 to 150 nm, a contact is formed with a semiconductor film that forms a source or drain region of the island-shaped semiconductor film, and an Al layer is stacked on the Ti film. Are formed with a thickness of 300 to 400 nm. With this configuration, the pixel electrode 376 is in contact with only the Ti film that forms the drain wiring 378. As a result, the reaction between the transparent conductive film material and Al can be prevented.
[0056]
The material of the transparent conductive film is indium oxide (In ₂ O _Three ) Or indium tin oxide alloy (In ₂ O _Three -SnO ₂ ; ITO) or the like can be formed using a sputtering method, a vacuum deposition method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, etching of ITO is likely to generate a residue, so in order to improve etching processability, an indium oxide-zinc oxide alloy (In ₂ O _Three —ZnO) may also be used. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and thermal stability with respect to ITO, it can prevent a corrosion reaction with Al coming into contact with the end face of the drain wiring 378. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0057]
In this manner, an active matrix substrate corresponding to a transmissive liquid crystal display device can be completed. Although this embodiment has been described as a process similar to that of Embodiment 1, such a configuration can be applied to the active matrix substrate shown in Embodiment 2 or Embodiment 3.
[0058]
[Example 3]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 or Embodiment 2 will be described. As shown in FIG. 8, spacers made of columnar spacers are formed on the active matrix substrate in the state of FIG. The spacer may be provided by dispersing particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning it is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co. is used, and after applying with a spinner, a predetermined pattern is formed by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing. Preferably, the columnar spacers 401 and 402 have a columnar shape and a flat top portion. The mechanical strength of the liquid crystal display device can be ensured when the side substrates are combined. There is no particular limitation on the shape, such as a cone or a pyramid. However, depending on the liquid crystal material used, the height is 3 to 8 μm for nematic liquid crystal and 1 to 4 μm for smectic liquid crystal.
[0059]
The arrangement of the columnar spacers may be determined arbitrarily. Preferably, as shown in FIG. 8, in the pixel region, the columnar spacers 401 may be formed so as to overlap the contact portions 373 of the pixel electrodes 350 and cover the portions. . Since the flatness of the contact portion 373 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 401 is formed in this manner by filling the contact portion 373 with the resin for the spacer, thereby allowing disclination and the like. Can be prevented.
[0060]
Thereafter, an alignment film 403 is formed. A polyimide resin is used for the alignment film. After the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned with a certain pretilt angle. The region that is not rubbed in the rubbing direction from the end of the columnar spacer 401 provided in the pixel region is set to 2 μm or less. Also, the occurrence of static electricity is often a problem in the rubbing process. However, if the columnar spacer 402 is formed also on the TFT of the drive circuit, the original role as a spacer and the effect of protecting the TFT from static electricity can be obtained. Can do.
[0061]
A counter electrode 405 and an alignment film 406 formed of a transparent conductive film are formed on the counter substrate 404 on the counter side. Then, the active matrix substrate on which the pixel region and the drive circuit are formed and the counter substrate are bonded together with a sealant (not shown). Thereafter, liquid crystal 407 is injected between both substrates and completely sealed with a sealing material (not shown). A known liquid crystal material may be used as the liquid crystal material. In this manner, the active matrix type liquid crystal display device shown in FIG. 8 is completed.
[0062]
FIG. 9 is a top view of an active matrix substrate on which a spacer and a sealing agent are formed, and is a top view showing a positional relationship between the pixel portion and the drive circuit portion and the spacer and the sealing agent. Around the pixel region 588, a scanning signal driving circuit 585 and an image signal driving circuit 586 are provided as driving circuits. Further, a signal processing circuit 587 such as a CPU or a memory may be added. These drive circuits are connected to an external input / output terminal 582 by a connection wiring 583. In the pixel portion 588, a gate wiring group 589 extending from the scanning signal driving circuit 585 and a source wiring group 590 extending from the image signal driving circuit 586 intersect with each other in a matrix to form a pixel. A pixel TFT 354 and a storage capacitor 355 shown in (C) are provided.
[0063]
The columnar spacers 401 provided in the pixel region may be provided for all pixels, but may be provided every several to several tens of pixels arranged in a matrix. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is preferably 20 to 100%. Further, the spacer 402 provided in the driver circuit portion may be provided so as to cover the entire surface, or may be provided by being divided into a plurality according to the positions of the source and drain wirings of each TFT as shown in FIG. good. The sealant 579 is formed outside the pixel portion 588 and the scanning signal control circuit 585, the image signal control circuit 586, and other signal processing circuits 587 on the substrate 301 and inside the external input / output terminal 582.
[0064]
The structure of such an active matrix liquid crystal display device will be described with reference to the perspective view of FIG. In FIG. 10, the active matrix substrate includes a pixel portion 588, a scanning signal driving circuit 585, an image signal driving circuit 586, and other signal processing circuits 587 formed on the substrate 301. A pixel TFT 354 and a storage capacitor 355 are provided in the pixel portion 588, and a driver circuit provided in the periphery of the pixel portion is configured based on a CMOS circuit. The scanning signal driving circuit 585 and the image signal driving circuit 586 are connected to the pixel TFT 354 by a gate wiring 322 and a source wiring 349, respectively. Further, a flexible printed circuit (FPC) 591 is connected to an external input terminal 582 and used for inputting an image signal or the like. Connection wiring 583 is connected to each drive circuit. Further, although not shown, the counter substrate 404 is provided with a light shielding film and a transparent electrode.
[0065]
The liquid crystal display device having such a structure can be formed using the active matrix substrate shown in Embodiments 1 and 2. When the active matrix substrate shown in Embodiment 1 is used, a reflective liquid crystal display device can be obtained. When the active matrix substrate shown in Embodiment 2 is used, a transmissive liquid crystal display device can be obtained.
[0066]
[Example 4]
The semiconductor device of the present invention can be applied to display devices for various electronic devices, various integrated circuits, or circuit applications in place of conventional integrated circuits. Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, a projector, and the like. Examples of these are shown in FIGS.
[0067]
FIG. 11A illustrates a mobile phone, which includes a display panel 2701, an operation panel 2702, and a connection portion 2703. The display panel 2701 includes a display device 2704 typified by a liquid crystal display device or an EL display device, and an audio output. A portion 2705, an antenna 2709, and the like are provided. The operation panel 2702 is provided with operation keys 2706, a power switch 2702, a voice input unit 27058, and the like. The present invention can be used in a manufacturing process of a display device 2904 and a semiconductor integrated circuit associated therewith.
[0068]
FIG. 11B illustrates a video camera which includes a main body 9101, a display device 9102 typified by a liquid crystal display device or an EL display device, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be used in a manufacturing process of the display device 9102 and a semiconductor integrated circuit associated therewith.
[0069]
FIG. 11C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205 typified by a liquid crystal display device or an EL display device. . The present invention can be used in a manufacturing process of the display device 9205 and a semiconductor integrated circuit associated therewith.
[0070]
FIG. 11D illustrates a television receiver which includes a main body 9401, a speaker 9402, a display device 9403 typified by a liquid crystal display device or an EL display device, a receiving device 9404, an amplifying device 9405, and the like. The present invention can be used for a manufacturing process of the display device 9403 and a semiconductor integrated circuit associated therewith.
[0071]
FIG. 11E illustrates a portable book which includes a main body 9501, display devices 9502 and 9503 typified by a liquid crystal display device or an EL display device, a storage medium 9504, an operation switch 9505, and an antenna 9506. MD) or data stored in a DVD or data received by an antenna is displayed.
The present invention can be used in manufacturing steps of the display devices 9502 and 9503 and the semiconductor integrated circuit accompanying the display devices.
[0072]
FIG. 12A illustrates a personal computer, which includes a main body 9601, an image input portion 9602, a display device 9603 typified by a liquid crystal display device or an EL display device, and a keyboard 9604. The present invention can be used for a manufacturing process of a display device 9601 and a semiconductor integrated circuit associated therewith.
[0073]
FIG. 12B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 9701, a display device 9702 typified by a liquid crystal display device or an EL display device, a speaker unit 9703, and a recording medium 9704 and an operation switch 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be used for manufacturing a display device 9702 and a semiconductor integrated circuit accompanying the display device 9702.
[0074]
FIG. 12C illustrates a digital camera which includes a main body 9801, a display device 9802 typified by a liquid crystal display device or an EL display device, an eyepiece unit 9803, an operation switch 9804, and an image receiving unit (not shown). The present invention can be used for a manufacturing process of a display device 9802 and a semiconductor integrated circuit associated therewith.
[0075]
FIG. 21A illustrates a front type projector that includes a projection device 3601 and a screen 3602. The present invention can be used in a manufacturing process of a display device 3601 and a semiconductor integrated circuit associated therewith.
[0076]
FIG. 21B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, and a screen 3704. The present invention can be used in a manufacturing process of the display device 3702 and a semiconductor integrated circuit associated therewith.
[0077]
FIG. 21C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 21A and 21B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0078]
FIG. 21D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 21D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0079]
Although not shown here, the present invention can also be applied to a display device incorporated in a navigation system, a refrigerator, a washing machine, a microwave oven, a fixed telephone, a facsimile, and the like. Thus, the application range of the present invention is very wide and can be applied to various products.
[0080]
【The invention's effect】
By determining the peak position of the Raman scattered light spectrum of the impurity-added region formed by the ion implantation method or the ion doping method, the sheet resistance after activation can be predicted before the impurity-added region is activated. Based on the result, if necessary, additional doping can be performed to reduce the sheet resistance after activation in the impurity added region to 1 kΩ / □ or less. By applying such a method of the present invention, variation in characteristics of a semiconductor element manufactured using crystalline silicon can be reduced.
[Brief description of the drawings]
FIG. 1 is a result of measuring Raman scattering light spectrum by adding phosphorus (P) to crystalline silicon from an insulating film by ion doping. The peaks indicated by arrows and dotted lines are due to crystalline silicon.
FIG. 2 shows the relationship between the position of the peak shown in FIG. 1 and the sheet resistance obtained by conducting an electrical measurement after heat-treating the sample at 850 ° C. for 30 minutes.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 6 is a top view showing a pixel in a pixel region.
FIG. 7 is a cross-sectional view illustrating a structure of a pixel of a transmissive liquid crystal display device.
FIG. 8 is a cross-sectional view illustrating a structure of a liquid crystal display device.
FIG. 9 is a top view illustrating the arrangement of input terminals, wiring, circuit arrangement, spacers, and sealant of a liquid crystal display device.
10 is a perspective view illustrating a structure of a liquid crystal display device. FIG.
FIG 11 illustrates an example of a semiconductor device.
FIG 12 illustrates an example of a semiconductor device.
FIG. 13 is a diagram showing an example of a projector.

Claims (3)

A method for manufacturing a semiconductor device in which an impurity is added to a crystalline semiconductor by ion implantation or ion doping, and activation is performed under a predetermined condition, whereby a sheet resistance of the crystalline semiconductor is set to a target value or less.
Obtaining data of the relationship between the peak position of the Raman scattered light spectrum before the activation and the sheet resistance of the semiconductor after the activation,
Adding the impurity to the crystalline semiconductor;
Measure the peak position of the Raman scattered light spectrum of the crystalline semiconductor,
Using the data and the result of the measurement, it is determined whether or not the amount of the impurity that provides a sheet resistance below the target value has been added
When the amount of the impurity that gives a sheet resistance equal to or less than the target value is added, the activation is performed under the predetermined condition,
A method for manufacturing a semiconductor device, comprising adding an impurity again when an amount of the impurity that provides a sheet resistance equal to or less than the target value is not added. Oite to claim 1,
The method for manufacturing a semiconductor device, wherein the target value is 1 kΩ / □. In claim 1 or claim 2 ,
The method of manufacturing a semiconductor device, wherein the activation is any one of thermal activation, rapid thermal annealing, and laser activation.

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