JP4641717B2 - Semiconductor device evaluation method and element substrate - Google Patents

Description

  The present invention relates to a thin film transistor evaluation method or a manufacturing method, or a manufacturing method of a semiconductor device including the thin film transistor. Furthermore, the present invention relates to a program or a recording medium that controls the amount of impurity addition based on an evaluation method.

  As a physical phenomenon related to the lifetime in a semiconductor element typified by a thin film transistor (hereinafter referred to as TFT), there is a characteristic deterioration phenomenon due to hot carriers. Hot carriers are caused by non-equilibrium holes and electrons exceeding the temperature of the lattice system, and the electrons are particularly called hot electrons. As the device dimensions decrease, the local electric field increases. The resulting hot carriers cause a malfunction of the semiconductor device, a decrease in operation function, and a decrease in drain current with respect to the drain voltage, thereby degrading device characteristics and performance of the semiconductor device.

Here, the phenomenon of deterioration due to hot electrons will be described. When the semiconductor element is operated, a high electric field region is formed in the vicinity of the drain region, particularly a junction region between the channel formation region and the drain region, and electrons flowing into the high electric field region become hot electrons having very high energy. . At this time, some of the hot electrons are injected into the gate oxide film, or an interface state is generated at the Si—SiO ₂ interface, resulting in variations in device characteristics. There are also substrate hot electrons in addition to hot electrons due to channel electrons.

Furthermore, carriers generated by impact ionization or avalanche multiplication are injected into the oxide film as hot carriers (drain avalanche hot carrier: DAHC), and hot electron injection generated by secondary impact ionization ( Secondarily Generated Hot Electron (SGHE). For details, see Submicron Device 2p1.
21-142 (by Mitsumasa Koyanagi, published by Maruzen Co., Ltd.).

  As a means for preventing the deterioration due to hot carriers, a lightly doped drain (LDD) in which a region (first low concentration impurity region) to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region. ) Structural TFT is known. In addition, as a means of preventing performance degradation due to parasitic resistance in the LDD region, a gate overlap region (second low-concentration impurity region) in which the LDD region is disposed so as to overlap the gate electrode through a gate insulating film is provided. Overlapped LDD (GOLD) structure TFT is known. With such a structure, it is known that a high electric field in the vicinity of the drain is relaxed, hot carrier injection is prevented, and the deterioration phenomenon is effective.

  The reliability of this GOLD structure TFT depends greatly on the impurity concentration in the gate overlap region. When the impurity concentration of the gate overlap region is high, a strong electric field is generated at the interface between the channel formation region and the gate overlap region, the amount of hot carriers generated increases, and the TFT characteristics deteriorate, for example, the ON current decreases.

  On the other hand, when the impurity concentration in the gate overlap region is reduced to some extent, the electric field strength at the interface between the channel formation region and the gate overlap region decreases, and the electric field strength at the interface between the drain region and the gate overlap region increases. However, it is preferable because the maximum value of the electric field is reduced and the deterioration of TFT characteristics is also reduced.

  However, if the impurity concentration of the gate overlap region is further reduced, a strong electric field is generated at the interface between the drain region and the gate overlap region. Therefore, even if the impurity concentration of the gate overlap region is low, Characteristic degradation increases. Therefore, in order to improve the reliability of the semiconductor element, it is important to grasp the impurity concentration in the gate overlap region more accurately.

Therefore, in the field of LSI, a method of predicting impurity introduction and impurity concentration distribution in the thermal diffusion region in consideration of dose dependency by simulation has been used. This is a process including a calculation based on the total amount of impurities introduced in the impurity concentration distribution of the impurity diffusion region in the case where an impurity diffusion region is obtained by introducing the impurity into the semiconductor substrate and performing the heat treatment to diffuse the impurity. This is a simulation method (see Patent Document 1).
Japanese Patent Laid-Open No. 8-139044

  In particular, in the field of thin film transistors, in order to grasp the impurity concentration of the gate overlap region (Lov region) that overlaps only with the lower conductive film of the gate electrode, only the lower conductive film is formed on the semiconductor film and then impurities are added. A method of measuring the resistance of a measurement element formed in this manner has been used. In this case, only the resistance measurement element in the gate overlap region is manufactured on a separate substrate, or the resistance measurement element is manufactured on a part of the substrate by increasing the number of masks.

  However, these methods not only increase the number of steps, but the gate electrode in the gate overlap region produced by the self-aligned process is produced by taper etching and anisotropic etching, so the resistance in the Lov region is accurately measured. It was difficult. This is because the TFT and the measuring element could not be manufactured on the same substrate and in the same process.

  Therefore, the present invention has an object to provide a method for producing an element for measuring Lov resistance, an evaluation method using the element for measuring Lov resistance, an element substrate having the element for measuring Lov resistance, and a panel. To do.

  In view of the above-described problems, the present invention provides a TEG (Evaluation Element Group; Test Element Group) having an evaluation element (an evaluation element for measuring the impurity concentration of the gate overlap region is particularly referred to as a Lov resistance monitor). It is characterized by forming. In particular, the mask resistance used for manufacturing the gate electrode of the Lov resistance monitor (mask alignment) is intentionally shifted, and the sheet resistance distribution along the source / drain region (high concentration impurity region), the gate overlap region, and the channel formation region is prepared. Thus, it is possible to accurately grasp the impurity concentration of each region.

  Further, the present invention is characterized in that the mask misalignment is evaluated by measuring the electrical characteristics of the Lov resistance monitor without performing observation with an SEM or the like. Note that misalignment of the mask and the like can be evaluated even in a single gate structure other than the GOLD structure.

  Specifically, as shown in FIG. 1, evaluation elements (A) to (D) manufactured as Lov resistance monitors in which the mask alignment is shifted at sub-μm intervals are manufactured, and resistances are measured. At this time, the gate electrode of the evaluation element has a laminated structure of the lower conductive film (first conductive film) 101 and the upper conductive film (second conductive film) 102, and the end of the lower conductive film is the end of the upper conductive film. It has a structure extending beyond the end.

  The evaluation element (A) constitutes a Lov resistance monitor for measuring the sheet resistance of the source / drain region, and the lower conductive film 101 and the upper conductive film are seen from an enlarged view of a top view or a cross-sectional view of AA ′. The end of 102 is provided so as not to exceed the side end of the semiconductor film 103 (one of the ends parallel to the direction in which carriers flow in FIG. 1).

  The evaluation element (B) constitutes a Lov resistance monitor for measuring the sheet resistance of the gate overlap region. When viewed from the enlarged view of the upper surface or the cross-sectional view of BB ′, the end of the lower conductive film 101 is It is provided so as to coincide with the side end portion of the semiconductor film 103.

  The evaluation element (C) also constitutes a Lov resistance monitor for measuring the sheet resistance in the gate overlap region. When viewed from an enlarged view of the upper surface or a cross-sectional view of CC ′, the end and upper portions of the lower conductive film 101 are formed. A side end portion of the semiconductor film 103 is provided between the ends of the conductive film 102.

The evaluation element (D) constitutes a Lov resistance monitor for measuring the sheet resistance of the channel formation region, and the end of the upper conductive film 102 is a semiconductor film when viewed from an enlarged view of the upper surface or a cross-sectional view of DD ′. The end portions of the upper conductive film 102 and the lower conductive film 101 are provided so as to extend beyond the side end portions of the semiconductor film 103.

  Next, the measurement of sheet resistance will be described. For example, when the sheet resistance in the source / drain region is measured using the evaluation element (A), the sheet resistance is proportional to the length L and inversely proportional to the width W. Therefore, 1 / (− X−α) Is known to be proportional to Here, X represents a condition (alignment condition) in which the mask alignment is deliberately shifted, and α represents a mask alignment shift (alignment shift) in which each evaluation element is formed by shifting the mask.

  By utilizing this characteristic, the misalignment α can be obtained, and the sheet resistance such as the gate overlap region can be calculated using the calculated α. Further, according to the present invention, it is possible to evaluate mask misalignment by measuring electrical characteristics without performing observation with an optical microscope or SEM.

  FIG. 8A shows a substrate on which a panel portion (a region used as a panel on the substrate, including a pixel portion and a driver circuit portion) 801 provided with TFT elements and a Lov resistance monitor 802 is formed. 800 is shown. Thus, the present invention is characterized in that a TEG and a TFT such as a Lov resistance monitor can be formed on the same substrate. In other words, taper etching and anisotropic etching can be simultaneously performed on the TFT gate electrode and the TEG gate electrode such as the Lov resistance monitor, so that the low concentration impurity region formed in the gate overlap region can be evaluated. Accurately grasp.

  FIG. 8B shows an enlarged view of the Lov resistance monitor. The Lov resistance monitor 802 is provided with a TEG having a semiconductor film 804 and a gate electrode 805 and a Lov resistance monitor in which pads connected to the gate electrode, the source electrode, and the drain electrode are formed. Then, the alignment conditions of the evaluation element of the Lov resistance monitor may be determined. In FIG. 8B, the alignment conditions are X = a, b, c, d.

  By measuring the sheet resistance of the Lov resistance monitor formed in this way, it is possible to obtain a resistance distribution in the gate overlap region corresponding to the tapered shape of the gate electrode that cannot be obtained by the conventional method. That is, according to the present invention, it is possible to more accurately grasp the impurity concentration of the gate overlap region, the source / drain region, and the channel formation region.

  Further, the present invention makes it possible to create a database of the obtained resistance distribution and select an optimum impurity addition amount under various design conditions such as a circuit. The present invention can provide a program selected from a database or a computer-readable recording medium, and can obtain a desired impurity addition amount (dose amount) in a short time without depending on the experience of the practitioner. Then, it is possible to provide a manufacturing method (design management system) of a semiconductor device that outputs the obtained dose amount to a doping apparatus and efficiently designs a device having desired characteristics.

  Further, according to the present invention, by obtaining the alignment deviation α by measuring the electrical properties of the TEG such as a Lov resistance monitor, it is possible to accurately evaluate the Max alignment deviation without observing with an SEM or the like. In this case, the TEG such as the Lov resistance monitor has a lightly doped drain (LDD) region provided with a region doped with an impurity element at a lower concentration than the source / drain region (low concentration impurity region). Even a so-called GOLD structure in which the LDD region overlaps the gate electrode may be a so-called single drain structure that does not have a low-concentration impurity region.

  The present invention can provide an element substrate having a TEG such as a Lov resistance monitor, a panel, and a method for manufacturing them. A panel is a panel of a display device mounted on a display portion of a semiconductor device such as a display device having a liquid crystal element (liquid crystal display device) or a display device having a light emitting element (light emitting device), and the panel is a pixel. Part and a drive circuit part. Of course, the TEG such as the Lov resistance monitor may be cut and removed when the panel is completed.

  According to the present invention, a TEG having an evaluation element on a part of a TFT substrate can be manufactured. Since the TFT element and the evaluation element are simultaneously etched by taper etching or the like, the evaluation element manufactured on a separate substrate is used. Rather, the resistance of the Lov region, that is, the impurity concentration of the Lov region can be grasped more accurately.

  In addition, by creating a database of the impurity concentration and formation conditions of the semiconductor element obtained by the present invention and the correlation between them and reliability, it is possible to obtain the optimum impurity addition amount in a short time without depending on the experience of the practitioner. . Furthermore, it is possible to evaluate deterioration using the resistance measurement result as a criterion.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the impurity to be doped in the gate overlap region at the time of evaluation of the Lov resistance monitor described in the following embodiment may be a donor or an acceptor.

(Embodiment 1)
In this embodiment, a method for manufacturing evaluation elements (A) to (D) of the Lov resistance monitor and a method for obtaining sheet resistance in the source / drain region, the gate overlap region, and the channel formation region will be specifically described.

  FIG. 2 shows a manufacturing process of the GOLD structure TFT (hereinafter referred to as TFT) provided in the panel portion and the evaluation elements (A) to (D) shown in FIG. 1, and aa ′ and bb ′. , Cc ′, and dd ′ are sectional views. First, as illustrated in FIG. 2A, a base film 201 is formed over a substrate (insulating substrate) 200 having an insulating surface in order to prevent impurities from entering from the substrate. Then, an impurity is added to the crystallized semiconductor film 202 on the base film to control the threshold (channel dope), a gate insulating film 204 is formed, a TaN film 205a is formed as a lower conductive film of the gate electrode, and an upper film is formed. A W film 205b is formed as a conductive film. Then, a first resist 206 is formed on the W film, and taper etching is performed on the W film 205a and the TaN film 205b.

  Thereafter, as shown in FIG. 2B, without removing the resist 206, the W film was etched by anisotropic etching to form a gate electrode.

  Next, as shown in FIG. 2C, phosphorus (P) ions were implanted to form a source / drain region 209 and a gate overlap region 208. In the present Lov resistance monitor, the source / drain region and the gate overlap region are added simultaneously.

  Then, as shown in FIG. 2D, a passivation film 210 and an interlayer insulating film 215 are formed.

  As described above, resistance measurement is performed on the Lov resistance monitor, which is a TEG formed on the same substrate as the TFT.

  Next, resistance measurement will be described. In each Lov resistance monitor measured in the present embodiment, the alignment condition X is 0, ± 0.5, ± 1.0, ± 1,. 5, ± 2.0 and 0.5 μm intervals.

First, in the evaluation element (A), when the resistance in the channel formation region and the gate overlap region is ignored,
R ₁ = R _SD · L / (− X ₁ −α) (1)
R ₂ = R _SD · L / (− X ₂ −α) (2)
Is established. However, X ₁ and X ₂ are alignment conditions deviated from mask alignment, R ₁ and R ₂ are resistance values measured by X ₁ and X ₂ , R _SD is a sheet resistance of the source / drain region, and L is a lower conductive layer. The width of the film, α, indicates the misalignment of the mask. However, L is sufficiently larger than the width of the gate overlap region.

From the above formulas (1) and (2),
α = (− R ₁ · X ₁ + R ₂ · X ₂ ) / (R ₁ −R ₂ ) (3)
Since the equation (3) is established, the alignment deviation α can be calculated by substituting the measurement value R and the alignment condition X into this equation. That is, Formula (4) is materialized.
R _SD = R (−X−α) / L (4)

  In the evaluation element (A), the mask alignment deviation α was α≈0.3.

In the evaluation element (B) and the evaluation element (C), the following equation is established when the resistance in the channel formation region is ignored.
R = R _Lov · L / {L _Lov − (X + α)} (5)
Here, R _Lov represents the sheet resistance of the gate overlap region, and L _Lov represents the length of the gate overlap region.

From equation (5)
R _Lov = R (L _Lov −X−α) / L (6)
Is guided.

Further, in the evaluation element (D), the following expression is established.
R = R _ch · L / W (7)
Where R _ch represents the sheet resistance of the channel formation region.

From equation (7)
R _ch = R · W / L (8)
Is guided.

  As described above, the sheet resistance of each region can be obtained from the equations (4), (6), and (8).

FIG 5 And, has the structure shown in the evaluation device (A), a channel dope amount that was ^{1.8 × 10 13 ions / cm 2} ( measuring element 1,2), 1.5 × ^{10 13} The resistance value of the source / drain region measured by using ions / cm ² (measuring elements 3 and 4) is shown. FIG. 5 is a graph that takes into account correction of mask misalignment obtained from equation (4).

As shown in FIG. 5, by correcting the misalignment of the mask, the resistance R and -1 / (-X-α) have a proportional relationship, and it can be confirmed that the calculated α is correct. As can be seen from R = (L / R _SD ) · (1 / −X−α) obtained by modifying FIG. 5 or Expression (4), the present invention has a proportional relationship between the resistance R and (1 / −X−α). Correlation with having

  Further, by using the mask misalignment α and the equations (4), (6), and (8), as shown in FIG. 6, a channel formation region, a gate overlap region, and a source / source region corresponding to the taper shape of the gate electrode are obtained. The resistance distribution in the channel length direction of the drain region can be obtained more accurately. Further, FIG. 7 shows a graph in which the resistance of FIG. 6 is converted into sheet resistance.

  In the conventional method, the resistance of the gate overlap region does not correspond to the taper shape of the gate electrode and can only be calculated as an average value. However, according to the present invention, a resistance distribution corresponding to the taper shape of the gate electrode can be obtained. It becomes possible. As can be seen from FIG. 7, the present invention accurately shows the sheet resistance according to the taper of the gate overlap region. Compared with the conventional method in which this is an average value, the present invention provides accurate electrical characteristics. Obtainable.

  In particular, since the reliability of the GOLD structure is greatly affected by the impurity concentration in the gate overlap region, the lifetime of the TFT can be obtained without performing a long-term reliability test by using the obtained sheet resistance value of the gate overlap region. It becomes a standard of prediction.

(Embodiment 2)
The present invention makes it possible to measure the actual misalignment by measuring the electrical characteristics by utilizing the characteristic of the misalignment α of the mask of the evaluation element. The actual misalignment means deviating from the designed position due to the contraction of the substrate. This alignment deviation can be accurately evaluated by obtaining it from the electrical characteristic measurement using the alignment deviation α. At this time, the TFT and the TEG may have a structure other than the GOLD structure, for example, a simple single drain (not having a low concentration impurity region) structure. That is, the actual misalignment can be evaluated by an evaluation element in which a semiconductor film and a conductive film forming a gate electrode are stacked and shifted by α on the reference line.

  Therefore, in this embodiment, a method for measuring an actual misalignment by measuring electrical characteristics will be described.

  By arranging a plurality of evaluation elements on the substrate, preferably at the four corners of the substrate, the contraction or expansion of the substrate due to the heating process is grasped. That is, the evaluation elements as shown in FIG. 8B are arranged at the four corners of the substrate, and after the heat treatment such as activation, the mask misalignment α of each evaluation element is calculated. Expansion can be evaluated and actual misalignment can be evaluated. At this time, in order to calculate the deviation in the X-axis and Y-axis directions, TEGs obtained by rotating the TEG orientation shown in FIG. 8B by 90 degrees may be formed in each column.

  For example, as shown in FIG. 9, the contraction or expansion of the substrate can be evaluated from the difference between the alignment deviations α1 and α3 of the evaluation elements provided at the four corners of the substrate and the difference between α2 and α4. In addition, it is good in the shrinkage | contraction and expansion | swelling of the board | substrate which were calculated | required being 15-20 ppm or less.

  By obtaining the misalignment based on the measurement of the electrical characteristics of the evaluation element, the max misalignment can be accurately evaluated without observing with an SEM or the like.

(Embodiment 3)
In this embodiment, the sheet resistance value of the gate overlap region and its length dependency in the channel length direction (gate overlap length condition), the activation condition dependency, and the length dependency of the active layer in the channel length direction ( A computer system for creating a database of conditions such as (channel length condition), TFT structure, reliability condition, etc. and controlling the impurity addition amount (dose amount) will be described with reference to FIG.

  FIG. 3A illustrates a configuration of a computer system, which includes a terminal 301, a doping apparatus 302, a computer 311, and a measuring unit 321.

  The terminal 301 includes means for inputting manufacturing conditions for semiconductor elements and design conditions for a device (a plurality of semiconductor elements having a predetermined function such as a shift register and a signal line driver circuit). Note that the terminal 301 may use a personal digital assistant (PDA), a computer, or the like. The terminal 301 and the doping apparatus 302 are provided in a device manufacturing place (for example, a clean room).

  The computer 311 includes various computers such as a personal computer, a workstation, and a mainframe computer. The computer is a hardware provided in a general computer such as a central processing unit (CPU), a main storage device (main memory: RAM), a coprocessor, an image accelerator, a cache memory, an input / output control device (I / O), etc. Means. Further, an external storage device such as a hard disk device and a communication means such as the Internet can be provided.

  The measuring means 321 has a function of measuring the resistance of the TEG.

  Then, the computer 311 calculates the mask alignment deviation from the resistance value measured by the measuring unit 321 and obtains the resistance distribution, the condition of the semiconductor element or device input from the terminal, the gate overlap region A storage unit 313 for inputting reliability information such as an optimum resistance value and recording the conditions in a database; a determination unit 314 for determining and selecting an optimum impurity addition amount from the database; and a doping apparatus for selecting the selected addition amount And setting means 315 for setting to. The computer 311 may include an output unit that can output a predetermined addition amount by printing or display. Preferably, the unique conditions of each doping apparatus are recorded in the storage unit 313, and the optimum addition amount is selected by the determination unit 314.

  When the optimum addition amount is selected from the database (the path indicated by the solid line), the determination unit 314 determines the optimum addition amount based on the correlation calculated by the calculation unit 312 and the conditions stored in the storage unit 313. The selection unit 315 causes the doping apparatus 302 to set the addition amount.

  Alternatively, when the addition amount is set using the measured resistance value (path indicated by a dotted line), the calculation unit 312 calculates the mask misalignment based on the resistance obtained from the measurement unit 321, and the correlation is calculated. The doping amount may be set based on the correlation obtained by the setting means 315 by confirming that the resistance distribution is accurate.

  Such a computer 311 may be provided in a place where a device is manufactured or may be provided in another place. When providing in another place, each condition of the terminal 301 may be input to the determination unit 314 via the network. The measuring means 321 may also be provided at a place where the device is manufactured or at another place. When providing in another place, each result of the measuring means may be input to the computing means 312 via the network. Further, the measuring means 321 and the computer 311 may be provided at the same place.

  Next, using the flowchart shown in FIG. 3B, a system flow relating to a route will be described with a solid line. First, the resistances of the evaluation elements (A) to (D) formed under each condition are measured, and the computer calculates the misalignment α from the above equation based on the resistance value, and the correlation between the resistance and (−X−α). Get. A database in which these formation conditions (specifically, activation conditions, channel length conditions, gate overlap conditions, reliability conditions and other conditions, TFT structures), resistance values, misalignment α, and the like are stored. The optimum impurity concentration in the gate overlap region is determined and selected according to the desired device application.

  Thereafter, the result of the selected addition amount may be displayed, and the addition amount may be set in the doping apparatus or printed and output. Further, the obtained addition amount data and the like may be stored and recorded in a database.

  Such a computer system may use software such as a program or may be manufactured using hardware. The computer system may be installed in a doping apparatus or may be performed through network communication.

  With the computer system for controlling the addition amount as described above, the addition amount of impurities can be determined efficiently. Further, the computer system of the present invention can obtain a constant result in a short time without depending on the experience of the practitioner.

  Furthermore, if the correlation between the impurity concentration of the gate overlap region, the reliability, and the initial characteristics is stored in a database, the TEG can be evaluated to be a criterion for predicting the lifetime. For example, in a mass production factory or the like, it is difficult to perform time-consuming reliability evaluation (deterioration test), but it is possible to evaluate deterioration using a resistance measurement result as a criterion.

(Embodiment 4)
Using the technical idea of the present invention, it is possible to measure the resistance of a TFT having a single drain structure. Therefore, in this embodiment, resistance measurement using an evaluation element having a single drain structure will be described. The sheet resistance in the source / drain region and the channel formation region can be obtained by an evaluation element having a single drain structure (an evaluation element for measuring the impurity concentration of the source / drain region is expressed as an SD resistance monitor).

  Similarly to the above embodiment, a single drain structure TFT and an SD resistance monitor are formed in the panel portion under the same manufacturing conditions and manufacturing steps. For example, in FIG. 1, a single drain structure TFT and an SD resistance monitor may be formed as a structure in which the upper conductive film 102 is not provided. At this time, a conductive film having an end portion on the minus side by the reference line, a conductive film having an end portion in contact with the reference line, and a conductive film having an end portion on the plus side from the reference line To form an SD resistance monitor.

  Thereafter, resistance measurement is performed on each SD resistance monitor. Then, the sheet resistance in the source / drain region and the channel formation region in the measured SD resistance monitor (measuring element) can be obtained. At the same time, by utilizing the characteristics of the misalignment of the mask of the SD resistance monitor, which is an evaluation element, it is possible to measure the actual misalignment by measuring the electrical characteristics. By obtaining the misalignment based on the measurement of the electrical characteristics of the evaluation element, the max misalignment can be accurately evaluated without observing with an SEM or the like.

  A TFT having a single drain structure is often mounted on a panel portion more than a TFT having a GOLD structure. Therefore, resistance measurement for a single drain structure TFT is often used as in this embodiment.

  In the panel portion, a single drain TFT and a GOLD TFT are often formed together. In this case, it is preferable to form a Lov resistance monitor and an SD resistance monitor as evaluation elements and perform resistance measurement.

The figure which shows TEG of this invention. The figure which shows the preparation processes of TEG of this invention. The figure which shows the computer system of this invention. The figure which shows the experimental result of this invention. The figure which shows the experimental result of this invention. The figure which shows the experimental result of this invention. The figure which shows the experimental result of this invention. The figure which shows TEG of this invention. The figure which shows the evaluation method of the misalignment of the mask using this invention.

Claims (7)

A method for evaluating a semiconductor device using a plurality of TEGs,
The semiconductor device has a plurality of TFTs,
The plurality of TFTs are provided on the same substrate as the plurality of TEGs,
The plurality of TEGs and the plurality of TFTs each have a semiconductor film and a gate electrode provided on the semiconductor film ,
The gate electrode includes a first conductive film and a second conductive film stacked in order from the semiconductor film, and an end of the first conductive film is longer than an end of the second conductive film. ,
The semiconductor film includes a low concentration impurity region overlapping the first conductive film beyond an end of the second conductive film , a channel formation region inside the low concentration impurity region, and an outside of the low concentration impurity region. It has a pair of impurity regions in,
The plurality of TEGs include first to fourth TEGs,
The first TEG is provided so that an end of the first conductive film and an end of the second conductive film do not exceed a side end of the semiconductor film,
In the second TEG, the end of the first conductive film coincides with the side end of the semiconductor film, and the end of the second conductive film does not exceed the side end of the semiconductor film. Provided in
The third TEG includes a side end portion of the semiconductor film between an end of the first conductive film and an end of the second conductive film,
The fourth TEG is provided so that an end of the first conductive film and an end of the second conductive film extend beyond a side end of the semiconductor film,
The plurality of TEGs and the plurality of TFTs use a mask when etching the gate electrode,
The first TEG includes a first measurement element having an alignment condition of the mask as X1, and a second measurement element having the alignment condition as X2.
The resistors R1, R2 of the non-pure product region of the first measuring element and the second measuring element and measurement,
An alignment deviation α of the mask is calculated from X1 and X2 of the alignment condition and the resistors R1 and R2.
The sheet resistance of the pair of impurity regions of the first TEG, the resistance R measured for the pair of impurity regions, the alignment condition, the misalignment, and the width of the first conductive film The first relationship of
Measuring the resistance R3 of the low concentration impurity region of the second TEG and the third TEG;
Sheet resistance of the low concentration impurity region of the second TEG and the low concentration impurity region of the third TEG, resistance R3 measured for the low concentration impurity region, the alignment condition, and the alignment A second relationship between the deviation and the width of the first conductive film is obtained,
Measuring the resistance R4 of the low concentration impurity region of the fourth TEG;
A third relationship between the sheet resistance of the channel formation region of the fourth TEG, the resistance R4 measured for the channel formation region, and the width of the first conductive film is obtained,
A method of evaluating a semiconductor device, comprising determining the resistance of the channel formation region, the low-concentration impurity region, and the impurity region in the TFT from the misalignment and the first to third relationships. . A method for evaluating a semiconductor device using a plurality of TEGs,
The semiconductor device has a plurality of TFTs,
The plurality of TFTs are provided on the same substrate as the plurality of TEGs,
The plurality of TEGs and the plurality of TFTs each have a semiconductor film and a gate electrode provided on the semiconductor film,
The gate electrode includes a first conductive film and a second conductive film stacked in order from the semiconductor film, and an end of the first conductive film is longer than an end of the second conductive film. ,
The semiconductor film includes a low concentration impurity region overlapping the first conductive film beyond an end of the second conductive film, a channel formation region inside the low concentration impurity region, and an outside of the low concentration impurity region. A pair of impurity regions
The plurality of TEGs include first to fourth TEGs,
The first TEG is provided so that an end of the first conductive film and an end of the second conductive film do not exceed a side end of the semiconductor film,
In the second TEG, the end of the first conductive film coincides with the side end of the semiconductor film, and the end of the second conductive film does not exceed the side end of the semiconductor film. Provided in
The third TEG includes a side end portion of the semiconductor film between an end of the first conductive film and an end of the second conductive film,
The fourth TEG is provided so that an end of the first conductive film and an end of the second conductive film extend beyond a side end of the semiconductor film,
The plurality of TEGs and the plurality of TFTs use a mask when etching the gate electrode,
The first TEG includes a first measurement element having an alignment condition of the mask as X1, and a second measurement element having the alignment condition as X2.
Measuring resistances R1 and R2 of impurity regions of the first measurement element and the second measurement element;
An alignment deviation α of the mask is calculated from X1 and X2 of the alignment condition and the resistors R1 and R2.
Sheet resistance (R) of the pair of impurity regions of the first TEG _SD ), The resistance (R) measured for the pair of impurity regions, the alignment condition (X), the misalignment (α), and the width (L) of the first conductive film. 1 relationship is R _SD = R (−X−α) / L,
Measuring the resistance R3 of the low concentration impurity region of the second TEG and the third TEG;
Sheet resistance (R) of the low-concentration impurity region of the second TEG and the low-concentration impurity region of the third TEG _Lov ) And the length (L _LOV ), The resistance (R) measured for the low-concentration impurity region, the alignment condition (X), the misalignment (α), and the width (L) of the first conductive film. 2 relationship is R _Lov = R (L _Lov -X-α) / L,
Measuring the resistance R4 of the low concentration impurity region of the fourth TEG;
Sheet resistance (R) of the channel formation region of the fourth TEG _ch ), The length (W) of the channel formation region, the resistance (R) measured with respect to the channel formation region, and the width (L) of the first conductive film is R _ch = R · W / L
A method of evaluating a semiconductor device, comprising determining the resistance of the channel formation region, the low-concentration impurity region, and the impurity region in the TFT from the misalignment and the first to third relationships. . According to claim 1 or 2, the evaluation method of a semiconductor device ends and the end of the second conductive film of the first conductive film is characterized by having a taper. An element substrate on which a semiconductor device is formed,
The semiconductor device has a plurality of TFTs,
The plurality of TFTs are provided on the same substrate as the plurality of TEGs,
The plurality of TEGs and the plurality of TFTs each have a semiconductor film and a gate electrode provided on the semiconductor film,
The gate electrode includes a first conductive film and a second conductive film stacked in order from the semiconductor film, and an end of the first conductive film is longer than an end of the second conductive film. ,
The semiconductor film includes a low concentration impurity region overlapping the first conductive film beyond an end of the second conductive film, a channel formation region inside the low concentration impurity region, and an outside of the low concentration impurity region. A pair of impurity regions
The plurality of TEGs include first to fourth TEGs,
The first TEG is provided so that an end of the first conductive film and an end of the second conductive film do not exceed a side end of the semiconductor film,
In the second TEG, the end of the first conductive film coincides with the side end of the semiconductor film, and the end of the second conductive film does not exceed the side end of the semiconductor film. Provided in
The third TEG includes a side end portion of the semiconductor film between an end of the first conductive film and an end of the second conductive film,
The fourth TEG is provided so that an end of the first conductive film and an end of the second conductive film extend beyond a side end of the semiconductor film,
The plurality of TEGs and the plurality of TFTs use a mask when etching the gate electrode,
The first TEG includes an element substrate having a first measurement element having an alignment condition of the mask as X1 and a second measurement element having the alignment condition as X2. According to claim 4, wherein the first conductive end and said second conductive layer of the end element substrate which is characterized that you have a taper of the membrane. 6. The element substrate according to claim 4 , wherein the first conductive film is a TaN film and the second conductive film is a W film. In any one of claims 4 to 6, wherein the first TEG to the fourth TEG, an element substrate which is characterized in that provided in a plurality of layers.

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