JP5414712B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device applied to a display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device.

  Thin film transistors are used for display devices. As an example of such a thin film transistor, an n-type thin film transistor having an LDD (Lightly Doped Drain) structure described in Patent Document 1 will be described.

  An n-type thin film transistor having an LDD structure includes a source region, a drain region, a channel region, an LDD region, a gate insulating film, a gate electrode, and the like, and is formed over a glass substrate. In the n-type thin film transistor, by applying a higher voltage to the drain than to the gate, a relatively large electric field is generated at the drain side junction.

  Electrons accelerated by this electric field cause an impact ionization phenomenon, and pairs of electrons and holes are generated. This phenomenon is repeated, the number of electron-hole pairs increases, the drain current increases, and avalanche breakdown occurs. The drain voltage at this time becomes the source / drain breakdown voltage.

  In a thin film transistor having an LDD structure, LDD regions are formed in a region between a channel region and a source region and a region between a channel region and a drain region, respectively. The impurity concentration of the LDD region is set higher than the impurity concentration of the channel region and lower than the impurity concentration of the source region and the drain region. The impact ionization phenomenon is suppressed by relaxing the electric field in the vicinity of the drain region by the LDD region, and the source / drain breakdown voltage can be improved.

  However, the thin film transistor having the LDD structure has a problem that the ON current of the thin film transistor is low because the resistance of the LDD region acts as a parasitic resistance.

  In order to solve this problem, Patent Document 2 proposes a thin film transistor having a GOLD (Gate Overlapped Lightly Doped Drain) structure. An n-type thin film transistor having a GOLD structure is formed over a glass substrate having a source region, a drain region, a channel region, a GOLD region, a gate insulating film, a gate electrode, and the like.

  The GOLD region is formed in a region located immediately below the gate electrode among the region between the channel region and the source region and the region between the channel region and the drain region. Is overlapping. Since the GOLD region has a relatively low impurity concentration and is located in a region immediately below the gate, a relatively high ON current can be obtained. Also, a relatively good source / drain breakdown voltage can be secured.

JP 2001-345448 A JP 2002-76351 A

  However, even in a conventional thin film transistor having a GOLD structure, the resistance in the GOLD region causes a parasitic resistance. An object of the present invention is to provide a semiconductor device that further reduces the parasitic resistance.

  A semiconductor device according to the present invention is a semiconductor device including a semiconductor element having a semiconductor layer, an insulating film, and an electrode and formed on a predetermined substrate. The semiconductor element includes a first impurity region and a second impurity. A first element having a region, a channel region, a third impurity region, and a fourth impurity region is provided. The first impurity region is formed in the semiconductor layer and has a predetermined impurity concentration. The second impurity region is formed in the semiconductor layer at a distance from the first impurity region, and has a predetermined impurity concentration. The channel region is formed in the portion of the semiconductor layer located between the first impurity region and the second impurity region and spaced apart from the first impurity region and the second impurity region, and has a predetermined channel length. Become a channel. The third impurity region is formed in contact with the channel region at a portion of the semiconductor layer located between the first impurity region and the channel region, and has a lower impurity concentration than the first impurity region. The fourth impurity region is formed in a portion of the semiconductor layer located between the second impurity region and the channel region so as to be in contact with the channel region, and has a lower impurity concentration than the second impurity region. In the first element, the electrode has one side portion and the other side portion facing each other, and is formed to overlap with the channel region, the third impurity region portion, and the fourth impurity region portion. ing. The first insulating film is formed between the semiconductor layer and the electrode so as to be in contact with the semiconductor layer and the electrode, respectively. Then, from the first overlap length in the channel length direction of the portion where the electrode and the third impurity region overlap each other from the portion where the plane including the one side intersects the semiconductor layer to the channel region, The second overlap length in the channel length direction of the portion where the electrode and the fourth impurity region overlap each other from the portion where the plane including the other side portion intersects the semiconductor layer to the channel region is increased. Is formed.

  According to this configuration, the thin film transistor including the first impurity region to the fourth impurity region, the electrode, and the channel region is configured, and in the thin film transistor, the portion where the electrode and the third impurity region are opposed to each other, The electrode and the fourth impurity region are opposed to each other and overlapped with each other. In addition, the electrode and the fourth impurity region are opposed to each other and overlapped with each other than the first overlap length in the channel length direction of the portion where the electrode and the third impurity region overlap each other. The second overlap length in the channel length direction is formed to be long. Accordingly, the parasitic capacitance of the thin film transistor can be reduced without impairing the breakdown voltage between the first impurity region and the second impurity region, as compared with the case of the thin film transistor having the same first overlap length and second overlap length. Can do.

  Another semiconductor device according to the present invention is a semiconductor device including a semiconductor element having a semiconductor layer, an insulating film, and an electrode and formed on a predetermined substrate, and the semiconductor element includes a first impurity region. And a first element having a second impurity region, a channel region, and a third impurity region. The first impurity region is formed in the semiconductor layer and has a predetermined impurity concentration. The second impurity region is formed in the semiconductor layer at a distance from the first impurity region, and has a predetermined impurity concentration. The channel region is formed in a portion of the semiconductor layer located between the first impurity region and the second impurity region, with a distance from the second impurity region, and becomes a channel having a predetermined channel length. The third impurity region is formed at a portion of the semiconductor layer located between the second impurity region and the channel region so as to be in contact with the channel region, and has a lower impurity concentration than the second impurity region. In the first element, the electrode has one side portion and the other side portion facing each other, and is formed so as to overlap with the channel region and the third impurity region. The first insulating film is formed between the semiconductor layer and the electrode so as to be in contact with the semiconductor layer and the electrode, respectively. The junction between the first impurity region and the channel region and one side are located on substantially the same plane, and the electrode and the third impurity region are opposed to the portion where the surface including the other side intersects the semiconductor layer. Thus, the length of the overlapping portions in the channel length direction has a predetermined length.

  According to this configuration, the thin film transistor including the first impurity region to the third impurity region, the electrode, and the channel region is configured. In the thin film transistor, the electrode has a predetermined length only in addition to the channel region and the third impurity region. Only overlap in opposition. Thereby, as compared with the conventional thin film transistor, the parasitic capacitance of the thin film transistor can be reduced without impairing the breakdown voltage between the first impurity region and the second impurity region.

  A manufacturing method of a semiconductor device according to the present invention includes the following steps. An electrode is formed on a substrate having a main surface. A predetermined semiconductor layer is formed on the substrate. An insulating film is formed over the substrate between the step of forming the electrode and the step of forming the semiconductor layer. A first mask material is formed so as to cross the semiconductor layer. By introducing impurity ions of a predetermined conductivity type into the semiconductor layer using the first mask material as a mask, a portion of the semiconductor layer located immediately below the mask material is used as a channel region, and the mask material is sandwiched between one and the other. A pair of first impurity regions having a predetermined impurity concentration is formed in the portion of the semiconductor layer located. A second mask material is formed on the semiconductor layer to cover the entire channel region and the portions of the pair of first impurity regions. By introducing impurity ions of a predetermined conductivity type into the semiconductor layer using the second mask material as a mask, a predetermined impurity is formed in the first impurity region located on one side and the other side across the channel region. A pair of second impurity regions having an impurity concentration higher than the impurity concentration is formed. In the step of forming the electrode, the electrode has one side portion and the other side portion that face each other, and the entire channel region and each portion of the pair of first impurity regions face each other in an overlapping manner. Formed as follows. Further, the plane including the other side of the electrode is a pair of first impurity regions than the distance from the portion where the plane including the one side of the electrode intersects with one region of the pair of first impurity regions to the channel region. It is formed so that the distance from the portion intersecting with the other region to the channel region becomes long.

  According to this manufacturing method, the thin film transistor including the first impurity region, the second impurity region, the electrode, and the channel region is formed. In the thin film transistor, the electrode has both sides and is formed so as to be opposed to and overlap each of the pair of first impurity regions, and is directly below one side of both sides of the electrode. It is formed such that the distance from the portion of the other first impurity region located immediately below the other side portion to the channel region is longer than the distance from the portion of the one first impurity region located to the channel region. . Thereby, as compared with the conventional thin film transistor, the parasitic capacitance of the thin film transistor can be reduced without impairing the breakdown voltage between the pair of second impurity regions.

  In addition, another method for manufacturing a semiconductor device according to the present invention includes the following steps. An electrode is formed on a substrate having a main surface. A predetermined semiconductor layer is formed on the substrate. An insulating film is formed over the substrate between the step of forming the electrode and the step of forming the semiconductor layer. A first mask material is formed so as to cross the semiconductor layer. By introducing impurity ions of a predetermined conductivity type into the semiconductor layer using the first mask material as a mask, the portion of the semiconductor layer located immediately below the first mask material is used as a channel region, and the first mask material is sandwiched between them. A pair of first impurity regions having a predetermined impurity concentration is formed in the portion of the semiconductor layer located on one side and the other side. A second mask material is formed on the semiconductor layer so as to cover the entire channel region and cover the other region without covering one region of the pair of first impurity regions. By introducing impurity ions of a predetermined conductivity type into the semiconductor layer using the second mask material as a mask, a predetermined impurity is formed in a portion of the first impurity region located on one side and the other side across the channel region. A pair of second impurity regions having an impurity concentration higher than the concentration is formed. In the step of forming the electrode, the electrode has one side portion and the other side portion that face each other, and the entire channel region and the portion of the other region of the pair of first impurity regions overlap the electrode. To be formed. The junction between one side of the electrode and the channel region and one region of the pair of second impurity regions is located on the same plane, and the plane including the other side of the electrode is connected to the other regions of the first impurity region. It is formed to have a predetermined distance from the intersecting portion to the channel region.

  According to this manufacturing method, the thin film transistor including the first impurity region, the second impurity region, the electrode, and the channel region is formed. In the thin film transistor, the electrode has opposite side surfaces and is formed immediately above the channel region and overlaps with only the other portion of the pair of first impurity regions. It is formed. Thereby, as compared with the conventional thin film transistor, the parasitic capacitance of the thin film transistor can be reduced without impairing the breakdown voltage between the pair of second impurity regions.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 3 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device shown in FIG. 1 in the embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. In the same embodiment, it is a graph which shows the relationship between a source-drain breakdown voltage and the overlap length on the drain side. In the modification 4 which concerns on the embodiment, it is a graph which shows the relationship of the ratio with respect to the voltage at the time of charge of the overlap length of a source side, and voltage change. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the same embodiment. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the same embodiment. FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment. FIG. 41 is a cross-sectional view showing a process performed after the process shown in FIG. 40 in the same embodiment. FIG. 42 is a cross-sectional view showing a process performed after the process shown in FIG. 41 in the same Example. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 8 of this invention. FIG. 45 is a cross-sectional view showing a step performed after the step shown in FIG. 44 in the same embodiment. FIG. 46 is a cross-sectional view showing a step performed after the step shown in FIG. 45 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 9 of this invention. FIG. 49 is a cross-sectional view showing a step performed after the step shown in FIG. 48 in the same embodiment. FIG. 50 is a cross-sectional view showing a step performed after the step shown in FIG. 49 in the same embodiment. FIG. 52 is a cross-sectional view showing a step performed after the step shown in FIG. 50 in the same embodiment. FIG. 52 is a cross-sectional view showing a step performed after the step shown in FIG. 51 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 10 of this invention. FIG. 55 is a cross-sectional view showing a step performed after the step shown in FIG. 54 in the same embodiment. FIG. 56 is a cross-sectional view showing a step performed after the step shown in FIG. 55 in the same embodiment. FIG. 57 is a cross-sectional view showing a step performed after the step shown in FIG. 56 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 11 of this invention. FIG. 60 is a cross-sectional view showing a step performed after the step shown in FIG. 59 in the same embodiment. FIG. 63 is a cross-sectional view showing a step performed after the step shown in FIG. 60 in the same embodiment. FIG. 62 is a cross-sectional view showing a process performed after the process shown in FIG. 61 in the same Example. FIG. 63 is a cross-sectional view showing a step performed after the step shown in FIG. 62 in the same embodiment. In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 12 of this invention. FIG. 66 is a cross-sectional view showing a step performed after the step shown in FIG. 65 in the same embodiment. FIG. 67 is a cross-sectional view showing a step performed after the step shown in FIG. 66 in the same embodiment. FIG. 68 is a cross-sectional view showing a process performed after the process shown in FIG. 67 in the same Example; In the same embodiment, it is a figure which shows the result of the source-drain pressure | voltage resistance of a thin-film transistor. It is a block diagram which shows the structure of the liquid crystal display device which concerns on Embodiment 13 of this invention. FIG. 71 is a cross-sectional view showing a step of a method of manufacturing the liquid crystal display device shown in FIG. 70 in the embodiment. FIG. 72 is a cross-sectional view showing a process performed after the process shown in FIG. 71 in the same Example. FIG. 73 is a cross-sectional view showing a process performed after the process shown in FIG. 72 in the same Example. FIG. 74 is a cross-sectional view showing a step performed after the step shown in FIG. 73 in the same embodiment. FIG. 75 is a cross-sectional view showing a step performed after the step shown in FIG. 74 in the same embodiment. FIG. 76 is a cross-sectional view showing a step performed after the step shown in FIG. 75 in the same embodiment. FIG. 77 is a cross-sectional view showing a step performed after the step shown in FIG. 76 in the same embodiment. In the same embodiment, it is a figure which shows the gate occupation area of a thin-film transistor. It is sectional drawing which shows 1 process of the manufacturing method of the liquid crystal display device which concerns on Embodiment 14 of this invention. FIG. 80 is a cross-sectional view showing a step performed after the step shown in FIG. 79 in the same embodiment. FIG. 81 is a cross-sectional view showing a step performed after the step shown in FIG. 80 in the same embodiment. FIG. 82 is a cross-sectional view showing a process performed after the process shown in FIG. 81 in the same Example. FIG. 83 is a cross-sectional view showing a step performed after the step shown in FIG. 82 in the same embodiment. FIG. 84 is a cross-sectional view showing a step performed after the step shown in FIG. 83 in the same embodiment. FIG. 85 is a cross-sectional view showing a step performed after the step shown in FIG. 84 in the same embodiment. In the same embodiment, it is a figure which shows the gate occupation area of a thin-film transistor.

Embodiment 1
A semiconductor device according to the first embodiment of the present invention will be described. As shown in FIG. 1, a silicon nitride film 2 is formed on a glass substrate 1, and a silicon oxide film 3 is formed on the silicon nitride film 2. An island-like polycrystalline silicon film is formed on the silicon oxide film 3. In the polycrystalline silicon film, a source region 45 having a first impurity concentration and a drain region 46 having a second impurity concentration separated from the source region 45 are formed.

  In a region located between the source region 45 and the drain region 46, a channel region 40 having a predetermined channel length is formed at a distance from the source region 45 and the drain region 45.

  A GOLD region 41 having an impurity concentration lower than the first impurity concentration is formed between the source region 45 and the channel region 40 from the source region 45 to the channel region 40. A GOLD region 42 having an impurity concentration lower than the second impurity concentration is formed between the drain region 46 and the channel region 40 from the drain region 46 to the channel region 40.

  A gate insulating film 5 made of a silicon oxide film is formed so as to cover the island-like polycrystalline silicon film. A gate electrode 6 a is formed on the gate insulating film 5. An interlayer insulating film 7 made of, for example, a silicon oxide film is formed so as to cover the gate electrode 6a. A contact hole 7 a that exposes the surface of the source region 45 and a contact hole 7 b that exposes the surface of the drain region 46 are formed in the interlayer insulating film 7. A source electrode 8a and a drain electrode 8b are formed on the interlayer insulating film 7 so as to fill the contact holes 7a and 7b.

  A thin film transistor T is configured including the gate electrode 6 a, the source region 45, the drain region 46, the GOLD regions 41 and 42, and the channel region 40. In particular, the gate electrode 6a has opposite side portions and is formed immediately above the channel region 40, and is formed so as to overlap the GOLD region 41 and the GOLD region 42 in a plane.

  The length G2 in the channel length direction of the portion where the gate electrode 6a and the GOLD region 42 overlap in plane is the channel length of the portion where the gate electrode 6a and the GOLD region 41 overlap in plane. It is set to be longer than the length G1 in the direction.

  Further, in this structure, as shown in FIG. 1, assuming a plane H1 including one side portion of the gate electrode 6a and a plane H2 including the other side portion, the portion from the portion where the plane H1 intersects the semiconductor layer to the channel region 40 The gate electrode 6a and the GOLD from the portion where the plane H2 intersects the semiconductor layer to the channel region 40 rather than the length G1 in the channel length direction of the portion where the gate electrode 6a and the GOLD region 41 overlap each other. The length G2 in the channel length direction of the portion that overlaps with the region 42 is set to be long. The structure assuming the planes H1 and H2 is not limited to the present embodiment, and the same applies to each embodiment described later.

  Next, an example of a method for manufacturing the semiconductor device described above will be described. As shown in FIG. 2, first, as a substrate, a silicon nitride film 2 having a film thickness of about 100 nm is formed on the main surface of a glass substrate 1 of Corning 1737 by, for example, a plasma CVD (Chemical Vapor Deposition) method. A silicon oxide film 3 having a thickness of about 100 nm is formed on the silicon nitride film 2. Next, as shown in FIG. 2, an amorphous silicon film 4 having a thickness of about 50 nm is formed on the silicon oxide film 3.

The silicon nitride film 2 is formed to prevent the impurities contained in the glass substrate 1 from diffusing upward. In addition to the silicon nitride film, a material such as SiON, SiC, AlN, Al ₂ O ₃ or the like may be applied as the film for preventing the diffusion of impurities. Further, although the two-layer structure of the silicon nitride film 2 and the silicon oxide film 3 is used as the base film of the amorphous silicon film 4, the present invention is not limited to the two-layer structure, and these films may be omitted or further May be laminated.

  Next, the amorphous silicon film 4 is heat-treated in a predetermined vacuum to remove unnecessary hydrogen present in the amorphous silicon film 4. Next, the amorphous silicon film 4 is polycrystallized by irradiating the amorphous silicon film 4 with, for example, a laser beam from a XeCl laser to form a polycrystalline silicon film. The grain size of the polycrystalline silicon film is about 0.5 μm.

  In addition to the XeCl laser, for example, a YAG laser or a CW laser may be used. Further, the amorphous silicon film may be polycrystallized by thermal annealing. In particular, when thermal annealing is performed, polycrystalline silicon having a larger particle diameter can be obtained by using a catalyst such as nickel.

  Next, a predetermined resist pattern 61 (see FIG. 3) is formed on the polycrystalline silicon film. Next, as shown in FIG. 3, by performing anisotropic etching on the polycrystalline silicon film using the resist pattern 61 as a mask, an island-shaped polycrystalline silicon film 4a is formed. Thereafter, the resist pattern 61 is removed by performing ashing and chemical treatment.

  Next, as shown in FIG. 4, gate insulating film 5 made of a silicon oxide film having a thickness of about 100 nm is formed by plasma CVD, for example, so as to cover polycrystalline silicon film 4a. In this case, TEOS (Tetra Ethyl Ortho Silicate), which is a liquid material, is used as a material for the silicon oxide film.

Next, in order to control the threshold value of the thin film transistor, boron is implanted into the polycrystalline silicon film 4a at a dose of 1 × 10 ¹² atoms / cm ² and an acceleration energy of 60 KeV, for example. This injection step may be performed if necessary and may be omitted.

Next, as shown in FIG. 5, a resist pattern 62 is formed by performing predetermined photoengraving. Next, as shown in FIG. 6, using the resist pattern 62 as a mask, phosphorus is implanted into the polycrystalline silicon film 4a at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV, for example, to form impurity regions 4ab and 4ac. Is formed. This implantation amount becomes the implantation amount (impurity concentration) in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Next, as shown in FIG. 7, a chromium film 6 having a thickness of about 200 nm is formed on the entire surface of the gate insulating film 5 by sputtering. Next, as shown in FIG. 8, a resist pattern 63 is formed by performing predetermined photolithography. By performing wet etching on the chromium film 6 using the resist pattern 63 as a mask, a gate electrode 6a is formed as shown in FIG.

  The gate electrode 6a is formed so as to planarly overlap the impurity region 4ab and the impurity region 4ac located with the impurity region 4aa serving as a channel in between. Then, the length G2 where the gate electrode 6a and the impurity region 4ac located on the drain side overlap is longer than the length G1 where the gate electrode 6a and the impurity region 4ab located on the source side overlap. For example, the length G2 is 1.5 μm and the length G1 is 0.5 μm. Thereafter, the resist pattern 63 is removed by performing ashing and chemical treatment.

Next, as shown in FIG. 10, using the gate electrode 6a as a mask, phosphorus is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV, for example. Impurity regions 4ad and 4ae are formed. Thus, the impurity regions 4ab and 4ac left after the formation of the impurity regions 4ad and 4ae are lower than the impurity concentration of the source region and the drain region, and the GOLD region overlaps the gate electrode 6a in a plane. It becomes.

  Next, as shown in FIG. 11, an interlayer insulating film 7 made of a silicon oxide film having a thickness of about 400 nm is formed by plasma CVD, for example, so as to cover gate electrode 6a. Next, a predetermined photolithography process is performed on the interlayer insulating film 7 to form a resist pattern (not shown) for forming contact holes. Using the resist pattern as a mask, anisotropic etching is performed on interlayer insulating film 7 and gate insulating film 5 to form contact hole 7a exposing the surface of impurity region 4ad and impurity region 4ae as shown in FIG. A contact hole 7b exposing the surface is formed.

  Next, a laminated film (not shown) of a chromium film and an aluminum film is formed on the interlayer insulating film 7 so as to fill the contact holes 7a and 7b. A resist pattern (not shown) for forming electrodes is formed by performing a predetermined photolithography process on the laminated film. Next, wet etching is performed using the resist pattern as a mask to form a source electrode 8a and a drain electrode 8b as shown in FIG. Note that in the case of a display device as a semiconductor device, a pixel electrode is also formed at the same time in a pixel thin film transistor (not shown) formed in the display portion.

  As described above, the main part of the semiconductor device including the thin film transistor T is formed. In this thin film transistor T, the impurity region 4ad becomes the source region 45, the impurity region 4ae becomes the drain region 46, the impurity regions 4ab and 4ac become the GOLD regions 41 and 42, and the impurity region 4aa becomes the channel region 40.

  In the GOLD regions 41 and 42, as shown in FIG. 1, the length G2 of the GOLD region 42 located on the drain side in the channel length direction is longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction. Is also set to be long.

  That is, the overlap length G1 in the channel length direction of the GOLD region 41 that overlaps the gate electrode 6a in a planar manner from the portion located directly below one side of the gate electrode 6a having both sides to the channel region 40. Rather, the overlap length G2 in the channel length direction of the GOLD region 42 that planarly overlaps the gate electrode 6a from the portion located immediately below the other side of the gate electrode 6b to the channel region 40 becomes longer. It is formed as follows.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor T will be described. In the measurement, the gate width is 10 μm, the effective gate length is 5 μm, the overlap length G2 of the GOLD region 42 on the drain side is 1.5 μm, the overlap length G1 of the GOLD region 41 on the source side is 0.5 μm, and the channel length direction A thin film transistor in which the width of the gate electrode 6a (in the horizontal direction toward the paper surface) was 7 μm was used.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. The overlap length was 1.5 μm, the gate width was 10 μm, and the gate electrode width in the channel length direction was 8 μm.

  FIG. 14 shows the measurement results of the source / drain breakdown voltage. During measurement, the gate voltage is set to 0 V, and the source is grounded. The drain voltage when the drain current was 0.1 μA was defined as the source / drain breakdown voltage. As shown in FIG. 14, it was confirmed that the source / drain breakdown voltage of the GOLD structure thin film transistor (the thin film transistor of the present invention) according to this embodiment can achieve the same level of source / drain breakdown voltage as the conventional GOLD structure thin film transistor. It was.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment and the conventional GOLD structure thin film transistor. As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the parasitic capacitance due to the GOLD regions 41 and 42 having different overlap lengths with the gate electrode 6a has the same overlap length with the gate electrode. It was estimated to be about 68% of the parasitic capacitance in the thin film transistor.

  As described above, the thin film transistor having the GOLD structure according to the present embodiment reduces the parasitic capacitance due to the GOLD region while ensuring the same level of source / drain breakdown voltage as compared with the conventional thin film transistor having the GOLD structure. Turned out to be possible.

  In the above-described semiconductor device, the GOLD regions 41 and 42 have been described by taking as an example the case where the GOLD regions 41 and 42 have one impurity concentration. However, the present invention is not limited to this, and exceeds the impurity concentrations of the source region 45 and the drain region 46. It may be configured to have a plurality of different impurity concentrations within the range. By having a plurality of impurity concentrations, concentration of the electric field can be avoided and the source / drain breakdown voltage can be improved.

Next, a modified example related to the overlap length will be described.
Modification 1
In the above-described thin film transistor having the GOLD structure, the case where the overlap length of the GOLD region 42 on the drain side is 1.5 μm has been described as an example, but the overlap length is not limited to this length. By setting the overlap length longer, the source / drain breakdown voltage can be improved. Therefore, it is desirable that the overlap length is long from the viewpoint of source / drain breakdown voltage.

  FIG. 15 is a graph showing the relationship between the overlap length on the drain side and the source / drain breakdown voltage. Normally, since the thin film transistor is operated at a source-drain voltage of about 10 V, the overlap length is preferably 0.5 μm or more in consideration of this voltage and the source-drain breakdown voltage.

  On the other hand, when the overlap length is increased, the width of the gate electrode in the channel length direction must be increased accordingly, and the size of the thin film transistor increases. For this reason, the occupied area increases, and the overlap length cannot be excessively increased.

  The size of the thin film transistor having the GOLD structure according to the embodiment is the same level as the size of the conventional thin film transistor having the GOLD structure when the overlap length is about 2.5 μm. For this reason, setting the overlap length exceeding 2.5 μm is disadvantageous in terms of size (occupied area), so the upper limit of the overlap length is 2.5 μm.

Modification 2
The overlap length varies within the plane of the substrate or between substrates due to variations in the exposure process (photoengraving process). The variation in the overlap length is determined by the alignment accuracy when the resist pattern 63 for patterning the gate electrode is formed (see FIG. 8).

  Therefore, when setting the overlap length, it is necessary to consider the alignment accuracy in the exposure process. That is, in order to ensure the target overlap length, the overlap length needs to be set larger than the sum of the target value and the alignment accuracy. In the current exposure apparatus (stepper), the alignment accuracy is 0.3 μm (3σ). For this reason, in order to secure an overlap length of 0.5 μm at the drain side, it is necessary to set the set value of the overlap length on the drain side to 0.8 μm or more.

  On the other hand, when the overlap length is set without taking the alignment accuracy into consideration, according to the graph shown in FIG. 15, the target value of 0.5 μm on the drain side overlap length is within the range of variations in alignment accuracy. The source / drain breakdown voltage may be lower than 10V. Therefore, in such a case, there arises a problem that the source / drain breakdown voltage cannot be secured.

  The alignment accuracy is sufficiently taken into consideration particularly in a pattern that requires overlay accuracy. In general, the highest alignment accuracy is required for overlaying with a base pattern when forming contact holes or pad openings. For this reason, the positional deviation of the contact hole or the like (difference from the design value) with respect to the base pattern becomes a value corresponding to the alignment accuracy.

Modification 3
In the above-described thin film transistor having the GOLD structure, the case where the overlap length of the GOLD region 41 on the source side is 0.5 μm has been described as an example, but the overlap length is not limited to this length. By setting the overlap length shorter, the parasitic capacitance can be reduced. Therefore, it is desirable that the overlap length is short from the viewpoint of parasitic capacitance.

  As described in the second modification, the overlap length varies within the plane of the substrate or between the substrates due to variations in the exposure process (photoengraving process). The variation in the overlap length is determined by the alignment accuracy when forming a resist pattern for patterning the gate electrode.

  In order to secure the overlap length on the source side, it is necessary to set the overlap length setting value to be larger than the alignment accuracy. In the current exposure apparatus, since the alignment accuracy is 0.3 μm (3σ), it is necessary to set the set value of the overlap length on the source side to be larger than 0.3 μm.

  On the other hand, if the overlap length is set without considering the alignment accuracy, the overlap length cannot be secured on the source side within the range of the overlap length variation, and the GOLD region cannot be formed.

  In the thin film transistor having the GOLD structure, the channel length is the length (distance) between the GOLD region located on the source side and the GOLD region located on the drain side. However, when the overlap length cannot be secured on the source side, The channel length in such a case is determined by the distance between the source region and the GOLD region located on the drain side. For this reason, the channel length becomes shorter than the predetermined channel length, the breakdown voltage between the source and the drain is lowered, and characteristics such as threshold voltage and mutual conductance greatly vary.

  As described above, since the highest alignment accuracy is generally required for overlaying with a base pattern when forming a contact hole or pad opening, the positional deviation (design value and the like) of the contact hole with respect to the base pattern is required. Difference) is a value corresponding to the alignment accuracy.

Modification 4
In the above-described thin film transistor having the GOLD structure, the case where the overlap length of the GOLD region 41 on the source side is 0.5 μm has been described as an example, but the overlap length is not limited to this length. The gate electrode 6a and the source region 45 are capacitively coupled by a parasitic capacitance between them. Similarly, the gate electrode 6a and the drain region 46 are capacitively coupled by a parasitic capacitance therebetween.

  These parasitic capacitors are charged when a positive voltage is applied to the gate electrode 6a and the thin film transistor is turned on. When the thin film transistor performs the OFF operation, the voltage of the gate electrode 6a changes to the negative side, so that the amount of charge accumulated in the parasitic capacitance changes.

  When a load capacitance is coupled to the source region 45 or the drain region 46, the voltage acting on the load capacitance also changes due to a change in the amount of charge accumulated in the parasitic capacitance. Such a change in voltage leads to deterioration of display characteristics such as contrast in the display device.

  Here, FIG. 16 shows the relationship between the overlap length on the source side when the load capacitance is coupled to the source side and the ratio of the voltage change to the voltage at the time of charging. The load capacity was 3 pF. As shown in FIG. 16, it can be seen that as the overlap length on the source side increases, the rate of voltage change also increases. In particular, the rate of voltage change is relatively small in the range where the overlap length does not exceed 1.0 μm. From this, it can be seen that it is effective to set the overlap length on the source side to 1.0 μm or less from the viewpoint of reducing the change in voltage acting on the load capacity.

Modification 5
In the above-described thin film transistor having the GOLD structure, the case where the overlap length of the GOLD region 42 on the drain side is 1.5 μm and the overlap length of the GOLD region 41 on the source side is 0.5 μm has been described as an example. In this case, the difference between the overlap length of the drain-side GOLD region 42 and the overlap length of the source-side GOLD region 41 is 1.0 μm, but the difference in overlap length is not limited to this.

  As already described, the variation in the overlap length is determined by the alignment accuracy when forming the resist pattern for patterning the gate electrode, and the alignment accuracy is 0.3 μm (3σ). Therefore, in order to make the overlap length on the source side shorter than the overlap length on the drain side, the difference between the overlap length on the source side and the overlap length on the drain side must be set to 0.6 μm or more. There is.

  It should be noted that the overlap length in each of the above-described modified examples applies similarly to each embodiment described below.

Embodiment 2
In the method for manufacturing a semiconductor device described above, an n-channel thin film transistor is described as an example of a thin film transistor. However, a p-channel thin film transistor is also formed on a glass substrate at the same time. Here, the main steps of the method for manufacturing a p-channel thin film transistor will be described.

First, after the process shown in FIG. 4 described above, as shown in FIG. 17, a resist pattern 62 is formed by performing a predetermined photoengraving process. Using resist pattern 62 as a mask, boron is implanted into the polycrystalline silicon film at a dose of 5 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV, for example, to form impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed as shown in FIG. Next, using gate electrode 6a as a mask, for example, boron is implanted into impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV to form impurity regions 4ad and 4ae that become source and drain regions. Is formed.

  Thus, the impurity regions 4ab and 4ac left after the formation of the impurity regions 4ad and 4ae are lower than the impurity concentration of the source region and the drain region, and the GOLD region overlaps the gate electrode 6a in a plane. It becomes.

  Thereafter, through the same steps as those shown in FIGS. 11 to 13, the p-channel type GOLD thin film transistor is formed as shown in FIG.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. In the measurement, the gate width is 20 μm, the effective gate length is 5 μm, the overlap length G2 of the GOLD region 42 on the drain side is 1.5 μm, the overlap length G1 of the GOLD region 41 on the source side is 0.5 μm, and the channel length direction A thin film transistor in which the width of the gate electrode 6a was 7 μm was used.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. The overlap length was 1.5 μm and the gate width was 20 μm.

  FIG. 20 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 20, it was confirmed that the source / drain breakdown voltage of the thin film transistor of the GOLD structure according to the second embodiment (the thin film transistor of the present invention) can achieve the same level of source / drain breakdown voltage as the conventional thin film transistor of the GOLD structure. It was.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment and the conventional GOLD structure thin film transistor. As a result, in the thin film transistor having the GOLD structure according to the embodiment, the parasitic capacitance due to the GOLD regions 41 and 42 having different overlap lengths with the gate electrode 6a has the same overlap length with the gate electrode as in the conventional GOLD structure. It was estimated to be about 68% of the parasitic capacitance in the thin film transistor.

  Thus, it was confirmed that the parasitic capacitance can be significantly reduced in the thin film transistor having the GOLD structure according to the present embodiment while ensuring the same breakdown voltage as that of the conventional thin film transistor having the GOLD structure.

Embodiment 3
Here, a semiconductor device having a GOLD region only on the drain side and not having a GOLD region on the source side will be described as an example. First, the manufacturing method will be described. The steps up to forming the gate insulating film 5 shown in FIG. 21 and injecting a predetermined impurity for controlling the threshold value of the thin film transistor are the same as those up to the step shown in FIG.

Next, as shown in FIG. 22, a resist pattern 65 is formed by performing predetermined photoengraving. Next, using resist pattern 65 as a mask, phosphorus is implanted into polycrystalline silicon film 4a at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 65 is removed by performing ashing and chemical treatment.

  Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. In this case, the gate electrode 6a is formed so as to planarly overlap only the impurity region 4ac out of the impurity regions 4ab and 4ac located across the impurity region 4aa serving as a channel, and not to overlap the impurity region 4ab. The The length G2 at which the gate electrode 6a and the impurity region 4ac located on the drain side overlap is 1.5 μm.

Next, using the gate electrode 6a as a mask, phosphorus is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV, for example, so that the impurity regions 4ad and 4ae become source and drain regions. Is formed. In this way, the impurity region 4ac left by the formation of the impurity regions 4ad and 4ae becomes a GOLD region that is lower than the impurity concentration of the source region and the drain region and overlaps the gate electrode 6a in a plane. .

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13, the thin film transistor having the GOLD structure is formed as shown in FIG. The thin film transistor having the GOLD structure formed as described above includes a GOLD region 42 that planarly overlaps the gate electrode 6a only on the drain side, and a GOLD region that planarly overlaps the gate electrode 6a on the source side. Not.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. For the measurement, a thin film transistor having a gate width of 10 μm, an effective gate length of 5 μm, an overlap length G2 of the drain side GOLD region 42 of 1.5 μm, and a width of the gate electrode 6a in the channel length direction of 6.5 μm was used. .

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same.

  FIG. 25 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 25, the source / drain breakdown voltage of the GOLD structure thin film transistor according to the present embodiment is almost the same as the breakdown voltage of the GOLD structure thin film transistor according to the first embodiment, and is the same as the conventional GOLD structure thin film transistor. It was confirmed that a level of source / drain breakdown voltage could be achieved.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment and the conventional GOLD structure thin film transistor. As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the GOLD region overlapping the gate electrode 6a is only the GOLD region 42 located on the drain side, and the parasitic capacitance due to the GOLD region 42 is the same as that of the conventional GOLD. It was estimated to be about 50% of the parasitic capacitance in the structured thin film transistor, and it was found that the parasitic capacitance was further reduced.

  As described above, it was confirmed that the parasitic capacitance can be further reduced in the thin film transistor having the GOLD structure according to this embodiment while ensuring the same breakdown voltage as that of the conventional thin film transistor having the GOLD structure.

Embodiment 4
In Embodiment 3, an n-channel thin film transistor is described as an example of a thin film transistor; however, a p-channel thin film transistor is also formed over the glass substrate at the same time. Here, the main steps of the method for manufacturing a p-channel thin film transistor will be described.

First, after the process shown in FIG. 4 described above, as shown in FIG. 26, a predetermined photoengraving is performed to form a resist pattern 65. Using resist pattern 65 as a mask, boron is implanted into the polycrystalline silicon film, for example, at a dose of 5 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV to form impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 65 is removed by performing ashing and chemical treatment.

Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed as shown in FIG. Next, using gate electrode 6a as a mask, for example, boron is implanted into impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV to form impurity regions 4ad and 4ae that become source and drain regions. Is formed.

  In this way, the impurity region 4ac left on the drain side by forming the impurity regions 4ad, 4ae is lower than the impurity concentration of the source region and the drain region and overlaps the gate electrode 6a in a plane. It becomes an area.

  Thereafter, through the same steps as those shown in FIGS. 11 to 13, the p-channel type GOLD thin film transistor is formed as shown in FIG.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. For the measurement, a thin film transistor having a gate width of 20 μm, an effective gate length of 5 μm, an overlap length G2 of the drain-side GOLD region 42 of 1.5 μm, and a width of the gate electrode 6a in the channel length direction of 6.5 μm was used. .

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same.

  FIG. 29 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 29, the source / drain breakdown voltage of the GOLD structure thin film transistor according to the present embodiment is almost the same as the breakdown voltage of the GOLD structure thin film transistor according to the second embodiment, and is the same as that of the conventional GOLD structure thin film transistor. It was confirmed that a level of source / drain breakdown voltage could be achieved.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the fourth embodiment and the conventional GOLD structure thin film transistor. As a result, in the thin film transistor having the GOLD structure according to the fourth embodiment, the GOLD region overlapping the gate electrode 6a is only the GOLD region 42 located on the drain side, and the parasitic capacitance due to the GOLD region 42 is the same as that of the conventional GOLD. It was estimated to be about 50% of the parasitic capacitance in the structured thin film transistor, and it was found that the parasitic capacitance was further reduced.

  As described above, it was confirmed that the parasitic capacitance can be further reduced in the thin film transistor having the GOLD structure according to this embodiment while ensuring the same breakdown voltage as that of the conventional thin film transistor having the GOLD structure.

Embodiment 5
Here, a thin film transistor provided with both a GOLD region and an LDD region is taken as an example. First, the manufacturing method will be described. The steps up to forming the gate insulating film 5 shown in FIG. 30 and injecting a predetermined impurity for controlling the threshold value of the thin film transistor are the same as those up to the step shown in FIG.

Next, as shown in FIG. 31, a resist pattern 62 is formed by performing predetermined photolithography. Next, using the resist pattern 62 as a mask, phosphorus is implanted into the polycrystalline silicon film at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. 32 through the same steps as those shown in FIGS. At this time, the resist pattern 66 for forming the gate electrode 6a planarly overlaps with the impurity regions 4ab and 4ac located across the impurity region 4aa to be a channel, and overlaps with the impurity region 4ac in a plane. The length is formed to be longer than the length overlapping the impurity region 4ab in plan view.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, phosphorus is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV, for example. Impurity regions 4ad and 4ae are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

  Thus, in the impurity region 4ab left after the formation of the impurity regions 4ad and 4ae, the portion of the impurity region (part A) that overlaps the gate electrode 6a in plan view overlaps with the gate electrode. There is a portion (part B) of the impurity region that is not to be removed.

  Here, if the part A is the impurity region 4ab and the part B is the impurity region 4af, the impurity region 4ab becomes the GOLD region 41 and the impurity region 4af becomes the LDD region 43. Similarly, for the remaining impurity region 4ac, the impurity region 4ac becomes the GOLD region 42 and the impurity region 4ag becomes the LDD region 44. The length G2 of the GOLD region 42 located on the drain side in the channel length direction is set to be longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure having an LDD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the length G2 of the GOLD region 42 located on the drain side in the channel length direction is longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction. Is set. Further, an LDD region 43 is formed between the GOLD region 41 and the source region 45, and an LDD region 44 is formed between the GOLD region 42 and the drain region 46.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. For the measurement, the gate width is 10 μm, the effective gate length is 5 μm, the overlap length G2 of the drain-side GOLD region 42 is 1.5 μm, the length L2 of the drain-side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the overlap length G1 of the GOLD region 41 on the source side is 0.5 μm, the length L1 in the channel length direction of the LLD region 43 on the source side is 0.3 μm, and the width of the gate electrode 6a in the channel length direction is 7 μm. Using.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 1 was also measured.

  FIG. 34 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 34, the source / drain breakdown voltage of the thin film transistor having the GOLD structure according to the present embodiment is higher than the breakdown voltage of the conventional thin film transistor having the GOLD structure and the breakdown voltage of the thin film transistor according to the first embodiment. It was confirmed that it was possible.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the thin film transistor having the GOLD structure according to the embodiment, the conventional thin film transistor having the GOLD structure, and the thin film transistor according to the first embodiment. As a result, in the thin film transistor having the GOLD structure according to the embodiment, the parasitic capacitance due to the GOLD regions 41 and 42 having different overlap lengths with the gate electrode 6a has the same overlap length with the gate electrode as in the conventional GOLD structure. It was estimated that it was lower than the parasitic capacitance of the thin film transistor and was at the same level as the parasitic capacitance of the thin film transistor according to Embodiment 1.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional GOLD structure thin film transistor can be secured and the parasitic capacitance can be greatly reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 6
In Embodiment 5, an n-channel thin film transistor is described as an example of a thin film transistor, but a p-channel thin film transistor is also formed over the glass substrate at the same time. Here, the main steps of the method for manufacturing a p-channel thin film transistor will be described.

First, after the step shown in FIG. 4, as shown in FIG. 35, a resist pattern 62 is formed by performing predetermined photolithography. Next, using the resist pattern 62 as a mask, boron is implanted into the polycrystalline silicon film at a dose of 5 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. At this time, the resist pattern 66 for forming the gate electrode 6a planarly overlaps with the impurity regions 4ab and 4ac located across the impurity region 4aa to be a channel, and overlaps with the impurity region 4ac in a plane. The length is formed to be longer than the length overlapping the impurity region 4ab in plan view.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, boron is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV, for example. Impurity regions 4ad and 4ae are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

  Thus, in the impurity region 4ab left after the formation of the impurity regions 4ad and 4ae, the portion of the impurity region (part A) that overlaps the gate electrode 6a in plan view overlaps with the gate electrode. There is a portion (part B) of the impurity region that is not to be removed.

  Here, if the part A is the impurity region 4ab and the part B is the impurity region 4af, the impurity region 4ab becomes the GOLD region 41 and the impurity region 4af becomes the LDD region 43. Similarly, for the remaining impurity region 4ac, the impurity region 4ac becomes the GOLD region 42 and the impurity region 4ag becomes the LDD region 44. The length G2 of the GOLD region 42 located on the drain side in the channel length direction is set to be longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure having an LDD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the length G2 of the GOLD region 42 located on the drain side in the channel length direction is longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction. Is set. Further, an LDD region 43 is formed between the GOLD region 41 and the source region 45, and an LDD region 44 is formed between the GOLD region 42 and the drain region 46.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. In the measurement, the gate width is 20 μm, the effective gate length is 5 μm, the overlap length G2 of the drain side GOLD region 42 is 1.5 μm, the length L2 of the drain side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the overlap length G1 of the GOLD region 41 on the source side is 0.5 μm, the length L1 in the channel length direction of the LLD region 43 on the source side is 0.3 μm, and the width of the gate electrode 6a in the channel length direction is 7 μm. Using.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 2 was also measured.

  FIG. 38 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 38, the source / drain breakdown voltage of the thin film transistor having the GOLD structure according to the present embodiment is higher than the breakdown voltage of the conventional thin film transistor having the GOLD structure and the breakdown voltage of the thin film transistor according to the second embodiment. It was confirmed that it was possible.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment, the conventional GOLD structure thin film transistor, and the thin film transistor according to the second embodiment. As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the parasitic capacitance due to the GOLD regions 41 and 42 having different overlap lengths with the gate electrode 6a has the same overlap length with the gate electrode. It was estimated that the parasitic capacitance of the thin film transistor was lower than that of the thin film transistor and the same level as the parasitic capacitance of the thin film transistor according to the second embodiment.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be greatly reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 7
Here, another example of a thin film transistor having both a GOLD region and an LDD region will be described. First, the manufacturing method will be described. The steps up to forming the gate insulating film 5 shown in FIG. 39 and injecting a predetermined impurity for controlling the threshold value of the thin film transistor are the same as those up to the step shown in FIG.

Next, as shown in FIG. 40, a resist pattern 62 is formed by performing predetermined photoengraving. Then, using resist pattern 62 as a mask, phosphorus is implanted into polycrystalline silicon film 4a at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. 41 through the same steps as those shown in FIGS. At this time, the resist pattern 66 for forming the gate electrode 6a is formed so as to planarly overlap one impurity region 4ac among the impurity regions 4ab and 4ac located across the impurity region 4aa serving as a channel. Has been.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, phosphorus is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV, for example. Impurity regions 4ad and 4ae are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

  In this way, in the impurity region 4ac left by the formation of the impurity regions 4ad and 4ae, the portion of the impurity region (part A) that overlaps the gate electrode 6a in plan view overlaps with the gate electrode. There is a portion (part B) of the impurity region that is not to be removed.

  Here, if the part A is the impurity region 4ac and the part B is the impurity region 4ag, the impurity region 4ac becomes the GOLD region 42 and the impurity region 4ag becomes the LDD region 44. A GOLD region is not formed on the source side.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the GOLD region 42 and the LDD region 44 are formed on the drain side, and are not formed on the source side.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. For the measurement, the gate width is 10 μm, the effective gate length is 5 μm, the overlap length G2 of the drain-side GOLD region 42 is 1.5 μm, the length L2 of the drain-side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the width of the gate electrode 6a in the channel length direction was 6.5 μm was used.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 1 was also measured.

  FIG. 43 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 43, the source / drain breakdown voltage of the thin film transistor having the GOLD structure according to the present embodiment is higher than the breakdown voltage of the conventional thin film transistor having the GOLD structure and the breakdown voltage of the thin film transistor according to the first embodiment. It was confirmed that it was possible.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the thin film transistor having the GOLD structure according to the embodiment, the conventional thin film transistor having the GOLD structure, and the thin film transistor according to the first embodiment. As a result, in the thin film transistor having the GOLD structure according to the embodiment, the GOLD region overlapping the gate electrode 6a is formed only on the drain side and not formed on the source side. It was estimated that the parasitic capacitance of the thin film transistor having the GOLD structure was reduced to about 50%. Further, it was estimated that the parasitic capacitance can be further reduced by not forming the GOLD region on the source side as compared with the thin film transistor according to the first embodiment.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be further reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 8
In Embodiment 7, an n-channel thin film transistor is described as an example of a thin film transistor, but a p-channel thin film transistor is also formed over the glass substrate at the same time. Here, the main steps of the method for manufacturing a p-channel thin film transistor will be described.

First, after the process shown in FIG. 4, as shown in FIG. 44, a resist pattern 62 is formed by performing predetermined photoengraving. Next, using resist pattern 62 as a mask, boron is implanted into polycrystalline silicon film 4a at a dose of 5 × 10 ¹³ atoms / cm ² and acceleration energy of 60 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. At this time, the resist pattern 66 for forming the gate electrode 6a is formed so as to planarly overlap one impurity region 4ac among the impurity regions 4ab and 4ac located across the impurity region 4aa serving as a channel. Has been.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, boron is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV, for example. Impurity regions 4ad and 4ae are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

  In this way, in the impurity region 4ac left by the formation of the impurity regions 4ad and 4ae, the portion of the impurity region (part A) that overlaps the gate electrode 6a in plan view overlaps with the gate electrode. There is a portion (part B) of the impurity region that is not to be removed.

  Here, if the part A is the impurity region 4ac and the part B is the impurity region 4ag, the impurity region 4ac becomes the GOLD region 42 and the impurity region 4ag becomes the LDD region 44. A GOLD region is not formed on the source side.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure is formed as shown in FIG.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. In the measurement, the gate width is 20 μm, the effective gate length is 5 μm, the overlap length G2 of the drain side GOLD region 42 is 1.5 μm, the length L2 of the drain side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the width of the gate electrode 6a in the channel length direction was 6.5 μm was used.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 2 was also measured.

  FIG. 47 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 47, the source / drain breakdown voltage of the thin film transistor having the GOLD structure according to the present embodiment is higher than the breakdown voltage of the conventional thin film transistor having the GOLD structure and the breakdown voltage of the thin film transistor according to the second embodiment. It was confirmed that it was possible.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the thin film transistor having the GOLD structure according to the embodiment, the conventional thin film transistor having the GOLD structure, and the thin film transistor according to the seventh embodiment. As a result, in the thin film transistor having the GOLD structure according to the embodiment, the GOLD region overlapping the gate electrode 6a is formed only on the drain side and not formed on the source side. It was estimated that the parasitic capacitance of the thin film transistor having the GOLD structure was reduced to about 50%. In addition, it was estimated that the parasitic capacitance of the thin film transistor according to the second embodiment could be reduced.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be further reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 9
Here, another example of a thin film transistor having both a GOLD region and an LDD region will be described. First, the manufacturing method will be described. The steps up to forming the gate insulating film 5 shown in FIG. 48 and injecting a predetermined impurity for controlling the threshold value of the thin film transistor are the same as those up to the step shown in FIG.

Next, as shown in FIG. 49, a resist pattern 62 is formed by performing predetermined photoengraving. Next, using the resist pattern 62 as a mask, phosphorus is implanted into the polycrystalline silicon film at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. At this time, the resist pattern 66 for forming the gate electrode 6a is formed so as to planarly overlap the impurity regions 4ab and 4ac. In particular, the channel between the resist pattern 66 and the impurity region 4ac located on the drain side is formed. The overlapping length in the long direction is formed to be longer than the overlapping length in the channel length direction between the resist pattern 66 and the impurity region 4ab located on the source side.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, phosphorus is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV, for example. Impurity regions 4ad and 4ae are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

Next, as shown in FIG. 51, using gate electrode 6a as a mask, for example, phosphorus is implanted into impurity regions 4ab and 4ac at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV to become an LDD region. Regions 4af and 4ag are formed.

  Thereby, the impurity region 4ab becomes the GOLD region 41 and the impurity region 4af becomes the LDD region 43 on the source side. On the drain side, the impurity region 4ac becomes the GOLD region 42, and the impurity region 4ag becomes the LDD region 44. The length G2 of the GOLD region 42 located on the drain side in the channel length direction is set to be longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the length G2 of the GOLD region 42 located on the drain side in the channel length direction is longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction. Is set. Further, an LDD region 43 is formed between the GOLD region 41 and the source region 45, and an LDD region 44 is formed between the GOLD region 42 and the drain region 46.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. For the measurement, the gate width is 10 μm, the effective gate length is 5 μm, the overlap length G2 of the drain-side GOLD region 42 is 1.5 μm, the length L2 of the drain-side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the overlap length G1 of the GOLD region 41 on the source side is 0.5 μm, the length L1 in the channel length direction of the LLD region 43 on the source side is 0.3 μm, and the width of the gate electrode 6a in the channel length direction is 7 μm. Using.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 1 was also measured.

  FIG. 53 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 53, it was confirmed that the source / drain breakdown voltage of the GOLD structure thin film transistor according to this embodiment is higher than the breakdown voltage of the conventional GOLD structure thin film transistor.

  Further, in comparison with the thin film transistor according to the first embodiment, it is confirmed that the source / drain breakdown voltage can be further improved by forming the LDD regions 42 and 43 in the thin film transistor having the GOLD structure according to the present embodiment. It was.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment and the conventional GOLD structure thin film transistor. As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the parasitic capacitance due to the GOLD regions 41 and 42 having different overlap lengths with the gate electrode 6a has the same overlap length with the gate electrode. It was estimated to be lower than the parasitic capacitance in the thin film transistor.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be further reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 10
In Embodiment 9, an n-channel thin film transistor is described as an example of a thin film transistor. Here, the main steps of the method for manufacturing a p-channel thin film transistor will be described.

  First, after the step shown in FIG. 4, as shown in FIG. 54, a resist pattern 62 is formed by performing predetermined photoengraving.

Next, using the resist pattern 62 as a mask, boron is implanted into the polycrystalline silicon film at a dose of 5 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. At this time, the resist pattern 66 is formed so as to planarly overlap the impurity regions 4ab and 4ac, and in particular, the overlap length in the channel length direction between the resist pattern 66 and the impurity region 4ac located on the drain side is the resist pattern 66. The pattern 66 and the impurity region 4ab located on the source side are formed to be longer than the overlapping length in the channel length direction.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, boron is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV, for example. Impurity regions 4ad and 4ae serving as drain regions are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

Next, as shown in FIG. 56, using gate electrode 6a as a mask, for example, boron is implanted into impurity regions 4ab and 4ac at a dose of 5 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV to become an LDD region. Regions 4af and 4ag are formed.

  Thereby, the impurity region 4ab becomes the GOLD region 41 and the impurity region 4af becomes the LDD region 43 on the source side. On the drain side, the impurity region 4ac becomes the GOLD region 42, and the impurity region 4ag becomes the LDD region 44. The length G2 of the GOLD region 42 located on the drain side in the channel length direction is set to be longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the length G2 of the GOLD region 42 located on the drain side in the channel length direction is longer than the length G1 of the GOLD region 41 located on the source side in the channel length direction. Is set. Further, an LDD region 43 is formed between the GOLD region 41 and the source region 45, and an LDD region 44 is formed between the GOLD region 42 and the drain region 46.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. In the measurement, the gate width is 20 μm, the effective gate length is 5 μm, the overlap length G2 of the drain side GOLD region 42 is 1.5 μm, the length L2 of the drain side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the overlap length G1 of the GOLD region 41 on the source side is 0.5 μm, the length L1 in the channel length direction of the LLD region 43 on the source side is 0.3 μm, and the width of the gate electrode 6a in the channel length direction is 7 μm. Using.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 2 was also measured.

  FIG. 58 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 58, it was confirmed that the source / drain breakdown voltage of the GOLD structure thin film transistor according to this embodiment is higher than the breakdown voltage of the conventional GOLD structure thin film transistor.

  Further, in comparison with the thin film transistor according to the second embodiment, it is confirmed that the source / drain breakdown voltage can be further improved by forming the LDD regions 42 and 43 in the thin film transistor having the GOLD structure according to the present embodiment. It was.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment and the conventional GOLD structure thin film transistor. As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the parasitic capacitance due to the GOLD regions 41 and 42 having different overlap lengths with the gate electrode 6a has the same overlap length with the gate electrode. It was estimated to be lower than the parasitic capacitance in the thin film transistor.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be further reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 11
Here, still another example of a thin film transistor having both a GOLD region and an LDD region will be given. First, the manufacturing method will be described. The steps up to forming the gate insulating film 5 shown in FIG. 59 and injecting a predetermined impurity for controlling the threshold value of the thin film transistor are the same as those up to the step shown in FIG.

Next, as shown in FIG. 60, a resist pattern 62 is formed by performing predetermined photoengraving. Next, using the resist pattern 62 as a mask, phosphorus is implanted into the polycrystalline silicon film 4a at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, through the same steps as those shown in FIGS. 7 to 9, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. At this time, the resist pattern 66 is formed so as to planarly overlap with the impurity region 4ac located on the drain side of the impurity regions 4ab and 4ac and not to overlap with the impurity region 4ab.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 left, using the resist pattern 66 as a mask, phosphorus is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 60 KeV, for example. Impurity regions 4ad and 4ae serving as regions are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

Next, as shown in FIG. 62, using gate electrode 6a as a mask, phosphorus is implanted into impurity regions 4ab and 4ac at a dose of 1 × 10 ¹³ atoms / cm ² and acceleration energy of 60 KeV, for example, to become an LDD region. Regions 4af and 4ag are formed.

  Thereby, on the source side, the impurity region 4af becomes the LDD region 43, and the GOLD region is not formed. On the drain side, the impurity region 4ac becomes the GOLD region 42, and the impurity region 4ag becomes the LDD region 44.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the GOLD region 42 is formed on the drain side, and the GOLD region is not formed on the source side. An LDD region 43 is formed between the source region 45 and the channel region 40, and an LDD region 44 is formed between the GOLD region 42 and the drain region 46.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. For the measurement, the gate width is 10 μm, the effective gate length is 5 μm, the overlap length G2 of the drain-side GOLD region 42 is 1.5 μm, the length L2 of the drain-side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the width of the gate electrode 6a in the channel length direction was 6.5 μm was used.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 1 was also measured.

  FIG. 64 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 64, it was confirmed that the source / drain breakdown voltage of the GOLD structure thin film transistor according to this embodiment is higher than the breakdown voltage of the conventional GOLD structure thin film transistor and the breakdown voltage of the thin film transistor described in Embodiment 1. It was.

  Next, the parasitic capacitance was estimated by actually observing the respective shapes of the thin film transistor having the GOLD structure according to the present embodiment, the thin film transistor according to the first embodiment, and the conventional thin film transistor having the GOLD structure.

  As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the parasitic capacitance due to the GOLD region 42 is reduced to about 50% of the parasitic capacitance in the conventional thin film transistor having the GOLD structure having the same overlap length with the gate electrode. It was estimated that Further, in comparison with the thin film transistor according to Embodiment 1, it was estimated that the parasitic capacitance was further reduced.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be further reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 12
In Embodiment 11, an n-channel thin film transistor is described as an example of a thin film transistor. Here, the main steps of the method for manufacturing a p-channel thin film transistor will be described.

  First, after the step shown in FIG. 4, as shown in FIG. 65, a predetermined photoengraving is performed to form a resist pattern 62.

Next, using resist pattern 62 as a mask, boron is implanted into polycrystalline silicon film 4a at a dose of 5 × 10 ¹³ atoms / cm ² and acceleration energy of 60 KeV, for example, thereby forming impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Impurity region 4aa serving as a channel is formed between impurity region 4ab and impurity region 4ac. Thereafter, the resist pattern 62 is removed by performing ashing and chemical treatment.

  Thereafter, the gate electrode 6a is formed on the gate insulating film 5 as shown in FIG. 66 through the same steps as those shown in FIGS. At this time, the resist pattern 66 is formed so as to planarly overlap with the impurity region 4ac located on the drain side of the impurity regions 4ab and 4ac and not to overlap with the impurity region 4ab.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist pattern 66 remaining, using this resist pattern 66 as a mask, boron is implanted into the impurity regions 4ab and 4ac at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV, for example. Impurity regions 4ad and 4ae are formed. Thereafter, the resist pattern 66 is removed by performing ashing and chemical treatment.

Next, as shown in FIG. 67, using gate electrode 6a as a mask, for example, boron is implanted into impurity regions 4ab and 4ac at a dose of 5 × 10 ¹³ atoms / cm ² and an acceleration energy of 60 KeV to become an LDD region. Regions 4af and 4ag are formed.

  Thereby, on the source side, the impurity region 4af becomes the LDD region 43, and the GOLD region is not formed. On the drain side, the impurity region 4ac becomes the GOLD region 42, and the impurity region 4ag becomes the LDD region 44.

  Thereafter, through a process similar to the process shown in FIGS. 11 to 13 described above, a thin film transistor having a GOLD structure is formed as shown in FIG.

  In the thin film transistor having the GOLD structure formed as described above, the GOLD region 42 is formed on the drain side, and the GOLD region is not formed on the source side. An LDD region 43 is formed between the source region 45 and the channel region 40, and an LDD region 44 is formed between the GOLD region 42 and the drain region 46.

  Next, the results of measuring the source / drain breakdown voltage of the above-described thin film transistor will be described. In the measurement, the gate width is 20 μm, the effective gate length is 5 μm, the overlap length G2 of the drain side GOLD region 42 is 1.5 μm, the length L2 of the drain side LDD region 44 in the channel length direction is 0.3 μm, A thin film transistor in which the width of the gate electrode 6a in the channel length direction was 6.5 μm was used.

  On the other hand, for comparison, measurement was performed using a conventional GOLD structure thin film transistor in which the overlap length of the GOLD region on the drain side and the overlap length of the GOLD region on the source side were the same. In addition, the thin film transistor described in Embodiment 3 was also measured.

  FIG. 69 shows the measurement results of the source / drain breakdown voltage. Measurement conditions and the like are the same as those described above. As shown in FIG. 69, it is confirmed that the source / drain breakdown voltage of the GOLD structure thin film transistor according to the present embodiment is higher than the breakdown voltage of the conventional GOLD structure thin film transistor and the breakdown voltage of the thin film transistor described in Embodiment 2. It was.

  Next, the parasitic capacitance was estimated by actually observing the shapes of the GOLD structure thin film transistor according to the present embodiment, the conventional GOLD structure thin film transistor, and the thin film transistor according to the second embodiment.

  As a result, in the thin film transistor having the GOLD structure according to the present embodiment, the parasitic capacitance due to the GOLD region 42 is reduced to about 50% of the parasitic capacitance in the conventional thin film transistor having the GOLD structure having the same overlap length with the gate electrode. It was estimated that Further, in comparison with the thin film transistor according to the second embodiment, it was estimated that the parasitic capacitance is further reduced.

  Thus, it was confirmed that the withstand voltage higher than the withstand voltage of the conventional thin film transistor with the GOLD structure can be secured and the parasitic capacitance can be further reduced in the thin film transistor with the GOLD structure according to the present embodiment.

Embodiment 13
Here, a liquid crystal display device is described as an example of a semiconductor device including a thin film transistor. First, the structure of the liquid crystal display device will be described.

  As shown in FIG. 70, the liquid crystal display device has a scanning line for controlling the operation of the display unit 21 for displaying an image and the pixel portion thin film transistor 23 provided in each of the plurality of pixels 22 constituting the display unit 21. A drive circuit unit 28 and a data line drive circuit unit 30 are provided.

  The pixels 22 are arranged in an array on the display unit 21. In the pixel 22, a liquid crystal (not shown) is filled between the pixel electrode 24 and a counter electrode (not shown) to form a pixel capacitor (not shown). The voltage applied to the liquid crystal is determined by the voltage applied between the pixel electrode 24 and the counter electrode. The alignment state of the liquid crystal is changed by the voltage applied to the liquid crystal, and the intensity of light transmitted through the liquid crystal is controlled. A storage capacitor 25 is formed between the pixel portion thin film transistor 23 and the common electrode 26.

  Data lines 29 connected to the data line drive circuit unit 30 and scanning lines 27 connected to the scan line drive circuit unit 28 are connected to the pixels 22 arranged in an array. A pixel signal is output from the data line driving circuit unit 30, and the output pixel signal is input to the pixel 22 through the data line 29. A pixel selection signal is output from the scanning line driving circuit unit 28, and the output pixel selection signal is input to the pixel 22 through the scanning line 27.

  The scanning line driving circuit unit 28 is mainly configured by including a shift register and an output circuit, and shifts the register by an input clock signal. If the register is at a high (H) level, the output circuit is switched to the ON voltage of the pixel 22. On the other hand, if the register is at the low (L) level, the output circuit is switched to the OFF voltage of the pixel 22. In this way, the scanning line driving circuit unit 28 sequentially applies an ON voltage and an OFF voltage to the scanning lines of the pixels 22.

  The data line driving circuit unit 30 sequentially latches input pixel data signals (for example, 6-bit pixel data) in accordance with the timing of the clock signal, and takes them into the data line driving circuit unit 30. The captured pixel data is converted into an analog signal by a DA converter in the data line drive circuit unit 30. The pixel data converted into the analog signal is sent to the data line 29.

  When sending an analog signal to the data line 29, the frequency of the analog signal increases when the data signal is sent to each data line sequentially (dot sequential method). For this reason, a method of sending pixel data in parallel to several data lines 29 (line sequential method) is usually employed to prevent the frequency from becoming high.

  The gate of the pixel portion thin film transistor 23 of the pixel 22 is controlled by a signal sent from the scanning line 27. When an ON signal is input to the gate and the gate of the pixel thin film transistor is turned on, a signal sent from the data line 29 is accumulated in the pixel capacitor and the storage capacitor 25. The accumulated signal is held in the pixel capacitor and the holding capacitor for one frame until the screen is rewritten after the gate is turned off.

  At this time, when a leak current is generated in the pixel thin film transistor, the voltage applied to the liquid crystal decreases with the holding time, and the display quality in the display unit 21 is deteriorated. For this reason, the pixel thin film transistor of the display unit 21 is required to reduce the leakage current as much as possible.

  The selection signal input to the gate is output from the scanning line driving circuit unit 28. In order to input a selection signal to the gate, it is necessary to charge all the gate capacitances of the pixel thin film transistors connected to the gate. Since many pixels 22 are connected to the gate, the capacity to be charged becomes extremely large. Therefore, in order to charge these capacitors, the scanning line driving circuit unit 28 is required to have a high driving capability and a high ON current.

  Since the pixel signal output from the data line driving circuit is sequentially output to each data line while the gate is selected, the frequency of the pixel signal is significantly faster than the selection signal. For this reason, the data line driving circuit unit 30 is required to have a high operating speed.

  In addition, in order to write a pixel signal sent from the data line driving circuit unit 30 to the pixel 22, it is necessary to charge a stray capacitance represented by a stray capacitance with the gate line in addition to the pixel capacitance and the holding capacitance. is there. Therefore, a high driving capability is required for the data line driving circuit. Thus, the data line driving circuit is required to have a high operating speed, a high driving capability, and a high on-current.

  As described above, the required characteristics of the pixel 22, the scanning line driving circuit unit 28, and the data line driving circuit unit 30 are different. Therefore, a method for manufacturing a liquid crystal display device including different types of thin film transistors including a thin film transistor having a GOLD structure to cope with such different characteristics will be described next.

  First, the silicon nitride film 2 and the silicon oxide film 3 are formed on the glass substrate 1 in the same manner as described in the first embodiment. An island-like polycrystalline silicon film is formed on each silicon oxide film 2 located in predetermined regions R1 to R3 where thin film transistors are formed on the glass substrate 1 (see FIG. 71). In the regions R1 to R3, different types of thin film transistors are formed.

A gate insulating film 5 made of a silicon oxide film is formed so as to cover the polycrystalline silicon film. Next, as shown in FIG. 71, in order to control the threshold value of the thin film transistor, boron is implanted into the polycrystalline silicon film at a dose of 1 × 10 ¹² atoms / cm ² and an acceleration energy of 60 KeV, for example. A shaped impurity region 4aa is formed.

  Next, as shown in FIG. 72, by performing predetermined photoengraving, a resist pattern 62a for forming a thin film transistor having an n-type GOLD structure is formed in the region R1, and a thin film transistor having an n-type LDD structure is formed. In the region R2 and the region R3 where the normal P-type thin film transistor is formed, a resist pattern 62b covering these regions R2 and R3 is formed.

Using resist patterns 62a and 62b as masks, for example, phosphorus is implanted into impurity region 4aa at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV to form impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Thereafter, the resist patterns 62a and 62b are removed by performing ashing and chemical treatment.

  Next, a chromium film (not shown) having a film thickness of about 200 nm is formed on the entire surface of the gate insulating film 5 by sputtering. Next, by performing predetermined photoengraving, a resist pattern 63b for patterning the gate electrode is formed in the region R3, and a resist pattern 63a covering the region R1 and the region R2 is formed (FIG. 73). reference).

  Next, as shown in FIG. 73, the chromium film is wet-etched using the resist patterns 63a and 63b as masks, thereby forming the gate electrode 6a in the region R3. Further, the chromium film 6b covering the region R1 and the region R2 is left. Thereafter, the resist patterns 63a and 63b are removed by performing ashing and chemical treatment.

Next, as shown in FIG. 74, using the remaining chromium film 6b and gate electrode 6a as a mask, boron is implanted, for example, at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV. Impurity regions 4 a a and 4 ae are formed in the impurity region 4 aa located at the source region and drain region of the p-type thin film transistor. At this time, since the regions R1 and R2 are covered with the chromium film 6b, boron is not implanted into these regions R1 and R2.

  Next, as shown in FIG. 75, resist patterns 66a and 66b for patterning the gate electrode are formed in regions R1 and R2 by performing predetermined photoengraving, and this region R3 is formed in region R3. A resist pattern 66c is formed to cover the pattern.

  At this time, the resist pattern 66a is formed so as to planarly overlap the impurity regions 4ab and 4ac. In particular, the overlapping length in the channel length direction between the resist pattern 66a and the impurity region 4ac located on the drain side The pattern 66a and the impurity region 4ab located on the source side are formed to be longer than the overlapping length in the channel length direction. A portion where the resist pattern 66a and the impurity regions 4ab and 4ac overlap in a plane is a GOLD region.

  By etching the chromium film 6b using the resist patterns 66a, 66b, and 66c as a mask, the gate electrodes 6a are formed in the regions R1 and R2, respectively. At this time, the gate electrode 6a formed in the region R3 is not etched because it is covered with the resist pattern 66c.

  Note that, by performing wet etching, etching is performed on the side surface of the chromium film serving as the gate electrode, but the etching amount can be controlled by the time for performing overetching.

With the resist patterns 66a, 66b and 66c remaining, using the resist patterns 66a, 66b and 66c as a mask, for example, phosphorus is implanted at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV. Impurity regions 4ab and 4ac located in the region R1 are formed with an impurity region 4ad serving as a source region and an impurity region 4ae serving as a drain region of a thin film transistor having an n-type GOLD structure, respectively.

  In the region (impurity region) 4aa located in the region R2, an impurity region 4ad serving as a source region and an impurity region 4ae serving as a drain region of a thin film transistor having an n-type LDD structure are formed. At this time, since the region R3 is covered with the resist pattern 66c, phosphorus is not implanted into the region R3. Thereafter, the resist patterns 66a, 66b, and 66c are removed by performing ashing and chemical treatment.

Next, as shown in FIG. 76, by using the gate electrode 6a as a mask, for example, phosphorus is implanted at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV, thereby remaining impurities located in the region R1. In the regions 4ab and 4ac, an impurity region 4af serving as a source-side LDD region and an impurity region 4ag serving as a drain-side LDD region of a thin film transistor having an n-type GOLD structure are formed, respectively.

  In the remaining impurity regions 4ab and 4ac located in the region R2, an impurity region 4af serving as a source-side LDD region and an impurity region 4ag serving as a drain-side LDD region of an n-type LDD thin film transistor are respectively provided. It is formed.

  At this time, phosphorus is also implanted into the impurity regions 4ad and 4ae into which boron serving as the source region and drain region of the p-type thin film transistor located in the region 3 is implanted. Therefore, the implantation of phosphorus into the impurity regions 4ad and 4ae located in the region 3 is not a problem.

  Thereafter, in the same manner as described in the first embodiment, an interlayer insulating film 7 made of a silicon oxide film is formed on the glass substrate 1 as shown in FIG. Next, a predetermined photolithography process is performed on the interlayer insulating film 7 to form a resist pattern (not shown) for forming contact holes.

By using the resist pattern as a mask, the interlayer insulating film 7 and the gate insulating film 5 are subjected to anisotropic etching to expose the surface of the impurity region 4ad located in each of the regions R1 to R3 and the impurity region 4ae. Next, a contact hole 7b exposing the surface of each is formed. Next, a laminated film (not shown) of a chromium film and an aluminum film is formed on the interlayer insulating film 7 so as to fill the contact holes 7a and 7b. Is done. A resist pattern (not shown) for forming electrodes is formed by performing a predetermined photolithography process on the laminated film. By performing wet etching using the resist pattern as a mask, the source electrode 8a and the drain electrode 8b are formed in each of the regions R1 to R3.

  As described above, the thin film transistor T1 having the n-type GOLD structure is formed in the region R1, the thin film transistor T2 having the n-type LDD structure is formed in the region R2, and the normal p-type thin film transistor T3 is formed in the region R3.

  In the thin film transistor T1 having the n-type GOLD structure, the impurity region 4ad becomes the source region 45, the impurity region 4ae becomes the drain region 46, the impurity regions 4ab and 4ac become the GOLD regions 41 and 42, and the impurity regions 4af and 4ag become the LDD region 43, 44. In particular, in the GOLD regions 41 and 42, the length in the channel length direction of the GOLD region 42 located on the drain side is set to be longer than the length in the channel length direction of the GOLD region 41 located on the source side. .

  In the thin film transistor T2 having the n-type LDD structure, the impurity region 4ad becomes the source region 45, the impurity region 4ae becomes the drain region 46, and the impurity regions 4af and 4ag become the LDD regions 43 and 44, respectively. In the p-type thin film transistor T3, the impurity region 4ad becomes the source region 45, and the impurity region 4ae becomes the drain region 46.

  In the above-described liquid crystal display device, the thin film transistor having the GOLD structure and the thin film transistor having the LDD structure are appropriately arranged based on a predetermined layout in accordance with each characteristic. For example, a thin film transistor having a GOLD structure is employed in a circuit portion that requires an ON current, such as a liquid crystal driving circuit. An LDD-structured thin film transistor is employed in a circuit portion that requires a relatively low off current, such as a pixel thin film transistor.

  The size of the thin film transistor having the LDD structure is smaller than that of the thin film transistor having the GOLD structure. Therefore, by appropriately disposing the thin film transistor having the LDD structure, it is possible to suppress an increase in the area occupied by the circuit portion in the liquid crystal display device.

  Here, the occupied area of the gate portion of the thin film transistor having the GOLD structure and the thin film transistor having the LDD structure is specifically compared. First, the gate width of a thin film transistor having a GOLD structure is 10 μm, the effective gate length is 5 μm, the overlap length of the GOLD region 42 on the drain side is 1.5 μm, and the length in the channel length direction of the LDD region 44 on the drain side is 0.3 μm. The overlap length of the source side GOLD region 41 is 0.5 μm, the length of the source side LDD region 44 in the channel length direction is 0.3 μm, and the width of the gate electrode 6a in the channel length direction is 7 μm.

  On the other hand, the gate width of the LDD-structured thin film transistor is 10 μm, the effective gate length is 5 μm, and the length of the drain side LDD region 44 and the source side LDD region 44 in the channel length direction is 0.3 μm.

In this case, as shown in FIG. 78, the gate occupied area of the thin film transistor of the GOLD structure according to the present invention is about 70 μm ² , whereas the occupied area of the thin film transistor of the conventional LDD structure is about 50 μm ² . It can be seen that the gate occupation area of the LDD thin film transistor is about 70% of the gate occupation area of the GOLD thin film transistor.

  In the liquid crystal display device, in particular, the area occupied by the logic circuit portion is relatively large. Thus, by employing an LDD-structured thin film transistor for the logic circuit portion, an increase in the area occupied by the circuit portion can be minimized.

  As described above, in a liquid crystal display device, the capability of the liquid crystal display device is maximized by appropriately disposing a GOLD structure thin film transistor or an LDD structure thin film transistor so as to meet current characteristics required for each circuit portion. As a result, the increase in the area occupied by the circuit portion can be minimized.

  Further, in the above-described manufacturing method of the liquid crystal display device, the GOLD structure thin film transistor is replaced with another type of different LDD structure by adding only one mask for forming a resist pattern (FIG. 72) serving as an implantation mask. The thin film transistor and a normal thin film transistor can be formed at the same time.

Embodiment 14
Here, another liquid crystal display device including different kinds of thin film transistors including a thin film transistor having a GOLD structure is taken as an example. First, the manufacturing method will be described. Through steps similar to those shown in FIG. 71 described above, as shown in FIG. 79, island-shaped impurity regions 4aa for forming different types of thin film transistors are formed in regions R1 to R3.

  Next, as shown in FIG. 80, by performing predetermined photoengraving, a resist pattern 62a for forming a thin film transistor having an n-type GOLD structure is formed in region R1, and an n-type SD (Single Drain) structure is formed. In the region R2 where the thin film transistor is formed and the region R3 where the normal P-type thin film transistor is formed, a resist pattern 62b covering these regions R2 and R3 is formed.

Using resist patterns 62a and 62b as masks, for example, phosphorus is implanted into impurity region 4aa at a dose of 1 × 10 ¹³ atoms / cm ² and an acceleration energy of 80 KeV to form impurity regions 4ab and 4ac. This injection amount becomes the injection amount in the GOLD region. Thereafter, the resist patterns 62a and 62b are removed by performing ashing and chemical treatment.

  Next, a chromium film (not shown) having a film thickness of about 200 nm is formed on the entire surface of the gate insulating film 5 by sputtering. Next, by performing predetermined photoengraving, a resist pattern 63b for patterning the gate electrode is formed in the region R3, and a resist pattern 63a covering the region R2 is formed in the regions R1 and R2. 81).

  Next, as shown in FIG. 81, wet etching is performed on the chromium film using the resist patterns 63a and 63b as masks, whereby the gate electrode 6a is formed in the region R3. Further, the chromium film 6b covering the region R1 and the region R2 is left. Thereafter, the resist patterns 63a and 63b are removed by performing ashing and chemical treatment.

Next, as shown in FIG. 82, using the remaining chromium film 6b and gate electrode 6a as a mask, boron is implanted at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration energy of 60 KeV, for example. Impurity regions 4 a a and 4 ae are formed in the impurity region 4 aa located at the source region and drain region of the p-type thin film transistor. At this time, since the regions R1 and R2 are covered with the chromium film 6b, boron is not implanted into these regions R1 and R2.

  Next, as shown in FIG. 83, resist patterns 66a and 66b for patterning the gate electrode are formed in the regions R1 and R2 by performing predetermined photolithography, and in the region R3, the region R3 is formed. A covering resist pattern 66c is formed.

  At this time, the resist pattern 66a is formed so as to planarly overlap the impurity regions 4ab and 4ac. In particular, the overlapping length in the channel length direction between the resist pattern 66a and the impurity region 4ac located on the drain side The pattern 66a and the impurity region 4ab located on the source side are formed to be longer than the overlapping length in the channel length direction. A portion where the resist pattern 66a and the impurity regions 4ab and 4ac overlap in a plane is a GOLD region.

  By etching the chromium film 6b using the resist patterns 66a, 66b, and 66c as a mask, the gate electrodes 6a are formed in the regions R1 and R2, respectively. At this time, the gate electrode 6a formed in the region R3 is not etched because it is covered with the resist pattern 66c. Thereafter, the resist patterns 66a, 66b, and 66c are removed by performing ashing and chemical treatment.

Next, as shown in FIG. 84, a resist pattern 67 covering the R3 region is formed by performing a predetermined photoengraving process. Next, by using the gate electrode 6a and the resist pattern 67 as a mask, for example, phosphorus is implanted at a dose of 1 × 10 ¹⁴ atoms / cm ² and an acceleration energy of 80 KeV, thereby leaving the remaining impurity regions 4ab located in the region R1, In the portion 4ac, an impurity region 4ad serving as a source region and an impurity region 4ae serving as a drain region of a thin film transistor having an n-type GOLD structure are formed.

  In the remaining impurity regions 4ab and 4ac located in the region R2, an impurity region 4ad serving as a source region and an impurity region 4ae serving as a drain region of an n-type SD thin film transistor are formed, respectively. At this time, since the region R3 is covered with the resist pattern 67, phosphorus is not implanted into the region R3. Thereafter, the resist pattern 67 is removed by performing ashing and chemical treatment.

  Thereafter, through a process similar to the process shown in FIG. 77 described above, interlayer insulating film 7 made of a silicon oxide film is formed on glass substrate 1 as shown in FIG. A contact hole 7a exposing the surface of the impurity region 4ad located in R3 and a contact hole 7b exposing the surface of the impurity region 4ae are formed. A source electrode 8a and a drain electrode 8b are formed in each of the regions R1 to R3 so as to fill the contact holes 7a and 7b.

  As described above, the thin film transistor T4 having the n-type GOLD structure is formed in the region R1, the thin film transistor T5 having the n-type SD structure is formed in the region R2, and the normal p-type thin film transistor T6 is formed in the region R3.

  In the thin film transistor T4 having the n-type GOLD structure, the impurity region 4ad becomes the source region 45, the impurity region 4ae becomes the drain region 46, and the impurity regions 4ab and 4ac become the GOLD regions 41 and 42. In particular, in the GOLD regions 41 and 42, the length in the channel length direction of the GOLD region 42 located on the drain side is set to be longer than the length in the channel length direction of the GOLD region 41 located on the source side. .

  In the n-type SD thin film transistor T5, the impurity region 4ad becomes the source region 45, and the impurity region 4ae becomes the drain region 46. In the p-type thin film transistor T6, the impurity region 4ad becomes the source region 45, and the impurity region 4ae becomes the drain region 46.

  In the above-described liquid crystal display device, the thin film transistor having the GOLD structure and the thin film transistor having the SD structure are appropriately arranged based on a predetermined layout in accordance with each characteristic. For example, a thin film transistor having an SD structure is employed in a circuit portion that does not require a withstand voltage such as a logic circuit. In addition, a thin film transistor having a GOLD structure is employed in a circuit portion that requires a withstand voltage, such as a liquid crystal driving circuit or a pixel portion (thin film transistor).

Moreover, the size of the thin film transistor S D structure as compared with the thin film transistor of the GOLD structure is small. Therefore, it is possible to suppress by proper placement of the thin film transistor S D structure, minimizing to increase the area occupied by the circuit portion in a liquid crystal display device.

  Here, the occupied area of the gate portion of the thin film transistor having the GOLD structure and the thin film transistor having the SD structure is specifically compared. First, the gate width of a thin film transistor having a GOLD structure is 10 μm, the effective gate length is 5 μm, the overlap length of the GOLD region 42 on the drain side is 1.5 μm, the overlap length of the GOLD region 41 on the source side is 0.5 μm, and the channel length The width of the gate electrode 6a in the direction is 7 μm. On the other hand, the gate width of the thin film transistor having the SD structure is 10 μm and the effective gate length is 5 μm.

In this case, as shown in FIG. 86, the gate occupied area of the GOLD structure thin film transistor according to the present invention is about 70 μm ² , whereas the conventional SD structure thin film transistor has an area occupied about 50 μm ² . It can be seen that the gate occupation area of the thin film transistor having the SD structure is about 70% of the gate occupation area of the thin film transistor having the GOLD structure.

  In the liquid crystal display device, in particular, the area occupied by the logic circuit portion is relatively large. Therefore, by adopting an SD structure thin film transistor in the logic circuit portion, an increase in the area occupied by the circuit portion can be minimized.

  As described above, in a liquid crystal display device, the performance of the liquid crystal display device is maximized by appropriately arranging a thin film transistor having a GOLD structure or a thin film transistor having an SD structure so as to meet the breakdown voltage characteristics required for each circuit portion. As a result, the increase in the area occupied by the circuit portion can be minimized.

  Further, in the above-described method for manufacturing a liquid crystal display device, a thin film transistor having a GOLD structure can be replaced with another type of LDD structure by adding only one mask for forming a resist pattern (FIG. 80) serving as an implantation mask. The thin film transistor and a normal thin film transistor can be formed at the same time.

  In the liquid crystal display device described in the thirteenth and fourteenth embodiments, the thin film transistor having the GOLD region on both the source side and the drain side is described as an example of the thin film transistor having the GOLD structure. A thin film transistor including a GOLD region may be employed.

  Further, in the region 3, the case where a normal p-type thin film transistor is formed has been described as an example. However, an LDD structure thin film transistor, a GOLD structure thin film transistor, or a structure in which an LDD structure and a GOLD structure are combined as necessary. A thin film transistor may be formed. Thereby, the breakdown voltage of the p-type thin film transistor can be improved.

  In each of the above embodiments, a thin film transistor having a so-called planar structure in which a gate electrode is formed on a semiconductor layer in which a source region, a drain region, and the like are formed as a thin film transistor with a gate insulating film interposed therebetween is taken as an example. explained.

  The thin film transistor having a GOLD structure according to the present invention is not limited to such a thin film transistor having a planar structure, and a so-called reverse staggered structure in which a semiconductor layer serving as a source region and a drain region is formed on a gate electrode with a gate insulating film interposed therebetween. A thin film transistor having a structure may be used.

  In such a thin film transistor having an inverted stagger structure, a portion where the plane including one side portion of the gate electrode intersects the semiconductor layer and the channel region overlaps with the gate electrode facing one GOLD region. Than the GOLD length in the channel length direction (first overlap length), the gate electrode and the other GOLD region face each other from the portion where the plane including the other side of the gate electrode intersects the semiconductor layer to the channel region. Since the GOLD length (second overlap length) in the channel length direction of the overlapping portion is increased, the source / drain breakdown voltage is impaired as in the case of the planar type thin film transistor. Therefore, the parasitic capacitance of the thin film transistor can be reduced.

  In such an inverted staggered thin film transistor, a gate electrode is formed first, and a semiconductor layer is formed on the gate electrode with a gate insulating film interposed therebetween. Then, a predetermined implantation mask such as a resist pattern is formed on the semiconductor layer in relation to the position of the gate electrode, and ion implantation is performed, so that a predetermined GOLD region, LDD is formed in the same manner as a planar thin film transistor. A region, a source region, and a drain region are formed.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 glass substrate, 2 silicon nitride film, 3 silicon oxide film, 4 amorphous silicon film, 4aa, 4ab, 4ac, 4ad, 4ae, 4af, 4ag impurity region, 5 gate insulating film, 6 chromium film, 6a gate electrode, 7 Interlayer insulating film, 7a, 7b Contact hole, 8a Source electrode, 8b Drain electrode, 21 Display part, 22 Pixel, 23 Pixel part Thin film transistor, 24 Pixel electrode, 25 Storage capacitor, 26 Common electrode, 27 Scan line, 28 Scan line Drive circuit section, 29 data lines, 30 data line drive circuit sections, 40 channel region, 41, 42 GOLD region, 43, 44 LDD region, 45 source region, 46 drain region.

Claims (6)

A semiconductor device including a plurality of semiconductor elements formed on a predetermined substrate having a semiconductor layer, an insulating film, and an electrode,
The semiconductor element is
A first impurity region formed in the semiconductor layer and having a predetermined impurity concentration;
A second impurity region formed in the semiconductor layer at a distance from the first impurity region and having a predetermined impurity concentration;
A channel having a predetermined channel length formed in the portion of the semiconductor layer located between the first impurity region and the second impurity region and spaced apart from the first impurity region and the second impurity region. A channel region to be
A third impurity region formed in contact with the channel region at a portion of the semiconductor layer located between the first impurity region and the channel region, and having an impurity concentration lower than that of the first impurity region;
A fourth impurity region formed in contact with the channel region at a portion of the semiconductor layer located between the second impurity region and the channel region and having an impurity concentration lower than that of the second impurity region; Comprising a first element;
In the first element,
The electrode has one side portion and the other side portion facing each other, and is formed to overlap the entire channel region, the entire third impurity region, and the entire fourth impurity region. ,
Before Kize' Enmaku is formed between the semiconductor layer and the electrode in contact respectively with the electrode and the semiconductor layer,
The first overlap length in the channel length direction of the portion where the electrode and the third impurity region overlap each other from the portion where the plane including the one side portion intersects the semiconductor layer to the channel region In addition, the second portion in the channel length direction of the portion where the electrode and the fourth impurity region overlap each other from the portion where the plane including the other side portion intersects the semiconductor layer to the channel region is opposed. It is formed so that the overlap length is long,
The semiconductor element further includes:
A fifth impurity region formed in the semiconductor layer and having a predetermined impurity concentration;
A sixth impurity region formed in the semiconductor layer at a distance from the fifth impurity region and having a predetermined impurity concentration;
A channel formed in the semiconductor layer located between the fifth impurity region and the sixth impurity region so as to be in contact with each of the fifth impurity region and the sixth impurity region, and having a predetermined channel length; A second element having a single drain structure having a channel region,
A seventh impurity region formed in the semiconductor layer and having a predetermined impurity concentration;
An eighth impurity region formed in the semiconductor layer at a distance from the seventh impurity region and having a predetermined impurity concentration;
A channel formed in the semiconductor layer located between the seventh impurity region and the eighth impurity region so as to be in contact with each of the seventh impurity region and the eighth impurity region, and having a predetermined channel length; A third element having a channel region comprising:
In the second element,
The electrode has one side portion and the other side portion facing each other, and is formed so as to overlap with the entire channel region,
The junction between the fifth impurity region and the channel region and the one side are located on substantially the same plane, and the junction between the sixth impurity region and the channel region and the other side are substantially on the same plane. Formed on the top,
In the single drain structure, only the fifth impurity region becomes a source region, only the sixth impurity region becomes a drain region,
In the third element,
The electrode has one side portion and the other side portion facing each other, and is formed so as to overlap with the entire channel region,
The junction between the seventh impurity region and the channel region and the one side are located on substantially the same plane, and the junction between the eighth impurity region and the channel region and the other side are substantially on the same plane. Formed on the top,
The semiconductor device, wherein conductivity types of impurities contained in the seventh impurity region and the eighth impurity region are different from those of impurities contained in the fifth impurity region and the sixth impurity region.   The semiconductor device according to claim 1, wherein the second overlap length is not less than 0.5 μm and not more than 2.5 μm.   The semiconductor device according to claim 1, wherein a length of the first overlap length is 1.0 μm or less.   The semiconductor device according to claim 1, wherein a difference between the length of the first overlap length and the length of the second overlap length is 0.6 μm or more.   The semiconductor device according to claim 1, wherein the semiconductor layer is one of polycrystalline silicon and amorphous silicon.   The semiconductor device according to claim 1, wherein the substrate includes a glass substrate.

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