JP2002083973A - Thin film transistor, its manufacturing method, and liquid crystal display device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor improved in performance and reliability by suppressing the OFF current (photoconductive current) when the channel region of the transistor is irradiated with light. SOLUTION: The thin film transistor has a polysilicon semiconductor layer on which a channel region and source and drain regions arranged on both sides of the channel region are formed. A depletion layer is formed between the channel region and drain region so that the width of the depletion layer may have a proportional relation with the photoconductive current which is generated when the channel region is irradiated with light. In order to suppress the photoconductive current to a prescribed allowable value or lower, the width of the depletion layer is adjusted to a value found based on the proportional relation or smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor, a method of manufacturing the same, and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art (First Prior Art) Conventionally, the driving performance of pixels of an active matrix type liquid crystal display device formed of amorphous silicon (hereinafter referred to as "a-Si") is a-Si. Although it is sufficiently satisfied, it is difficult in terms of performance to configure a signal line driver circuit on the same substrate by the same process, and an external driver circuit (driver) formed of single-crystal Si is used. Driving panel.

However, the mobility of a-Si is 0.5
~1cm a ² · s ^-1 · V ^-1, future, when the number of pixels of the liquid crystal panel is increased, up to 1 time to turn ON the TFT of the pixel corresponding to the horizontal period becomes increasingly shorter in general,
Insufficient ability to write to pixels.

On the other hand, when the TFT of the pixel is made of polysilicon (hereinafter referred to as "p-Si"), the mobility of the TFT is smaller than that of the TFT made of a-Si. Since the power is higher by one to two digits or more, the ability to charge the pixel is increased. Therefore, it is advantageous to form the pixel TFT with p-Si as the definition of the liquid crystal panel becomes higher (FPD Expo Forum 97, 2-14).

Generally, the structure of a p-Si TFT is as follows.
There are two types, a top gate type in which the gate electrode is located above the channel layer and a bottom gate type in which the gate electrode exists on the substrate side with respect to the channel layer. The top gate type structure is advantageous in miniaturization because a TFT having a small parasitic capacitance can be formed by doping impurities in a self-aligned manner using the gate electrode as a mask, as compared with the bottom gate type structure.

When the top gate type TFT is applied to, for example, a liquid crystal display device and light is irradiated from the back surface of the TFT, the light of the backlight is directly applied to the channel region of the TFT. When the channel region is irradiated with light, there is a problem that a photoconductive current is generated in this portion and the OFF current increases. Here, the “photoconductive current” will be described.

The mechanism of the generation of photoconductive current in semiconductors has been described in many papers (for example, edited by Kazunori Tanaka, “Basics of Amorphous Semiconductor,” 1)
982), but few have discussed the mechanism of photoconductive current generation in p-Si TFTs.

In general, a photoconductive current is generated by generating an electron / hole pair through a band gap in a state where an electric field is applied, and the generated electron / hole pair drifts due to the electric field. Is observed in the form of carrier recombination current with respect to the increase of the majority carriers in the region. In the channel region under the gate electrode, holes are induced directly under the channel under a reverse bias condition, but the carrier concentration is very low. On the other hand, electrons which are majority carriers on the drain side have a sheet resistance in the n- region of 20 kΩ / □ or less.
10 ¹⁶ / cm ³ to 10 ¹⁸ / c in the range of 100 kΩ / □
It is estimated that the carrier density is about m ³ . In this case, electrons that are majority carriers in the n − region diffuse toward the channel side to form a diffusion potential Vd. Note that the width of the depletion layer is represented by Wd.

The irradiation of light generates electron / hole pairs in the depleted region. The generated electron / hole pairs are attracted to each other by the electric field, so that the electrons move toward the drain and the holes move toward the channel. The electrons that have moved to the drain side and the holes that have moved to the channel side recombine and disappear in their respective regions. The electric charge consumed by the recombination is supplied by the source and drain electrodes, respectively, and this is observed as a photoconductive current.

(Second Prior Art) Also, a p-Si TFT
Since the substrate has high mobility, part or all of the active matrix element and the signal driving circuit in the screen can be formed simultaneously on the glass substrate. However, p-
The SiTFT has a disadvantage that the OFF current is large as compared with the a-SiTFT and the MOS field effect transistor.

Therefore, in order to reduce the OFF current, as disclosed in Japanese Patent Application Laid-Open No. 5-136417,
A method of providing a low-concentration impurity region (LDD region) adjacent to at least one of the source region and the drain region (first conventional method) has been performed.

As another method for forming an LDD region, a method of controlling the LDD region by the presence or absence of TaOx (Euro Display '96 pp547) is disclosed (second conventional method).

The mechanism by which the LDD region is effective in reducing the OFF current is described in JP-A-5-136417, since the LDD region has a higher resistance than the drain region, so that the channel / LDD region junction is reduced. It is considered that the electric field applied to the portion becomes smaller than when the LDD region is not provided.

In the above two methods, both methods are L
The presence or absence of TaOx is controlled by masking the DD region,
Alternatively, portions having different doping concentrations are formed by controlling the presence or absence of a resist film. In this method, in order to ensure an LDD region, the length of the LDD region must be longer than the dimensional accuracy of mask alignment.

On the other hand, there is a third conventional method for forming an LDD region in a self-aligned manner with respect to a gate electrode, as shown in Japanese Patent Application Laid-Open No. 7-140485. In this method, an Al oxide layer serving as a gate electrode is formed by anodic oxidation to form an Al oxide layer on a side surface thereof, and an N-type or P-type impurity element is introduced using the Al oxide layer as a mask. And a low-concentration impurity layer having substantially the same thickness as the oxide layer on the side surface.

By using this method, an LDD region can be formed in a self-aligned manner with respect to the gate electrode.
The mask for forming the D region can be reduced, and the length of the region having a high impurity concentration is set to 0.1 μm to 0.5 μm corresponding to the thickness of the oxide existing on the side surface of the anodized Al.
It can be formed as small as possible.

[0017]

(Problems to be Solved by the First Prior Art) When the OFF current increases (deterioration of OFF characteristics) due to the photoconductive current as described above, the following problem occurs. The image quality degradation caused by the degradation of the off characteristic is a luminance gradient and crosstalk. As shown in FIG. 38 (a), the luminance gradient is caused by a difference in the current / luminance characteristics of the liquid crystal between the upper part and the lower part of the screen, and a difference occurs between the upper part and the lower part of the screen. On the other hand, crosstalk is a phenomenon in which when a black box pattern is displayed in the center of white as shown in FIG. 38B, the black image trails in the vertical or horizontal direction. In addition, the deterioration of the off characteristics has a great effect on the image quality, such as an increase in flicker and uneven brightness.

(Problem with Second Conventional Example) The LDD structure is highly effective in reducing the OFF current.
In the ON state where the channel under the gate electrode of T is inverted, there is a disadvantage that the ON current is reduced by inserting the LDD region, which is a relatively high resistance layer, in series with the channel region.

Originally, the LDD region has a high resistance with respect to the source and drain regions, and the effect of the resistance tends to remarkably appear as the characteristics of the TFT increase. Therefore, the length of the LDD region, which is the high resistance region, must be sufficient to reduce the OFF current and have a sufficiently low resistance value to ensure a high ON current.

However, at present, there is no method for determining the guideline of the length of the LDD region, and it is necessary to secure the LDD region more than necessary to reduce the OFF current. Generally, it is necessary to secure an LDD region longer than 1.5 μm, and as a result, it causes a reduction in the ON current of the TFT.

According to the method shown in the third conventional example,
The LDD region can be formed as small as about 0.1 μm to 0.5 μm. However, when it is generally used as a driver of a liquid crystal panel or a TFT of a pixel, a driving voltage is about 5 to 15 V, and a general IC is used. Considerably higher than. Therefore, the LDD region is 0.1 μm to 0.5 μm.
In the case of m, the effect becomes insufficient and the OFF current cannot be sufficiently reduced in this process.

In view of the above, the present invention suppresses the OFF current (photoconductive current) at the time of light irradiation, thereby suppressing deterioration in image quality such as luminance gradient and crosstalk, and achieving high performance. A first object is to provide a thin film transistor which realizes high reliability.

Also, while suppressing the OFF current, the LD
It is a second object of the present invention to provide a thin film transistor having high performance and high reliability by adopting a configuration in which the length of the D region is suppressed to a necessary minimum to suppress a decrease in ON current.

[0024]

According to a first aspect of the present invention, there is provided a thin film transistor comprising a channel region, and a source region and a drain disposed on both sides of the channel region. A polycrystalline silicon semiconductor layer in which a region is formed, a depletion layer is formed between the channel region and the drain region, and when the light is irradiated to the width of the depletion layer and the channel region. The generated photoconductive current has a proportional relationship, and the width of the depletion layer is set to be equal to or less than a value obtained based on the proportional relationship in order to keep the photoconductive current within a predetermined allowable value. And

As described above, it has been newly found that the width of the depletion layer has a proportional relationship with the photoconductive current.
By controlling the width of the depletion layer, the photoconductive current can be reduced to a predetermined allowable value or less, and a thin film transistor without image quality deterioration such as luminance gradient and crosstalk can be provided.

The invention described in claim 2 is the first invention.
Wherein the sheet resistance of the drain region is R (kΩ / □) and the channel width of the channel region is W (μm), wherein the relationship of Expression (1) is satisfied. . A is a constant determined by the photoconductive current and the light intensity. (R + 30) · W <A … (1)

The third aspect of the present invention is the second aspect of the present invention.
Wherein the sheet resistance of the drain region is R (kΩ / □) and the channel width of the channel region is W (μm), wherein the relationship of Expression (2) is satisfied. . (R + 30) · W <1 × 10 ³ (2)

As shown in the above equations (1) and (2), the OFF during light irradiation depends on the relationship between the newly controllable factor (sheet resistance of the drain region) and the channel width of the channel region.
The range in which the current (photoconductive current) is suppressed can be defined. The thin film transistor that satisfies the above formulas (1) and (2) can suppress an increase in OFF current at the time of light irradiation, so that cross talk and luminance gradient can be prevented. High reliability can be realized.

The invention described in claim 4 is the same as the claim 3.
Wherein the channel width W of the channel region is 2 μm or less.

The relationship of the above equation (2) indicates that even when the channel width W of the channel region is 2 μm or less, the increase in the OFF current during light irradiation can be suppressed by the sheet resistance R and the channel width W. it can.

The invention described in claim 5 is the same as the claim 3
5. The thin film transistor according to claim 4, wherein the drain region has a sheet resistance of 20 kΩ / □ or more.
0 kΩ / □ or less.

The reason for this restriction is that the sheet resistance is 2
When the sheet resistance is 100 kΩ / □ or more, the ON current of the transistor decreases and the operation of the panel becomes unstable when the sheet resistance is 100 kΩ / □ or more. The range of the sheet resistance of the drain region is 20
By setting kΩ / □ or more and 100 kΩ / □ or less, O
It is possible to provide a thin film transistor in which the FF current can be reduced and the ON current does not decrease.

According to a sixth aspect of the present invention, there is provided a liquid crystal display device comprising a channel region and a polycrystalline silicon semiconductor layer having a source region and a drain region disposed on both sides of the channel region. A thin film transistor provided, wherein a luminance of a backlight constituting the liquid crystal display device is set to 2000 (cd / m ² ) or more, between the source region and the channel region;
Alternatively, a low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region is formed in at least one of the drain region and the channel region. It is characterized in that it is not more than 0 μm.

By forming the low-concentration impurity region as described above, the extension of the depletion layer can be made to be within the range of the low-concentration impurity region having the length ΔL of 1.0 μm or less. A thin film transistor in which current (OFF current) does not increase can be obtained.

According to a seventh aspect of the present invention, a channel region and a source region and a drain region disposed on both sides of the channel region are formed, and between the source region and the channel region or between the source region and the drain region. A thin film transistor including a polycrystalline silicon semiconductor layer in which a low-concentration impurity region having an impurity concentration lower than that of a source region and a drain region is formed in at least one of a channel region and a source region and a drain region. Let ΔL
(Μm), the source-drain voltage is Vlc (V), and the channel width of the channel region is W (μm),
It is characterized by satisfying the relationship of Expression (3). ΔL> (W · Vlc) / 36 (3)

By satisfying such a relationship, when the thin film transistor is turned off, the low-concentration impurity region becomes a high-resistance layer in which carriers are depleted, so that the OFF current can be reduced. Then, from the above equation (1), L
The guideline for the length of the DD region can be determined, and there is no need to secure an LDD region more than necessary to reduce the OFF current.

The invention described in claim 8 is the same as that in claim 7.
Wherein the relationship of Expression (4) is satisfied when the channel length of the channel region is L (μm). ΔL <1.5 · (W / L) (4)

By further satisfying such a relationship,
When the thin film transistor is turned on, electrons acting as carriers are accumulated in the low-concentration impurity region below the gate electrode to become a low-resistance region due to the action of an electric field from the gate electrode, and the ON current does not decrease. Therefore, the thin-film transistor can secure a sufficient ON current and reduce the OFF current.

The invention according to claim 9 is the same as the invention according to claim 8
Wherein the channel width W (μm) of the channel region is 2 μm or less.

The relationship of the above equation (2) indicates that even when the channel width W of the channel region is 2 μm or less, the increase in the OFF current during light irradiation can be suppressed by the sheet resistance R and the channel width W. it can.

According to a tenth aspect of the present invention, there is provided the thin film transistor according to the eighth or ninth aspect,
The low-concentration impurity region has a sheet resistance of 20 kΩ / □ or more and 100 kΩ / □ or less.

According to an eleventh aspect of the present invention, in the thin film transistor according to the tenth aspect, the low-concentration impurity region is formed only between the drain region and the channel region. I have.

The reason why the low concentration impurity region is provided is to alleviate the electric field acting on the drain region.
From this point of view, it is not necessary to provide low-concentration impurity regions in both the drain region and the channel region. Therefore,
If a low-concentration impurity region is formed between at least one of the drain region and the channel region or between the drain region and the channel region, the area of the thin film transistor can be reduced.

According to a twelfth aspect of the present invention, there is provided a liquid crystal panel unit having the thin film transistor according to the first aspect as a switching element, and a backlight unit for supplying light to the liquid crystal panel unit from the back side. A liquid crystal display device comprising: a sheet resistance of the drain region is set to R (kΩ /
□), the brightness of the backlight portion is B (cd / m ² ),
When the channel width of the channel region is W (μm), the relationship of Expression (5) is satisfied.
Note that C is a constant determined by the photoconductive current. (R + 30) ・ B ・ W <C … (5)

The invention according to claim 13 is the liquid crystal display device according to claim 12, wherein the sheet resistance of the drain region is R (kΩ / □) and the luminance of the backlight portion is B ( cd / m ² ), and when the channel width of the channel region is W (μm), the relationship of Expression (6) is satisfied. (R + 30) · B · W <1 × 10 ⁶ (6)

According to a fourteenth aspect of the present invention, there is provided an EL device, comprising: a light emitting layer on a pixel electrode formed on a substrate having a thin film transistor; and a counter electrode formed on the light emitting layer. 2. The device according to claim 1, wherein the thin film transistor is the thin film transistor according to claim 1, and the light intensity applied to a channel region of the thin film transistor is B.
When (cd / m ² ), the relationship of Expression (5) is satisfied. Note that C is a constant determined by the photoconductive current. (R + 30) ・ B ・ W <C … (5)

The invention according to claim 15 is the EL display device according to claim 14, wherein the sheet resistance of the drain region is R (kΩ / □), and the light intensity applied to the channel region is Is B (cd / m ² ), and the channel width of the channel region is W (μm), and the relationship of Expression (6) is satisfied. (R + 30) · B · W <1 × 10 ⁶ (6)

According to a sixteenth aspect of the present invention, a polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate, and a gate insulating film is formed on the polycrystalline silicon semiconductor layer. A gate insulating film forming step;
A gate electrode forming step of forming a gate electrode in a pattern on the gate insulating film; an oxidizing step of oxidizing a side surface of the gate electrode to form a metal oxide film covering the side surface of the gate electrode; An impurity doping step of doping an impurity in a silicon semiconductor layer using the gate electrode as a mask, comprising: controlling the thickness of a metal oxide film formed in the anodic oxidation step; It is characterized in that the length ΔL of the low concentration impurity region formed in the doping step is 1.0 μm or less.

The invention according to claim 17 is a method for manufacturing a thin film transistor, wherein a polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate; A gate insulating film forming step of forming a gate insulating film thereon, a gate electrode forming step of forming a gate electrode on the gate insulating film in a pattern, and an impurity using the gate electrode as a mask in the polycrystalline silicon semiconductor layer. A first impurity doping step of doping, and a shielding film formed on the semiconductor region doped with the impurity by the first impurity doping step, and the shielding film is formed in a pattern by anisotropic etching. Forming a polycrystalline silicon semiconductor layer with an impurity using the shielding film as a mask to form a lower region of the shielding film and other regions. So that a low-concentration impurity has a lower impurity concentration than the source region and the drain region in at least one of the source region and the channel region or the drain region and the channel region. A second impurity doping step of forming a region and reducing the length of the low concentration impurity region to 1.0 μm or less;
It is characterized by having.

According to an eighteenth aspect of the present invention, there is provided the method of manufacturing a thin film transistor according to the seventeenth aspect, wherein the low concentration impurity region has a length ΔL of 1.0 μm or less as a non-defective product. It is characterized by including.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Invention Group] (Concept of First Invention Group) First, the concept of the first invention group will be described, and then specific embodiments will be described with reference to the drawings. .

The first invention group aims at suppressing the photoconductive current at the time of irradiating light to the TFT.

Therefore, in order to achieve the above object, the present inventors searched for a parameter having a correlation with the photoconductive current, and as a result, found that the depletion layer width had a proportional relationship with the photoconductive current. Newly found. By controlling (decreasing) the width of the depletion layer based on this proportional relationship, the photoconductive current can be reduced to an allowable value or less, and a thin film transistor free from image quality deterioration such as luminance gradient and crosstalk can be provided. .

The "depletion layer width" is defined in FIG.
As shown in (a), it is defined as the distance between each tangent of two points where the electric field strength rises.

Conventionally, it has been known that the luminance B of the backlight and the channel width W of the channel region are correlated with the photoconductive current, and the TFT has been designed based on these two control parameters. . However, the two control parameters alone are not sufficient for suppressing the photoconductive current, and may cause an error in designing the TFT.

Therefore, the present inventors have further studied the above “proportional relationship between the depletion layer width and the photoconductive current” and have found that the sheet resistance of the drain region has a correlation with the photoconductive current. Newly found. As a result, the control parameter becomes three by using the new factor of the sheet resistance R as the evaluation criterion, and the conventional control parameter becomes two.
The accuracy of designing the thin film transistor is improved as compared with the case of using the thin film transistor, and the photoconductive current can be significantly suppressed. Hereinafter, the relationship between the depletion layer width and the photoconductive current will be described first, and then the relationship among the backlight brightness B, the sheet resistance R of the drain region, and the channel width W of the channel region will be described. Then, the principle of a specific manufacturing method of a TFT for suppressing a photoconductive current will be described.

First, the present inventors measured the relationship between the channel width of the channel region constituting the TFT and the photoconductive current, and also measured the relationship between the sheet resistance of the drain region and the photoconductive current. Further, operation analysis was performed by simulation, and the range of the depletion layer width was obtained.

FIG. 1A shows the channel width W of the channel region constituting the TFT and the photoconductive current (OFF current:
6 is a graph showing the relationship with I _OFF ). The solid line is 60
00 cd / cm ² , the broken line indicates 4000 cd / cm ² , and the one-dot chain line indicates the relationship between the channel width W and the photoconductive current I _OFF when light of 2000 cd / cm ² is irradiated.

As shown in FIG. 1A, the OFF current I at the time of light irradiation
It is clear that _OFF is proportional to the channel width W.
FIG. 1B is a graph showing the relationship between the backlight luminance and the photoconductive current. It was confirmed that the OFF current I _OFF was proportional to the backlight luminance B.

FIG. 2A is a graph showing the result of simulating the electric field when the TFT is turned off. According to the simulation result shown in FIG. 2A, the electric field is almost concentrated only at the junction of the channel / drain region. When the sheet resistance of the LDD region is 20 kΩ / □ (solid line), the width of the depletion layer is about 0. It is about 5 μm, and it is understood that the depletion layer region mainly extends to the channel side. On the other hand, when the sheet resistance is 100 kΩ / □ (broken line), the depletion layer width is about 0.9 μm, and the LDD
It is confirmed that it has spread to the area.

As a result, it has been newly found that the width of the depletion layer changes as the sheet resistance changes. Then, the present inventors investigated the relationship between the sheet resistance and the depletion layer width. The result is shown in FIG. FIG. 3 shows the relationship between the sheet resistance and the depletion layer width obtained by simulation. It was confirmed that the width Wd of the depletion layer was proportional to the sheet resistance R. This is considered to be because the depletion layer extends in a region having a low carrier concentration, similarly to the expansion of the depletion layer in the case of the p / n junction. The relationship between the sheet resistance and the depletion layer width in FIG. 3 is shown in the following equation (7). Wd = 8 × 10 ⁻³ .R + 0.24 (7)

FIG. 4 shows the result of measuring the relationship between the depletion layer width obtained by simulation (when W = 4 μm) and the photoconductive current at the sheet resistance corresponding to the depletion layer width.

When the depletion layer width and the photoconductive current were plotted logarithmically, a straight line having a slope of approximately 1 was obtained. This suggests that the photoconductive current is generated by the depletion region. The relationship between the depletion layer width Wd and the photoconductive current can be expressed by the following equation (8). I _photo = 5 × 10 ^-15 · Wd ... (8)

In the above equation (8), I _photo is a value per 1 (cd / m ² ) of light intensity at a channel width of 4 μm.

Thus, from the above equation (8), the depletion layer width W
It has been found that d has a proportional relationship with the photoconductive current I _photo , whereby the photoconductive current can be reduced to an allowable value or less by controlling (decreasing) the width of the depletion layer. And a thin film transistor that achieves high performance and high reliability without image quality deterioration.
The “allowable value” is, for example, 10 pA
The following values.

From FIG. 1A, since I _off is proportional to the channel width W and the light intensity B, I _off and I _off
Photo satisfies the relationship of the following equation (9). I _off = I _photo・ (W / 4) ・ B ... (9)

Then, from the above equations (9) and (8), I
_{When photo} is deleted, the following equation (10) is obtained.

I _off (4 / (W · B)) = 5 × 10 ⁻¹⁵ · Wd (10) Then, when the depletion layer width Wd is eliminated from the above equations (7) and (10), the following equation (11) is obtained. An expression is obtained. Here, FIG.
From (a), I _off is proportional to the channel width W. R = I _off · 10 ¹⁷ / (B · W) −30 (11)

By the way, generally, in order to maintain high quality image quality, I _off needs to be 10 pA or less.
The reason will be described below. FIG. 5 shows an equivalent circuit of the active matrix.

When the OFF resistance R _{off of the} TFT becomes small, the charge cannot be held until the next writing, resulting in a voltage loss. The pixel voltage V after the time T is described by Expression (12). V = V ₀ ｛1−exp (T / (R _off × Ctot)) (12) where Ctot = Cs + Clc

Further, the OFF current of the TFT (R _off = V _sd /
FIG. 6 shows a simulation result of time and voltage loss when I _off ) is used as a parameter. According to FIG.
With a holding time of sec (1/60 Hz), a voltage loss of 0.0
It is confirmed that in order to suppress the current to 2 V or less, it is necessary to set the OFF current to 10 pA or less in a backlight irradiation state.

Therefore, I _off of the above equation (11) is set to 10p
If A or less, the following equation is obtained. (R + 30) · B · W <10 · 10 ⁻¹² · 10 ¹⁷ = 1 × 10 ⁶ (6) Further, the value for suppressing the OFF current changes depending on the conditions in which the thin film transistor is used, so that it can be expressed as the following equation (5). (R + 30) ・ B ・ W <C .. (5) where C is a constant determined by the photoconductive current.

As described above, the thin film transistor satisfying the above formula (6) can suppress the photoconductive current, and therefore can prevent the crosstalk and the luminance gradient, and have excellent image quality and high performance. , High reliability can be realized.

The above equation (6) is an equation including the luminance of the backlight as a liquid crystal panel. However, in general, the thin film transistor is not always limited to a transmissive type having a backlight. Therefore, the backlight brightness B is set to a maximum of 5000.
Assuming cd / m ² , the above equation (6) becomes (R + 30) · W <2 × 10 ² (2 ′), and the thin film transistor satisfying the above equation (2 ′) is:
A thin film transistor can be obtained regardless of the luminance B of the backlight, that is, regardless of the type of transmission or reflection.

Preferably, the above equation (2 ′) can be expressed by the following equation (2) in consideration of the design margin of the thin film transistor. (R + 30) · W <1 × 10 ³ (2)

The above equation (11) is represented by the following equation (11 ′)
It can be expressed as an equation. That is, (R + 30) · W <(I _off · 10 ¹⁷ ) / B (11 ′)

When the right side of the above (11 ') is replaced by a constant A determined by I _off and B, the following expression (1) can be obtained. (R + 30) · W <A ... (1) (A is a constant determined by photoconductive current and light intensity)

Further, in the structure of the TFT, LDD
By forming the region, the depletion layer does not spread beyond the LDD region, and the photoconductive current proportional to the width of the depletion layer can be suppressed as described above. FIG.
No. 6 shows that the TFT is O in the channel region and the LDD region.
When in the FF state (Vg = -10 V, Vd = 6 V)
The result of simulating the electric field of FIG.

According to the simulation results, the region to which the electric field is applied depends on the sheet resistance. When the sheet resistance in the LDD region is 20 kΩ / □, it is about 0.4 μm, and when the sheet resistance is 100 kΩ / □, it is 1.0 μm. It was confirmed that it was.

Although the channel width is set to 4 μm, when the channel width W of the channel region is reduced to 2 μm or less, the above-mentioned relational expressions (1) and (2)
The formula is an effective guideline for manufacturing a thin film transistor. In the following embodiment, a TFT manufactured based on the simulation will be specifically described.

(Embodiment 1-1) FIG. 7 is a schematic sectional view of a liquid crystal display device using a thin film transistor according to Embodiment 1 of the present invention as a pixel switching element, and FIG.
FIG. 9 is a schematic plan view of the thin film transistor according to the first embodiment of the present invention. FIG.

As shown in FIG. 7, the liquid crystal display device 50
The transmission type liquid crystal display device includes a liquid crystal panel section 51 and a backlight section 52 and the like disposed on the back side of the liquid crystal panel section 51. The liquid crystal panel 51 includes a polarizing plate 53.
53, glass substrates 2 and 54b, thin film transistors 1 arranged in a matrix, pixel electrodes 55, alignment films 56,
It is composed of a liquid crystal layer 57, a common electrode 58 and the like.

The thin film transistor 1 (hereinafter, referred to as TFT) and the pixel electrode 55 are formed on the glass substrate 2, and the common electrode 58 is formed on the substrate 54b.
On the substrates 2 and 54b, alignment films 56 and 56 made of polyimide resin or the like are formed, respectively.
The rubbing process is performed on the substrates 6 and 56 in a direction in which the alignment directions are orthogonal to each other, and the substrates 2 and 54b are arranged to face each other via a spacer (not shown).

A liquid crystal layer 5 is provided between the substrates 2 and 54b.
7, the liquid crystal in the liquid crystal layer 57 is twisted and oriented by 90 degrees. Further, polarizing plates 53 are arranged on the outer surface of the 2.54b so that the directions of vibration of the regulated light beams are parallel to each other.

A backlight unit 52 is disposed on the back (lower) side of the liquid crystal panel unit 51. The backlight unit 52 includes a light emitting element such as a cold cathode tube, a light dispersion plate for uniformizing light, and the like.

Next, the thin film transistor will be described with reference to FIGS.

The thin film transistor 1 has a polycrystalline silicon layer 3 having a thickness of 500 °
A gate insulating layer 4 made of SiO ₂ (silicon dioxide) of 00 °, a gate electrode 5a made of aluminum, and S
An interlayer insulating layer 6 made of iO ₂ is sequentially laminated.

The polycrystalline silicon layer 3 includes a channel region 3c located immediately below the gate electrode 5a, a source region 3a (n + layer) having a high concentration, and a drain region (n + layer) 3b having a high impurity concentration. It is composed of In the present embodiment, the LDD region (n-layer) 3
The length ΔL of d · 3e is set to 0.4 μm. The channel width W of the channel region 3c is set to 5 μm.

Here, the sheet resistance of the drain region is R (kΩ / □), the luminance of the backlight section 52 of the liquid crystal display device 50 using this active matrix TFT is B (cd / m ² ), and the channel region is When the channel width of 3c is W (μm), it is designed to satisfy the following equation (6). (R + 30) · B · W = I _off <1 × 10 ⁶ (6)

The TFT 1 is further provided with a source electrode 7 and a drain electrode 8 made of, for example, aluminum. The source electrode 7 is provided with a contact hole 9 a formed in the gate insulating layer 4 and the interlayer insulating layer 6. Is connected to the source region 3a via the drain electrode 8
Is connected to the drain region 3b through a contact hole 9b formed in the gate insulating layer 4 and the interlayer insulating layer 6.

Next, a method of manufacturing a thin film transistor will be described. FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to Embodiment 1-1 of the present invention, and FIG.
2 is a flowchart showing a method for manufacturing a thin film transistor.

(1) First, an a-Si layer 15 having a thickness of 500 ° is deposited on a glass substrate 2 by a plasma CVD method, and then dehydrogenated at 400 ° C. (FIG. 10).
(A)). The purpose of this dehydrogenation treatment is to prevent ablation of the Si film due to desorption of hydrogen during crystallization. In addition, the process of forming a-Si can use processes other than plasma CVD, such as low pressure CVD and sputtering. Alternatively, a polysilicon film can be directly deposited by using plasma CVD or another method. In this case, a later-described laser annealing step becomes unnecessary.

(2) Next, the a-Si layer 1 is subjected to laser annealing using an excimer laser having a wavelength of 308 nm.
5 is melt-recrystallized (p-Si) to form a polycrystalline silicon layer 16 (FIG. 10B).

(3) Next, the polycrystalline silicon layer 16 is formed into islands in a predetermined shape to form the polycrystalline silicon layer 3 (FIG. 10C).

(4) Then, an SiO ₂ (silicon dioxide) layer having a thickness of 1000 ° and serving as a gate insulating layer 4 is formed on the glass substrate 2 so as to cover the polycrystalline silicon layer 3 (FIG. 10). (D)).

(5) Next, a metal layer 17 made of aluminum to be the gate electrode 5a is formed (FIG. 10).
(E)).

(6) Next, the metal layer 17 is patterned into a predetermined shape to form the gate electrode 5a (FIG. 10).
(F)).

(7) Then, impurities are doped using gate electrode 5a as a mask (FIG. 10).
(G)). Specifically, phosphorus ions are doped as impurities by an ion doping method. Thereby, the channel region 3c located immediately below the gate electrode 5a is a region not doped with impurities. The region of the polycrystalline silicon layer 3 excluding the channel region 3c is a layer doped with impurities. In this case, the doping acceleration voltage is 80 kV, the beam current density is 1 μA / cm ^2, and an n-type region is formed with high acceleration.

(8) Next, covering the gate electrode 5a,
A photoresist 18 is formed (FIG. 10H).

(9) Next, a photoresist 18 is formed in a pattern by anisotropic etching to form a resist film 5b (FIG. 11 (i)). At this time, an accurate pattern of the resist film 5b can be formed by anisotropic etching.

(10) Next, as shown in FIG. 11J, a second impurity doping is performed using the resist film 5b as a mask. Specifically, phosphorus ions are doped as impurities by an ion doping method.
The doping acceleration voltage in this case is 12 kV, the beam current density is 0.5 μA / cm ^2, and an n-type region with low acceleration and high concentration is formed.

(11) Next, an interlayer insulating layer (SiOx)
6 is formed (FIG. 11 (k)).

(12) Next, contact holes 9a and 9b are opened in the interlayer insulating layer 6 and the gate insulating layer 4 (FIG. 11 (L)).

(13) Then, the contact holes 9a and 9b are filled with a metal layer such as Al by sputtering, and the upper portions of the metal layers are patterned into a predetermined shape to form the source electrode 7 and the drain electrode 8 ( FIG.
(M)). Thus, the TFT 1 is manufactured.

In the above example, an n-channel TFT has been described. However, a p-channel TFT can be manufactured by a similar manufacturing process.

The thin film transistor formed by the above-described manufacturing method
5000 cd / m from the back of the star ^TwoThe place where the light was irradiated
In this case, the OFF current is approximately 5 pA. As previously mentioned,
Set the OFF current to 10 pA or less in the backlight
The thin-film transistor according to the present embodiment.
Can ensure good display characteristics.

FIG. 13 shows the voltage / current characteristics of the thin film transistor, and FIG. 14 shows the variation of the OFF current in the substrate surface. As shown in FIG. 13, the TFT 1 (the graph of L3) according to the present embodiment was able to secure a stable large ON current and small OFF current. Also, from FIG.
In the TFT 1 manufactured in this manner, variation on the substrate surface can be reduced.

FIG. 15 shows the result of simulating the Vg-Id characteristics of the thin film transistor using the concentration of the n-type region as a parameter. Sheet resistance in LDD area is 20k
The OFF current sharply increases below Ω / □. Therefore,
The sheet resistance in the LDD region needs to be at least 20 kΩ / □ or more. On the other hand, the sheet resistance in the LDD region is set to 1
When it was set to 00 kΩ / □ or more, the ON current of the transistor decreased, and the operation of the panel became unstable. Therefore, LD
The range of the sheet resistance in the D region is 20 kΩ / □ or more and 100
It is desirable to be kΩ / □ or less.

Generally, the backlight luminance is up to 500
0 cd / m^Two, Where the photoconductive current is 10
When the depletion layer width Wd for suppressing the current to pA or less is obtained, the following is obtained.
Become like That is, W = 4 and B = 50 in the equation (10).
00, Ioff = 10 × 10 ^-12By substituting
The width of the depletion layer can be obtained, and Wd = 0.4 μm.
You.

Since the width of the depletion layer does not exceed the length of the LDD region, by setting the length ΔL of the LDD region to 0.4 μm or less, the effective depletion layer region becomes 0.4 μm or less. Is suppressed (10 pA or less). When the LDD region is smaller than 0.1 μm, the electric field relaxation effect is lost and the OFF current increases as shown in FIG. 2B. Therefore, the LDD region is preferably larger than 0.1 μm.

In the equation (10), when the backlight luminance B is, for example, 2000 cd / m ² ,
The depletion layer width Wd is 1 μm.

Therefore, since the width of the depletion layer does not exceed the length of the LDD region, the length ΔL of the LDD region is set to 1.0 μm
The effective depletion layer region is 1.0 μm
As described below, the photoconductive current can be suppressed. still,
More preferably, the thickness is 0.4 μm or less.

In the inspection step, a device whose LDD region exceeds 1.0 μm cannot satisfy the OFF characteristics. Therefore, the length ΔL of the LDD region is 1.0 μm
By performing an inspection process in which the following items are regarded as non-defective products, non-defective products and defective products can be selected, and material loss in the panel process can be reduced.

Further, as shown in Table 1, Experimental Examples 1 to 3
(That is, those satisfying the above formula (2)) are O
Although the FF current can be suppressed, the experimental examples 4 and 5 (that is, those which do not satisfy the above-mentioned formula (6)) show O 2 at the time of light irradiation.
It was confirmed that the FF current could not be suppressed.

[Table 1]

Thus, according to the above equation (6), the relationship between the newly controllable factor (the sheet resistance of the drain region) and the channel width of the channel region causes the O.D.
A range in which the FF current (photoconductive current) is suppressed can be defined. Therefore, by manufacturing a thin film transistor that satisfies the relationship of the above formula (6), an increase in OFF current can be suppressed, so that a cross talk and a luminance gradient can be prevented, and a high performance and high reliability thin film transistor is realized. Can be provided.

(Embodiment 1-2) A method of manufacturing a thin film transistor according to Embodiment 1-2 of the present invention will be described.

In the thin film transistor of Embodiment 1-2, the length of the LDD region is set to 0.2 μm or less by anodic oxidation.
It is formed as small as 0.5 μm. Than this,
Since the region on the drain side is a high-concentration impurity region, LD
Since the width of the depletion layer does not extend beyond the length of the D region,
Photoconductive current can be suppressed. A specific description of the manufacturing method will be described below. FIG. 17 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to Embodiment 1-2 of the present invention, and FIG. 18 is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor.

As in Embodiment 1-1 described above,
A-Si layer 15 is deposited on the glass substrate 2 and then
Melt recrystallization (p-Si) of the a-Si layer 15 by laser annealing using an excimer laser having a wavelength of 308 nm.
) To form a polycrystalline silicon layer 16. Next, the polycrystalline silicon layer 16 is islanded into a predetermined shape to form the polycrystalline silicon layer 3. Next, a gate insulating layer 4 is formed on the glass substrate 2 so as to cover the polycrystalline silicon layer 3. (FIGS. 17A to 17D).

Next, a metal layer 17 is formed, and the metal layer 1 is formed.
A photoresist 17a is formed in a pattern on the substrate 7, and the metal film 17 is patterned by an etching technique to form a gate electrode 5a. Next, the side surface of the gate electrode 5a is anodized to form an oxide insulating layer 5b. (FIG. 17 (f)).

Next, as shown in FIG.
Using the gate electrode 5a as a mask, doping of impurities is performed. Specifically, phosphorus ions are doped as impurities by an ion doping method. Thereby, the channel region 3c located immediately below the gate electrode 5a is a region not doped with impurities. And the oxide insulating layer 5
LDD regions 3d and 3e are formed in regions immediately below b and 5b, and a channel region 3a and a drain region 3b are formed outside thereof.

Next, as shown in FIGS. 18 (h) to 18 (j), an interlayer insulating layer (SiOx) 6 is formed.
Contact holes 9 are formed in interlayer insulating layer 6 and gate insulating layer 4.
The contact holes 9a and 9b are filled in the contact holes 9a and 9b by a sputtering method, and a source electrode 7 and a drain electrode 8 are formed by patterning an upper portion of the metal layer into a predetermined shape. . Thus, TF
T is produced.

According to the anodic oxidation of the present embodiment, LDD
It is possible to make the length of the region as small as 0.2 μm to 0.5 μm. As a result, the region on the drain side becomes a high-concentration impurity region, so that the width of the depletion layer does not extend beyond the main length. Therefore, the photoconductive current can be reduced.

Thus, when the thin-film transistor is turned off, the low-concentration impurity region becomes a high-resistance layer in which carriers are depleted, so that the OFF current can be reduced.
Then, the guideline for the length of the LDD region can be determined from the above equation (2), and it is not necessary to secure the LDD region more than necessary to reduce the OFF current. In addition, when the above equation (2) further satisfies the equation (6), when the thin film transistor is turned on, electrons acting as carriers are accumulated in the low concentration impurity region below the gate electrode by the action of the electric field from the gate electrode. The region becomes a low resistance region, and the ON current does not decrease. Therefore, the thin film transistor that satisfies the expressions (2) and (6) can secure a sufficient ON current and reduce the OFF current.

In addition, the impurity doping is performed when the acceleration voltage is 10 kV or more and 30 kV or less and the beam current density is 0.0 kV or less.
By using an ion doping method at a low speed of 5 μA / cm ² or more and 1 μA / cm ² or less, damage at the time of doping can be reduced because the ion acceleration voltage at the time of ion doping is low. In addition, even when a resist is used as a mask at the time of impurity doping, the resist can be removed without deterioration.

(Embodiment 1-3) Embodiment 3 of the present invention will be described with reference to FIGS.
FIG. 19 is a plan view showing a wiring pattern of a C-MOS inverter using a thin film transistor according to Embodiment 1-3 of the present invention, and FIG. 20 is an equivalent circuit diagram thereof.
1 is a sectional view taken along the line XX ′ of FIG.

The C-MOS inverter 50 constitutes, for example, a drive circuit of a liquid crystal display. The C-MOS inverter 50 includes an n-channel TFT 22 and a p-channel TFT
23. The n-channel TFT 22
It has a configuration similar to that of the n-channel TFT 1 of the first embodiment, and corresponding portions are denoted by the same reference numerals.

The p-channel TFT 23 is a normal type TFT having no LDD structure. That is, in the TFT 23, a polycrystalline silicon layer 24, a gate insulating layer 4 made of SiO ₂ (silicon dioxide), a gate electrode 25 made of aluminum, and an interlayer insulating layer 6 made of SiO ₂ are sequentially laminated on the glass substrate 2. It is configured. The polycrystalline silicon layer 24 includes a channel region 24c located immediately below the gate electrode 25, a source region 24a (p + layer) and a drain region 24b disposed on both sides of the channel region 24c.
(P + layer). Furthermore, this TFT2
3 is provided with a source electrode 26 and a drain electrode 27 made of, for example, aluminum. Source electrode 26
Is connected to the source region 24a via a contact hole 28a formed in the gate insulating layer 4 and the interlayer insulating layer 6. Further, the drain electrode 27 is connected to the drain region 24b via a contact hole 28b formed in the gate insulating layer 4 and the interlayer insulating layer 6. The gate electrode 5 of the n-channel TFT 22 and the gate electrode 25 of the p-channel TFT 23 are commonly connected to the input terminal 30 as shown in FIG. The drain electrode 8 of the n-channel TFT 22 and the drain electrode 27 of the p-channel TFT 23 are commonly connected to an output terminal 31, as shown in FIG.

In the present embodiment 1-3, only the drain side of the n-channel TFT has the LDD structure described in the embodiment 1-1, the size of the TFT can be reduced, and the distance between the source and the drain can be reduced. Can be suppressed to about 6 μm, and LDD is provided for both the source and the drain.
The size can be reduced to about 50% or less as compared with the case where the region is formed, and the TFT can be miniaturized.

Note that an n-channel TFT and a p-channel TF
Both of T may have an LDD structure. However, if only one of the n-channel TFT and the p-channel TFT has the LDD structure in order to reduce the circuit area occupied in the array substrate, the n-channel TF
It is desirable to be on the T side. Because p-channel TFT
Comparing the mobilities of holes, which are carriers, and electrons, which are carriers of n-channel TFTs, electrons are much larger. Therefore, p-channel TFT and n-channel TF
When the same electric field is applied to T and n-channel TFT
Is more impacted by the carrier, so that the n-channel TFT is more likely to deteriorate. Therefore, from the viewpoint of preventing TFT deterioration and improving reliability, n
This is because it is desirable that the channel TFT has an LDD structure.

On / of in C-MOS inverter
FIG. 22 shows operating points in the bias state of the n-ch transistor at f. As described above, in the n-ch TFT of the inverter, the polarity of the gate electrode always operates at a voltage higher than 0 V with respect to the negative power supply. Therefore, the negative power supply is always n-ch TFT
And the output side always functions as a drain electrode. Therefore, using a circuit in which only the output side portion is configured as described above contributes to a reduction in the area occupied by the circuit portion on the array substrate. In addition, this contributes to a reduction in parasitic capacitance at this portion.

(Other Matters) Embodiments 1-1 to 1-3
In the above, an LDD region having one type of concentration has been described, but the present invention is not limited to this, and a plurality of LDD regions having different concentration differences may be provided.
That is, by forming the LDD region from a plurality of junction regions in which the impurity concentration decreases stepwise toward the channel region, the impurity concentration can be changed in multiple steps. Concentration of the electric field can be further reduced.

Further, the LDD region may be formed only between the drain region and the channel region. With such a configuration, the effect of reducing the OFF current and the like can be obtained, and the area of the thin film transistor can be reduced. It becomes possible.

In Embodiments 1-1 to 1-3, the description has been made using the top gate type TFT. However, the present invention can be applied to a bottom gate type TFT.

Further, the thin film transistors described in Embodiments 1-1 to 1-3 can be applied to EL devices in addition to liquid crystal display devices. That is, the first embodiment
By forming a plurality of thin film transistors described in -1 to 1-3 as switching elements on a substrate and forming an EL device including the substrate, a structure in which photoconductive current is suppressed can be obtained.

[Second Invention Group] (Concept of Second Invention Group) The present invention suppresses the OFF current of a thin film transistor (hereinafter referred to as “TFT”) and suppresses the length of an LDD region to a necessary minimum. It is an object of the present invention to realize a TFT having high performance and high reliability by adopting a configuration that suppresses a decrease in ON current. Then, the present inventors analyzed the operation of the LDD region portion by simulation in order to obtain the truly necessary length of the LDD region, and determined the extent to which the electric field was applied.

FIG. 23 is a graph showing a result of simulating the Vg-Id characteristics when the LDD region is changed from 0.5 μm to 3 μm using the sheet resistance as a parameter.

From these results, it was confirmed that the Vg-Id characteristic has a large dependency on the concentration of the LDD region, but has no dependency on the length of the LDD region. The cause will be discussed below.

FIG. 24 shows a case where the TFT is turned off (Vg = −10) in the channel region and the LDD region.
V, Vd = 6 V).

According to the simulation result, the region where the electric field is applied depends on the sheet resistance.
In the case of 0 kΩ / □, the sheet resistance is about 0.4 μm and the sheet resistance is 10
In the case of 0 kΩ / □, it was confirmed that the thickness was 1.0 μm.

Accordingly, it has been found that even if the LDD region is made larger than the region to which the electric field is applied, the effect of relaxing the electric field has no effect, and a resistor is simply inserted in series in the channel region of the transistor.

FIG. 25 is a graph showing the relationship between the length (ΔL) of the LDD region and the OFF current, and the relationship between the length (ΔL) of the LDD region and the ON current of the TFT having the actual LDD region. The sheet resistance in the LDD region is 100 kΩ.
/ □.

As shown in FIG. 25A, even if the LDD region is longer than 1 μm, there is no effect of reducing the OFF current.
This reflects the simulation results described above. Also,
As shown in FIG. 25B, when the LDD region was longer than 1.5 μm, the ON current could not be sufficiently secured and the ON current decreased. According to this result, by setting the range of the LDD region to 1 μm or more and 1.5 μm or less, it is possible to sufficiently secure the ON current and to keep the OFF current small. In the following embodiment, a TFT manufactured based on the simulation will be specifically described. Further, in the actual TFT manufacturing process, as will be described later, in order to ensure the above-mentioned LDD region, it can be determined by an alignment mark at the time of mask alignment.

(Embodiment 2-1) FIG. 26 is a simplified cross-sectional view of a thin film transistor according to Embodiment 2-1. FIG. 27 is a schematic plan view of FIG.

Embodiment 2-1 shows an example in which the present invention is applied to an n-channel thin film transistor. This thin film transistor (hereinafter, referred to as TFT) 101
A polycrystalline silicon layer 103 having a thickness of 500 °, a gate insulating layer 104 made of SiO ₂ (silicon dioxide) having a thickness of 1000 °, a gate electrode 105 made of aluminum, and an interlayer made of SiO ₂ on a glass substrate 102. The insulating layers 106 are sequentially stacked. The gate electrode 105a is formed so as to be covered with a resist film 105b. Note that a metal film may be used instead of the resist film 105b.

The polycrystalline silicon layer 103 has a channel region 103 located immediately below the gate electrode 105a.
c and the source region 103a (n + layer) having a high impurity concentration
And a drain region (n + layer) 103b having a high impurity concentration
And a low concentration impurity region (LDD region:
n-layer) 103d and 103e. The low-concentration impurity region 103d is interposed between the source region 103a and the channel region 103c, and
03e denotes a drain region 103b and a channel region 103
c. These low concentration impurity regions 10
3d and 103e are gate electrodes 1 of the resist film 105b.
It is located immediately below the portions 105b1 and 105b2 protruding from 05a. Therefore, the bonding surface between the low-concentration impurity region 103d and the source region 103a is
1 (left end face in FIG. 1), and the junction surface between the low-concentration impurity region 103d and the channel region 103c almost coincides with the end face of the gate electrode 105a (left end face in FIG. 1). Further, the bonding surface between the low concentration impurity region 103e and the drain region 103b is
1 (right end face in FIG. 1), and the junction surface between the low-concentration impurity region 103d and the channel region 103c almost coincides with the end face of the gate electrode 105a (right end face in FIG. 1). In the present invention, the length ΔL of the low-concentration impurity region is 1 μm or more and 1.5 μm or less,
The channel width W is set to 5 μm.

The TFT 101 is further provided with a source electrode 107 and a drain electrode 108 made of, for example, aluminum. The source electrode 107 is formed in a contact hole 109 a formed in the gate insulating layer 104 and the interlayer insulating layer 106. Through the source region 103a
The drain electrode 108 is connected to the drain region 103b via a contact hole 109b formed in the gate insulating layer 104 and the interlayer insulating layer 106.

Next, a method for manufacturing a thin film transistor according to Embodiment 2-1 of the present invention will be described. FIG. 28 and FIG. 29
Is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to Embodiment 2-1 of the present invention, and FIG. 30 is a flowchart showing a method for manufacturing a thin film transistor according to Embodiment 2-1 of the present invention.

(1) First, an a-Si layer 105 having a thickness of 500 ° is formed on a glass substrate 102 by a plasma CVD method.
Is deposited, and then a dehydrogenation treatment is performed at 400 ° C. (FIG. 28A). The purpose of this dehydrogenation treatment is to prevent ablation of the Si film due to desorption of hydrogen during crystallization. In addition, the process of forming a-Si can use processes other than plasma CVD, such as low pressure CVD and sputtering. Also, a polysilicon film can be directly deposited by using plasma CVD or another method. In this case, a later-described laser annealing step becomes unnecessary.

(2) Next, the a-Si layer 1 is subjected to laser annealing using an excimer laser having a wavelength of 308 nm.
The polycrystalline silicon layer 116 is formed by performing melt recrystallization (p-Si conversion) of No. 15 (FIG. 28B).

(3) Next, the polycrystalline silicon layer 116 is islanded into a predetermined shape to form the polycrystalline silicon layer 103 (FIG. 28C).

(4) Then, a SiO ₂ (silicon dioxide) layer having a thickness of 1000 ° and serving as a gate insulating layer 104 is formed on the glass substrate 102 so as to cover the polycrystalline silicon layer 103 (FIG. 28). (D)).

(5) Next, a metal layer 117 made of aluminum, which will be the gate electrode 105a, is formed (FIG. 28E).

(6) Next, the metal layer 117 is patterned into a predetermined shape to form the gate electrode 105a (FIG. 2).
8 (f)).

(7) Next, the first impurity doping is performed using the gate electrode 105a as a mask (FIG. 28 (g)). Specifically, phosphorus ions are doped as impurities by an ion doping method. Thus, the channel region 103c located immediately below the gate electrode 105a is a region where impurities are not doped. Then, the regions A and B of the polycrystalline silicon layer 103 excluding the channel region 103c become n- layers doped with impurities. In this case, the doping acceleration voltage was 80 kV, the beam current density was 1 μA / cm ^2, and high acceleration and low concentration n
This is for creating a mold area.

(8) Next, a photoresist 118 is formed to cover the gate electrode 105a (FIG. 28).
(H)).

(9) Next, the photoresist 118 is patterned to form a resist film 105b (FIG. 29).
(A)). Here, regarding the step (9), FIGS.
This will be described in detail with reference to FIG. FIG. 31 is a schematic cross-sectional process diagram illustrating a process of forming an LDD region, and FIG.
A perspective view of the photomask and the substrate, FIG.
FIG. 34 is a schematic sectional view of the thin film transistor after forming the LDD region.

As shown in FIG. 7, the photomask 140 and the substrate 102 are arranged to face each other, and a positioning light source (not shown) is arranged above the photomask 140. A laser beam is incident on the alignment marks 141 and 142 formed on the photomask 140 and the substrate 102 from the alignment light source, and the alignment is performed by reading the position signal of each alignment mark.

At a predetermined position of the photomask 140 (102 corners of the photomask), a substantially square alignment mark 141 is formed. At the center of the photomask 140, a pattern (not shown) of a shielding film to be transferred to the substrate 102 is formed.

On the glass substrate 102, alignment marks 142 are formed at positions corresponding to the alignment marks 141. The alignment mark 142
Is a substantially square transparent area surrounded by a black area. Although not shown, the shape of the alignment marks 141 and 142 is not limited to a square shape, and may be, for example, a circular shape.

As shown in FIG. 33A, when the position of the photomask 140 and the position of the substrate 102 are not displaced, the alignment mark 141 formed on the photomask 140 is formed on the substrate 102. LDD at the center of the transparent area of the alignment mark 142
When the region is formed, the LDD region 103d
The length ΔL of 3e is set to be 1.25 μm.

The substrate 102 and the photomask 14
0 is shifted, and if the alignment mark 141 is not included in the alignment mark 142, the LDD
It can be seen that the length of the region is greater than 1.5 μm,
Therefore, in such a case, the alignment mark 142
The position of the substrate and the photomask is adjusted so that the alignment mark 141 is inserted into the inside. Even if the alignment mark 141 is aligned with the center of the alignment mark 142, actually, as shown in FIG. However, in the case of the present invention, since the accuracy of the alignment device is ± 0.25 μm, the alignment mark 41 is included in the alignment mark 42.
Can be located. In this way,
As shown in FIG. 34, the formed LDD regions 3d and 3e
Can be made within the range of 1 to 1.5 μm. The accuracy of the positioning device is ± 0.25 μm, but if a more accurate positioning device is used, L
Variations in the DD region can be further reduced.

Next, the step of aligning the substrate and the photomask will be described.

As shown in FIG. 31A, the gate electrode 1
A photoresist serving as a shielding film is formed on 05a.

Next, as shown in FIGS. 31 (b) and (c), the photoresist is exposed through a photomask 140, developed, and developed to form a predetermined patterned shielding film 10.
5b is formed.

In this case, as described above, the exposure is performed after confirming that the alignment mark 141 is included in the transparent portion of the alignment mark 142.

(10) Next, as shown in FIG. 29B, a second impurity doping is performed using the resist film 105b as a mask. Specifically, phosphorus ions are doped as impurities by an ion doping method. The doping acceleration voltage in this case is 12 kV, the beam current density is 0.5 μA / cm ^2, and an n-type region with low acceleration and high concentration is formed.

As a result, ions are doped into a region of the polycrystalline silicon layer 103 except a region located immediately below the resist film 105b. Therefore, the regions A, in which impurities have already been doped by the first ion doping,
Of B, a region which is not covered with the resist film 105b (corresponding to the source region 103a and the drain region 103b) is further doped with impurities, and becomes a high impurity concentration region (n + layer). On the other hand, in the regions A and B, which are covered with the resist film 105b (corresponding to the low-concentration impurity regions 103d and 103e), no impurities are doped by the second ion doping, and the low-concentration impurity regions (N-layer). Thus, a low concentration impurity region 103d (n− layer) is formed between the source region 103a (n + layer) and the channel region 103c,
Further, a low-concentration impurity region 103e (n− layer) is provided between the drain region 103b (n + layer) and the channel region 103c.
Can be formed. Moreover, the gate electrode 105a
Performs the first ion doping with the mask as a mask,
Further, since the second ion doping is performed using the resist film 5b as a mask, the source region 103a, the low-concentration impurity regions 103d and 103e, and the drain region 103 are formed.
b can be formed in a self-aligned manner, and the overlapping portion of the gate electrode 5 and the source region 103a and the gate electrode 1
An overlapping portion between the region 05 and the drain region 103b can be suppressed to a small size that cannot be taken into consideration. Therefore, LD
A thin film transistor in which the length of the D region is 1 to 1.5 μm can be formed, the OFF current can be reduced, and the decrease in the ON current can be suppressed as much as possible.

(11) Next, an interlayer insulating layer (SiOx)
The film 106 is formed (FIG. 29C).

(12) Next, contact holes 109a, 109 are formed in the interlayer insulating layer 106 and the gate insulating layer 104.
b is opened (FIG. 29D).

(13) Then, a metal layer of, for example, Al or the like is formed in the contact holes 109a and 109 by sputtering.
9b, and the upper portion of the metal layer is patterned into a predetermined shape to form a source electrode 107 and a drain electrode 108 (FIG. 29E). Thus, the TFT 101 is manufactured.

In the above example, the n-channel TFT has been described, but the p-channel TFT can be manufactured by the same manufacturing process.

FIG. 35 shows the voltage / current characteristics of the thin film transistor manufactured by the above-described manufacturing method. Further OFF
FIG. 36 shows the variation of the current in the substrate surface.

As shown in FIG. 35, the present embodiment 2-1
Since the TFT 101 (graph L3) according to (1) has a small LDD region of 1 to 1.5 μm, which is a high resistance region, a stable large ON current and small OFF current can be secured.

It goes without saying that if the alignment accuracy of the aligner is improved, the length of the LDD region can be further reduced. By increasing the carrier concentration in the n− region, the region to which the electric field is applied becomes smaller, but the peak value of the electric field becomes higher, so that the OFF current increases.

FIG. 37 shows a result of simulating the Vg-Id characteristics of the thin film transistor using the concentration of the LDD region as a parameter.

When the sheet resistance in the LDD region is 20 kΩ / □ or less, the OFF current sharply increases. Therefore, the sheet resistance in the n- region needs to be at least 20 kΩ / □ or more. On the other hand, the sheet resistance in the LDD region is 100 kΩ /
In the case of □ or more, the ON current of the transistor decreased, and the operation of the panel became unstable. Therefore, it is desirable that the range of the sheet resistance in the LDD region is not less than 20 kΩ / □ and not more than 100 kΩ / □.

[0177] In addition, the first impurity doping by an acceleration voltage of 30kV or less and the beam current density than 10kV is an ion doping method in 0.05 A / cm ² or more 1 .mu.A / cm ² or less slow, ion doping Since the acceleration voltage of ions at the time is low, damage during doping can be reduced.

Even when the resist is used as a mask at the time of the first impurity doping, the resist can be removed cleanly without deterioration.

Alternatively, in the second impurity doping, the accelerating voltage is 30 kV or more and the beam current density is 1 μA / cm.
It is also possible to use a high-speed ion doping method of ² or more to implant sufficient ions into polysilicon even at the time of the second ion doping.

In the present embodiment 2-1, the TFT 10
1, the length ΔL of the LDD region is 1 μm or more and 1.5
μm or less, the source-drain voltage Vlc is 6 V,
This is performed under the condition that the channel width W is 6 μm. by the way,
Generally, the OFF current is determined by the electric field between the source and the drain, and Vlc is applied only to the channel region / LDD region. Therefore, the intensity of the electric field is expressed as Vlc / ΔL (Solid State Electron, 38, 2075 (1995), and the strength of the electric field is expressed by the following equation: 4 × 10 ⁶ <Vlc / ΔL <6 × 10 ⁶

Since the OFF current is proportional to the channel width W, the length ΔL of the LDD region and the source current
The relationship between the drain-to-drain voltage Vlc and the channel width W can be expressed by the following equation (3). ΔL> (W · Vlc) / 36 (3)

The meaning of equation (3) will be described. T
When the size of the FT is reduced, the values of ΔL and W are reduced, and accordingly, the source-drain voltage Vl
c decreases. Table 2 shows the characteristics of the TFT in which the length ΔL of the LDD region, the source-drain electrode Vlc, and the channel width W are changed.

[Table 2]

As shown in Table 2, in Experimental Examples 1 to 5 and 7 (that is, those satisfying the expression (1)), the OFF current can be suppressed, but in Experimental Example 6 (that is, (3) ) That does not satisfy the expression cannot suppress the OFF current.

The channel width of the channel region is W
In this case, the relationship between the length ΔL of the LDD region and the channel width L and channel width W of the channel region can be expressed by the following equation (4 ′). ΔL <3 · (W / L) (4 ′)

The above equation (4) shows the limitation of the ON current, which is a condition derived from the fact that the ON current is proportional to W / L. The condition of the ON current is W / L = 0.5. Is derived from the experimental result that ΔL decreases below 1.5 μm. Then, as shown in Table 1, in Experimental Examples 1, 3, 4, and 6 satisfying the above equation (4), the ON current could be secured.

As a preferable condition for securing the ON current further than the above equation (4 '), the ON current can be secured by the following equation (4). ΔL <1.5 · (W / L) (4)

As described above, when the thin film transistor is turned off, the low-concentration impurity region becomes a high-resistance layer in which carriers are depleted, so that the OFF current can be reduced.
Then, the guideline for the length of the LDD region can be determined from the above equation (3), and it is not necessary to secure the LDD region more than necessary to reduce the OFF current. In addition, when the above formula (3) further satisfies the formula (4), when the thin film transistor is turned on, electrons serving as carriers are accumulated in the low concentration impurity region below the gate electrode by the action of an electric field from the gate electrode. The region becomes a low resistance region, and the ON current does not decrease. Therefore, the thin-film transistor satisfying the expressions (3) and (4) can secure a sufficient ON current and can reduce the OFF current. Although the channel width is set to 5 μm, when the channel width W of the channel region is reduced to 2 μm or less,
In particular, the above-mentioned relational expressions (3) and (4) are effective guidelines in manufacturing a thin film transistor.

(Embodiment 2-2) In Embodiment 2-2, when the resist film 105b is formed in the manufacturing process of Embodiment 2-1, the LDD region is formed by using the alignment mark. A thin film transistor in which the length of the LDD region is within the above-mentioned range by an inspection process in which the length of the LDD region satisfies the condition of 1 μm or more and 1.5 μm or less without setting the length of the LDD region to 1 μm or more and 1.5 μm or less Can be obtained. Therefore, it is possible to secure a sufficient ON current and to keep the OFF current small.
In the present embodiment 2-2, the LDD region is not limited to 1 μm or more and 1.5 μm or less, but falls within the range of the expressions (3) and (4) described in the embodiment 2-1. be able to.

(Other Items) Embodiments 2-1 and 2
In -2, the low concentration impurity region having one type of concentration has been described, but the present invention is not limited to this, and a plurality of low concentration impurity regions having different concentration differences may be provided. That is, by forming the low-concentration impurity region from a plurality of junction regions in which the impurity concentration gradually decreases toward the channel region, the impurity concentration can be changed in multiple steps, so that the semiconductor The concentration of the electric field in the layer can be further reduced.

The low-concentration impurity region may be formed only between the drain region and the channel region. With such a configuration, the effect of reducing the OFF current and the like can be obtained, and the area of the thin film transistor can be reduced. It is possible to reduce the size. Further, such a thin film transistor can be applied to a device other than a liquid crystal display device.

In the C-MOS inverter circuit, at least the n-channel thin film transistor of the p-channel thin film transistor and the n-channel thin film transistor can be constituted by the thin film transistors according to the embodiments 2-1 and 2-2.

[0192]

As described above, according to the structure of the present invention, the object of the present invention can be sufficiently achieved.

That is, in the first invention group, a sufficient ON current can be ensured, and the photoconductive current at the time of light irradiation can be kept small, so that the power consumption is small, and the reliability and the characteristics are improved. The effect is extremely large.

In the second invention group, the ON current can be sufficiently ensured and the OFF current can be suppressed to a small value, so that the power consumption is small. Can be provided.

[Brief description of the drawings]

FIG. 1 shows a channel width W of a channel region constituting a TFT.
And photoconductive current (OFF current: I _OFF) And the relationship
5 is a graph showing the relationship between backlight brightness and photoconductive current.
You.

FIG. 2 is a graph showing a result of simulating an electric field when a TFT is turned off.

FIG. 3 is a graph showing the relationship between sheet resistance and depletion layer width obtained by simulation.

FIG. 4 is a graph showing a measurement result of a relationship between a depletion layer width obtained by a simulation (when W = 4 μm) and a photoconductive current at a sheet resistance corresponding to the depletion layer width.

FIG. 5 is a diagram showing an equivalent circuit of an active matrix.

FIG. 6 is a graph showing a simulation result of a pixel voltage loss.

FIG. 7 is a schematic cross-sectional view of a liquid crystal display device using the thin film transistor according to Embodiment 1-1 of the present invention as a pixel switching element.

FIG. 8 is a schematic sectional view of a thin film transistor according to Embodiment 1-1 of the present invention. It is a schematic diagram for explaining.

FIG. 9 is a schematic plan view of FIG.

FIG. 10 is a schematic sectional view showing the method for manufacturing the thin film transistor according to Embodiment 1-1 of the present invention.

FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor.

FIG. 12 is a flowchart showing a method for manufacturing a thin film transistor.

FIG. 13 is a graph showing voltage / current characteristics of a thin film transistor.

FIG. 14 is a graph showing a variation in an OFF current in a substrate surface.

FIG. 15 is a graph showing a result of simulating the Vg-Id characteristics of a thin film transistor using the concentration of an n-type region as a parameter.

FIG. 16 is a graph showing a result of simulating an electric field when a TFT is turned off.

FIG. 17 is a schematic sectional view showing the method for manufacturing the thin film transistor according to Embodiment 1-2 of the present invention.

FIG. 18 is also a schematic sectional view showing the method for manufacturing the thin film transistor.

FIG. 19 is a plan view showing a wiring pattern of a C-MOS inverter using the thin film transistor according to Embodiment 1-3 of the present invention.

FIG. 20 is an equivalent circuit diagram of FIG. 19;

21 is a sectional view taken along the line X-X 'of FIG.

FIG. 22 shows on / off in a C-MOS inverter.
7 is a graph showing operating points in a bias state of the n-ch transistor at the time.

FIG. 23 shows Vg-Id when the LDD region is changed from 0.5 μm to 3 μm using sheet resistance as a parameter.
9 is a graph showing a result of simulating characteristics.

FIG. 24 shows TFs in a channel region and an LDD region.
When T is turned off (Vg = −10 V, Vd = 6
The result of simulating the electric field at V) is shown.

FIG. 25 is a graph showing the relationship between the length (ΔL) of the LDD region and the OFF current and the length (ΔL) of the LDD region and the ON current of a TFT having an actual LDD region.

FIG. 26 is a simplified cross-sectional view of the thin film transistor according to Embodiment 2-1.

FIG. 27 is a schematic plan view of FIG. 26;

FIG. 28 is a schematic sectional view showing the method for manufacturing the thin film transistor according to Embodiment 2-1 of the present invention.

FIG. 29 is a schematic cross-sectional view showing the method for manufacturing the thin film transistor according to Embodiment 2-1 of the present invention.

FIG. 30 is a flowchart showing a method for manufacturing a thin film transistor according to Embodiment 2-1 of the present invention.

FIG. 31 is a schematic cross-sectional process drawing explaining a process of forming an LDD region;

FIG. 32 is a perspective view of a photomask and a substrate.

FIG. 33 is a plan view of the same.

FIG. 34 is a schematic sectional view of a thin film transistor after an LDD region is formed.

FIG. 35 is a graph showing voltage / current characteristics of the thin film transistor according to Embodiment 2-1.

FIG. 36 is a graph showing variation in the off-state current of the thin film transistor in the substrate surface according to Embodiment 2-1.

FIG. 37 shows TF obtained by using the concentration of the LDD region as a parameter.
6 is a graph showing a result of simulating the Vg-Id characteristic of T.

FIG. 38 is a schematic diagram for explaining a luminance gradient and crosstalk.

[Explanation of symbols]

1: thin film transistor 2: glass substrate 3: polycrystalline silicon layer 3a: source region 3b: drain region 3c: channel region 3d, 3e: low concentration impurity region (LDD region: n-layer) 4: gate insulating layer 5a: gate electrode 5b: resist film 6: interlayer insulating layer 7: source electrode 8: drain electrode 9a / 9b: contact hole 15: a-Si layer 16 polycrystalline silicon layer 17: metal layer 18: photoresist 22: polysilicon 23: silicon oxide Film 24/24: Contact hole 25: Gate electrode 26: Gate electrode pattern 27: Drain electrode 30: Interlayer insulating film 31: Source electrode 32: Drain electrode 50: Liquid crystal display 51: Liquid crystal panel 52: Backlight 53: Polarizing plate 54b: glass substrate 55: pixel electrode 56: alignment film 57: liquid crystal layer 8: Common electrode 101: Glass substrate ΔL: Length of LDD region L: Length of channel region W: Width of channel region 101: Thin film transistor 102: Glass substrate 103: Polycrystalline silicon layer 103a: Source region 103b: Drain region 103c : Channel regions 103d and 103e: low concentration impurity regions (LDD regions:
n-layer) 104: gate insulating layer 105a: gate electrode 105b: resist film 106: interlayer insulating layer 107: source electrode 108: drain electrode 109a / 109b: contact hole 115: a-Si layer 117: metal layer 118: photoresist 122: n-channel TFT 123: p-channel TFT 124: polycrystalline silicon layer 125: gate electrode 126: source electrode 127: drain electrode 140: photomask 141/142: alignment mark

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Okada 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Terms (Reference) 2H091 FA41Z GA02 GA13 LA16 2H092 JA24 JA32 JA49 JB31 KA05 MA05 MA08 MA13 MA17 MA24 MA27 MA30 NA21 PA13 5F110 AA06 BB02 BB04 CC02 DD02 EE03 EE34 FF02 GG02 GG13 GG25 GG12 GG23 GG23 GG23 GG23 GG43 GG43 GG23 GG43 GG43 GG43 GG01 PP35 QQ11

Claims (18)

[Claims] A polycrystalline silicon semiconductor layer having a channel region and a source region and a drain region disposed on both sides of the channel region, wherein a depletion is provided between the channel region and the drain region A layer is formed, and the width of the depletion layer and the photoconductive current generated when the channel region is irradiated with light have a proportional relationship, and in order to keep the photoconductive current within a predetermined allowable value, depletion is caused. A thin film transistor having a structure in which a width of a layer is equal to or less than a value obtained based on the proportional relationship. 2. The sheet resistance of the drain region is R (k
Ω / □), and the channel width of the channel region is W (μm).
2. The thin film transistor according to claim 1, wherein the relationship of Expression (1) is satisfied. (R + 30) · W <A … (1) 3. The sheet resistance of the drain region is R (k
Ω / □), and the channel width of the channel region is W (μm).
3. The thin film transistor according to claim 2, wherein the relationship of Expression (2) is satisfied. (R + 30) · W <1 × 10 ³ (2) 4. A channel width W of said channel region is 2 μm.
4. The thin film transistor according to claim 3, wherein m is equal to or less than m. 5. A sheet resistance of the drain region is 20 k.
The thin film transistor according to claim 3, wherein the resistance is not less than Ω / □ and not more than 100 kΩ / □. 6. A thin film transistor provided as a switching element in a liquid crystal display device, comprising: a channel region; and a polycrystalline silicon semiconductor layer in which a source region and a drain region are arranged on both sides of the channel region. The brightness of the backlight constituting the display device is set to 20.
In the case where the impurity concentration is not less than 00 (cd / m ² ), the impurity concentration is at least one of between the source region and the channel region or between the drain region and the channel region. A thin film transistor, wherein a low-concentration impurity region having a very low concentration is formed, and a length ΔL of the low-concentration impurity region is 1.0 μm or less. 7. A channel region, and a source region and a drain region disposed on both sides of the channel region are formed, and at least one of between the source region and the channel region or between the drain region and the channel region. On the other hand, a thin film transistor having a polycrystalline silicon semiconductor layer in which a low concentration impurity region having an impurity concentration lower than that of a source region and a drain region is formed, wherein the length of the low concentration impurity region is ΔL (μm),
A thin film transistor which satisfies the relationship of Expression (3) when a drain-to-drain voltage is Vlc (V) and a channel width of the channel region is W (μm). ΔL> (W · Vlc) / 36 (3) 8. The channel length of the channel region is L (μ
8. The thin film transistor according to claim 7, wherein when m), the relationship of Expression (4) is satisfied. ΔL <1.5 · (W / L) (4) 9. A channel width W (μ) of the channel region.
9. The thin film transistor according to claim 8, wherein m) is 2 μm or less. 10. The thin film transistor according to claim 8, wherein the low-concentration impurity region has a sheet resistance of 20 kΩ / □ or more and 100 kΩ / □ or less. 11. The thin film transistor according to claim 10, wherein the low concentration impurity region is formed only between the drain region and the channel region. 12. A liquid crystal display device comprising: a liquid crystal panel unit including the thin film transistor according to claim 1 as a switching element; and a backlight unit that supplies light to the liquid crystal panel unit from a back surface side. When the sheet resistance of the drain region is R (kΩ / □), the luminance of the backlight portion is B (cd / m ² ), and the channel width of the channel region is W (μm), the following equation (5) is used.
A liquid crystal display device characterized by satisfying the following relationship: (R + 30) ・ B ・ W <C … (5) 13. The sheet resistance of the drain region is set to R
(KΩ / □), and the brightness of the backlight portion is represented by B (cd /
13. The liquid crystal display device according to claim 12, wherein, when m ² ) and the channel width of the channel region is W (μm), the relationship of Expression (6) is satisfied. (R + 30) · B · W <1 × 10 ⁶ (6) 14. An EL device having a light emitting layer on a pixel electrode formed on a substrate having a thin film transistor and a counter electrode formed on the light emitting layer, wherein the thin film transistor is a thin film transistor according to claim 1. A thin film transistor,
An EL device, which satisfies the relationship of Expression (5) when the light intensity applied to the channel region of the thin film transistor is B (cd / m ² ). (R + 30) ・ B ・ W <C … (5) 15. The sheet resistance of the drain region is R
(KΩ / □), the light intensity applied to the channel region is B (cd / m ² ), and the channel width of the channel region is W
15. The EL display device according to claim 14, wherein the relationship of Expression (6) is satisfied when (μm) is set. (R + 30) · B · W <1 × 10 ⁶ (6) 16. A polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate; a gate insulating film forming step of forming a gate insulating film on the polycrystalline silicon semiconductor layer; A gate electrode forming step of forming a gate electrode in a pattern on an insulating film; an oxidizing step of oxidizing a side surface of the gate electrode to form a metal oxide film covering the side surface of the gate electrode; An impurity doping step of doping the layer with an impurity using the gate electrode as a mask, comprising: controlling the thickness of a metal oxide film formed in the anodic oxidation step; Characterized in that the length ΔL of the low concentration impurity region formed in step (a) is 1.0 μm or less. 17. A polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate; a gate insulating film forming step of forming a gate insulating film on the polycrystalline silicon semiconductor layer; A gate electrode forming step of forming a gate electrode in a pattern on an insulating film; a first impurity doping step of doping the polycrystalline silicon semiconductor layer with an impurity using the gate electrode as a mask; and a first impurity doping step Forming a shielding film on a semiconductor region doped with impurities, and forming the shielding film in a pattern by anisotropic etching; and using the shielding film as a mask in the polycrystalline silicon semiconductor layer. The source region and the channel region are doped by doping impurities so that a difference in impurity concentration exists between the lower region of the shielding film and the other region. A low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region in at least one of the region and the drain region and the channel region. A method for manufacturing a thin film transistor, comprising: a second impurity doping step described below. 18. The method of manufacturing a thin film transistor according to claim 17, further comprising an inspection step of determining a low-concentration impurity region having a length ΔL of 1.0 μm or less as a non-defective product.