JP4144248B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a current mirror circuit in which variation in characteristics due to variation in processing accuracy in a semiconductor manufacturing process is suppressed.
[0002]
[Prior art]
FIG. 6 shows a planar structure of a conventional semiconductor device. In FIG. 6, two gate electrodes 3 are formed in parallel in the active region, a source diffusion layer 5 is formed in a region sandwiched between the two gate electrodes 3, and the two gate electrodes 3 are formed on the source diffusion layer 5. A drain diffusion layer 4 is formed in the opposite region. This prior art semiconductor device is a mirror MOSFET in which a MOSFET structure is formed symmetrically with respect to a source electrode (not shown).
[0003]
2 is a cross-sectional view taken along the line CC ′ of FIG. In FIG. 2, reference numeral 1 is a silicon semiconductor substrate, 2 is a gate oxide film, 7a is a source electrode, 7b is a drain electrode, 6 is an insulating interlayer film that insulates the gate oxide film 2 from the drain electrode 7b and the source electrode 7a , L 1 and L2 are MOSFET channel lengths. The structure shown in FIG. 2 is a current mirror circuit, and has a common source electrode 7a.
[0004]
FIG. 7 is an example of a circuit connection diagram of a current mirror circuit using a conventional semiconductor device. In FIG. 7, reference numeral 300 denotes a mirror MOSFET, 310 denotes one MOSFET in the mirror MOSFET 300, and 320 denotes the other MOSFET with respect to the MOSFET 310. Further, 30 is a drain terminal of the MOSFET 310, 31 is a drain terminal of the MOSFET 320, and 39 is a source terminal of the mirror MOSFET 300. In the current mirror circuit shown in FIG. 7, when the voltage of the same potential in addition to the drain terminal 30 and 31, the current flowing to the drain terminal 30, the current flowing to the drain terminal 31 is substantially the same value.
[0005]
FIGS. 3A to 3D are cross-sectional views of the manufacturing process up to the formation of the drain diffusion layer of the conventional semiconductor device. In the prior art semiconductor device, first, (a) an n-well diffusion layer is formed on a semiconductor substrate, then (b) the semiconductor substrate is oxidized to deposit a gate oxide film, and then a gate electrode material is formed on the gate oxide film. To deposit. (C) The gate electrode material is etched by an arbitrary photolithography technique to form a gate wiring. (d) A resist is patterned on the drain diffusion layer forming portion by arbitrary photolithography, and impurities are implanted. In FIG. 3D, reference numeral 8 denotes a photoresist patterned in the drain diffusion layer forming step by arbitrary photolithography.
[0006]
[Problems to be solved by the invention]
In the prior art, the resist 8 is removed when the drain diffusion layer is formed using the resist, the gate electrode, and the LOCOS as a mask in the impurity implantation step of the drain diffusion layer portion of FIG. As shown in FIG. 3D, a phenomenon has occurred in which impurities are implanted into the silicon surface directly under the gate electrode in the portion that has been formed.
[0007]
It has been found that this phenomenon is caused by variations in the thickness of the gate electrode member and in-plane variations. Further, due to the alignment accuracy of the resist 8, there also arises a problem that the channel lengths of the two MOSFETs having the MOS structure in line symmetry with respect to the source electrode are different. This is because the channel lengths of the MOSFET 310 and the MOSFET 320 in FIG. 7 are different, and the value of the current flowing through the drain terminal 30 and the drain terminal 31 of the current mirror circuit changes . That is, there arises a problem that a difference between two drain current values occurs.
[0008]
Since the current mirror circuit of the above-described conventional semiconductor device is used for the power supply voltage circuit of the IC, there is a problem that a failure of the IC power supply voltage is caused.
[0009]
The object of the present invention is to cause a problem in the current mirror circuit using the above-mentioned mirror MOSFET, that is, even in a circuit that requires an equivalent current value, the difference between the current values flowing through the semiconductor device due to the change in channel length is large. An object of the present invention is to provide a semiconductor device that does not become necessary .
[0010]
[Means for Solving the Problems]
A semiconductor device according to the present invention is a semiconductor device having a planar structure in which the channel width of a conventional mirror MOSFET is 0.50 times, and using a current mirror circuit in which the semiconductor devices are arranged in parallel, Circuit wiring and wiring structure in which the current value of the other transistor and the current value of the other transistor are the same.
[0011]
The semiconductor device of the present invention includes two gate electrodes formed in parallel in an active region, a source diffusion layer formed in a region sandwiched between the two gate electrodes, and the above-mentioned 2 for the source diffusion layer. A MOS structure semiconductor device having a drain diffusion layer formed in a region opposite to one gate electrode on the surface of a semiconductor substrate, wherein one of the two gate electrodes formed in parallel in the active region Are connected to each other, the other end is not connected, and two semiconductor devices having a MOS structure are juxtaposed in parallel, and the gate electrodes of the two semiconductor devices juxtaposed in parallel are commonly wired. In addition, the source diffusion layer is commonly wired by a source electrode extending in a strip shape, and one two drain diffusion layers of the two semiconductor devices arranged in parallel are commonly wired, and the other semiconductor Equipment The drain diffusion layer is a common wiring circuit, the drain-side two terminals are arranged on the opposite side of the source-side terminal with the gate electrode in between, and the drain electrode is a strip-shaped extension of the source electrode. Four symmetrical axes are arranged, two opposing drain electrodes are connected to each other, and an electrode pattern extends perpendicularly from the center of the source electrode toward the source side terminal. It is characterized by being arranged with the electrode pattern directed from the center of the source electrode at a right angle to the terminal on the source side as the axis of symmetry.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, the case of a P-channel MOSFET will be described as an example, but the same applies to an N-channel MOSFET.
[0013]
FIG. 1 is a plan view of the semiconductor device according to the present embodiment before drain / source electrode wiring. In FIG. 1, symbols W1 and W2 denote channel widths of the mirror MOSFETs 100 and 200, respectively. The semiconductor device of this embodiment has a mirror MOSFET 100 whose channel width is half that of the prior art MOSFET shown in FIG. 6 and whose other dimensions are about the same as those of the prior art MOSFET shown in FIG. The mirror MOSFET 200 having the same structure as the mirror MOSFET 100 is arranged in parallel. As shown in FIG. 1, in this embodiment, two gate electrodes 3 are arranged in parallel to the active region, one end of which is connected, and the other end is not connected. Further, as shown in FIG. 1, two gate electrodes 3 in which two active regions arranged in the vertical direction are arranged in parallel are connected. Although not shown in FIG. 1, the source electrode is disposed in a portion that covers the space between the parallel portions of the two gate electrodes connected to the one end.
[0014]
The semiconductor device of this embodiment is manufactured by the same process as that of the prior art semiconductor device shown in FIG. 3, and includes an arbitrary photolithography pattern in the LOCOS forming step, the gate electrode forming step, and the drain / source electrode forming step. Has changed. The cross-sectional structures of AA ′ and BB ′ in FIG. 1 are the same as the cross-sectional structure of the conventional semiconductor device CC ′ in FIG.
[0015]
FIG. 4 is an example of a circuit connection diagram using the semiconductor device of this embodiment. The semiconductor device of this embodiment is a mirror MOSFET 100 and a mirror MOSFET 200. 4, reference numeral 110 and 120 corresponds to a MOSFET T in MOSFET100 mirror of FIG. 1, reference numeral 210 and 220 corresponds to MOSFET in MOSFET200 mirror of FIG. Terminals 20 and 21 are terminals on the drain side, and terminal 29 is a terminal on the source side. In this embodiment, the current mirror circuit is formed in this way.
[0016]
FIG. 8 is a plan structural view in which the wiring shown in FIG. 4 is performed on the semiconductor device of the present invention. The same reference numerals in FIGS. 4 and 8 correspond to the same components. As shown in FIG. 8, two terminals 20 and 21 on the drain side are arranged on the opposite side to the terminal 29 on the source side with the gate electrode 3 interposed therebetween. Further, four drain electrodes 7b are arranged with the source electrode 7a extending in a strip shape as the axis of symmetry, and two opposing drain electrodes are connected. Further, an electrode pattern extends from the center of the source electrode 7a toward the source-side terminal 29 at a right angle. The drain electrode 7b is arranged with the electrode pattern directed from the center of the source electrode 7a at a right angle to the terminal 29 on the source side as an axis of symmetry.
[0017]
Since the MOSFETs 110, 120, 210, and 220 shown in FIG. 4 are formed by the same process, the dimensions, impurity concentrations, and the like other than the channel length are all the same or very close values. When the channel lengths corresponding to the MOSFETs 110, 120, 210, and 220 are L110, L120, L210, and L220, the relationship between the channel lengths is expressed by the following (Equation 1) depending on the alignment accuracy of the drain diffusion layer formation in FIG. It becomes like Formula or (Formula 2) Formula.
[0018]
L110 = L210 ≠ L120 = L220 (Equation 1)
L110 = L210 = L120 = L220 (Expression 2)
That is, MOSFETs 110 and 210 have the same semiconductor structure, and MOSFETs 120 and 220 are the same.
[0019]
Here, the current flowing through the terminal 20 in FIG. 4 and the terminal 30 in FIG.
[0020]
The drain current of the MOSFET is expressed by the following formulas (3) and (4).
[0021]
If VG-VT <VT:
ID = W / L · μpn · Cox [(VG−VT) −0.50 · VT ² ] (Equation 3)
When VG-VT ≧ VT:
ID = 0.50 · W / L · μpn · Cox (VG-VT) ² (Expression 4)
In equations (3) and (4), ID is drain current, VG is gate voltage, VT is threshold voltage, W is channel width, L is channel length, μpn is hole / electron mobility, Cox : A gate insulating film capacitance per unit area.
[0022]
In the equations (3) and (4) representing the drain current, VT = 1 [V], VG = 10 [V], μn = 700 [cm ² / V · s], Cox = 3.54 × 6 and 7 under the conditions of 10 ⁴ [pF / cm ² ], W1 and W2 = 21.0 [μm], W3 = 42.0 [μm], L110 + L120 = L210 + L220 = 10.0 [μm]. The relationship between the current value of the terminals 20 and 30 and the drain-source voltage when the channel length fluctuated was simulated using the structure of the related art shown and the structure of this example. The result is shown in FIG.
[0023]
FIG. 5 shows the case where the left and right MOSFETs are formed symmetrically in the element structure of FIG. 1 (L110 = L120 = 5.0 μm), and the channel length fluctuates ± 3.0 μm (L110 = 2 μm, L120 = 8 μm; L110 = 8 μm, L120 = 2 μm), the relationship between the current value at the terminal 20 and the drain-source voltage.
[0024]
FIG. 5 also shows the relationship between the current value at the terminal 30 and the drain-source voltage when the channel length L310 in FIG. 6 varies from 5 μm to ± 3.0 μm (L310 = 2 μm, 8 μm). The change amount ± 3.0 μm of the channel length in this embodiment is due to the fact that the control value in the manufacturing process is ± 3.0 μm.
[0025]
In the planar structure of the prior art, the difference between the current values I30 and I31 flowing through the terminal 30 in FIG. 7 and the terminal 31 is maximum | I30−I31 | ≈7.39 mA when the channel length varies ± 3.0 μm. there were. On the other hand, in this embodiment, the difference between the current values I20 and I21 flowing through the terminal 20 and the terminal 21 in FIG. 4 is | I20−I21 | = 0.0 mA, that is, I20 = I21 regardless of the variation of the channel length. Met. Thus, in this embodiment, the current value flowing through the terminal 20 and the current value flowing through the terminal 21 are equal, and there is no difference between the two drain current values in the current mirror circuit using the mirror MOSFET structure.
[0026]
According to FIG. 5, the current value I30 of the terminal 30 in the circuit diagram 7 using the semiconductor device having the planar structure of the prior art is I30 = 2.45 to 9.84 mA, and the change amount ΔI30 is ΔI30≈ 7.39 mA. On the other hand, in the present embodiment shown in FIG. 4, the current value I20 flowing through the terminal 20 is I20 = 3.93 to 6.15 mA, and the change amount ΔI20 is as small as ΔI20≈3.22 mA. The variation is reduced. As described above, according to the present embodiment, it is possible to reduce a phenomenon in which the current flowing through one drain terminal in the current mirror circuit of FIG. 6 varies due to variations in processing accuracy during device manufacturing.
[0027]
【The invention's effect】
According to the present invention, it is possible to reduce an error in a current value flowing through a semiconductor device due to a change in channel length due to a manufacturing error of the semiconductor device. Further, a circuit that requires an equivalent current value by two semiconductor devices can solve the problem that a difference between current values flowing through the semiconductor device increases due to a change in channel length.
[Brief description of the drawings]
FIG. 1 is a plan structural view of a semiconductor device of the present invention before forming a drain, a source electrode and an insulating interlayer film.
2 is a cross-sectional view taken along the lines AA ′ and BB ′ of FIG. 1 and is a cross-sectional view taken along the line CC ′ of FIG. 6;
FIG. 3 is a cross-sectional structure diagram of a manufacturing process until formation of a drain diffusion layer of a semiconductor device of the present invention.
FIG. 4 is a circuit connection diagram of a current mirror circuit using the semiconductor device of the present invention.
FIG. 5 is a VI characteristic (drain-source voltage-current) simulation result with respect to a change in channel length between the semiconductor device of the prior art and the semiconductor device of the present invention.
FIG. 6 is a plan structural view of a conventional semiconductor device before forming a drain, a source electrode, and an insulating interlayer film;
FIG. 7 is a circuit connection diagram of a current mirror circuit of a conventional semiconductor device.
8 is a plan structural view in which the wiring shown in FIG. 4 is provided in the semiconductor device of the present invention. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon semiconductor substrate, 2 ... Gate oxide film, 3 ... Gate electrode, 4 ... Drain diffused layer, 5 ... Source diffused layer, 6 ... Insulating interlayer film, 7a ... Source electrode, 7b ... Drain electrode, 8 ... Photoresist, 9 ... LOCOS, 20, 21, 29, 30, 31, 39 ... terminals, 100, 200, 300 ... mirror MOSFETs, 110, 120, 210, 220, 310, 320 ... MOSFETs.

Claims (1)

And two gate electrodes formed in parallel with the active region, two source diffusion layer formed in the area between the gate electrode said, on the opposite side of the two gate electrodes to said source diffusion layer A MOS structure semiconductor device comprising a drain diffusion layer formed in a region on a surface of a semiconductor substrate,
One end of two gate electrodes formed in parallel in the active region is connected, the other end is not connected, and two semiconductor devices having MOS structures are arranged in parallel. The gate electrodes of the semiconductor devices arranged in parallel are commonly wired, and the source diffusion layer is commonly wired by the source electrode extending in a strip shape , and further, the two semiconductor devices arranged in parallel are arranged. One drain diffusion layer is commonly wired, and the other drain diffusion layer of the other semiconductor device is commonly wired, and the two drain-side terminals are opposite to the source-side terminals across the gate electrode. The four drain electrodes are arranged with the source electrode extending in a band shape as the axis of symmetry, and two opposing drain electrodes are connected to each other. The electrode pattern extends from the portion at a right angle toward the source side terminal, and the drain electrode is arranged with the electrode pattern at a right angle from the central portion of the source electrode toward the source side terminal as an axis of symmetry. A featured semiconductor device.

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