JP2007258568A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce resist (mask) required for pocket injection treatment for the manufacturing method of a semiconductor device for performing diffusion treatment of impurities by using pocket injection. <P>SOLUTION: The manufacturing method of a semiconductor device includes a process for performing pocket injection by oblique injection from at least two directions. Resist 27 for pockets in which a source (S) side is open and a drain (D) side is masked is used for at least two MOSFET (Tr<SB>1</SB>, Tr<SB>2</SB>) sets, in which gate (G) directions are in parallel and sources (S) face in a process for performing pocket injection, and pockets are collectively injected to a plurality of source areas by the resist 27 for pockets. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that performs impurity diffusion processing using pocket implantation.

  As a field effect transistor mounted on a semiconductor integrated circuit device, for example, an insulated gate field effect transistor called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is known. This MOSFET is widely used as a circuit element constituting an integrated circuit because it has a feature that it is easily integrated.

  In addition, in order to increase the speed and reduce the power consumption, development of a fine transistor with a shortened gate length is in progress. If the MOSFET is miniaturized while keeping the power supply voltage constant, the electric field in the vicinity of the drain is increased, which causes a problem of deterioration in reliability due to hot electrons.

  One method for reducing the reliability degradation due to hot electrons is to reduce the power supply voltage. However, in order to achieve both low voltage and high performance, the threshold value (threshold value) of the MOSFET must be lowered. When the threshold value of the MOSFET is lowered, there arises a problem that the off current of the MOSFET increases and the standby power of the LSI increases, and that the screening and testing of the LSI becomes difficult due to the increase of the off current.

  As a method of dealing with this reliability degradation due to hot electrons, the impurity concentration on the drain side of the channel region (source-drain passage) of the MOSFET is made lower than the impurity concentration on the source side, that is, the p-type halo layer is made asymmetric. There is a method of relaxing the drain electric field (see Patent Document 1). The halo layer is also called a pocket layer, and both indicate the same content.

  FIG. 1 shows a MOSFET manufacturing method using the pocket implantation technique disclosed in Patent Document 1.

  First, as shown in FIG. 1A, a p-type well 3 (active region) is formed in a silicon substrate 1, and an element isolation region 2 is formed on the main surface of the silicon substrate 1 on which the p-type well 3 is formed. Form.

  Next, a thermal oxidation process is performed to form a gate insulating film 5 in an element formation region on the main surface of the silicon substrate 1, and then a polycrystalline silicon film having a predetermined thickness is formed on the entire main surface of the silicon substrate 1. Form. Subsequently, this polycrystalline silicon film is patterned to form two gate electrodes 6A and 6B adjacent to each other on the element formation region of the main surface of the silicon substrate 1 as shown in FIG. 2 and 3 are plan views of the silicon substrate 1. FIG. As shown in each figure, the gate electrodes 6A and 6B are arranged at a predetermined interval in the X direction of the main surface of the silicon substrate 1, and are formed to extend in the Y direction on the main surface of the silicon substrate 1. Is done.

  Next, channel impurities (for example, boron (B)) are ion-implanted into the element formation region of the main surface of the silicon substrate 1 to form the asymmetric p-type halo layer 4. This channel impurity ion implantation is performed in two steps.

  In the first ion implantation, as shown in FIG. 1C, after a first resist 7 is formed on the silicon substrate 1, ion implantation is performed obliquely from the upper left side of the silicon substrate 1 in the drawing. The direction of this ion implantation is performed at an acute angle with respect to the main surface of the silicon substrate 1.

  The first resist 7 has an opening 7A in the ion implantation region. As shown in FIGS. 1C and 2, the inner wall on the right side of the opening 7A in the drawing is close to the gate electrode 6A, and the inner wall on the left side in the drawing of the opening 7A is separated from the gate electrode 6B. Yes. The gate electrodes 6A and 6B are erected on the main surface of the silicon substrate 1 in the opening 7A of the first resist 7. For this reason, when ion implantation is performed obliquely, ion implantation is not performed at positions that are shaded by the first resist 7 and the gate electrodes 6A and 6B. FIG. 2 is a plan view of FIG.

  When the first ion implantation is completed, the first resist 7 is removed. Subsequently, a second resist 8 for second ion implantation is formed on the main surface of the silicon substrate 1. The second resist 8 has an opening 8A in a portion where ion implantation is performed.

  In the second ion implantation, as shown in FIG. 1D, after the first resist 7 is formed on the silicon substrate 1 as described above, the ion implantation is performed obliquely from the upper right side of the silicon substrate 1 in the drawing. Done. The direction of the second ion implantation is also performed at an acute angle with respect to the main surface of the silicon substrate 1.

  In the second resist 8, an opening 8A is formed in the ion implantation region. As shown in FIGS. 1D and 3, the inner wall on the right side of the opening 8A in the drawing is separated from the gate electrode 6A, and the inner wall on the left side in the drawing of the opening 8A is close to the gate electrode 6B. Yes. For this reason, when ion implantation is performed obliquely, ion implantation is not performed at positions that are shaded by the second resist 8 and the gate electrodes 6A and 6B. By doping the channel impurity in this way, an asymmetric p-type halo layer 4 is obtained as shown in FIG. FIG. 3 is a plan view of FIG.

  Next, an extension impurity is ion-implanted into the element formation region on the main surface of the silicon substrate 1 to form a source / drain extension 10 as shown in FIG. The sidewall spacer forming process, the source / drain forming process, the wiring process, and the like performed after the source / drain extension 10 is formed use well-known methods, and thus illustration and description thereof will be omitted. .

As described above, even in a MOSFET manufacturing method using the conventional pocket implantation technique, two MOSFETs (Tr that have an asymmetric channel impurity distribution in which channel impurities are not doped on the drain side of the channel region (indicated by D in the figure)) (Tr ₁ , Tr ₂ ) could be formed.
JP 2003-059493 A

  Incidentally, as described above, the MOSFET is formed on the silicon substrate 1 in a highly integrated manner. For this reason, the source and drain are also arranged in a complicated manner on the silicon substrate 1. For this reason, the drains or sources of a plurality of MOSFETs may be laid out close to each other on the silicon substrate 1.

  Conventionally, even when the drains or sources of a plurality of MOSFETs are laid out close to each other as described above, the p-type halo layer 4 is formed using the two resists 7 and 8 without considering this. I was going. As described above, the method using the plurality of resists 7 and 8 for pocket implantation has a problem that the manufacturing process becomes complicated and the manufacturing cost increases. Further, the line widths of the resists 7 and 8 become too thin, and there is a problem that it is difficult to further improve the degree of integration due to restrictions on fine processing accuracy.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing a resist (mask) required for pocket implantation processing.

  In order to solve the above-described problems, the present invention is characterized by the following measures.

The invention described in claim 1
A method for manufacturing a semiconductor device including a step of performing pocket implantation by oblique implantation from at least two directions,
In the step of performing the pocket injection,
The pocket implantation is performed using a resist having an opening on the source side and a mask on the drain side with respect to a set of two or more transistors in which the gate directions are parallel and the sources face each other.

The invention according to claim 2
A method for manufacturing a semiconductor device including a step of performing pocket implantation by oblique implantation from at least two directions,
In the step of performing the pocket injection,
The pocket implantation is performed using a resist having an opening on the drain side and a mask on the source side with respect to a set of two or more transistors in which the gate directions are parallel and the drain sides face each other.

The invention according to claim 3
A method of manufacturing a semiconductor device including a step of forming a source / drain extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
Impurity is implanted into a set of two or more transistors in which the gate directions are parallel and the sources are opposed to each other, using the resist having an opening on the source side and a mask on the drain side to form the source / drain extension region. It is characterized by.

The invention according to claim 4
A method of manufacturing a semiconductor device including a step of forming a source / drain extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
Impurity is implanted into a set of two or more transistors in which the gate directions are parallel and the drains face each other, using the resist having an opening on the drain side and a mask on the source side to form the source / drain extension region. It is characterized by.

The invention according to claim 5
A method for manufacturing a semiconductor device, comprising: a step of performing pocket implantation by oblique implantation from at least two directions; and a step of forming a source / drain extension region by implanting impurities on both sides of the gate electrode,
In the step of performing the pocket implantation, the pocket implantation is performed using a resist in which the source side is opened and the drain side is masked for a set of two or more transistors in which the gate direction is parallel and the sources face each other.
In the step of forming the source / drain extension region, impurities are implanted using the resist to form the source / drain extension region.

  According to the present invention, the number of masks (resist) required for performing pocket implantation can be reduced, so that a semiconductor device capable of extending hot carrier life and reducing junction leakage can be manufactured at low cost with few steps. Become. Further, from another viewpoint, since the processing accuracy of the resist necessary for pocket implantation can be afforded, further integration is possible.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings.

  4 and 5 are views for explaining a method of manufacturing a semiconductor manufacturing apparatus according to an embodiment of the present invention. In this embodiment, an example in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed as a field effect transistor mounted on a semiconductor integrated circuit device will be described. However, the application of the present invention is not limited to the MOSFET, but can also be applied to a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The present invention can also be applied to a field effect transistor installed on an SOI (Silicon on insulator).

  As described above, when a MOSFET is formed on the silicon substrate 1 in a highly integrated manner, the source and drain are also arranged in a complicated manner on the silicon substrate 1, and for this reason, different MOSFET drains (D ) Or the source (S) may be laid out in close proximity.

For example, the source (S) of the MOSFET (Tr ₁ ) and the source (S) of the MOSFET (Tr ₂ ) shown in FIG. 6 are arranged close to each other. At this time, the extending direction of the MOSFET (Tr ₁ ) gate 26A and the gate 26B of the MOSFET (Tr ₂ ) is in the direction of the arrow Y in the figure, and is configured in parallel with each other. The gate 26 is disposed such that the pair of gate electrodes 26 face each other. This embodiment is characterized in that ion implantation is performed with the same pocket resist 27 (mask) at the time of pocket implantation at the portion where the same type of electrodes face each other. A specific MOSFET manufacturing method will be described below.

  In order to manufacture the MOSFET manufacturing method, first, as shown in FIG. 4A, a p-type well 23 (active region) is formed in the silicon substrate 20. The silicon substrate 20 is a p-type substrate, and p-type wells 23 are formed by implanting, for example, boron (B) ions into the silicon substrate 20. Next, an element isolation region 22 that partitions an element formation region is formed on the main surface of the silicon substrate 1 on which the p-type well 23 is formed.

  In the element isolation region 22, a shallow groove is formed on the main surface of the P-type well 23, and then an insulating film made of, for example, a silicon oxide film is formed on the main surface of the P-type well 23 by the CVD method. The film is formed by planarization by CMP so that only the inside of the shallow groove remains.

  Next, a thermal oxidation process is performed to form a gate insulating film 25 made of, for example, a silicon oxide film in the element formation region on the main surface of the silicon substrate 20. Thereafter, a polycrystalline silicon film having a thickness corresponding to the height of the gate electrode 26 is formed on the entire surface of the silicon substrate 20 by the CVD method. At this time, conductive impurities are added to the polycrystalline silicon (this addition may be after the gate electrodes 26A and 26B are formed). This polycrystalline silicon film is patterned by photolithography and dry etching, and a large number of gate electrodes 26A and 26B forming a pair are formed on the silicon substrate 20. FIG. 4B shows a state in which the gate electrodes 26A and 26B are formed.

  By the way, when a MOSFET is formed on the silicon substrate 20, the formation position of the source (S) and the position of the drain (D) are determined in advance at the time of design. Therefore, in the present embodiment, a part of the source (S) and the drain (D) formed on the silicon substrate 20 where the sources or the drains face each other is detected in advance. In the present embodiment, for convenience of explanation, as shown in FIG. 4B, the source (S) is arranged so that the source (S) is opposed to each other in any of the illustrated gate electrodes 26A and 26B. To do.

  When the gate insulating film 25 and the gate electrodes 26A and 26B are formed as described above, a pocket resist 27 is subsequently formed on the main surface of the silicon substrate 20. The pocket resist 27 has a structure in which an opening 27A is formed by performing exposure and development processing after a photosensitive resin is disposed on the silicon substrate 20. The opening 27A is formed so that the gate electrodes 26A and 26B are located inside the opening 27A and the gate electrodes 26A and 26B are close to the inner wall of the opening 27A.

  Next, a channel impurity (for example, boron (B)) is ion-implanted into the element formation region of the main surface of the silicon substrate 20 to form an asymmetric p-type halo layer 24. Channel impurity ion implantation is performed in two steps.

  In the first ion implantation, as shown in FIG. 4C, a pocket resist 27 is formed on the silicon substrate 20 and then a pot implantation is performed in which ion implantation is performed obliquely from the upper left side of the silicon substrate 20 in the figure. Is done. The direction of ion implantation by the pot implantation is performed at an acute angle with respect to the main surface of the silicon substrate 1.

  The pocket resist 27 has an opening 27A in the ion implantation region. As shown in FIGS. 4C and 6, the inner wall on the right side of the opening 27A in the drawing is close to the gate electrode 26A, and the left inner wall in the drawing of the opening 27A is also close to the gate electrode 26B. Yes. That is, the pocket resist 27 is formed so as to cover the drain (D) formation region.

  For this reason, ion implantation is not performed in the portion covered with the pocket resist 27 (region where the drain (D) is formed) and the position shaded by the opening 27A (position near the gate electrode 26A). FIG. 6 is a plan view of FIG.

  When the first pocket implantation process (ion implantation process) is completed, a second pocket implantation process (ion implantation process) is subsequently performed. This embodiment is characterized in that the pocket resist 27 used in the first pocket implantation process is used as it is in the second pocket implantation process.

In the second ion implantation, as shown in FIG. 4D, the pocket resist 27 is used as it is, and the ion implantation is performed obliquely from the upper right side of the silicon substrate 20 in the drawing. The direction of the second ion implantation is also performed at an acute angle with respect to the main surface of the silicon substrate 1. However, even during the second pocket implantation, the drain (D) formation region is covered with the pocket resist 27, so that no ion implantation is performed. By doping the channel impurities in this way, as shown in FIG. 4D, the source (S) side of the gate 26A of the MOSFET (Tr ₁ ) and the source side (at the source side of the gate 26B of the MOSFET (Tr ₂ )) The asymmetric p-type halo layer 4 (channel impurity region) is obtained on both the D) side.

  As described above, in this embodiment, only one pocket resist 27 is used for the pocket implantation, and the first pocket implantation shown in FIG. Since the second pocket implantation can be performed, the number of resists (number of masks) necessary for pocket implantation can be reduced. As a result, it is possible to form a MOSFET capable of extending the hot carrier lifetime and reducing junction leakage at a low cost with a small number of steps. In addition, since the resist width can be increased compared to the conventional resists 7 and 8 shown in FIGS. 1 to 3, the processing accuracy of the resist necessary for performing the pocket implantation can be afforded. Integration is possible.

  When the formation process of the P-type halo layer 24 is completed as described above, the pocket resist 27 is removed, and subsequently, an extension source / drain extension resist 28 is formed. The source / drain extension resist 28 used in this embodiment has a configuration in which all of the extension forming regions are opened regardless of the source side and the drain side.

  Next, an extension impurity (for example, arsenic (As)) is ion-implanted into the element formation region on the main surface of the silicon substrate 20, and as shown in FIG. 4E, the extension 30 which is a low-concentration n-type diffusion layer. Form.

  Next, an insulating film made of, for example, a silicon oxide film is formed on the entire main surface of the silicon substrate 20 by a CVD method, and thereafter, the insulating film is subjected to anisotropic etching such as RIE, so that FIG. As shown, sidewall spacers 33 are formed on the side surfaces of each gate electrode 26.

Next, after an SD formation resist 34 is formed on the silicon substrate 20, an impurity (for example, As) is ion-implanted into an element formation region on the main surface of the silicon substrate 20 to form a high-concentration n-type diffusion layer 35. To do. Accordingly, as shown in FIG. 5B, two MOSFETs (Tr ₁ , Tr ₂ ) having an asymmetric channel impurity distribution in which the channel impurity is not doped on the drain side of the channel region (the p-type halo layer is not formed). Is obtained. Therefore, it is possible to improve the hot electron resistance of the MOSFETs (Tr ₁ , Tr ₂ ) without reducing the degree of integration.

  Next, the SD formation resist 34 is removed, and a resist 36 is newly formed on the main surface of the silicon substrate 20. The resist 36 has an opening 36 </ b> A at the position where the bias electrode 37 is formed. Then, an impurity (for example, boron (Bo)) is ion-implanted into the portion where the main surface between the pair of element isolation regions 22 of the silicon substrate 20 is exposed by using the resist 36, and a high-concentration P-type diffusion layer. Form. This high concentration P-type diffusion layer functions as a bias electrode 37 for applying a bias to the silicon substrate 20.

Next, the resist 36 is removed as shown in FIG. 5D, and the contact 38 connected to the source (S), drain (D), and bias electrode 37 as shown in FIG. A forming process is performed to manufacture a semiconductor device having MOSFETs (Tr ₁ , Tr ₂ ).

In the above-described embodiment, an example of manufacturing two MOSFETs (Tr ₁ , Tr ₂ ) having an asymmetric channel impurity distribution in which channel impurities are not doped on the drain side of the channel region (a p-type halo layer is not formed) is manufactured. As described above, it is also possible to form two MOSFETs having an asymmetric channel impurity distribution in which channel impurities are not doped (a p-type halo layer is not formed) on the source side of the channel region.

  In this case, pocket implantation is performed on a set of two or more MOSFETs (transistors) whose gate directions are parallel and whose drain sides face each other, using a pocket resist that is open on the drain (D) side and masked on the source (S) side. . At this time, as a specific manufacturing method, only the drain (D) and the source (S) are interchanged in the above-described embodiment, and the manufacturing is performed in the same process except that the types of ions to be implanted are different. be able to.

  Next, first to third modifications of the embodiment according to the present invention will be described with reference to FIGS. 7 to 9, the same components as those shown in FIGS. 4 to 6 used in the description of the above embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 7 is a diagram for explaining a first modification of the present invention. In the above-described embodiment, when the extension is formed, the extension 30 is collectively formed on the source side and the drain side by using one source / drain extension resist 28 (see FIG. 4E). ). For this reason, the impurity concentration of the extension 30, which is an n-type diffusion layer formed on the source side and the drain side, is set to be approximately equal.

  On the other hand, this modification is characterized in that the impurity concentration of the extension 30 is changed on the source side and the drain side. As a specific method, first, as shown in FIG. 7A, the first source / drain extension resist 29A in which the source (S) region is opened and the drain (D) region is masked is used as the main substrate of the silicon substrate 20. A source / drain extension 30A is formed in the source (S) region using the first source / drain extension resist 29A.

  Next, after removing the first source / drain extension resist 29A, the source (S) region is masked and the drain (D) region is opened as shown in FIG. A source / drain extension 30B is formed in the drain (D) region using the second source / drain extension resist 29B.

  By using this method, the impurity concentration of the source / drain extension 30A on the source (S) side and the source / drain extension 30B on the drain (D) side can be changed. Therefore, for example, by increasing the impurity concentration on the source (S) side, the electrical resistance of the source can be reduced, and the operating speed of the MOSFET to be formed can be improved.

  FIG. 8 is a diagram for explaining a second modification of the present invention. In the embodiment described above, an example in which the source (S) or the drain (D) faces each other in the direction of the arrow X in the drawing has been described. However, when a plurality of pairs facing the source (S) or the drain (D) are arranged in the arrow Y direction, a pocket resist 27 having an opening 27A that exposes them in a lump is formed. Thus, a method of performing pocket injection may be used.

  In the example shown in FIG. 8, four sources are collectively exposed from the pocket resist 27 through the opening 27A, and pocket implantation can be performed on these collectively.

  FIG. 9 is a diagram for explaining a third modification of the present invention. In the above-described embodiment, the example in which the source (S) or the drain (D) face each other in a completely straight line in the drawing has been described. However, the arrangement of the transistors is slightly different as in the example shown in FIG. The present invention can be applied even when there is a deviation.

  FIG. 10 is a diagram for explaining a fourth modification of the present invention. In each of the above-described embodiments, the example in which only the MOSFET is formed on the silicon substrate 20 has been described. However, in recent years, in addition to the above-described increase in density, the number of circuits mounted on the silicon substrate 20 has been increased so that passive elements such as resistors and capacitors are mounted on the silicon substrate 20. .

  A region surrounded by a broken line shown in FIG. 10 is a capacitor region 40 in which the capacitor plate 39 is formed. Even when the MOSFET is connected to the capacitor region 40, the layout may be such that the source (S) or the drain (D) face each other. In such a case, as described above, it is possible to perform pocket implantation using a resist in which the source side (drain side) is opened and the drain side (source side) is masked. The occurrence of junction leak from 40 can be suppressed.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
A method for manufacturing a semiconductor device including a step of performing pocket implantation by oblique implantation from at least two directions,
In the step of performing the pocket injection,
A method of manufacturing a semiconductor device, characterized in that the pocket implantation is performed using a resist having an opening on the source side and a mask on the drain side for a set of two or more transistors whose gate directions are parallel and sources are facing each other. .
(Appendix 2)
A method for manufacturing a semiconductor device including a step of performing pocket implantation by oblique implantation from at least two directions,
In the step of performing the pocket injection,
A method of manufacturing a semiconductor device, characterized in that the pocket implantation is performed using a resist having an opening on the drain side and a mask on the source side for a set of two or more transistors whose gate directions are parallel and facing the drain side .
(Appendix 3)
A method of manufacturing a semiconductor device including a step of forming an extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
The extension region is formed by implanting impurities using a resist having an opening on the source side and a mask on the drain side for a set of two or more transistors in which the gate directions are parallel and the sources face each other. A method for manufacturing a semiconductor device.
(Appendix 4)
A method of manufacturing a semiconductor device including a step of forming an extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
The extension region is formed by implanting impurities using a resist having an opening on the drain side and a mask on the source side for a set of two or more transistors in which the gate directions are parallel and the drains face each other. A method for manufacturing a semiconductor device.
(Appendix 5)
A method of manufacturing a semiconductor device including a step of forming an extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
A first extension region is formed by implanting an impurity using a resist having an opening on the source side and a mask on the drain side for a set of two or more transistors in which the gate directions are parallel and the sources face each other. A first step of:
And a second step of forming a second extension region by injecting an impurity into the set of two or more transistors using a resist having an opening on the drain side and a mask on the source side. A method of manufacturing a semiconductor device.
(Appendix 6)
A method for manufacturing a semiconductor device, comprising: a step of performing pocket implantation by oblique implantation from at least two directions; and a step of forming an extension region by implanting impurities on both sides of the gate electrode,
In the step of performing the pocket implantation, the pocket implantation is performed using a resist in which the source side is opened and the drain side is masked for a set of two or more transistors in which the gate direction is parallel and the sources face each other.
In the step of forming the source / drain extension region, an impurity is implanted using the resist to form the extension region.
(Appendix 7)
A method for manufacturing a semiconductor device, comprising: a step of performing pocket implantation by oblique implantation from at least two directions; and a step of forming an extension region by implanting impurities on both sides of the gate electrode,
In the step of performing the pocket implantation, the pocket implantation is performed using a resist in which the drain side is opened and the source side is masked for a set of two or more transistors in which the gate direction is parallel and the drain side faces each other.
In the step of forming the source / drain extension region, an impurity is implanted using the resist to form the extension region.

1A to 1E are cross-sectional views for explaining a method of manufacturing a semiconductor device which is a conventional example. FIG. 2 is a plan view for explaining a first resist used when pocket implantation is performed in a conventional method of manufacturing a semiconductor device. FIG. 3 is a plan view for explaining a second resist used when pocket implantation is performed in a conventional method for manufacturing a semiconductor device. 4A to 4E are cross-sectional views for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention (No. 1). 5A to 5E are cross-sectional views for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention (No. 2). FIG. 6 is a plan view for explaining a resist used for pocket implantation in the method of manufacturing a semiconductor device according to an embodiment of the present invention. 7A and 7B are cross-sectional views for explaining a first modification of the present invention. FIG. 8 is a plan view for explaining a second modification of the present invention. FIG. 9 is a plan view for explaining a third modification of the present invention. FIG. 10 is a plan view for explaining a fourth modification of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Source drain extension 11 Active region 20 Silicon substrate 22 Element isolation region 23 P type well 24 P type halo layer 25 Gate insulating film 26 Gate electrode 27 Pocket resist 27A Opening 28 Source / drain extension resist 29A First source drain extension Resist 29B second source / drain extension resists 30, 30A, 30B source / drain extension 39 capacitor plate

Claims (5)

A method for manufacturing a semiconductor device including a step of performing pocket implantation by oblique implantation from at least two directions,
In the step of performing the pocket injection,
A method of manufacturing a semiconductor device, characterized in that the pocket implantation is performed using a resist having an opening on the source side and a mask on the drain side for a set of two or more transistors whose gate directions are parallel and sources are facing each other. . A method for manufacturing a semiconductor device including a step of performing pocket implantation by oblique implantation from at least two directions,
In the step of performing the pocket injection,
A method of manufacturing a semiconductor device, characterized in that the pocket implantation is performed using a resist having an opening on the drain side and a mask on the source side for a set of two or more transistors whose gate directions are parallel and facing the drain side . A method of manufacturing a semiconductor device including a step of forming a source / drain extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
Impurity is implanted into a set of two or more transistors in which the gate directions are parallel and the sources are opposed to each other, using the resist having an opening on the source side and a mask on the drain side to form the source / drain extension region. A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device including a step of forming a source / drain extension region by implanting impurities on both sides of a gate electrode,
In the step of forming the source / drain extension region,
Impurity is implanted into a set of two or more transistors in which the gate directions are parallel and the drains face each other, using the resist having an opening on the drain side and a mask on the source side to form the source / drain extension region. A method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device, comprising: a step of performing pocket implantation by oblique implantation from at least two directions; and a step of forming a source / drain extension region by implanting impurities on both sides of the gate electrode,
In the step of performing the pocket implantation, the pocket implantation is performed using a resist in which the source side is opened and the drain side is masked for a set of two or more transistors in which the gate direction is parallel and the sources face each other.
In the step of forming the source / drain extension region, an impurity is implanted using the resist to form the source / drain extension region.

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