JPH06349854A - Manufacture of transistor - Google Patents

Abstract

PURPOSE:To improve electric characteristic of a transistor by reducing a lithography process for forming an ion implantation mask, by forming a pocket diffusion layer at a source region side and by forming an LDD diffusion layer at a drain region side. CONSTITUTION:After a gate electrode 15 is formed on a semiconductor substrate 11 with a gate insulation film 14 in between, an ion implantation mask 16 is formed and an opening part 19 is provided which opens above a first specified region S1 at the side of the gate electrode 15 of a drain formation region 17 and above a second specified region S2 at the side of the gate electrode 15 of a source formation region 18. Thereafter, first impurities 41 for forming a pocket diffusion layer 22 on the semiconductor substrate 11 at the side of the source formation region 18 are introduced by oblique ion implantation method, and then, second impurities 43 for forming LDD diffusion layers 23, 25 are introduced. After the ion implantation mask 16 is removed, third impurities 43 are introduced and each impurity introduction region is activated and an N-channel transistor 1 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor, and more particularly, to a method of manufacturing a transistor having an LDD structure.

[0002]

2. Description of the Related Art A conventional example will be described with reference to the manufacturing process chart of FIG. In the figure, the case where an N-channel transistor is formed is shown as an example.

As shown in FIG. 4A, the semiconductor substrate 5
1, an element isolation region 53 that divides the transistor formation region 52 is formed. The semiconductor substrate 51 is
At least the transistor formation region 52 is formed to be P-type. Further, on the semiconductor substrate 51 in the transistor formation region 52, the gate electrode 5 is formed via the gate insulating film 54.
5 is formed.

After that, an ion implantation mask 56 made of, for example, a resist is formed on the semiconductor substrate 51 by a usual coating technique and a lithography technique. The ion implantation mask 56 is provided with an opening 57 on a region where an LDD diffusion layer described later is formed.

Then, an N-type impurity 91 is introduced into the transistor formation region 52 on both sides of the gate electrode 55 through the opening 57 by an ion implantation method for forming a normal LDD diffusion layer. After that, the ion implantation mask 56 is removed by asher processing or wet etching.

Next, as shown in FIG. 4B, an ion implantation mask 58 made of, for example, a resist is formed on the semiconductor substrate 51 by a normal coating technique. Then, an opening 60 is formed in the ion implantation mask 58 on the source formation region 59 in the transistor formation region 52 by a normal lithography technique.

Then, an impurity 92 of the same conductivity type (P type) as that of the transistor forming region 52 is introduced into the semiconductor substrate 51 through the opening 60 by the oblique ion implantation method. The impurity 92 forms a P-type pocket diffusion layer in a subsequent step, and is made of a P-type impurity [for example, phosphorus (P) or arsenic (As)].

After that, the ion implantation mask 58 is removed by asher processing or wet etching.

Then, as shown in FIG. 4C, sidewalls 61 are formed on both sides of the gate electrode 55 by a normal sidewall forming process. The width of the sidewall 61 determines a distance between the gate electrode 15 and a source region described later and a distance between the gate electrode 15 and a drain region described later. Furthermore, an insulating film 62 made of, for example, silicon oxide, which serves as a buffer at the time of ion implantation, is formed on at least the semiconductor substrate 51 by a thermal oxidation method or a chemical vapor deposition method, for example.

Next, an ion implantation mask (not shown) is formed in a predetermined region by a resist coating technique and a lithography technique, and then P type impurities 93 for forming source / drain regions are introduced by an ion implantation method.

Thereafter, as shown in (4) of FIG. 4, activation annealing treatment is performed to form a P-type pocket diffusion layer 63 on the semiconductor substrate 51 on one side of the gate electrode 55. At the same time, an N-type source region 65 is formed on the P-type pocket diffusion layer 63 via the N-type LDD diffusion layer 64. Further, almost at the same time, the gate electrode 55
On the other side of the semiconductor substrate 51, an N-type drain region 67 is formed via an N-type LDD diffusion layer 66. In this way, the N-channel transistor 50 is formed.

Although the N-channel transistor 50 has been described as an example in the above-mentioned conventional example, it can be applied to a P-channel transistor by reversing the conductivity type.

[0013]

However, in the above manufacturing method, the ion implantation mask used for forming the LDD diffusion layer and the ion implantation mask used for forming the pocket diffusion layer only on the source region side are formed. Must. Therefore, the number of lithography steps for forming the pocket diffusion layer is increased as compared with the case where the pocket diffusion layer is formed on the source region side and the drain region side.

When the ion implantation mask used for forming the pocket diffusion layer is also used as the ion implantation mask used for forming the LDD diffusion layer, the LDD diffusion layer cannot be formed on the drain region side. As described above, when the LDD diffusion layer cannot be formed on the drain region side, the current capability of the transistor decreases.

It is an object of the present invention to provide a method for manufacturing a transistor which is excellent in electric characteristics of the transistor, particularly in the current capability of the transistor.

[0016]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a transistor, which has been made to achieve the above object.
That is, in the first step, a gate electrode is formed on the transistor formation region of the semiconductor substrate via the gate insulating film. Next, in a second step, an opening is provided that opens at least the first predetermined region on the gate electrode side in the drain formation region of the transistor formation region and the second predetermined region on the gate electrode side in the source formation region. After forming an ion implantation mask on the semiconductor substrate, a first impurity of the same conductivity type as the transistor formation region and forming a pocket diffusion layer on the semiconductor substrate on the source formation region side is formed by an oblique ion implantation method. Introduce. Subsequently, in a third step, a second impurity that forms an LDD diffusion layer is introduced into the semiconductor substrate on both sides of the gate electrode by an ion implantation method using an ion implantation mask. Then, in a fourth step, a third impurity for forming a source region and a drain region is introduced into the semiconductor substrate in the transistor formation region which is separated from the gate electrode by a predetermined distance. Then, in a fifth step, each of the regions introduced with the first to third impurities is activated to form a source region and a drain region in the transistor formation region on both sides of the gate electrode via the LDD diffusion layer, and at least A pocket diffusion layer having the same conductivity type as that of the transistor formation region is formed on the LDD diffusion layer in the source region on the channel region side.

[0017]

In the above-described manufacturing method, the opening for opening at least the first predetermined region on the gate electrode side in the drain formation region of the transistor formation region and the second predetermined region on the gate electrode side in the source formation region is provided. By using the ion implantation mask and introducing the first impurity forming the pocket diffusion layer and the second impurity forming the LDD diffusion layer into the transistor formation region, the lithography process is reduced by one process.

The formation of the pocket diffusion layer suppresses the short channel effect. Further, by forming the LDD diffusion layer on the drain region side, the current capability of the transistor is enhanced. Further, since the pocket diffusion layer is not formed on the drain region end side, the concentration of the transistor formation region at the drain region end does not increase. Therefore, the junction leak does not increase. Further, in the case of an N-channel transistor, the junction capacitance is reduced, so that the hot carrier resistance is improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the manufacturing process drawing of FIG. In the figure, as an example, the case where the N-channel transistor 1 is formed is shown.

As shown in FIG. 1A, the semiconductor substrate 1
1, an element isolation region 13 that divides the transistor formation region 12 is formed. The semiconductor substrate 11 is
At least the transistor formation region 12 is formed to be P-type.

First, in the first step, the gate insulating film 14 is formed on the semiconductor substrate 11 in the transistor formation region 12 by, for example, a thermal oxidation method. This gate insulating film 1
4 is made of, for example, silicon oxide. Then, a gate electrode 15 is formed on the gate insulating film 14 by a normal gate electrode forming method. The gate electrode 15 is made of polycide, for example.

Next, an ion implantation mask 16 made of, for example, a resist is formed on the semiconductor substrate 11 by a usual coating technique. Then, the drain formation region 1 of the transistor formation region 12 is formed by a normal lithography technique.
In FIG. 7, an opening 19 is formed which opens on the first predetermined region S1 on the gate electrode 15 side in the first electrode 7 and on the first predetermined region S2 on the gate electrode 15 side in the source formation region 18. When the gate electrode 15 functions as an ion implantation mask, the opening 19 is also formed on a part of the gate electrode 15 as shown in the figure.

Now, let the film thickness of the ion implantation mask 16 be d,
The distance between the gate electrode 15 and the ion implantation mask 16 in the first predetermined region S1 is s1, the distance between the gate electrode 15 and the ion implantation mask 16 in the first predetermined region S1 is s2, and the formation accuracy of the ion implantation mask is Δsw. , The alignment accuracy is Δsa, and the ion implantation angle for forming the pocket diffusion layer is θ1. At this time, in order not to introduce impurities for forming the pocket diffusion layer on the drain end side, the following expressions (1) and (2) must be satisfied.

Tan θ1> [s1 + (Δsw ² + Δsa ² ) ^1/2 ] / d (1)

Tan θ1 <[s1− (Δsw ² + Δsa ² ) ^1/2 ] / d (2)

When the ion implantation angle for forming the LDD diffusion layer is θ2, the following expression (3) must be satisfied.

Tan θ2 <[s1- (Δsw ² + Δsa ² ) ^1/2 ] / d (3)

Then, a first impurity 41 of the same conductivity type (P type) as the transistor forming region 12 is introduced into the semiconductor substrate 11 through the opening 19 by the oblique ion implantation method. This first impurity 41 is added to the P
To form a P-type pocket diffusion layer, which is a P-type impurity [for example, boron (B) or boron difluoride (BF ₂ )].
Etc.]. When forming a P-channel transistor, the N-type pocket diffusion layer is formed in order to form an N-type pocket diffusion layer.
Type impurities [eg phosphorus (P) or arsenic (As), etc.]
To introduce.

As the oblique ion implantation conditions, for example, when boron (B ⁺ ) is used as the first impurity 41, the implantation energy is about several tens keV, the ion implantation angle is θ1, and the dose amount is 1T. / cm ² ~10T number / c
Set to m ² . When phosphorus (P ⁺ ) is used for the first impurity 41, for example, the implantation energy is about several tens keV to hundreds of tens keV, the ion implantation angle is θ1, and the dose amount is 1 T / cm ^2. Set to 10 T / cm ² .

Then, a third step shown in FIG. 1C is performed. In this step, the opening 19 is formed, for example, by an oblique ion implantation method using the ion implantation mask 16.
Then, the second impurity 42 is introduced into the semiconductor substrate 11.
This second impurity 42 is added to the N-type LD in the subsequent process.
It forms the D diffusion layer and is made of N type impurities [for example, phosphorus (P) or arsenic (As)]. When forming a P-channel transistor, a P-type impurity [for example, boron (B) or boron difluoride (BF ₂ )]
To introduce. In the figure, the illustration of the impurity 41 that has already been introduced is omitted.

The oblique ion implantation conditions are, for example, arsenic (As ⁺ ) or phosphorus (P) as the second impurity 42.
⁺ ) Is used, the implantation energy is several tens ke
V, ion implantation angle θ2, dose amount 10T /
cm ² is set to ~100T pieces / cm ^2. The second impurity 42 may be boron (B ⁺ ) or boron difluoride (BF).
₂ ⁺ ) is used, for example, the implantation energy is about several tens keV, the ion implantation angle is θ2, and the dose is 1
It is set to the T / cm ² ~10T pieces / cm ^2.

Usually, the first for forming the pocket diffusion layer
The ion implantation angle θ1 of the impurity 41 is set to an angle larger than 45 °. For example, setting θ1 = 60 °,
Δsw = 0.1 μm, Δsa = 0.1 μm, d = 1.0
Assuming that μm is, s1 in the opening 19 of the ion implantation mask 16 is 0.72 μm from the above formulas (1) and (2).
It may be set in the range of <s1 <1.59 μm.

Further, the ion implantation angle θ2 of the second impurity 42 forming the LDD diffusion layer is set to an angle smaller than 45 °. For example, if θ2 = 30 ° is set, s2 in the opening 19 of the ion implantation mask 16 may be set to s2> 1.87 μm from the above formula (3).

After that, the ion implantation mask 16 is removed by asher processing or wet etching.

Then, the fourth step shown in FIG. 1C is performed. In this step, the sidewalls 20 are formed on both sides of the gate electrode 15 by a normal sidewall forming process. Further, for example, by a thermal oxidation method or a chemical vapor deposition method, an insulating film 21 serving as a buffer at the time of ion implantation is formed on at least the semiconductor substrate 11. The insulating film 21 is made of, for example, a silicon oxide film.

Next, after an ion implantation mask (not shown) is formed in a predetermined region by a resist coating technique and a lithography technique, a third impurity 43 for forming a source region and a drain region is introduced by an ion implantation method. To do.

As the ion implantation conditions, when forming an N-channel transistor, for example, arsenic (As ⁺ ) or phosphorus (P ⁺ ) is used as the third impurity 43, and the implantation energy is about several tens keV. Ion implantation angle 0 ° to several °, dose amount 1 P / cm ^{2 to} 10 P / c
Set to m ² . When forming a P-channel transistor, boron (B ⁺ ) or boron difluoride (BF ₂ ⁺ ) is used as the third impurity 43, and the implantation energy is about several tens keV and the ion implantation angle is 0 °. to several °, set the dose to 1P pieces / cm ² ~10P pieces / cm ^2.

Thereafter, a fifth step shown in FIG. 1 (4) is performed. In this step, activation annealing treatment is performed to form a pocket diffusion layer 22 on the semiconductor substrate 11 on one side of the gate electrode 15, and the P-type pocket diffusion layer 22 is formed.
An N-type source region 24 is formed on the upper layer via the N-type LDD diffusion layer 23. Further, the N-type drain region 26 is formed on the semiconductor substrate 11 on the other side of the gate electrode 15 with the N-type LDD diffusion layer 25 interposed therebetween. And LDD
A channel region 27 is formed between the diffusion layers 23 and 25. In this way, the N-channel transistor 1 is formed.

After that, as shown in FIG. 2, an interlayer insulating film 31 is formed by a normal chemical vapor deposition method so as to cover the N-channel transistor 1. Then, the source region 24 is formed by lithography and etching.
Contact holes 32 and 33 are formed in the interlayer insulating film 31 between the top and the drain region 26.

Then, the plug 3 is inserted into each of the contact holes 32 and 33 by a normal plug forming technique, for example.
4, 35 are formed. Further, the wirings 36 and 37 connected to the plugs 34 and 35 are formed by a normal wiring forming technique. Although not shown, a wiring connected to the gate electrode 15 is also formed in the same manner.

Further, in the ion implantation mask 16, as shown in (1) of FIG.
If the formula (3) is satisfied, the opening 19 of the ion implantation mask 16 (the hatched region) is in a state where the first predetermined region S1 on the gate electrode 15 side in the source formation region 18 is opened. It is formed. On the other hand, the opening 19 on the drain formation region 17 side is opened only on the second predetermined region S2 on the gate electrode 15 side in the drain formation region 17. Further, as shown in (2) of FIG.
The opening portion 19 on the eighth side may be formed in a state where the entire source formation region 18 is opened.

In the manufacturing method described above, the ion implantation mask used to form the LDD diffusion layers 23 and 25 is
By using the ion implantation mask 16 used to form the pocket diffusion layer 22 only on the source region 24 side,
It is not necessary to form the ion implantation mask used to form the LDD diffusion layers 23 and 25, thus reducing the lithography process.

In the above manufacturing method, the pocket diffusion layer 22 having the same conductivity type as the transistor formation region 12 is formed only on the source region 25 side, so that the concentration of the semiconductor substrate 11 on the end side of the drain region 26 does not increase. Therefore, the junction leak does not increase. Further, the drain region 24
By forming the LDD diffusion layer 25 on the side as well, the current capability of the transistor is increased. Further, in the case of an N-channel transistor, the junction capacitance is reduced, so that the hot carrier resistance is improved.

As described in the above embodiment, this manufacturing method can be applied to both N-channel transistor manufacturing and P-channel transistor manufacturing.

The numerical values used in the description of the embodiments are examples, and the values are not limited to those values.

[0043]

As described above, according to the present invention,
An ion implantation mask having an opening is formed on the first predetermined region on the gate electrode side in the drain formation region of the transistor formation region and on the second predetermined region on the gate electrode side in the source formation region on the semiconductor substrate. Then, ion implantation is performed to introduce the first impurity forming the pocket diffusion layer only into the source formation region side of the semiconductor substrate, and
Since the second impurity forming the LDD diffusion layer is introduced into the semiconductor substrate on both sides of the gate electrode, the lithography process is reduced by one process. Therefore, the manufacturing cost can be reduced and the throughput can be shortened.

Furthermore, since the pocket diffusion layer is formed only on the source region side, the concentration of the semiconductor substrate on the drain region side does not increase, and the increase in junction leak can be suppressed. Therefore, the short channel effect can be suppressed, so that the current capability of the transistor can be improved. Moreover, since the LDD diffusion layer is formed on the drain region side, the current capability of the transistor can be enhanced.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a wiring forming process.

FIG. 3 is a layout diagram of an ion implantation mask.

FIG. 4 is a manufacturing process diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-channel transistor 11 Semiconductor substrate 12 Transistor formation region 14 Gate insulating film 15 Gate electrode 16 Ion implantation mask 17 Drain formation region 18 Source formation region 19 Opening 22 Pocket diffusion layer 23 LDD diffusion layer 24 Source region 25 LDD diffusion layer 26 Drain Region 27 Channel Region 41 First Impurity 42 Second Impurity 43 Third Impurity S1 First Predetermined Region S2 Second Predetermined Region

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8617-4M H01L 21/265 S 9054-4M 29/78 301 P

Claims (1)

[Claims] 1. A first step of forming a gate electrode on a transistor formation region of a semiconductor substrate via a gate insulating film, and a first predetermined region on the gate electrode side in a drain formation region of the transistor formation region. After forming an ion implantation mask having an opening that opens on the second predetermined region on the gate electrode side in the source formation region on the semiconductor substrate, the same conductivity type as that of the transistor formation region is formed by an oblique ion implantation method. And a second step of introducing a first impurity for forming a pocket diffusion layer into the semiconductor substrate on the source formation region side, and an ion implantation method using the ion implantation mask,
A third step of introducing a second impurity forming an LDD diffusion layer into the semiconductor substrate on both sides of the gate electrode, and a source region and a drain region in the semiconductor substrate in the transistor formation region separated from the gate electrode by a predetermined distance. And a fourth step of introducing a third impurity to form an LDD diffusion layer in a transistor formation region on both sides of the gate electrode by activating the first, second, and third impurity introduced regions. And a source region and a drain region are formed through the via, and a fifth step of forming a pocket diffusion layer having the same conductivity type as that of the transistor forming region on at least the channel region side of the LDD diffusion layer in the source region is performed. Manufacturing method of transistor.