KR100313090B1 - Method for forming source/drain junction of semiconductor device - Google Patents
Method for forming source/drain junction of semiconductor device Download PDFInfo
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- KR100313090B1 KR100313090B1 KR1019990067392A KR19990067392A KR100313090B1 KR 100313090 B1 KR100313090 B1 KR 100313090B1 KR 1019990067392 A KR1019990067392 A KR 1019990067392A KR 19990067392 A KR19990067392 A KR 19990067392A KR 100313090 B1 KR100313090 B1 KR 100313090B1
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- forming
- source
- drain
- fluorine
- heat treatment
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 25
- 239000011737 fluorine Substances 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 24
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 19
- 229910052796 boron Inorganic materials 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- -1 fluorine ions Chemical class 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000002019 doping agent Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 238000009792 diffusion process Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 150000002221 fluorine Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Abstract
본 발명은 반도체장치의 소오스/드레인 형성방법에 관한 것으로서, 전면개방형 접합영역을 격자무늬나 줄무늬의 패턴을 갖는 형태로 형성하여 다량의 불소 이온주입으로 표면에 패턴화된 불소이온주입층(80)인 비정질층을 형성하고 낮은 온도영역에서 저온열처리와 RTA열처리를 동시에 실시함으로써 실리콘 표면에 패턴화된 불소이온주입층(80)의 비정질층과 비정질층과 결정층사이의 접합면을 따라 불소의 적층 농도를 극대화시키고 이 패터닝 불소 비정질층을 통해 붕소 이온주입을 실시함으로 같은 에너지에서도 패터닝화된 소오스와 드레인(65)을 만들 수 있는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a source / drain of a semiconductor device, wherein a front open junction region is formed in a form having a lattice pattern or a stripe pattern, and the fluorine ion implantation layer 80 patterned on the surface by a large amount of fluorine ion implantation Formation of fluorine along the junction between the amorphous layer, the amorphous layer and the crystalline layer of the fluorine ion implanted layer 80 patterned on the silicon surface by forming a phosphorus amorphous layer and simultaneously performing low temperature heat treatment and RTA heat treatment in a low temperature region By maximizing the concentration and performing boron ion implantation through this patterned fluorine amorphous layer, there is an advantage in that the patterned source and drain 65 can be made at the same energy.
Description
본 발명은 반도체장치의 소오스/드레인 형성방법에 관한 것으로서, 보다 상세하게는 전면개방형 접합영역을 격자무늬나 줄무늬의 패턴을 갖는 형태로 형성하여 다량의 불소 이온주입으로 표면에 패턴화된 불소이온주입층인 비정질층을 형성하고 낮은 온도영역에서 저온열처리와 RTA열처리를 동시에 실시함으로써 실리콘 표면에 패턴화된 불소이온주입층의 비정질층과 비정질층과 결정층사이의 접합면을 따라 불소의 적층 농도를 극대화시키고 이 패터닝 불소 비정질층을 통해 붕소 이온주입을 실시함으로 같은 에너지에서도 패터닝화된 소오스와 드레인을 만들 수 있도록 한 반도체장치의 소오스/드레인 형성방법에 관한 것이다.The present invention relates to a method for forming a source / drain of a semiconductor device, and more particularly, to form a front open junction region in the form of a lattice pattern or a stripe pattern, thereby injecting fluorine ions patterned on the surface by a large amount of fluorine ion implantation. By forming an amorphous layer as a layer and simultaneously performing low temperature heat treatment and RTA heat treatment in a low temperature region, the concentration of fluorine was deposited along the junction between the amorphous layer, the amorphous layer, and the crystal layer of the fluorine ion implanted layer patterned on the silicon surface. The present invention relates to a method for forming a source / drain in a semiconductor device which maximizes and performs boron ion implantation through the patterned fluorine amorphous layer so that patterned sources and drains can be made at the same energy.
반도체장치의 집적도가 높아지면서 디바이스의 속도 향상과 소형화를 위해서 게이트전극의 최소 선폭이 0.25∼0.1㎛까지 계속 줄어들고 있다. 이렇게 게이트전극 선폭이 작아질수록 쇼트 채널 효과에 따라 문턱전압이 급격히 감소하며 동시에 핫 캐리어 효과도 심하게 발생한다.As the degree of integration of semiconductor devices increases, the minimum line width of the gate electrode continues to decrease from 0.25 to 0.1 mu m in order to improve the speed and size of the device. As the gate electrode line width decreases, the threshold voltage decreases rapidly according to the short channel effect, and at the same time, the hot carrier effect occurs severely.
이러한 쇼트 채널 및 핫 캐리어 효과는 불순물이 주입된 접합영역의 깊이와 관련이 있기 때문에 접합영역 깊이가 얕은 모스트랜지스터의 개발이 요구되고 있다. 이를 위해 게이트전극의 에지 근방에 불순물이 저농도로 주입된 LDD(Lightly Doped Drain) 구조의 모스트랜지스터가 등장하게 되었다.Since the short channel and hot carrier effects are related to the depth of the junction region into which impurities are implanted, the development of a morph transistor having a shallow junction region depth is required. To this end, a morph transistor of a lightly doped drain (LDD) structure in which impurities are injected at a low concentration near the edge of the gate electrode has emerged.
한편, 반도체장치의 제조과정 중의 하나인 이온주입은 소정의 이온에 에너지를 가하여 이온이 목표물의 표면을 뚫고 들어가 목표물 내부에 위치하도록 하는 것인데, 대개는 실리콘 내부에 불순물 이온을 주입하는 것으로, 트랜지스터의 소오스나 드레인영역을 형성하기 위해 사용된다.On the other hand, ion implantation, which is one of the manufacturing processes of a semiconductor device, applies energy to predetermined ions so that ions penetrate the surface of a target and are positioned inside the target. In general, impurity ions are implanted into silicon. Used to form source or drain regions.
또한, 트랜지스터의 게이트전극의 전압에 채널 영역을 형성하기 위해서는 기판의 원자 격자사이에 위치한 불순물이 그 원자의 위치에 있어야 한다. 이렇게 불순물의 위치가 변하는 것을 활성화라고 한다. 이러한 불순물의 활성화는 외부의 에너지에 의해 일어나며 대개 열처리 공정에 의해서 이루어진다.In addition, in order to form the channel region at the voltage of the gate electrode of the transistor, impurities located between the atomic lattice of the substrate must be at the position of the atom. This change in the position of impurities is called activation. The activation of these impurities is caused by external energy and usually by heat treatment.
도 1 내지 도 2는 종래 기술에 의한 반도체장치의 소오스/드레인 형성방법을 설명하기 위한 단면도들이다.1 to 2 are cross-sectional views illustrating a method of forming a source / drain of a semiconductor device according to the prior art.
우선, 도 1에 도시된 바와 같이, 반도체기판으로서 실리콘 기판(10)에 활성 영역 및 소자간 분리영역을 정의하기 위한 소자분리막(20)을 형성하고, 기판(10)의 활성 영역 위에 순차 적층된 게이트산화막(30) 및 게이트전극(40)을 형성한 후에 게이트전극(40) 측벽에 스페이서(50)를 형성한다.First, as shown in FIG. 1, an isolation layer 20 for defining an active region and an isolation region between elements is formed on a silicon substrate 10 as a semiconductor substrate, and is sequentially stacked on the active region of the substrate 10. After forming the gate oxide film 30 and the gate electrode 40, a spacer 50 is formed on the sidewalls of the gate electrode 40.
그런 다음, 도 2에 도시된 바와 같이 게이트전극(40)을 마스크로 삼아서 많은 양의 도우즈와 얕은 접합형성을 위하여 이불화붕소 이온주입을 통하여 스페이서(50)의 에지와 소자분리막(20)의 기판(10) 내에 p+ 소오스/드레인 영역(60)을 형성한다.Next, as shown in FIG. 2, the edge of the spacer 50 and the substrate of the device isolation layer 20 are formed through the boron difluoride ion implantation using a gate electrode 40 as a mask to form a large amount of dose and a shallow junction. P + source / drain regions 60 are formed in (10).
그리고 나서, 소오스/드레인 영역(60)에 주입된 도펀트를 전기적으로 활성화시키고 이온주입된 도펀트에 의해 생긴 비정질층을 재결정화시키기 급속열처리(Rapid Thermal Process) 공정을 통해 어닐링을 실시하여 소오스/드레인 영역(60)을 형성하게 된다.Then, the source / drain region is annealed through a rapid thermal process to electrically activate the dopant implanted into the source / drain region 60 and recrystallize the amorphous layer formed by the ion implanted dopant. 60 will be formed.
위와 같이 형성방법에 의해 소오스/드레인 영역(60)을 형성할 때 저접합 형성을 위한 이온주입에서, 이불화붕소 이온주입에 의해 잔류 불소의 농도증가로 인해 유발되는 결함 등이 접합 누설전류 증가의 원인이 되는 문제점이 있다.In the ion implantation for low junction formation when forming the source / drain regions 60 by the formation method as described above, defects caused by an increase in the concentration of residual fluorine due to boron difluoride ion implantation may cause an increase in the junction leakage current. There is a problem that causes it.
또한, p+ 소오스와 드레인 영역(60)을 형성하기 위한 도펀트로써 사용되고 있는 많은 양의 이불화붕소 이온에 포함된 잔류 불소 이온의 영향으로 게이트 산화막의 악화가 발생할 수 있는 문제점이 있다.In addition, there is a problem that deterioration of the gate oxide film may occur due to the influence of residual fluorine ions contained in a large amount of boron difluoride ions used as a dopant for forming the p + source and the drain region 60.
그리고, 접합표면의 재결정화와 도펀트의 전기적 활성화를 위한 열처리공정에서 소만으로 형성된 접합에서는 도펀트의 확산으로 인해 접합 깊이의 지나친 증가가 초래될 뿐만 아니라 이 확산에 의한 채널의 단 채널 효과를 피할 수 없어 전기적으로 나쁜 결과를 초래하는 문제점이 있다.In addition, in the junction formed only in the heat treatment process for recrystallization of the junction surface and the electrical activation of the dopant, the diffusion of the dopant not only causes an excessive increase in the junction depth, but also the short channel effect of the channel due to the diffusion cannot be avoided. There is a problem that causes an electrically bad result.
한편, 기존의 불소이온주입기술에 있어서는 단일 마스크를 이용하여 이온주입을 실시함으로써 불소의 게이트 산화막 내로의 확산을 피할 수가 없어서 불소이온주입의 효과를 극대화할 수 없는 문제점이 있다.On the other hand, in the conventional fluorine ion implantation technology, the ion implantation is performed using a single mask, so that diffusion of fluorine into the gate oxide film cannot be avoided, thereby maximizing the effect of fluorine ion implantation.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 불순물 접합 영역을 포토레지스트 패터닝을 통하여 저에너지 다량의 불소 이온주입을 실시하여 패턴화된 불소 적층 비정질층을 형성하고, 저온 RTP를 통해 표면지향 확산 특성이 강한 불소를 표면으로의 적층을 극대화하고, 패턴화된 불소적층으로 접합 영역내의 불소의 농도를 줄이면서도 효과적으로 접합층의 면적을 증가시킬 수 있도록 한 반도체장치의 소오스/드레인 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to form a patterned fluorine laminated amorphous layer by performing a low-energy large amount of fluorine ion implantation through photoresist patterning an impurity junction region, and at a low temperature. RTP maximizes the stacking of fluorine with strong surface-oriented diffusion to the surface, and reduces the concentration of fluorine in the junction area with patterned fluorine deposition, while effectively increasing the area of the junction layer. A drain forming method is provided.
도 1 내지 도 2는 종래 기술에 의한 반도체장치의 소오스/드레인 형성방법을 설명하기 위한 단면도들이다.1 to 2 are cross-sectional views illustrating a method of forming a source / drain of a semiconductor device according to the prior art.
도 3 내지 도 5는 본 발명에 의한 반도체장치의 소오스/드레인 형성방법을 설명하기 위한 단면도들이다.3 to 5 are cross-sectional views illustrating a method of forming a source / drain of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 20 : 소자분리막10: substrate 20: device isolation film
30 : 게이트산화막 40 : 게이트전극30: gate oxide film 40: gate electrode
50 : 스페이서 52 : 스페이서 산화막50 spacer 52 spacer oxide film
54 : 스페이서 질화막 60,65 : 소오스/드레인54: spacer nitride film 60, 65: source / drain
70 : 패턴 포토레지스트 80 : 불소이온주입층70 pattern photoresist 80 fluorine ion implantation layer
상기와 같은 목적을 실현하기 위한 본 발명은 기판에 소자분리막과 게이트산화막과 게이트전극을 형성하는 단계와, 접합영역 부위에 포토레지스트 패터닝을 실시하여 패턴 포토레지스트를 형성하는 단계와, 패턴 포토레지스트를 마스크로 불소이온을 주입하여 접합영역에 불소이온주입층을 형성하는 단계와, 불소이온주입층을 형성한 후 낮은 온도에서 제 1차 열처리공정을 진행하는 단계와, 제 1차 열처리공정을 진행한 후 게이트전극에 저압 CVD공정을 이용하여 스페이서 산화막과 스페이서 질화막을 순차적으로 형성하는 단계와, 불소이온주입층을 통하여 고농도의 도펀트를 주입하여 소오스/드레인을 형성하는 단계와, 소오스/드레인을 형성한 후 고온에서 짧은 시간동안 제 2차 열처리공정을 진행하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is the step of forming a device isolation film, a gate oxide film and a gate electrode on the substrate, and forming a pattern photoresist by performing photoresist patterning on the junction region, the pattern photoresist Forming a fluorine ion injection layer in the junction region by injecting fluorine ions with the mask, performing a first heat treatment process at a low temperature after forming the fluorine ion injection layer, and performing a first heat treatment process. And forming a spacer oxide film and a spacer nitride film sequentially on the gate electrode using a low pressure CVD process, implanting a high concentration of dopant through a fluorine ion implantation layer to form a source / drain, and forming a source / drain. After the second heat treatment for a short time at a high temperature comprising the step of All.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 3 내지 도 5는 본 발명에 의한 반도체장치의 소오스/드레인 형성방법을 설명하기 위한 단면도들이다.3 to 5 are cross-sectional views illustrating a method of forming a source / drain of a semiconductor device according to the present invention.
도 3에 도시된 바와 같이, 반도체기판으로서 실리콘 기판(10)에 활성 영역 및 소자간 분리영역을 정의하기 위한 소자분리막(20)을 형성하고, 기판(10)의 활성영역 위에 순차 적층된 게이트산화막(30) 및 게이트전극(40)을 형성한다.As shown in FIG. 3, a device isolation film 20 is formed on the silicon substrate 10 as a semiconductor substrate to define an active region and an isolation region between the devices, and the gate oxide film sequentially stacked on the active region of the substrate 10. 30 and the gate electrode 40 are formed.
그런다음 도 4의 (가)와 같이 얕은 접합영역 형성과 도펀트로 사용될 붕소의 TED(Transient Enhanced Diffusion) 방지를 위한 격자무늬의 포토레지스트 패터닝을 실시하여 패턴 포토레지스트(70)를 형성한다. (나)는 패턴 포토레지스트(70)의 평면도로써 격자무늬 패턴으로 형성된 것을 알 수 있다.Then, as shown in FIG. 4A, a patterned photoresist 70 is formed by performing photoresist patterning of a lattice pattern to form a shallow junction region and to prevent TED (Transient Enhanced Diffusion) of boron to be used as a dopant. (B) is a plan view of the pattern photoresist 70, and it can be seen that it is formed in a lattice pattern.
그런다음, 도 5와 같이 패턴 포토레지스트(70)를 마스크로하여 불소이온을 1∼15 KeV의 에너지로 주입량은 1×1015∼ 1×1016ions/㎠로 하여 불소이온을 주입하여 접합영역에 불소이온주입층(80)을 형성한다. 그런다음 불소이온주입층(80)의 불필요한 불소를 제거하며, 후속 붕소이온에 의한 p+ 소오스/드레인을 형성하기 위하여 불소의 외부지향 확산(oriented out-diffusion)을 이용하기 위하여 저온 RTP를 실시하여 표면의 고밀도 결함을 갖는 비정질층의 형성과 이온주입시 생성된 비정질층의 재결정화를 방지하기 위하여 낮은 온도에서 제 1차 열처리공정을 진행한다.Then, as shown in Fig. 5, the fluorine ions are implanted with the energy of 1-15 KeV and the fluorine ions are implanted at 1 × 10 15 to 1 × 10 16 ions / cm 2 with the patterned photoresist 70 as a mask, thereby joining the junction region. The fluorine ion implantation layer 80 is formed in this. The surface of the fluorine ion implantation layer 80 is then removed by removing cold fluorine, and subjected to low temperature RTP to use oriented out-diffusion of fluorine to form p + source / drain by subsequent boron ions. In order to prevent the formation of an amorphous layer having a high density of defects and recrystallization of the amorphous layer formed during ion implantation, the first heat treatment process is performed at a low temperature.
이때 제 1차 열처리공정은 승온온도를 100℃/sec로 450℃∼600℃ 정도를 유지하며 RTP 진행시 표면에 산화막의 생성을 방지하기 위해 공정의 진행은 N2분위기에서 진행한다.At this time, in the first heat treatment process, the temperature is maintained at about 450 ° C. to 600 ° C. at 100 ° C./sec. In order to prevent formation of an oxide film on the surface during RTP, the process is performed in an N 2 atmosphere.
그런다음 게이트산화막(30)의 보호를 위하여 600∼800℃의 저압 CVD공정을 이용하여 스페이서 산화막(52)을 형성한다.Then, to protect the gate oxide film 30, a spacer oxide film 52 is formed by using a low pressure CVD process at 600 to 800 ° C.
그런다음 도 6과 같이 스페이서 산화막(52)의 손상을 방지하기 위하여 저압CVD 600∼800℃ 공정을 적용하여 스페이서 질화막(54)을 증착하고, p+ 소오스/드레인(65) 형성을 위해 패턴화된 불소이온주입층(80)을 통하여 고농도의 붕소이온을 주입하여 PMOS의 소오스/드레인(65)을 형성한다.Then, as shown in FIG. 6, the spacer nitride layer 54 is deposited by using a low pressure CVD 600 to 800 ° C. process to prevent damage to the spacer oxide layer 52, and the fluorine patterned to form the p + source / drain 65 is formed. High concentrations of boron ions are implanted through the ion implantation layer 80 to form the source / drain 65 of the PMOS.
이때 붕소이온 주입은 1∼5 KeV의 에너지와 1×1015∼ 5×1015ions/㎠의 도우즈를 사용하여 주입한다.In this case, the boron ion is implanted using an energy of 1-5 KeV and a dose of 1 × 10 15 -5 × 10 15 ions / cm 2.
그런다음 접합영역에 주입된 도펀트를 활성화시키고 비정질층의 재결정화를 위하여 고온에서 매우 짧은 시간동안 RTP로 제 2차 열처리공정을 진행한다. 이때 제 2차 열처리공정은 950∼1050℃ 정도에서 약 1초 정도 실시한다. 또한 불소는 낮은 온도에서 외부지향 확산을 시작하기 때문에 비정질층과 결정층사이의 접합면 즉, A/C면(amorphous/crystal interlayer)에 잔류하는 불소에 의해 붕소의 TED를 방지한다. 또한, 도펀트의 확산을 최소화하기 위해 제 2차 열처리공정의 승온온도를 100℃/s ∼ 200℃/s정도로 빠른 승온을 실시한다.Then, the second heat treatment process is performed with RTP for a very short time at high temperature to activate the dopant implanted in the junction region and to recrystallize the amorphous layer. In this case, the second heat treatment step is performed at about 950 to 1050 ° C. for about 1 second. In addition, fluorine initiates outward diffusion at low temperatures, thereby preventing TED of boron due to fluorine remaining at the junction between the amorphous layer and the crystal layer, that is, the A / C plane (amorphous / crystal interlayer). In addition, in order to minimize the diffusion of the dopant, the temperature rising temperature of the second heat treatment process is rapidly increased to about 100 ° C / s to about 200 ° C / s.
상기한 바와 같이 본 발명은 포토레지스트 패터닝에 의한 접합 영역에 비정질층과 결정층사이의 총면적을 증가시키고 비정질 불소적층의 농도구배를 증가시켜 얕은 접합영역을 가능하게 하고 이중 열처리에 의해 기존의 이불화붕소를 통해 형성된 접합에서 발생하는 접합 내부의 잔류 불소에 의한 피해를 줄일 수 있고 표면에 비정질층과 결정층사이의 접합면인 A/C면의 증가에 따른 잔류불소증가에 의한붕소이온주입시 차단효과증가와 적층된 불소 비정질층을 통해 붕소를 이온주입하여 접합을 형성함으로써 채널링을 줄이고 얕은 접합영역이 가능하며 표면 손상된 불소층에 의해 기존 붕소 이온주입보다 잔류붕소의 도우즈를 증가시킬 수 있는 이점이 있다.As described above, the present invention increases the total area between the amorphous layer and the crystalline layer in the junction region by photoresist patterning and increases the concentration gradient of the amorphous fluorine layer to enable the shallow junction region and the existing fluoride by double heat treatment. It is possible to reduce the damage by residual fluorine in the junction formed through the boron formation and to block the boron ion implantation due to the increase of residual fluorine due to the increase of the A / C surface, which is the junction between the amorphous and crystal layers on the surface. Increasing the effect and forming the junction by ion implanting boron through the laminated fluorine amorphous layer, which reduces channeling and allows shallow junction area, and can increase the dose of residual boron over the conventional boron ion implantation by the surface damaged fluorine layer There is this.
또한, 반도체장치의 전기적 특성을 향상시킴으로서 수율을 향상시킬 수 있는 이점이 있다.In addition, there is an advantage that the yield can be improved by improving the electrical characteristics of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06196492A (en) * | 1992-12-24 | 1994-07-15 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
| JPH06326123A (en) * | 1993-05-14 | 1994-11-25 | Sony Corp | Manufacture of semiconductor device |
| JPH06349854A (en) * | 1993-06-11 | 1994-12-22 | Sony Corp | Manufacture of transistor |
| JPH09107096A (en) * | 1995-10-11 | 1997-04-22 | Nec Corp | Semiconductor device and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06196492A (en) * | 1992-12-24 | 1994-07-15 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
| JPH06326123A (en) * | 1993-05-14 | 1994-11-25 | Sony Corp | Manufacture of semiconductor device |
| JPH06349854A (en) * | 1993-06-11 | 1994-12-22 | Sony Corp | Manufacture of transistor |
| JPH09107096A (en) * | 1995-10-11 | 1997-04-22 | Nec Corp | Semiconductor device and its manufacture |
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