KR0136532B1 - Thin film transistor - Google Patents
Thin film transistorInfo
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- KR0136532B1 KR0136532B1 KR1019940017685A KR19940017685A KR0136532B1 KR 0136532 B1 KR0136532 B1 KR 0136532B1 KR 1019940017685 A KR1019940017685 A KR 1019940017685A KR 19940017685 A KR19940017685 A KR 19940017685A KR 0136532 B1 KR0136532 B1 KR 0136532B1
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- thin film
- polysilicon
- polysilicon layer
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- 239000010409 thin film Substances 0.000 title claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 239000010408 film Substances 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- -1 silicon ions Chemical class 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000001953 recrystallisation Methods 0.000 claims 1
- 210000004185 liver Anatomy 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 239000007790 solid phase Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 박막트랜지스터의 제조방법에 관한 것으로, 박막트랜지스터 각각의 소자에 포함되는 폴리실리콘의 그레인경계의 수를 최소한으로 줄이고, 또 그 숫자를 동일하게 하여 높은 온/오프전류비를 얻음과 동시에 소자간의 특성을 균일하게 하여 신뢰성을 높일 수 있도록 한 것이다.The present invention relates to a method for manufacturing a thin film transistor, wherein the number of grain boundaries of polysilicon included in each element of the thin film transistor is reduced to a minimum, and the number is the same to obtain a high on / off current ratio and at the same time It is to improve the reliability by making the liver characteristics uniform.
본 발명은 반도체기판상에 절연층을 형성하는 공정과, 상기 절연층상에 도전층을 형성하는 공정, 상기 도전층을 패터닝하여 게이트전극을 형성하는 공정, 기판 전면에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 폴리실리콘층을 형성하는 공정, 상기 게이트전극 상부의 상기 폴리실리콘층부위상에 마스크층을 형성하는 공정, 실리콘이온을 소정깊이로 주입하여 상기 마스크층 하부의 폴리실리콘층부위를 비정질화시키는 공정, 상기 마스크층을 마스크로 이용하여 상기 폴리실리콘층에 선택적으로 불순물이온을 주입하여 소오스 및 드레인영역을 형성하는 공정, 상기 마스크층을 제거하는 공정, 열처리에 의해 상기 비정질화된 폴리실리콘층부위를 재결정화시키는 공정을 포함하여 이루어지는 박막트랜지스터 제조방법을 제공한다.The present invention provides a process for forming an insulating layer on a semiconductor substrate, forming a conductive layer on the insulating layer, forming a gate electrode by patterning the conductive layer, and forming a gate insulating film on the entire surface of the substrate. Forming a polysilicon layer on the gate insulating film, forming a mask layer on the polysilicon layer portion on the gate electrode, implanting silicon ions to a predetermined depth, and amorphous the polysilicon layer portion below the mask layer Forming the source and drain regions by selectively implanting impurity ions into the polysilicon layer using the mask layer as a mask, removing the mask layer, and performing the heat treatment of the amorphous polysilicon layer It provides a thin film transistor manufacturing method comprising the step of recrystallizing the site.
Description
제1도는 종래의 폴리실리콘 박막트랜지스터 단면구조도1 is a cross-sectional structure of a conventional polysilicon thin film transistor
제2도는 종래의 비정질실리콘 박막트랜지스터 단면구조도2 is a cross-sectional view of a conventional amorphous silicon thin film transistor
제3도는 본 발명에 의한 박막트랜지스터 제조방법을 도시한 공정순서도3 is a process flowchart showing a method of manufacturing a thin film transistor according to the present invention.
제4도는 본 발명의 박막트랜지스터의 적층구조의 깊이에 따른 주입된 실리콘이온의 농도를 도시한 도면4 is a view showing the concentration of implanted silicon ions according to the depth of the laminated structure of the thin film transistor of the present invention
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11:반도체기판 12:절연층11: semiconductor substrate 12: insulating layer
13:게이트전극 14:게이트절연막13: gate electrode 14: gate insulating film
15:바디 폴리실리콘층 16:고온산화막15: body polysilicon layer 16: high temperature oxide film
본 발명은 박막트랜지스터(Thin Film Transistor)의 제조방법에 관한 것으로, 특히 1메가비트이상의 SRAM(Static Random Access Memory)의 부하트랜지스터로 사용하기에 적당하도록 한 폴리실리콘 박막트랜지스터의 제조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a polysilicon thin film transistor suitable for use as a load transistor of at least 1 megabit of random random access memory (SRAM).
종래 SRAM의 부하트랜지스터를 형성함에 있어서 CVD(Chemical Vapor Deposition) 방법으로 증착한 폴리실리콘박막위에 트랜지스터를 형성하거나 비정질실리콘박막을 증착한 후에 열처리를 통한 고상결정화(solid Phase Crystallization)를 이용하여 그레인(grain) 크기를 증대시킨 다음 트랜지스터를 형성하는 방법들을 이용하였다.In forming a load transistor of a conventional SRAM, a transistor is formed on a polysilicon thin film deposited by CVD (Chemical Vapor Deposition) method, or an amorphous silicon thin film is deposited, followed by solid phase crystallization through heat treatment. ) To increase the size and then to form a transistor.
제1도는 폴리실리콘 박막트랜지스터의 단면구조를 나타낸 것으로, 기판(1)상의 절연층(2)상에 게이트(3)를 형성하고, 전면에 게이트절연막(4)을 형성한 후, 이위에 CVD방법에 의해 폴리실리콘박막(5)을 증착하고, 폴리실리콘박막(5)에 선택적으로 이온주입을 행하여 소오스(6)와 드레인(7)을 형성한 것이다.1 shows a cross-sectional structure of a polysilicon thin film transistor, in which a gate 3 is formed on an insulating layer 2 on a substrate 1, a gate insulating film 4 is formed on the entire surface thereof, and then a CVD method is performed thereon. The polysilicon thin film 5 is deposited, and ion implantation is selectively performed on the polysilicon thin film 5 to form the source 6 and the drain 7.
제2도는 비정질실리콘 박막트랜지스터의 단면구조를 나타낸 것으로, 기판(1)상의 절연층(2)상에 게이트(3)를 형성하고, 전면에 게이트절연막(4)을 형성한 후, 이위에 비정질실리콘박막(8)을 증착한 다음 고상결정화하여 그레인크기를 증가시킨 후, 비정질실리콘박막(8)에 선택적으로 이온주입을 행하여 소오스(6)와 드레인(7)을 형성한 것이다.2 shows a cross-sectional structure of an amorphous silicon thin film transistor, in which a gate 3 is formed on an insulating layer 2 on a substrate 1, a gate insulating film 4 is formed on an entire surface of the amorphous silicon thin film transistor, and then amorphous silicon is formed thereon. After the thin film 8 is deposited and then subjected to solid phase crystallization to increase grain size, ion implantation is selectively performed on the amorphous silicon thin film 8 to form the source 6 and the drain 7.
상기와 같이 CVD방법으로 증착한 폴리실리콘박막 또는 비정질실리콘의 고상결정화에 의한 폴리실리콘박막을 이용하여 트랜지스터를 제작하는 경우, 소자가 고집적화됨에 따라 소자의 크기가 그레인 크기에 가까워지게 된다. 이럴 경우 CVD방법으로 증착한 폴리실리콘에서는 채널내의 그레인 경계(Grain boundary)(제1도 및 제2도의 참조부호GB)가 다수 포함되어 온전류(on current)의 저하와 오프전류(off current)의 증가를 초래하며, 고상결정화시킨 폴리실리콘에서는 소자내에 그레인경계가 포함되는지의 여부에 따라서 소자간의 특성이 불균일성을 초래하여 소자의 신뢰성을 저하시키게 된다.When the transistor is fabricated using the polysilicon thin film deposited by the CVD method or the polysilicon thin film by the solid phase crystallization of amorphous silicon as described above, the size of the device becomes closer to the grain size as the device becomes highly integrated. In this case, the polysilicon deposited by the CVD method includes a large number of grain boundaries in the channel (reference numeral GB of FIGS. 1 and 2) to reduce the on current and the off current. In polysilicon solidified with crystallinity, the characteristics between the devices are nonuniform depending on whether or not the grain boundaries are included in the device, thereby reducing the reliability of the device.
본 발명은 상술한 문제를 해결하기 위한 것으로, 각각의 소자에 포함되는 폴리실리콘의 그레인경계의 수를 최소한으로 줄이고, 또 그 숫자를 동일하게 하여 높은 온/오프전류비를 얻음과 동시에 소자간의 특성을 균일하게 하여 신뢰성을 높일 수 있도록 한 박막트랜지스터 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and the number of grain boundaries of polysilicon included in each device is reduced to a minimum, and the number is the same to obtain a high on / off current ratio and at the same time the characteristics between the devices. It is an object of the present invention to provide a method for manufacturing a thin film transistor, which can increase the reliability by making it uniform.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터 제조방법은 반도체기판상에 절연층을 형성하는 공정과, 상기 절연층상에 도전층을 형성하는 공정, 상기 도전층을 패터닝하여 게이트전극을 형성하는 공정, 기판 전면에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 폴리실리콘층을 형성하는 공정, 상기 게이트전극 상부의 상기 폴리실리콘층부위상에 마스크층을 형성하는 공정, 실리콘이온을 소정깊이로 주입하여 상기 마스크층 하부의 폴리실리콘층부위를 비정질화시키는 공정, 상기 마스크층을 마스크로 이용하여 상기 폴리실리콘층에 선택적으로 불순물이온을 주입하여 소오스 및 드레인영역을 형성하는 공정, 상기 마스크층을 제거하는 공정, 열처리에 의해 상기 비정질화된 폴리실리콘층부위를 재결정화시키는 공정을 포함하여 이루어진다.The thin film transistor manufacturing method of the present invention for achieving the above object is a step of forming an insulating layer on a semiconductor substrate, a step of forming a conductive layer on the insulating layer, a step of forming a gate electrode by patterning the conductive layer, Forming a gate insulating film on the entire surface of the substrate; forming a polysilicon layer on the gate insulating film; forming a mask layer on the polysilicon layer on the gate electrode; implanting silicon ions to a predetermined depth; Amorphizing a portion of the polysilicon layer below the mask layer, forming a source and drain region by selectively implanting impurity ions into the polysilicon layer using the mask layer as a mask, removing the mask layer And recrystallizing the amorphous polysilicon layer by heat treatment. Is done.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도에 본 발명에 의한 박막트랜지스터 제조방법을 공정순서에 따라 도시하였다.3 shows a method of manufacturing a thin film transistor according to the present invention according to the process sequence.
먼저, 제3도 (a)에 도시된 바와 같이 반도체기판(11)상에 산화막등의 절연층(12)을 형성하고 이위에 게이트 형성용 도전층으로서, 예컨대 도우프드(doped) 폴리실리콘층(13)을 1000Å정도의 두께로 형성한다.First, as shown in FIG. 3A, an insulating layer 12, such as an oxide film, is formed on the semiconductor substrate 11, and a doped polysilicon layer, for example, as a conductive layer for forming a gate thereon. 13) is formed to a thickness of about 1000Å.
이어서 제3도 (b)에 도시된 바와 같이 상기 도우프드 폴리실리콘층(13)을 소정 패턴으로 패터닝하여 게이트전극을 형성한 후, 제3도(c)에 도시된 바와 같이 기판 전면에 고온산화막(HTO ; High Temperature Oxide)등의 게이트절연막(14)을 400Å정도의 두께로 형성하고, 이위에 바디(body) 폴리실리콘층(15)을 100-200Å정도의 두께로 형성한다. 이때, 620℃에서 폴리실리콘을 증착함으로써 증착 속도를 증가시킬 수 있다. 바디폴리실리콘의 두게를 얇게 하는 것은 역방향전류의 감소를 위한 것이며, 막의 두께가 얇아짐에 따라 pn접합의 단면적이 감소되고 역방향 누설전류를 줄일 수 있다.Subsequently, as shown in FIG. 3 (b), the doped polysilicon layer 13 is patterned in a predetermined pattern to form a gate electrode, and as shown in FIG. A gate insulating film 14 such as (HTO; High Temperature Oxide) is formed to a thickness of about 400 kPa, and the body polysilicon layer 15 is formed to a thickness of about 100 to 200 kPa on it. In this case, the deposition rate may be increased by depositing polysilicon at 620 ° C. Thinning the thickness of the body polysilicon is intended to reduce the reverse current, and as the thickness of the film becomes thinner, the cross-sectional area of the pn junction can be reduced and the reverse leakage current can be reduced.
다음에 제3도 (d)에 도시된 바와 같이 기판 전면에 이온주입 마스크층으로서, 예컨대 CVD방법으로 고온산화막(16)을 1000Å정도의 두께로 형성한 후, 이를 선택적으로 식각하여 바디폴리실리콘층(15)의 소오스 및 드레인영역이 될부분을 노출시키고 게이트전극 상부의 채널영역에만 남도록 한다.Next, as shown in FIG. 3 (d), as the ion implantation mask layer on the entire surface of the substrate, for example, a high temperature oxide film 16 is formed to a thickness of about 1000 kV by CVD, and then selectively etched to form a body polysilicon layer. The portions to be the source and drain regions of (15) are exposed and remain only in the channel region above the gate electrode.
이어서 제3도(e)에 도시된 바와 같이 실리콘이온을 5×1014cm-2의 도우즈량이로 100KeV의 에너지로 수직하게 주입하여 바디폴리실리콘층(15)의 채널부분만을 완전히 비정질화시킨다. 실리콘이온을 100KeV의 에너지로 주입하면 제4도에 도시한 바와 같이 주입된 실리콘의 피크(peak)는 고온산화막(16)이 덮인 채널영역의 중앙에 위치하여 채널부가 완전히 비정질화된다. 한편, 고온산화막(16)이 덮이지 않은 소오스 및 드레인영역(15A)에서는 바디폴리실리콘층 하부의 게이트절연막(14)에 주입된 실리콘의 피크가 오게 되며, 폴리실리콘에서는 이온채널링(ion channeling)이 일어나 (110)방향을 가지는 결정들이 잔존하게 된다.Subsequently, as shown in FIG. 3 (e), silicon ions are vertically implanted at an energy of 100 KeV at a dose of 5 × 10 14 cm −2 to completely amorphous only the channel portion of the body polysilicon layer 15. . When silicon ions are implanted at an energy of 100 KeV, the peak of the implanted silicon is located in the center of the channel region covered with the high temperature oxide film 16, as shown in FIG. On the other hand, in the source and drain regions 15A which are not covered with the high temperature oxide film 16, the peak of silicon injected into the gate insulating film 14 under the body polysilicon layer comes, and ion channeling is performed in the polysilicon. Crystals with the (110) direction remain.
이어서 상기 고온산화막(16)을 마스크로 하여 상기 바디폴리실리콘층(15)의 소오스 및 드레인의 형성될 영역(15A)에 선택적으로 불순물이온으로서, 예컨대 보론을 3×1014cm-2의 도우즈량으로 10KeV의 가속에너지에 의해 이온주입하여 소오스 및 드레인영역(15A)을 형성한다.Subsequently, a dose amount of 3 × 10 14 cm −2 as an impurity ion is selectively selected as an impurity ion in the region 15A to be formed of the source and the drain of the body polysilicon layer 15 using the high temperature oxide film 16 as a mask. Ion implanted by an acceleration energy of 10 KeV to form the source and drain regions 15A.
다음에 제3도 (f)에 도시된 바와 같이 채널상부의 상기 고온산화막(16)을 제거한 후, 질소분위기에서 600℃에서 12시간의 열처리를 행하여 재결정화시킨다. 이때, 소오스와 드레인부위에 잔존하는 결정을 중심으로 채널의 양측에서 결정화가 빠르게 이루어지며, 최종적으로는 제3도 (g)에 도시된 바와 같이 채널의 중앙부에 하나의 그레인 경계(GB)를 갖는 박막트랜지스터가 완성된다. 이와같이 제조되는 박막트랜지스터는 모두 동일한 조건으로 형성되어지므로 소자간의 특성차이가 없이 고신뢰성을 가진다. 또한, 채널상부의 산화막을 실리콘이 온 주입의 길이조절과 함께 소오스 및 드레인영역의 도핑시 불순물 이온주입에 대한 마스크로 쓸 수 있어 공정의 간소화를 꾀할 수 있다. 그리고 채널영역에 하나의 그레인경계만이 형성되므로 온/오프전류비가 증가하게 된다.Next, as shown in FIG. 3 (f), the high temperature oxide film 16 in the upper portion of the channel is removed and then recrystallized by heat treatment at 600 ° C. for 12 hours in a nitrogen atmosphere. At this time, crystallization is rapidly performed at both sides of the channel centering on the crystals remaining in the source and drain regions, and finally, as shown in FIG. 3 (g), one grain boundary (GB) is provided at the center of the channel. Thin film transistor is completed. Since the thin film transistors manufactured in this way are all formed under the same conditions, they have high reliability without difference in characteristics between the devices. In addition, the oxide film on the upper channel can be used as a mask for implanting impurity ions when doping the source and drain regions together with controlling the length of silicon ion implantation, thereby simplifying the process. In addition, since only one grain boundary is formed in the channel region, the on / off current ratio is increased.
이상 상술한 바와 같이 본 발명에 의하면, 박막트랜지스터의 제조공정을 단순화시킬 수 있으며, 박막트랜지스터의 특성을 개선시킬 수 있다.As described above, according to the present invention, the manufacturing process of the thin film transistor can be simplified, and the characteristics of the thin film transistor can be improved.
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| KR1019940017685A KR0136532B1 (en) | 1994-07-21 | 1994-07-21 | Thin film transistor |
| JP7194023A JP2826982B2 (en) | 1994-07-07 | 1995-07-07 | Crystallization method and method of manufacturing thin film transistor using the same |
| US08/499,255 US5753544A (en) | 1994-07-07 | 1995-07-07 | Crystallization process and method of manufacturing thin film transistor using same |
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