KR0166782B1 - Methd of manufacturing thin film transistor - Google Patents
Methd of manufacturing thin film transistor Download PDFInfo
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- KR0166782B1 KR0166782B1 KR1019940011194A KR19940011194A KR0166782B1 KR 0166782 B1 KR0166782 B1 KR 0166782B1 KR 1019940011194 A KR1019940011194 A KR 1019940011194A KR 19940011194 A KR19940011194 A KR 19940011194A KR 0166782 B1 KR0166782 B1 KR 0166782B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 39
- 239000012535 impurity Substances 0.000 claims abstract description 36
- 239000010408 film Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 24
- 150000002500 ions Chemical class 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000002425 crystallisation Methods 0.000 claims abstract description 9
- 230000008025 crystallization Effects 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- -1 silicon ions Chemical class 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000002019 doping agent Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 37
- 229920005591 polysilicon Polymers 0.000 description 37
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 6
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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Abstract
본 발명은 반도체 소자인 박막 트랜지스터 관한 것으로, 특히 SRAM의 메모리 셀(Memory Cell)에 적당하도록 한 박막 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, which are semiconductor devices, and more particularly, to a method of manufacturing thin film transistors suitable for memory cells of SRAM.
이와 같은 본 발명의 박막 트랜지스터의 제조방법은 절연기판위에 게이트 전극을 형성하고 전면에 게이트 절연막과 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화 하고, 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경사지게 90˚회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘을 2차 결정화시켜 그레인을 형성하는 공정, 상기 2차 결정화된 실리콘층에 선택적으로불순문 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어지고, 절연기판상에 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화하고 비정질 실리콘층 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화하고 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경사지게 90˚회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘층을 2차 결정화시켜, 그레인을 형성하는 공정, 전면에 케이트 절연막과 케이트용 반도체층을 차례로 증착하고, 상기 게이트용 반도체층을 선택적으로 식각하여 게이트 전극을 형성하고 공정, 상기2차 결정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어진다.In the method of manufacturing the thin film transistor of the present invention, a process of forming a gate electrode on an insulating substrate and a gate insulating film and an amorphous silicon layer on the entire surface thereof, first crystallizing the amorphous silicon layer, and selectively etching to form an active region Forming a grain by forming silicon ions by implanting silicon ions by inclining 90 DEG so as to cross the primary crystallized silicon, forming a grain by secondary crystallization of the amorphous silicon, and forming the grains on the second crystallized silicon layer. Forming an impurity diffusion region by selectively implanting an impurity ion; forming an amorphous silicon layer on an insulating substrate; firstly crystallizing the amorphous silicon layer and forming an amorphous silicon layer; Primary crystallization and selective etching of the silicon layer to form the active region A step of forming an amorphous silicon layer by injecting silicon ions by inclining it 90 ° so as to intersect the first crystallized silicon, forming a grain by second crystallization of the amorphous silicon layer, and a gate insulating film and a Kate on the entire surface thereof. And depositing a semiconductor layer for order, selectively etching the gate semiconductor layer to form a gate electrode, and selectively implanting impurity ions into the second crystallized silicon layer to form an impurity diffusion region. .
Description
제1도(a)∼(c)는 종래 제1실시예의 박막 트랜지스터 공정단면도.1A to 1C are cross-sectional views of a thin film transistor process according to a first embodiment of the prior art.
제2도(a)∼(c)는 종래 제2실시예의 박막트랜지스터 공정단면도.2A to 2C are cross-sectional views of a thin film transistor process according to a conventional second embodiment.
제3도(a)∼(d)는 본 발명 제1실시예의 박막 트랜지스터 공정단면도.3A to 3D are cross-sectional views of a thin film transistor process according to the first embodiment of the present invention.
제4도(a)∼(c)는 본 발명 제2실시예의 박막 트랜지스터 공정단면도.4A to 4C are cross-sectional views of a thin film transistor according to a second embodiment of the present invention.
제5도(a)∼(c)는 본 발명 제1실시예의 박막 트랜지스터 사시도.5A to 5C are perspective views of a thin film transistor according to the first embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1：절연기판 2：게이트전극1: Insulation substrate 2: Gate electrode
3：게이트 절연막 4,5：반도체층3: gate insulating film 4, 5: semiconductor layer
6,7：제1, 제2 감광막6,7: First, second photosensitive film
본 발명은 반도체 소자인 박막 트랜지스터에 관한 것으로, 특히 SRAM메모리셀(Me-mory Cell)에 적당하도록 한 박막 트랜지스터의 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, which are semiconductor devices, and more particularly, to a method of manufacturing thin film transistors suitable for SRAM memory cells.
일반적으로 박막 트랜지스터는 1M이상의 SRAM소자에서 로드 레지스터(Load Resistor)대신 사용하기도 하고, 액정표시 소자(Liquid Crystal Display)에서 각 화소영역의 화상테이타 신호를 스위칭하는 스위칭 소자로 널리 사용되고 있다.Generally, thin film transistors are used instead of load resistors in SRAM devices of 1M or more, and are widely used as switching devices for switching image data signals of respective pixel areas in liquid crystal displays.
이에 고품질의 SRAM을 제조하기 위해서는 MOS의 오프 커런트(Off Current)는 감소하고, 온 커런트(On Current)는 증가하여야만 SRAM 셀의 소비전력을 감소시킬수 있고, 기억특성을 향상시킬 수 있다.Therefore, in order to manufacture high quality SRAM, the off current of the MOS must be reduced and the on current must be increased to reduce power consumption of the SRAM cell and to improve memory characteristics.
이와 같은 온/오프 전류비(On/Off Current Ratio)를 향상시키기 위한 종래의 박막 트랜지스터 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional thin film transistor manufacturing method for improving the on / off current ratio is described below.
제1도는 종래제1실시예의 박막 트랜지스터 공정단면도로써 보텀(bottom)게이트 박막 트랜지스터 제조방법이다.FIG. 1 is a process cross-sectional view of a thin film transistor according to a first embodiment of the related art.
제1도(a)와 같이 절연기관(1)또는 절연막위에 폴리실리콘을 증착하고, 게이트 마스크를 이용한 사진식각 공정으로 폴리실리콘을 패터닝하여 게이트 전극(2)를 형성한다.As illustrated in FIG. 1A, polysilicon is deposited on the insulation engine 1 or the insulating layer, and the polysilicon is patterned by a photolithography process using a gate mask to form the gate electrode 2.
이어서 상기 전면에 게이트 절연막(3)과 반도체층(보디 폴리실리콘)(4)을 차례로 증착하고, 상기 반도체층(보디 폴리실리콘)(4)에 수직으로 실리콘(Si)불순물을 이온주입한다.Subsequently, the gate insulating film 3 and the semiconductor layer (body polysilicon) 4 are sequentially deposited on the entire surface, and silicon (Si) impurities are implanted perpendicularly to the semiconductor layer (body polysilicon) 4.
이때 상기 반도체층(보디 폴리실리콘)(4)의 그레인 격자구조는 수직으로 실리콘(Si) 불순물 이온주입함에 따라 수평으로 형성된 그레인(grain) 격자 구조가 파괴되어 비정질(Amorphous) 실리콘으로 형성된다.At this time, the grain lattice structure of the semiconductor layer (body polysilicon) 4 is formed as amorphous silicon by breaking the grain lattice structure formed horizontally by vertically implanting silicon (Si) impurity ions.
계속해서 상기 비정질 실리콘을 560℃∼650℃ 범위에서 장시간(5시간 이상)열처리 하여, 비정질 실리콘막을 재 결정화한 다음, 일정시간이 지나면 재 결정화된 반도체층(실리콘)(4)에 수직, 수평방향으로 그래인(grain)이 형성된다.Subsequently, the amorphous silicon is thermally treated in a range of 560 ° C. to 650 ° C. for a long time (at least 5 hours) to recrystallize the amorphous silicon film, and then, after a predetermined time, perpendicular to the recrystallized semiconductor layer (silicon) 4 and in a horizontal direction. Grain is formed.
제1도 (b) 같이 상기 반도체층(실리콘)(4)상에 제1감광막(6)을 증착하고, 노광 및 현상공정으로 LDD(Lightly Doped Drain) 형성될 영역을 정의한 다음, 상기 정의된 반도체층(실리콘)(4)에 저농도(P-) 불순물 이온주입하여 LDD구조를 형성한다.The first photoresist film 6 is deposited on the semiconductor layer (silicon) 4 as shown in FIG. 1 (b), and a region in which an LDD (Lightly Doped Drain) is formed is formed by an exposure and development process, and then the semiconductor defined above is defined. Low concentration (P − ) impurity ions are implanted into the layer (silicon) 4 to form an LDD structure.
그리고 제1도 (c)와 같이 상기 제1감광막(6)을 제거한 다음, 제2감광막(7)을 상기 반도체층(실리콘)(4)상에 증착하고, 노광 및 현상공정으로 불순물 확상영역을 정의한 후 정의된 반도체층(실리콘)에 고농도(P+)불순물 이온주입하여, 소오스, 드레인영역을 형성하므로써 보텀(bottom)게이트 박막 트랜지스터를 완성한다.After removing the first photoresist film 6 as shown in FIG. 1 (c), the second photoresist film 7 is deposited on the semiconductor layer (silicon) 4, and an impurity enlarged region is formed by an exposure and development process. After definition, a high concentration (P + ) impurity ion is implanted into the defined semiconductor layer (silicon) to form a source and drain region, thereby completing a bottom gate thin film transistor.
한편 제2도는 종래 제2실시예의 박막 트랜지스터의 공정단면도로써 탑게이트(Top Gate)박막 트랜지스터를 제조하였다.On the other hand, Figure 2 is a process cross-sectional view of a conventional thin film transistor of the second embodiment to manufacture a top gate thin film transistor.
제2도 (a)와 같이 절연기판(1) 또는 절연막위에 반도체층(폴리실리콘)(4)을 증착하고, 상기 반도체층(폴리실리콘)에 수직으로 실리콘(Si)불순물 이온주입 한다.As shown in FIG. 2A, a semiconductor layer (polysilicon) 4 is deposited on the insulating substrate 1 or the insulating film, and silicon (Si) impurity ions are implanted perpendicularly to the semiconductor layer (polysilicon).
이때 상기 반도체층(폴리실리콘)(4)의 그레인 격자구조는 수직으로 실리콘(Si)불순물 이온주입함에 따라 수평으로 형성된 그레인(grain) 격자구조가 파괴되어 비정질 실리콘으로 형성된다.At this time, the grain lattice structure of the semiconductor layer (polysilicon) 4 is formed as amorphous silicon by breaking the grain lattice structure formed horizontally by vertically implanting silicon (Si) impurities.
이어서 상기 비정질 실리콘을 560℃∼650℃ 범위에서 장시간(5시간 이상)열처리 하여 재 결정화한 다음, 일정시간이 끝나면 재 결정화된 반도체층(실리콘)(4)에 수직, 수평으로 그레인(grain)이 형성된다.Subsequently, the amorphous silicon is heat-treated in a range of 560 ° C. to 650 ° C. for a long time (at least 5 hours) to recrystallize, and after a predetermined time, grains are vertically and horizontally perpendicular to the recrystallized semiconductor layer (silicon) 4. Is formed.
제2도 (b)와 같이 상기 전면에 게이트 절연막(3)과 폴리실리콘을 차례로 증착하고 게이트 마스크를 이용한 사진식각 공정으로 상기 폴리실리콘을 패터닝하여 게이트전극(2)을 형성한 다음, 상기 상에 제1감광막(6)을 증착하고, 노광 및 현상공정으로 LDD(Lightly Doped Drain) 형성될 영역을 정의한 다음, 상기 정의된 반도체층(폴리실리콘)(4)에 저농도(P-)불순물 이온주입하여 LDD를 형성한다.As shown in FIG. 2 (b), the gate insulating film 3 and the polysilicon are deposited on the entire surface, and the polysilicon is patterned by a photolithography process using a gate mask to form a gate electrode 2, and then After depositing the first photoresist film 6 and defining a region in which an LDD (Lightly Doped Drain) is to be formed by exposure and development, a low concentration (P − ) impurity ion is implanted into the semiconductor layer (polysilicon) 4 defined above. Form an LDD.
이어서 제2도(c)와 같이 상기 제1감광막(6)을 제거한 다음, 제2감광막(7)을 반도체층(실리콘)(4)상에 증착하고 노광 및 현상공정으로 불순물 확산영역을 정의한 후 상기 정의된 반도체층(폴리실리콘)(4)에 고농도(P+)불순물 이온주입하여 종래의 탑게이트(Top Gate) 박막 트랜지스터를 완성한다.Subsequently, as shown in FIG. 2C, the first photoresist film 6 is removed, and then the second photoresist film 7 is deposited on the semiconductor layer 4 and the impurity diffusion region is defined by an exposure and development process. High concentration (P + ) impurity ions are implanted into the semiconductor layer (polysilicon) 4 defined above to complete a conventional Top Gate thin film transistor.
이와같은 종래의 박막 트랜지스터 제조방법에 있어서는 다음과 같은 문제점이 있었다.Such a conventional thin film transistor manufacturing method has the following problems.
첫째, 반도체층에 많은 그레인수가 형성됨에 따라 전자이동시 그레인 경계면에서 전자충돌에 인하여 전류손실이 발생한다.First, as a large number of grains are formed in the semiconductor layer, current loss occurs due to the collision of electrons at grain boundaries during electron movement.
둘째, 반도체층에 수직으로 실리콘 불순물 이온주입으로 반도체층에 수평으로 형성된 그레인 격자구조는 제거되나, 수직으로 형성된 그레인 격자구조는 잔존함에 따라 오프 커런트(Off Current)변화가 심하기 때문에 박막 트랜지스터의 신뢰성 및 집적도에 어려움이 있다.Second, the grain lattice structure formed horizontally in the semiconductor layer is removed by the implantation of silicon impurity ions perpendicularly to the semiconductor layer, but since the grain lattice structure formed vertically remains off current, the reliability of the thin film transistor is increased. There is difficulty in density.
이에 본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로써 온/오프(On/Off Current)특성을 개선하여 박막 트랜지스터를 고집적화 하는 데 그 목적이 있다.Accordingly, an object of the present invention is to improve the On / Off (Characteristics On / Off Current) characteristics to solve the above problems, and to provide high integration of thin film transistors.
이와 같은 목적을 달성하기 위한 본 발명의 박막 트랜지스터 제조방법은 절연기판위에 게이트전극을 형성하고 전면에 게이트 절연막과 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화 하고, 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경사지게 90°회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘을 2차 결정화시켜 그레인을 형성하는 공정, 상기 2차 결정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하고, 절연기판상에 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을1차 결정화하고 선택적으로 식각하여 활성영역을 형성하는 공정, 상기1차 결정화된 실리콘에 교차되도록 경사지게 90°회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘층을 2차 결정화시켜, 그레인을 형성하는 공정, 전면에 게이트 절연막과 게이트용 반도체층을 차례로 증착하고, 상기 게이트용 반도체층을 선택적으로 식각하여 게이트 전극을 형성하는 공정, 상기2차 결정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.The thin film transistor manufacturing method of the present invention for achieving the above object is a process of forming a gate electrode on an insulating substrate, a gate insulating film and an amorphous silicon layer on the front surface, the first crystallization of the amorphous silicon layer and selectively etching Forming an active region, rotating the wafer 90 ° so as to intersect the first crystallized silicon, implanting silicon ions to form amorphous silicon, forming the grain by secondary crystallization of the amorphous silicon, and the second crystallization And forming an impurity diffusion region by selectively implanting impurity ions into the silicon layer, and forming an amorphous silicon layer on an insulating substrate, and first crystallizing and selectively etching the amorphous silicon layer. To form an active region, the first crystallized silicon A process of forming an amorphous silicon by injecting silicon ions by inclining 90 ° to cross to form an amorphous silicon, forming a grain by second crystallizing the amorphous silicon layer, depositing a gate insulating film and a gate semiconductor layer on the entire surface, and sequentially And forming a gate electrode by selectively etching the semiconductor layer for forming the semiconductor layer, and forming an impurity diffusion region by selectively implanting impurity ions into the secondary crystallized silicon layer.
상기와 같은 본 발명은 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention as described above will be described in detail with reference to the accompanying drawings.
제3도는 본 발명 제1실시예의 박막 트랜지스터 공정단면도이고, 제5도는 본 발명 제1실시예의 박막 트랜지스터 사시도이다.3 is a cross-sectional view of a thin film transistor process according to the first embodiment of the present invention, and FIG. 5 is a perspective view of the thin film transistor according to the first embodiment of the present invention.
제3도는 제5도의 A-A′ 선상을 나타낸 것이다.FIG. 3 shows the line A-A 'of FIG.
제3도(a)와 같이 절연기판(1) 또는 절연막위에 게이트용 폴리실리콘을 증착하고 게이트 마스크를 이용한 사진식각 공정으로 게이트용 폴리실리콘을 패터닝하여 게이트전극(2)을 형성한다.As shown in FIG. 3A, the gate polysilicon is deposited on the insulating substrate 1 or the insulating layer, and the gate polysilicon is formed by patterning the gate polysilicon by a photolithography process using a gate mask.
이때 게이트전극(2) 형성시 증착한 폴리실리콘 대신 인시투 도핑된(In-Situ Doped) 폴리실리콘 또는 비정질 실리콘 인시투 도핑되지 않은 폴리실리콘 또는 비정질 실리콘 포클 도핑(PoCl3Doping)한 비정질 실리콘으로 증착하고 식각하여 게이트전극(2)을 형성하여도 무방하다.The gate electrode 2 is deposited a polysilicon instead of in-situ doped (In-Situ Doped) of polysilicon or amorphous silicon-situ non-doped polysilicon or amorphous silicon pokeul doped (PoCl 3 Doping) deposited in the amorphous silicon during the formation And the gate electrode 2 may be formed by etching.
이어서 상기 전면에 게이트 절연막(3)과 반도체층(비정질 실리콘)(5)을 차례로 형성하고 500℃∼1000℃ 범위에서 일절시간 열처리하여 상기 반도체층(비정질 실리콘)(5)을 실리콘으로 1차 결정화 한다.Subsequently, a gate insulating film 3 and a semiconductor layer (amorphous silicon) 5 are sequentially formed on the entire surface, and heat-treated at 500 ° C. to 1000 ° C. for a period of time to first crystallize the semiconductor layer (amorphous silicon) 5 to silicon. do.
그리고 상기 게이트 절연막(3)은 고온산화막(High Temperature Oxide), 고온저압 절연막(High Temperature Low Pressure Dielectric), 저온산화막(Low Temperature Oxide), 열적확산에 의한 산화막(Rapid Thermal Process Oxide) 열처리를 통한 고온산화막, 저온산화막, 고온저압 산화막등으로 형성한다.The gate insulating film 3 may be formed by a high temperature through heat treatment of a high temperature oxide film, a high temperature low pressure dielectric, a low temperature oxide film, and a thermal thermal process oxide. It is formed of an oxide film, a low temperature oxide film, a high temperature low pressure oxide film, or the like.
이어서 제3도 (b)와 같이 활성(active)마스크를 이용한 사진식각 공정으로 상기 1차 결정화된 반도체층(폴리실리콘)을 선택적으로 패터닝하여 활성영역을 형성한 다음, 상기 활성영역이 형성된 반도체층(폴리실리콘)에 실리콘 불순물 이온주입 한다.Subsequently, as shown in FIG. 3B, an active region is formed by selectively patterning the first crystallized semiconductor layer (polysilicon) using a photolithography process using an active mask, and then a semiconductor layer having the active region formed thereon. Silicon impurity ion implantation into (polysilicon).
이때 실리콘 불순물 이온주입은 상기 반도체층(폴리실리콘)상에 경사지게 이온주입한 다음, 교차되도록 90°회전하여 재차 경사지게 불순물 이온주입 한다.In this case, the silicon impurity ion implantation is implanted at an angle on the semiconductor layer (polysilicon) inclined, and then rotated by 90 ° to cross the impurity ion implantation.
따라서, 상기와 같은 방법으로 실리콘 불순물 이온주입하면 1차 재 결정화된 반도체층(폴리실리콘)의 수직방향과 수평방향의 격자구조가 피괴되어 비정질 실리콘으로 형성된다.Therefore, when silicon impurity ions are implanted in the same manner as described above, the lattice structure in the vertical and horizontal directions of the primary recrystallized semiconductor layer (polysilicon) is destroyed to form amorphous silicon.
이어서 반도체층(비정질 실리콘)(5)을 560℃∼650℃ 범위에서 장시간 열처리하여 폴리실리콘으로 2차 결정화다음, 일정시간이 지나면 2차 결정화 된 반도체층(폴리실리콘)(4)에 그레인(grain)이 형성된다.Subsequently, the semiconductor layer (amorphous silicon) 5 is heat-treated in the range of 560 ° C. to 650 ° C. for a long time to secondary crystallization with polysilicon, and then, after a certain time, grains are formed in the secondary crystallized semiconductor layer (polysilicon) 4. ) Is formed.
제3도(c)와 같이 그레인(grain)이 생성된 반도체층(폴리실리콘)(4)상에 제1감광막(6)을 증착하고, 노광 및 현상공정으로 LDD형성 영역을 정의한 다음, 상기 정의된 반도체층(4)에 저농도(P-) 불순물 이온주입하여 LDD를 형성한다.As shown in FIG. 3 (c), the first photoresist film 6 is deposited on the semiconductor layer (polysilicon) 4 on which grain is formed, and the LDD formation region is defined by an exposure and development process. LDN is formed by implanting low concentration (P − ) impurity ions into the semiconductor layer 4.
이어서 제3도(d)와 같이 상기 제1감광막(6)을 제거한 다음, 제2감광막(7)을 상기 반도체층(폴리실리콘)(4)에 증착하고 노광 및 현상공정으로 채널(channel)영역을 마스킹 한다.Subsequently, the first photoresist film 6 is removed as shown in FIG. 3 (d), and then the second photoresist film 7 is deposited on the semiconductor layer (polysilicon) 4, and the channel region is exposed and developed. Mask it.
이때 드레인영역 또는 소오스영역이 게이트전극(2)과 옵셋(Off-Set)되도록 채널영역을 마스킹 한다.At this time, the channel region is masked so that the drain region or the source region is offset (Off-Set) with the gate electrode 2.
이어서 상기 제2감광막(7)을 마스크로 고농도(P+) 불순물 이온주입하여 불순물 확산영역을 형성함으로써 본 발명의 보텀게이트(Bottom Gate)박막 트랜지스터를 완성한다.Subsequently, the bottom gate thin film transistor of the present invention is completed by forming the impurity diffusion region by implanting high concentration (P + ) impurity ions with the second photoresist film 7 as a mask.
한편 제4도는 본 발명 제2실시예이 박막 트랜지스터 공정단면도로써, 탑게이트(Top Gate) 박막 트랜지스터를 제조하였다.4 is a cross-sectional view illustrating a thin film transistor process according to a second embodiment of the present invention, and a top gate thin film transistor is manufactured.
제4도(a)와 같이 절연기판(1) 또는 절연막위에 반도체층(비정질 실리콘)(5)을 증착하고, 500℃∼1000℃범위에서 일정시간 열처리하여 상기 반도체층(비정질 실리콘)(5)을 폴리실리콘으로 1차 재 결정화한 다음, 활성(active)마스크로 이용한 사진식각 공정으로 1차 재 결정화된 반도체층(폴리실리콘)을 선택적으로 제거하여 활성영역을 형성한 다음, 상기 활성영역이 형성된 반도체층(폴리실리콘)에 실리콘(Si) 불순물이 이온주입 한다.As shown in FIG. 4A, a semiconductor layer (amorphous silicon) 5 is deposited on the insulating substrate 1 or the insulating film, and heat-treated at a temperature in a range of 500 ° C. to 1000 ° C. for a predetermined time. Is first recrystallized with polysilicon, and then selectively removed the first recrystallized semiconductor layer (polysilicon) by a photolithography process using an active mask to form an active region, and then the active region is formed. Silicon (Si) impurities are implanted into the semiconductor layer (polysilicon).
이때 실리콘(Si) 불순물 이온주입은 상기 활성영역이 형성된 반도체층(폴리실리콘)에 경사(tilt)지게 불순물 이온주입한 다음, 교차되도록 90℃회전하여 재차 경사지게 불순물 이온주입 한다.In this case, the silicon (Si) impurity ion implantation is performed by tilting impurity ions into the semiconductor layer (polysilicon) on which the active region is formed, and then rotating the substrate at 90 ° C. so as to cross the impurity ions.
따라서 상기와 같은 방법으로 실리콘(Si) 불순물 이온주입하면, 1차 결정화된 반도체층(폴리실리콘)의 수평방향과 수직방향의 그레인(grain) 격자구조가 파괴되어 비정질 실리콘으로 형성된다.Therefore, when silicon (Si) impurity ions are implanted in the same manner as above, the grain lattice structure in the horizontal and vertical directions of the first crystallized semiconductor layer (polysilicon) is destroyed to form amorphous silicon.
이어서 상기 반도체층(비정질 실리콘)(5)을 560℃∼650℃ 범위에서 장시간 열처리하여 폴리실리콘으로 2차 재 결정화한 다음, 일정시간이 지나면 2차 결정화된 반도체층(폴리실리콘)에 그레인(grain)이 형성된다.Subsequently, the semiconductor layer (amorphous silicon) 5 is heat-treated in the range of 560 ° C. to 650 ° C. for a long time to recrystallize secondary with polysilicon, and after a predetermined time, grains are crystallized into the secondary crystallized semiconductor layer (polysilicon). ) Is formed.
제4도 (b)와 같이 상기 전면에 게이트 절연막(3)과 게이트용 폴리실리콘을 차례로 증착하고 게이트 마스크를 이용한 사진식각 공정으로 상기 게이트용 폴리실리콘을 선택적으로 패터닝하여 게이트전극(2)을 형성한다.As shown in FIG. 4 (b), the gate insulating film 3 and the gate polysilicon are sequentially deposited on the front surface, and the gate polysilicon is formed by selectively patterning the gate polysilicon by a photolithography process using a gate mask. do.
이어서 상기 상에 제1감광막(6)을 증착하고 노광 및 현상공정으로 LDD(Lightly Doped Drain) 형성될 영역을 정의한 다음, 상기 정의된 반도체층(폴리실리콘)에 저농도(P-) 불순물 이온주입하여 LDD을 형성한다.The impurity ions implanted - then the deposited first photoresist layer (6) and the exposure and development process, which defines the region to be formed LDD (Lightly Doped Drain) Then, low-concentration (P) in the semiconductor layer (polysilicon) as defined above to the phase Form an LDD.
제4도 (c)와 같이 상기 제1감광막(6)을 제거한 다음, 상기 상에 제2감광막(7)을 증착하고, 노광 및 현상공정으로 채널영역을 마스킹 한다.After removing the first photoresist film 6 as shown in FIG. 4 (c), the second photoresist film 7 is deposited on the mask, and the channel region is masked by exposure and development processes.
이때 드레인영역 또는 소오스영역이 게이트전극(2)과 옵셋(Off-Set)되도록 채널영역을 마스킹 한다.At this time, the channel region is masked so that the drain region or the source region is offset (Off-Set) with the gate electrode 2.
이어서 상기 제2감광막(7)을 마스크로 고농도(P+) 불순물 이온주입하여 불순물 확산영역을 형성함으로써 본 발명의 탑게이트(Top Gate) 박막 트랜지스터를 완성한다.Subsequently, the top gate thin film transistor of the present invention is completed by forming a dopant diffusion region by implanting high concentration (P + ) impurity ions with the second photosensitive film 7 as a mask.
이상에서 설명한 바와 같은 본 발명의 박막 트랜지스터의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the thin film transistor of the present invention has the following effects.
첫째, 반도체층에 경사(tilt)지고 회전하여 실리콘 이온주입함으로써, 반도체층의 수직과 수형방향의 그레인을 제거함으로써 온/오프 커런트(On/Off Current)를 더욱 개선시킬수 있다.First, by injecting silicon ions by tilting and rotating the semiconductor layer, it is possible to further improve on / off current by removing grains in the vertical and vertical directions of the semiconductor layer.
둘째, 반도체층을 반복 열처리하여 그레인 입자크기를 크게 형성시킴으로써 소자특성이 향상된다.Second, device characteristics are improved by repeatedly heat treating the semiconductor layer to form a large grain size.
Claims (2)
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| KR1019940011194A KR0166782B1 (en) | 1994-05-23 | 1994-05-23 | Methd of manufacturing thin film transistor |
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| KR1019940011194A KR0166782B1 (en) | 1994-05-23 | 1994-05-23 | Methd of manufacturing thin film transistor |
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| KR0166782B1 true KR0166782B1 (en) | 1999-01-15 |
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