KR950034832A - Manufacturing Method of Thin Film Transistor - Google Patents

Manufacturing Method of Thin Film Transistor Download PDF

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KR950034832A
KR950034832A KR1019940011194A KR19940011194A KR950034832A KR 950034832 A KR950034832 A KR 950034832A KR 1019940011194 A KR1019940011194 A KR 1019940011194A KR 19940011194 A KR19940011194 A KR 19940011194A KR 950034832 A KR950034832 A KR 950034832A
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forming
amorphous silicon
silicon layer
ions
oxide film
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KR0166782B1 (en
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나사균
천영일
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명은 반도체 소자인 박막 트랜지스터에 관한 것으로, 특히 SRAM의 메모리 셀(Memory Cell)에 적당하도록 한 박막 트랜지스터의 제조방법에 관한 것이다. 이와 같은 본 발명의 박막 트랜지스터의 제조방법은 절연기판위에 게이트전극을 형성하고 전면에 게이트 절연막과 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화 하고, 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경사지게 90˚회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘을 2차 결정화시켜 그레인을 형성하는 공정, 상기 2차 결정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어지고, 절연기판상에 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화하고 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경상지게 90˚회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘층을 2차 결정화시켜, 그레인을 형성하는 공정, 전면에 게이트 절연막과 게이트용 반도체층을 차례로 증착하고, 상기 게이트용 반도체층을 선택적으로 식각하여 게이트 전극을 형성하는 공정, 상기 2차 결정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, which are semiconductor devices, and more particularly, to a method of manufacturing thin film transistors suitable for memory cells of an SRAM. Such a method of manufacturing a thin film transistor according to the present invention comprises the steps of forming a gate electrode on an insulating substrate and forming a gate insulating film and an amorphous silicon layer on the front surface, primary crystallization of the amorphous silicon layer and selectively etching to form an active region. Forming a grain by forming silicon ions by implanting silicon ions by inclining 90 DEG so as to cross the primary crystallized silicon, forming a grain by secondary crystallization of the amorphous silicon, and forming the grains on the second crystallized silicon layer. Forming an impurity diffusion region by selectively implanting impurity ions, forming an amorphous silicon layer on an insulating substrate, and forming an active region by first crystallizing and selectively etching the amorphous silicon layer When rotating 90˚ thinly to intersect the first crystallized silicon Implanting silicon ions to form amorphous silicon; forming the grains by secondary crystallization of the amorphous silicon layer; depositing a gate insulating film and a gate semiconductor layer in order on the entire surface, and selectively etching the gate semiconductor layer Forming a gate electrode, and selectively implanting impurity ions into the secondary crystallized silicon layer to form an impurity diffusion region.

Description

박막 트랜지스터의 제조방법Manufacturing Method of Thin Film Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 (a)~(d)는 본 발명 제1실시예의 박막 트랜지스터 공정단면도, 제4도 (a)~(c)는 본 발명 제2실시예의 박막 트랜지스터 공정단면도.3A to 3D are cross-sectional views of a thin film transistor of a first embodiment of the present invention, and FIGS. 4A to 4C are cross-sectional views of a thin film transistor of a second embodiment of the present invention.

Claims (8)

절연기판위에 게이트전극을 형성하고 전면에 게이트 절연막과 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화 하고, 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경사지게 90˚회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘을 2차 결정화시켜 그레인을 형성하는 공정, 상기 2차 경정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 박막 트랜지스터의 제조 방법.Forming a gate electrode on an insulating substrate, forming a gate insulating film and an amorphous silicon layer on the front surface, first crystallizing the amorphous silicon layer, and selectively etching to form an active region; intersecting the first crystallized silicon A process of forming silicon amorphous by implanting silicon ions by inclining 90 ° as inclined as possible, forming a grain by secondary crystallizing the amorphous silicon, and implanting impurity diffusion regions by selectively implanting impurity ions into the secondary hardened silicon layer A method of manufacturing a thin film transistor, comprising the step of forming. 제1항에 있어서, 비정질 실리콘층의 1차 결정화 공정은 500℃~1000℃로 5~10분간 열처리하여 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 1, wherein the first crystallization process of the amorphous silicon layer is formed by heat treatment at 500 ° C. to 1000 ° C. for 5 to 10 minutes. 제1항에 있어서, 비정질 실리콘층의 2차 결정화 공정은 560℃~650℃로 장시간 열처리하여 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 1, wherein the secondary crystallization process of the amorphous silicon layer is formed by heat treatment at 560 ° C. to 650 ° C. for a long time. 제1항에 있어서, 게이트전극은 인시투(In-Situ) 도핑된 폴리실리콘 또는 비정질 실리콘, 인시투 도핑되지 않은 폴리실리콘 또는 비정질 실리콘, 포클 도핑된(PoCl3Doping)비정질 실리콘으로 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.2. The gate electrode of claim 1, wherein the gate electrode is formed of in-situ doped polysilicon or amorphous silicon, in-situ-doped polysilicon or amorphous silicon, and PoCl 3 doping amorphous silicon. A manufacturing method of a thin film transistor. 제1항에 있어서, 게이트 절연막을 고온산화막, 고온저압 산화막, 저온산화막, 열적확산에 의한 산화막, 열처리를 통한 고온산화막 또는 저온산화막 또는 고온저압 산화막 등으로 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 1, wherein the gate insulating film is formed of a high temperature oxide film, a high temperature low pressure oxide film, a low temperature oxide film, an oxide film by thermal diffusion, a high temperature oxide film or a low temperature oxide film, or a high temperature low pressure oxide film by heat treatment. . 절연기판상에 비정질 실리콘층을 형성하는 공정, 상기 비정질 실리콘층을 1차 결정화하고 선택적으로 식각하여 활성영역을 형성하는 공정, 상기 1차 결정화된 실리콘에 교차되도록 경사지게 90˚회전시켜 실리콘 이온주입하여 비정질 실리콘으로 형성하는 공정, 상기 비정질 실리콘층을 2차 결정화시켜, 그레인을 형성하는 공정, 전면에 게이트 절연막과 게이트용 반도체층을 차례로 증착하고, 상기 게이트용 반도체층을 선택적으로 식각하여 게이트 전극을 형성하는 공정, 상기 2차 결정화된 실리콘층에 선택적으로 불순물 이온주입하여 불순물 확산영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 박막 트랜지스터의 제조방법.Forming an amorphous silicon layer on an insulating substrate; forming an active region by first crystallizing and selectively etching the amorphous silicon layer; rotating silicon in an inclined 90 ° to cross the primary crystallized silicon and implanting silicon ions; A process of forming amorphous silicon, secondary crystallization of the amorphous silicon layer to form grains, a gate insulating film and a gate semiconductor layer are sequentially deposited on the entire surface, and the gate semiconductor layer is selectively etched to form a gate electrode. And forming the impurity diffusion region by selectively implanting impurity ions into the secondary crystallized silicon layer. 제6항에 있어서, 비정질 실리콘층의 1차 결정화 공정은 500℃~1000℃로 5~10분간 열처리하여 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 6, wherein the first crystallization process of the amorphous silicon layer is formed by heat treatment at 500 ° C. to 1000 ° C. for 5 to 10 minutes. 제6항에 있어서, 비정질 실리콘층의 2차 결정화 공정은 560℃~650℃로 장시간 열처리하여 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 6, wherein the secondary crystallization process of the amorphous silicon layer is formed by heat treatment at 560 ° C. to 650 ° C. for a long time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940011194A 1994-05-23 1994-05-23 Methd of manufacturing thin film transistor KR0166782B1 (en)

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