JPH05109737A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

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Publication number
JPH05109737A
JPH05109737A JP29764791A JP29764791A JPH05109737A JP H05109737 A JPH05109737 A JP H05109737A JP 29764791 A JP29764791 A JP 29764791A JP 29764791 A JP29764791 A JP 29764791A JP H05109737 A JPH05109737 A JP H05109737A
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Prior art keywords
film
region
silicon film
thin film
amorphous silicon
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Pending
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JP29764791A
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Japanese (ja)
Inventor
Hiroyasu Yamada
裕康 山田
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Casio Comput Co Ltd
カシオ計算機株式会社
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Abstract

PURPOSE: To eliminate crystal defect, impurities, etc., from an element activation region, at the time of manufacturing a thin film transistor.
CONSTITUTION: On an insulative substrate 1, an amorphous silicon film 4 is deposited, thereon an oxide film 5 is formed, a photo resist mask 6 which is patterned and formed on the film 5 is us as a mask, and ions are implanted. Thereby only the amorphous silicon film 4 at the part corresponding to a region 3 where an element is not formed is turned into a high impurity region to forin a gettering layer 7. By laser annealing after the photo resist film 6 is eliminated, the amorphous silicon film 4 is crystallized to form a polycrystalline silicon film. At the same time, crystal defect, impurities, etc., in the amorphous silicon film 4 of the part corresponding to an element formation region 2 are made to be absorbed in a high impurity region 7 around the defect and impurities. After that, the oxide film 5 is eliminated, and the polycrystalline silicon film (the gettering layer 7) in unnecessary parts is eliminated by element isolation. In this state, the polycrystalline silicon film is formed only in the element formation region 2 on the insulative substrate 1.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】この発明は薄膜トランジスタの製造方法に関する。 BACKGROUND OF THE INVENTION This invention relates to a method of manufacturing a thin film transistor.

【0002】 [0002]

【従来の技術】シリコンウェーハを用いたトランジスタ製造技術では、ゲッタリング技術を用いて、結晶欠陥や不純物等を素子活性領域から除去することにより、良好な素子特性を得るようにしている。 The transistor fabrication technology using the Related Art Silicon wafers, using a gettering technique, by removing the crystal defects and impurities from the device active region, so as to obtain the excellent device characteristics. 一方、薄膜トランジスタ製造技術では、ガラス等からなる絶縁基板上にアモルファスシリコンやポリシリコン等からなる半導体薄膜を堆積した後素子分離することにより、素子形成領域に半導体薄膜をパターン形成しているので、シリコンウェーハを用いたトランジスタ製造技術で用いられているゲッタリング技術を利用することができない。 On the other hand, in the thin film transistor manufacturing technology, by isolation after depositing a semiconductor thin film made of amorphous silicon, polysilicon, or the like on an insulating substrate made of glass or the like, since the patterning of the semiconductor thin film in the element formation region, a silicon It can not be utilized gettering technique used in the transistor fabrication technology using wafer.

【0003】 [0003]

【発明が解決しようとする課題】このように、従来の薄膜トランジスタ製造技術では、シリコンウェーハを用いたトランジスタ製造技術で用いられているゲッタリング技術を利用することができないので、結晶欠陥や不純物等を素子活性領域から除去することができず、ひいては良好な素子特性を得ることができない場合があるという問題があった。 [Problems that the Invention is to Solve As described above, in the conventional thin film transistor manufacturing techniques, it is not possible to use a gettering technique used in the transistor fabrication technology using a silicon wafer, the crystal defects and impurities, etc. can not be removed from the device active region, there is a problem that it may not be possible to obtain thus excellent device characteristics. この発明の目的は、結晶欠陥や不純物等を素子活性領域から除去することのできる薄膜トランジスタの製造方法を提供することにある。 The purpose of the invention is to provide a method of manufacturing a thin film transistor capable of removing crystal defects and impurities from the device active region.

【0004】 [0004]

【課題を解決するための手段】この発明は、素子形成領域およびその周囲の非素子形成領域に半導体薄膜を堆積し、次いで非素子形成領域に対応する部分の半導体薄膜のみを高不純物領域化してゲッタリング層とし、次いでアニールすることにより、素子形成領域に対応する部分の半導体薄膜における結晶欠陥や不純物等をその周囲のゲッタリング層に吸収させ、次いでゲッタリング層を除去するようにしたものである。 Means for Solving the Problems] The present invention, by depositing a semiconductor thin film in the element forming region and a non-element forming region of the periphery thereof, then only the semiconductor thin film of a portion corresponding to the non-element forming region and the high impurity regions of and a gettering layer, followed by annealing, to absorb the crystal defects and impurities or the like in the semiconductor thin film in the portion corresponding to the element formation region to a gettering layer surrounding, then which was followed by removal of the gettering layer is there.

【0005】 [0005]

【作用】この発明によれば、非素子形成領域に対応する部分の半導体薄膜のみを高不純物領域化してゲッタリング層とした後アニールすることにより、素子形成領域に対応する部分の半導体薄膜における結晶欠陥や不純物等をその周囲のゲッタリング層に吸収させ、この後ゲッタリング層を除去しているので、結晶欠陥や不純物等を素子活性領域から除去することができる。 SUMMARY OF] According to the invention, by annealing after the gettering layer only semiconductor thin film of a portion corresponding to the non-element forming region and the high impurity regions of the crystal in the semiconductor thin film of a portion corresponding to the element formation region to absorb defects and impurities such as gettering layer surrounding, since the removal of the gettering layer after this, it is possible to remove the crystal defects and impurities from the device active region.

【0006】 [0006]

【実施例】図1〜図4はこの発明の一実施例における薄膜トランジスタの各製造工程を示したものである。 EXAMPLES 1 to 4 shows the manufacturing steps of the thin film transistor in an embodiment of the present invention. そこで、これらの図を順に参照しながら、薄膜トランジスタの製造方法について説明する。 Therefore, with reference to the drawings in order to describe a method of manufacturing the thin film transistor.

【0007】まず、図1に示すように、ガラス等からなる絶縁基板1の上面の素子形成領域2およびその周囲の非素子形成領域3にアモルファスシリコン膜4を堆積する。 [0007] First, as shown in FIG. 1, depositing an amorphous silicon film 4 in the non-element forming region 3 of the element formation regions 2 and around the upper surface of the insulating substrate 1 made of glass or the like. 次に、熱酸化により、アモルファスシリコン膜4の上面に酸化膜5を形成する。 Next, by thermal oxidation to form an oxide film 5 on the upper surface of the amorphous silicon film 4. 次に、素子形成領域2に対応する部分の酸化膜5の上面にフォトレジスト膜6をパターン形成する。 Next, the photoresist film 6 is patterned on the upper surface of the oxide film 5 in the portion corresponding to the element formation region 2. 次に、フォトレジスト膜6をマスクとして、非素子形成領域3に対応する部分のアモルファスシリコン膜4にイオン注入装置によりリン、ボロン、アルゴン、酸素、炭素等のゲッタリング用のイオンを注入し、非素子形成領域3に対応する部分のアモルファスシリコン膜4のみを高不純物領域化してゲッタリング層7 Next, the photoresist film 6 as a mask, phosphorus, boron, argon, oxygen, ions for gettering such as carbon is injected into the amorphous silicon film 4 in the portion corresponding to the non-element forming region 3 by ion implantation apparatus, only the amorphous silicon film 4 in the portion corresponding to the non-element forming region 3 and the high impurity regions of the gettering layer 7
とする。 To. この後、フォトレジスト膜6を除去する。 Thereafter, the photoresist film is removed 6.

【0008】次に、図2に示すように、レーザアニールすることにより、アモルファスシリコン膜4を結晶化してポリシリコン膜8とすると共に、素子形成領域2に対応する部分のアモルファスシリコン膜4における結晶欠陥や不純物等をその周囲のゲッタリング層7に吸収させる。 [0008] Next, as shown in FIG. 2, by laser annealing, the amorphous silicon film 4 is crystallized to a polysilicon film 8, the crystals in the amorphous silicon film 4 in the portion corresponding to the element formation region 2 to absorb defects and impurities such as the gettering layer 7 surrounding. この後、酸化膜5を除去し、次いで素子分離により、非素子形成領域3に対応する部分の不要なポリシリコン膜8つまりゲッタリング層7を除去する。 Thereafter, to remove the oxide film 5, followed by isolation, the unnecessary polysilicon film 8, that the gettering layer 7 in the portion corresponding to the non-element forming region 3 is removed. したがって、この状態では、絶縁基板1の上面の素子形成領域2 Therefore, in this state, the element of the upper surface of the insulating substrate 1 formed region 2
のみにポリシリコン膜8が形成されている。 Polysilicon film 8 is formed on only.

【0009】次に、図3に示すように、全表面に酸化シリコンや窒化シリコン等からなるゲート絶縁膜9を形成する。 [0009] Next, as shown in FIG. 3, a gate insulating film 9 made of silicon oxide or silicon nitride on the entire surface. 次に、ポリシリコン膜8のチャネル領域10に対応する部分のゲート絶縁膜9の上面にアルミニウムからなるゲート電極11をパターン形成する。 Then, a gate electrode 11 made of aluminum on the upper surface of the gate insulating film 9 of the portion corresponding to the channel region 10 of the polysilicon film 8 is patterned. 次に、ゲート電極11をマスクとしてイオン注入装置によりリンやボロン等のソース・ドレイン形成用のイオンを注入し、ゲート電極11の両側におけるポリシリコン膜8にソース・ドレイン領域12を形成する。 Then, the ions for the source and drain formation such as phosphorus or boron is implanted by ion implantation apparatus of the gate electrode 11 as a mask, the polysilicon film 8 on both sides of the gate electrode 11 to form the source and drain regions 12.

【0010】次に、図4に示すように、全表面に酸化シリコンや窒化シリコン等からなる層間絶縁膜13を形成する。 [0010] Next, as shown in FIG. 4, an interlayer insulating film 13 made of silicon oxide or silicon nitride on the entire surface. 次に、ソース・ドレイン領域12に対応する部分の層間絶縁膜13およびゲート絶縁膜9にコンタクトホール14を形成する。 Next, a contact hole 14 in the interlayer insulating film 13 and the gate insulating film 9 of the portion corresponding to the source and drain regions 12. 次に、コンタクトホール14を介してソース・ドレイン領域12と接続されるアルミニウムからなるソース・ドレイン電極15を層間絶縁膜13 Next, an interlayer source-drain electrodes 15 made of aluminum is connected to the source and drain regions 12 via the contact hole 14 insulating film 13
の上面にパターン形成する。 Patterning the upper surface. かくして、薄膜トランジスタが製造される。 Thus, the thin film transistor is manufactured.

【0011】このようにして製造された薄膜トランジスタでは、非素子形成領域3に対応する部分のアモルファスシリコン膜4のみを高不純物領域化してゲッタリング層7とした後アニールすることにより、素子形成領域2 [0011] In such a thin film transistor manufactured in the, by annealing after the gettering layer 7 only amorphous silicon film 4 in the portion corresponding to the non-element forming region 3 and the high impurity region of the element formation region 2
に対応する部分のアモルファスシリコン膜4における結晶欠陥や不純物等をその周囲のゲッタリング層7に吸収させ、この後ゲッタリング層7を除去しているので、結晶欠陥や不純物等を素子活性領域から除去することができ、ひいては良好な素子特性を得ることができる。 The crystal defects and impurities and the like in the amorphous silicon film 4 in the portion corresponding to the absorbed gettering layer 7 surrounding, since the removal of the gettering layer 7 Thereafter, the crystal defects and impurities from the device active region it can be removed, can be obtained and thus excellent device characteristics. また、1回のアニール工程により、アモルファスシリコン膜4を結晶化してポリシリコン膜8とすると同時に、素子形成領域2に対応する部分のアモルファスシリコン膜4における結晶欠陥や不純物等をその周囲のゲッタリング層7に吸収させることができ、また素子分離により、 Further, one of the annealing process, the amorphous silicon film 4 is crystallized at the same time as the polysilicon film 8, the periphery of gettering the crystal defects and impurities and the like in the amorphous silicon film 4 in the portion corresponding to the element formation region 2 can be absorbed into the layer 7, also by the element isolation,
非素子形成領域4に対応する部分の不要なポリシリコン膜8つまりゲッタリング層7を除去しているので、工程数がなるべく増加しないようにすることができる。 Since removal of the unnecessary polysilicon film 8, that the gettering layer 7 in the portion corresponding to the non-element forming region 4, the number of steps can be prevented as much as possible increases. さらに、ゲッタリング用のイオンとしてソース・ドレイン形成用のイオンと同じイオンを用いることにすれば、ゲッタリング用のイオンの注入をソース・ドレイン形成用のイオン注入装置によって行うこともできる。 Moreover, if in using the same ion as the ion for the source and drain formed as ions for gettering can be performed implantation of ions for gettering by the ion implantation apparatus for source and drain formation.

【0012】なお、上記実施例では、絶縁基板1の上面に堆積したアモルファスシリコン膜4を結晶化してポリシリコン膜8としているが、これに限らず、絶縁基板の上面にポリシリコン膜を直接堆積するようにしてもよい。 [0012] In the above embodiment, an amorphous silicon film 4 deposited on the upper surface of the insulating substrate 1 is a polycrystalline silicon film 8 is crystallized, not limited thereto, directly deposited polysilicon film on the upper surface of the insulating substrate it may be. また、イオン注入装置の代わりに、熱拡散法を用いてもよく、またレーザアニールの代わりに、高温熱処理を施してもよい。 Further, instead of the ion implantation apparatus, a thermal diffusion method may be used, also in place of the laser annealing may be subjected to high-temperature heat treatment. さらに、コプラナ型の薄膜トランジスタに限らず、スタガ型の薄膜トランジスタにも適用することができる。 Further, not limited to the coplanar type thin film transistor, it can be applied to staggered thin film transistor.

【0013】 [0013]

【発明の効果】以上説明したように、この発明によれば、非素子形成領域に対応する部分の半導体薄膜のみを高不純物領域化してゲッタリング層とした後アニールすることにより、素子形成領域に対応する部分の半導体薄膜における結晶欠陥や不純物等をその周囲のゲッタリング層に吸収させ、この後ゲッタリング層を除去しているので、結晶欠陥や不純物等を素子活性領域から除去することができ、ひいては良好な素子特性を得ることができる。 As described in the foregoing, according to the present invention, by annealing after the gettering layer only semiconductor thin film of a portion corresponding to the non-element forming region and the high impurity region of, the element formation region the corresponding crystal defects and impurities in the semiconductor thin film portions such as is absorbed into the gettering layer surrounding, since the removal of the gettering layer after this, it is possible to remove the crystal defects and impurities from the device active region , it can be obtained and thus excellent device characteristics.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】この発明の一実施例における薄膜トランジスタの製造に際し、絶縁基板の上面にアモルファスシリコン膜および酸化膜を形成し、さらにその上面にパターン形成したフォトレジスト膜をマスクとしてゲッタリング用のイオンを注入してゲッタリング層を形成した状態の断面図。 [1] In the production of a thin film transistor according to an embodiment of the present invention, the upper surface of the insulating substrate to form an amorphous silicon film and the oxide film, the more ions for gettering a photoresist film patterned on its upper surface as a mask It injected sectional view of a state of forming the gettering layer.

【図2】同薄膜トランジスタの製造に際し、フォトレジスト膜を除去した後レーザアニールすることにより、アモルファスシリコン膜を結晶化してポリシリコン膜とすると共に素子形成領域に対応する部分のアモルファスシリコン膜における結晶欠陥や不純物等をその周囲のゲッタリング層に吸収させた状態の断面図。 [2] In the production of the thin film transistor, by laser annealing after removing the photoresist film, the crystal defects in the amorphous silicon film in the portion corresponding to the element formation regions with an amorphous silicon film is crystallized to a polysilicon film sectional view of the state of being absorbed or impurities such as the gettering layer surrounding.

【図3】同薄膜トランジスタの製造に際し、酸化膜および不要なポリシリコン膜(ゲッタリング層)を除去した後ゲート絶縁膜およびゲート電極を形成し、さらにゲート電極をマスクとしてソース・ドレイン形成用のイオンを注入してソース・ドレイン領域を形成した状態の断面図。 [3] In the production of the thin film transistor, the oxide film and the unnecessary polysilicon film (gettering layer) forming a gate insulating film and a gate electrode after removal of further ions for the source and drain formation of the gate electrode as a mask sectional view of injecting a state in which a source-drain region.

【図4】同薄膜トランジスタの製造に際し、層間絶縁膜、コンタクトホールおよびソース・ドレイン電極を形成した状態の断面図。 [4] In the production of the thin film transistor, an interlayer insulating film, cross-sectional view of a state of forming contact holes and source and drain electrodes.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 絶縁基板 2 素子形成領域 3 非素子形成領域 4 アモルファスシリコン膜 5 酸化膜 7 ゲッタリング層 8 ポリシリコン膜 1 insulating substrate 2 element forming region 3 non element forming region 4 the amorphous silicon film 5 oxide film 7 gettering layer 8 polysilicon film

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 素子形成領域およびその周囲の非素子形成領域に半導体薄膜を堆積し、次いで前記非素子形成領域に対応する部分の前記半導体薄膜のみを高不純物領域化してゲッタリング層とし、次いでアニールすることにより、前記素子形成領域に対応する部分の前記半導体薄膜における結晶欠陥や不純物等をその周囲の前記ゲッタリング層に吸収させ、次いで該ゲッタリング層を除去することを特徴とする薄膜トランジスタの製造方法。 1. A deposit a semiconductor thin film in the element forming region and a non-element forming region of the periphery thereof, then the gettering layer and the high impurity region of only the semiconductor thin film in a portion corresponding to the non-element forming region, then by annealing, the said portion corresponding to the element formation region semiconductor crystal defects in thin films and impurities absorbed on the gettering layer surrounding, then the thin film transistor and removing the gettering layer Production method.
JP29764791A 1991-10-18 1991-10-18 Manufacture of thin film transistor Pending JPH05109737A (en)

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