JPH05109737A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

Info

Publication number
JPH05109737A
JPH05109737A JP29764791A JP29764791A JPH05109737A JP H05109737 A JPH05109737 A JP H05109737A JP 29764791 A JP29764791 A JP 29764791A JP 29764791 A JP29764791 A JP 29764791A JP H05109737 A JPH05109737 A JP H05109737A
Authority
JP
Japan
Prior art keywords
film
silicon film
region
thin film
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29764791A
Other languages
Japanese (ja)
Inventor
Hiroyasu Yamada
裕康 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP29764791A priority Critical patent/JPH05109737A/en
Publication of JPH05109737A publication Critical patent/JPH05109737A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To eliminate crystal defect, impurities, etc., from an element activation region, at the time of manufacturing a thin film transistor. CONSTITUTION:On an insulative substrate 1, an amorphous silicon film 4 is deposited, thereon an oxide film 5 is formed, a photo resist mask 6 which is patterned and formed on the film 5 is us as a mask, and ions are implanted. Thereby only the amorphous silicon film 4 at the part corresponding to a region 3 where an element is not formed is turned into a high impurity region to forin a gettering layer 7. By laser annealing after the photo resist film 6 is eliminated, the amorphous silicon film 4 is crystallized to form a polycrystalline silicon film. At the same time, crystal defect, impurities, etc., in the amorphous silicon film 4 of the part corresponding to an element formation region 2 are made to be absorbed in a high impurity region 7 around the defect and impurities. After that, the oxide film 5 is eliminated, and the polycrystalline silicon film (the gettering layer 7) in unnecessary parts is eliminated by element isolation. In this state, the polycrystalline silicon film is formed only in the element formation region 2 on the insulative substrate 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は薄膜トランジスタの製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

【0002】[0002]

【従来の技術】シリコンウェーハを用いたトランジスタ
製造技術では、ゲッタリング技術を用いて、結晶欠陥や
不純物等を素子活性領域から除去することにより、良好
な素子特性を得るようにしている。一方、薄膜トランジ
スタ製造技術では、ガラス等からなる絶縁基板上にアモ
ルファスシリコンやポリシリコン等からなる半導体薄膜
を堆積した後素子分離することにより、素子形成領域に
半導体薄膜をパターン形成しているので、シリコンウェ
ーハを用いたトランジスタ製造技術で用いられているゲ
ッタリング技術を利用することができない。
2. Description of the Related Art In a transistor manufacturing technique using a silicon wafer, a gettering technique is used to remove crystal defects, impurities and the like from an element active region to obtain good element characteristics. On the other hand, in the thin film transistor manufacturing technology, since a semiconductor thin film made of amorphous silicon, polysilicon, or the like is deposited on an insulating substrate made of glass or the like and then elements are separated, the semiconductor thin film is patterned in the element formation region. The gettering technology used in the transistor manufacturing technology using a wafer cannot be used.

【0003】[0003]

【発明が解決しようとする課題】このように、従来の薄
膜トランジスタ製造技術では、シリコンウェーハを用い
たトランジスタ製造技術で用いられているゲッタリング
技術を利用することができないので、結晶欠陥や不純物
等を素子活性領域から除去することができず、ひいては
良好な素子特性を得ることができない場合があるという
問題があった。この発明の目的は、結晶欠陥や不純物等
を素子活性領域から除去することのできる薄膜トランジ
スタの製造方法を提供することにある。
As described above, in the conventional thin film transistor manufacturing technology, the gettering technology used in the transistor manufacturing technology using the silicon wafer cannot be utilized, so that crystal defects, impurities, etc. are eliminated. There is a problem in that it may not be possible to remove from the element active region, and eventually good element characteristics may not be obtained. An object of the present invention is to provide a method of manufacturing a thin film transistor capable of removing crystal defects, impurities and the like from an element active region.

【0004】[0004]

【課題を解決するための手段】この発明は、素子形成領
域およびその周囲の非素子形成領域に半導体薄膜を堆積
し、次いで非素子形成領域に対応する部分の半導体薄膜
のみを高不純物領域化してゲッタリング層とし、次いで
アニールすることにより、素子形成領域に対応する部分
の半導体薄膜における結晶欠陥や不純物等をその周囲の
ゲッタリング層に吸収させ、次いでゲッタリング層を除
去するようにしたものである。
According to the present invention, a semiconductor thin film is deposited in a device forming region and a non-device forming region around the device forming region, and then only a portion of the semiconductor thin film corresponding to the non-device forming region is made into a high impurity region. A gettering layer is formed and then annealed so that crystal defects, impurities, etc. in the semiconductor thin film in the portion corresponding to the element formation region are absorbed in the surrounding gettering layer, and then the gettering layer is removed. is there.

【0005】[0005]

【作用】この発明によれば、非素子形成領域に対応する
部分の半導体薄膜のみを高不純物領域化してゲッタリン
グ層とした後アニールすることにより、素子形成領域に
対応する部分の半導体薄膜における結晶欠陥や不純物等
をその周囲のゲッタリング層に吸収させ、この後ゲッタ
リング層を除去しているので、結晶欠陥や不純物等を素
子活性領域から除去することができる。
According to the present invention, only the semiconductor thin film in the portion corresponding to the non-element formation region is made into a high impurity region to form a gettering layer and then annealed to crystallize the semiconductor thin film in the portion corresponding to the element formation region. Defects, impurities, etc. are absorbed by the gettering layer around them, and the gettering layer is removed thereafter. Therefore, crystal defects, impurities, etc. can be removed from the element active region.

【0006】[0006]

【実施例】図1〜図4はこの発明の一実施例における薄
膜トランジスタの各製造工程を示したものである。そこ
で、これらの図を順に参照しながら、薄膜トランジスタ
の製造方法について説明する。
1 to 4 show the steps of manufacturing a thin film transistor according to an embodiment of the present invention. Therefore, a method of manufacturing a thin film transistor will be described with reference to these drawings in order.

【0007】まず、図1に示すように、ガラス等からな
る絶縁基板1の上面の素子形成領域2およびその周囲の
非素子形成領域3にアモルファスシリコン膜4を堆積す
る。次に、熱酸化により、アモルファスシリコン膜4の
上面に酸化膜5を形成する。次に、素子形成領域2に対
応する部分の酸化膜5の上面にフォトレジスト膜6をパ
ターン形成する。次に、フォトレジスト膜6をマスクと
して、非素子形成領域3に対応する部分のアモルファス
シリコン膜4にイオン注入装置によりリン、ボロン、ア
ルゴン、酸素、炭素等のゲッタリング用のイオンを注入
し、非素子形成領域3に対応する部分のアモルファスシ
リコン膜4のみを高不純物領域化してゲッタリング層7
とする。この後、フォトレジスト膜6を除去する。
First, as shown in FIG. 1, an amorphous silicon film 4 is deposited on a device forming region 2 on the upper surface of an insulating substrate 1 made of glass or the like and a non-device forming region 3 around the device forming region 2. Next, an oxide film 5 is formed on the upper surface of the amorphous silicon film 4 by thermal oxidation. Next, a photoresist film 6 is patterned on the upper surface of the oxide film 5 in the portion corresponding to the element formation region 2. Then, using the photoresist film 6 as a mask, ions of gettering such as phosphorus, boron, argon, oxygen, and carbon are implanted into the amorphous silicon film 4 in a portion corresponding to the non-element formation region 3 by an ion implantation device, Only the portion of the amorphous silicon film 4 corresponding to the non-element formation region 3 is made into a high impurity region and the gettering layer 7 is formed.
And After that, the photoresist film 6 is removed.

【0008】次に、図2に示すように、レーザアニール
することにより、アモルファスシリコン膜4を結晶化し
てポリシリコン膜8とすると共に、素子形成領域2に対
応する部分のアモルファスシリコン膜4における結晶欠
陥や不純物等をその周囲のゲッタリング層7に吸収させ
る。この後、酸化膜5を除去し、次いで素子分離によ
り、非素子形成領域3に対応する部分の不要なポリシリ
コン膜8つまりゲッタリング層7を除去する。したがっ
て、この状態では、絶縁基板1の上面の素子形成領域2
のみにポリシリコン膜8が形成されている。
Next, as shown in FIG. 2, laser annealing is performed to crystallize the amorphous silicon film 4 to form a polysilicon film 8 and to crystallize the amorphous silicon film 4 in a portion corresponding to the element formation region 2. Defects and impurities are absorbed by the gettering layer 7 around the defects. After that, the oxide film 5 is removed, and then the unnecessary polysilicon film 8, that is, the gettering layer 7 in the portion corresponding to the non-element formation region 3 is removed by element isolation. Therefore, in this state, the element formation region 2 on the upper surface of the insulating substrate 1 is formed.
The polysilicon film 8 is formed only on the above.

【0009】次に、図3に示すように、全表面に酸化シ
リコンや窒化シリコン等からなるゲート絶縁膜9を形成
する。次に、ポリシリコン膜8のチャネル領域10に対
応する部分のゲート絶縁膜9の上面にアルミニウムから
なるゲート電極11をパターン形成する。次に、ゲート
電極11をマスクとしてイオン注入装置によりリンやボ
ロン等のソース・ドレイン形成用のイオンを注入し、ゲ
ート電極11の両側におけるポリシリコン膜8にソース
・ドレイン領域12を形成する。
Next, as shown in FIG. 3, a gate insulating film 9 made of silicon oxide, silicon nitride or the like is formed on the entire surface. Next, a gate electrode 11 made of aluminum is patterned on the upper surface of the gate insulating film 9 in a portion of the polysilicon film 8 corresponding to the channel region 10. Next, with the gate electrode 11 as a mask, source / drain forming ions such as phosphorus and boron are implanted by an ion implanter to form source / drain regions 12 in the polysilicon film 8 on both sides of the gate electrode 11.

【0010】次に、図4に示すように、全表面に酸化シ
リコンや窒化シリコン等からなる層間絶縁膜13を形成
する。次に、ソース・ドレイン領域12に対応する部分
の層間絶縁膜13およびゲート絶縁膜9にコンタクトホ
ール14を形成する。次に、コンタクトホール14を介
してソース・ドレイン領域12と接続されるアルミニウ
ムからなるソース・ドレイン電極15を層間絶縁膜13
の上面にパターン形成する。かくして、薄膜トランジス
タが製造される。
Next, as shown in FIG. 4, an interlayer insulating film 13 made of silicon oxide, silicon nitride or the like is formed on the entire surface. Next, contact holes 14 are formed in the interlayer insulating film 13 and the gate insulating film 9 in the portions corresponding to the source / drain regions 12. Next, the source / drain electrode 15 made of aluminum and connected to the source / drain region 12 through the contact hole 14 is formed on the interlayer insulating film 13.
Pattern on the upper surface of the. Thus, the thin film transistor is manufactured.

【0011】このようにして製造された薄膜トランジス
タでは、非素子形成領域3に対応する部分のアモルファ
スシリコン膜4のみを高不純物領域化してゲッタリング
層7とした後アニールすることにより、素子形成領域2
に対応する部分のアモルファスシリコン膜4における結
晶欠陥や不純物等をその周囲のゲッタリング層7に吸収
させ、この後ゲッタリング層7を除去しているので、結
晶欠陥や不純物等を素子活性領域から除去することがで
き、ひいては良好な素子特性を得ることができる。ま
た、1回のアニール工程により、アモルファスシリコン
膜4を結晶化してポリシリコン膜8とすると同時に、素
子形成領域2に対応する部分のアモルファスシリコン膜
4における結晶欠陥や不純物等をその周囲のゲッタリン
グ層7に吸収させることができ、また素子分離により、
非素子形成領域4に対応する部分の不要なポリシリコン
膜8つまりゲッタリング層7を除去しているので、工程
数がなるべく増加しないようにすることができる。さら
に、ゲッタリング用のイオンとしてソース・ドレイン形
成用のイオンと同じイオンを用いることにすれば、ゲッ
タリング用のイオンの注入をソース・ドレイン形成用の
イオン注入装置によって行うこともできる。
In the thin film transistor manufactured as described above, only the amorphous silicon film 4 in the portion corresponding to the non-element formation region 3 is made into a high impurity region to form the gettering layer 7 and then annealed to obtain the element formation region 2
The crystal defects and impurities in the portion of the amorphous silicon film 4 corresponding to are absorbed in the gettering layer 7 around the crystal defects, and the gettering layer 7 is removed thereafter. It can be removed, and good device characteristics can be obtained. Further, the amorphous silicon film 4 is crystallized into the polysilicon film 8 by one annealing step, and at the same time, crystal defects, impurities, etc. in the amorphous silicon film 4 in the portion corresponding to the element formation region 2 are gettered around the amorphous silicon film 4. Can be absorbed in the layer 7, and due to element isolation,
Since the unnecessary polysilicon film 8 in the portion corresponding to the non-element formation region 4, that is, the gettering layer 7, is removed, the number of steps can be prevented from increasing as much as possible. Further, if the same ions as the source / drain forming ions are used as the gettering ions, the gettering ions can be implanted by the source / drain forming ion implantation apparatus.

【0012】なお、上記実施例では、絶縁基板1の上面
に堆積したアモルファスシリコン膜4を結晶化してポリ
シリコン膜8としているが、これに限らず、絶縁基板の
上面にポリシリコン膜を直接堆積するようにしてもよ
い。また、イオン注入装置の代わりに、熱拡散法を用い
てもよく、またレーザアニールの代わりに、高温熱処理
を施してもよい。さらに、コプラナ型の薄膜トランジス
タに限らず、スタガ型の薄膜トランジスタにも適用する
ことができる。
In the above embodiment, the amorphous silicon film 4 deposited on the upper surface of the insulating substrate 1 is crystallized to form the polysilicon film 8. However, the present invention is not limited to this, and the polysilicon film is directly deposited on the upper surface of the insulating substrate. You may do so. Further, a thermal diffusion method may be used instead of the ion implantation apparatus, and high temperature heat treatment may be performed instead of laser annealing. Further, the invention can be applied not only to the coplanar type thin film transistor but also to a stagger type thin film transistor.

【0013】[0013]

【発明の効果】以上説明したように、この発明によれ
ば、非素子形成領域に対応する部分の半導体薄膜のみを
高不純物領域化してゲッタリング層とした後アニールす
ることにより、素子形成領域に対応する部分の半導体薄
膜における結晶欠陥や不純物等をその周囲のゲッタリン
グ層に吸収させ、この後ゲッタリング層を除去している
ので、結晶欠陥や不純物等を素子活性領域から除去する
ことができ、ひいては良好な素子特性を得ることができ
る。
As described above, according to the present invention, only the semiconductor thin film in the portion corresponding to the non-element formation region is made into a high impurity region to form a gettering layer and then annealed to form the element formation region. Since crystal defects, impurities, etc. in the corresponding portion of the semiconductor thin film are absorbed by the gettering layer around it and the gettering layer is removed thereafter, crystal defects, impurities, etc. can be removed from the element active region. As a result, good device characteristics can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例における薄膜トランジスタ
の製造に際し、絶縁基板の上面にアモルファスシリコン
膜および酸化膜を形成し、さらにその上面にパターン形
成したフォトレジスト膜をマスクとしてゲッタリング用
のイオンを注入してゲッタリング層を形成した状態の断
面図。
FIG. 1 is a cross-sectional view showing a method of manufacturing a thin film transistor according to an embodiment of the present invention, in which an amorphous silicon film and an oxide film are formed on an upper surface of an insulating substrate, and a patterned photoresist film is used as a mask to generate ions for gettering. Sectional drawing of the state which inject | poured and formed the gettering layer.

【図2】同薄膜トランジスタの製造に際し、フォトレジ
スト膜を除去した後レーザアニールすることにより、ア
モルファスシリコン膜を結晶化してポリシリコン膜とす
ると共に素子形成領域に対応する部分のアモルファスシ
リコン膜における結晶欠陥や不純物等をその周囲のゲッ
タリング層に吸収させた状態の断面図。
FIG. 2 is a view showing a crystal defect in a portion of the amorphous silicon film corresponding to an element formation region, which is obtained by crystallizing the amorphous silicon film into a polysilicon film by laser annealing after removing the photoresist film in manufacturing the same thin film transistor. FIG. 6 is a cross-sectional view showing a state in which impurities such as impurities are absorbed by a gettering layer around the impurities.

【図3】同薄膜トランジスタの製造に際し、酸化膜およ
び不要なポリシリコン膜(ゲッタリング層)を除去した
後ゲート絶縁膜およびゲート電極を形成し、さらにゲー
ト電極をマスクとしてソース・ドレイン形成用のイオン
を注入してソース・ドレイン領域を形成した状態の断面
図。
FIG. 3 is a view showing an ion for forming a source / drain when a gate insulating film and a gate electrode are formed after removing an oxide film and an unnecessary polysilicon film (gettering layer) in manufacturing the same thin-film transistor. FIG. 4 is a cross-sectional view showing a state where source / drain regions are formed by implanting silicon.

【図4】同薄膜トランジスタの製造に際し、層間絶縁
膜、コンタクトホールおよびソース・ドレイン電極を形
成した状態の断面図。
FIG. 4 is a cross-sectional view showing a state in which an interlayer insulating film, contact holes, and source / drain electrodes are formed in manufacturing the same thin film transistor.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 素子形成領域 3 非素子形成領域 4 アモルファスシリコン膜 5 酸化膜 7 ゲッタリング層 8 ポリシリコン膜 1 Insulating Substrate 2 Element Forming Area 3 Non-Element Forming Area 4 Amorphous Silicon Film 5 Oxide Film 7 Gettering Layer 8 Polysilicon Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 素子形成領域およびその周囲の非素子形
成領域に半導体薄膜を堆積し、次いで前記非素子形成領
域に対応する部分の前記半導体薄膜のみを高不純物領域
化してゲッタリング層とし、次いでアニールすることに
より、前記素子形成領域に対応する部分の前記半導体薄
膜における結晶欠陥や不純物等をその周囲の前記ゲッタ
リング層に吸収させ、次いで該ゲッタリング層を除去す
ることを特徴とする薄膜トランジスタの製造方法。
1. A semiconductor thin film is deposited on an element formation region and a non-element formation region around the element formation region, and then only a portion of the semiconductor thin film corresponding to the non-element formation region is made into a high impurity region to form a gettering layer. By annealing, a crystal defect, an impurity, or the like in the semiconductor thin film in a portion corresponding to the element forming region is absorbed in the gettering layer around it, and then the gettering layer is removed. Production method.
JP29764791A 1991-10-18 1991-10-18 Manufacture of thin film transistor Pending JPH05109737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29764791A JPH05109737A (en) 1991-10-18 1991-10-18 Manufacture of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29764791A JPH05109737A (en) 1991-10-18 1991-10-18 Manufacture of thin film transistor

Publications (1)

Publication Number Publication Date
JPH05109737A true JPH05109737A (en) 1993-04-30

Family

ID=17849297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29764791A Pending JPH05109737A (en) 1991-10-18 1991-10-18 Manufacture of thin film transistor

Country Status (1)

Country Link
JP (1) JPH05109737A (en)

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US5843225A (en) * 1993-02-03 1998-12-01 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
US5915174A (en) * 1994-09-30 1999-06-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for producing the same
US5956579A (en) * 1993-02-15 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
US6133119A (en) * 1996-07-08 2000-10-17 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device and method manufacturing same
US6197626B1 (en) 1997-02-26 2001-03-06 Semiconductor Energy Laboratory Co. Method for fabricating semiconductor device
US6251712B1 (en) 1995-03-27 2001-06-26 Semiconductor Energy Laboratory Co., Ltd. Method of using phosphorous to getter crystallization catalyst in a p-type device
US6319761B1 (en) 1993-06-22 2001-11-20 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US6337231B1 (en) * 1993-05-26 2002-01-08 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6348368B1 (en) * 1997-10-21 2002-02-19 Semiconductor Energy Laboratory Co., Ltd. Introducing catalytic and gettering elements with a single mask when manufacturing a thin film semiconductor device
JP2002203788A (en) * 2000-12-27 2002-07-19 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
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