JPH10333185A - Semiconductor device and its manufacture, and tft type liquid crystal display device - Google Patents

Semiconductor device and its manufacture, and tft type liquid crystal display device

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Publication number
JPH10333185A
JPH10333185A JP14768797A JP14768797A JPH10333185A JP H10333185 A JPH10333185 A JP H10333185A JP 14768797 A JP14768797 A JP 14768797A JP 14768797 A JP14768797 A JP 14768797A JP H10333185 A JPH10333185 A JP H10333185A
Authority
JP
Japan
Prior art keywords
silicon film
film
insulating film
polycrystalline silicon
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14768797A
Other languages
Japanese (ja)
Inventor
Kenji Mitsui
健二 三井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14768797A priority Critical patent/JPH10333185A/en
Publication of JPH10333185A publication Critical patent/JPH10333185A/en
Pending legal-status Critical Current

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain the semiconductor device which can decrease a leak current and make variance of transistor characteristics small by stabilizing the boundary surface between a gate insulating film and a polycrystalline silicon film and is simple in manufacture process by forming an amorphous silicon film containing hydrogen between a polycrystalline silicon film and a gate insulating film. SOLUTION: A two-layered structure film is laminated on a glass substrate 1 in the order of the polycrystalline silicon film 13' and amorphous silicon film 13. Then the gate insulating film 15 is formed on the amorphous silicon film 13, a gate electrode 16 is formed on the gate insulating film 15, and an inter-layer insulating film 17 is formed on the gate electrode 16. A source-drain wire electrode 19 is connected to the amorphous silicon film 13 through the inter-layer insulating film 17. Namely, this semiconductor device has the boundary surface between the gate insulating film 15 and polycrystalline silicon film 13 stabilized with hydrogen that the amorphous silicon film 13 contains since the amorphous silicon film 13 containing the hydrogen is formed between the polycrystalline silicon film 13' and gate insulating film 15.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、多結晶珪素膜を
用いたトランジスタのチャンネルを安定に形成するため
の半導体装置およびその製造方法ならびにTFT型液晶
表示装置に関するものである。
The present invention relates to a semiconductor device for stably forming a channel of a transistor using a polycrystalline silicon film, a method of manufacturing the same, and a TFT type liquid crystal display device.

【0002】[0002]

【従来の技術】近年のTFT型液晶表示装置は、パーソ
ナルコンピュータおよび電子式カメラ等に広く使用さ
れ、その使いやすさからさらに使用環境が広がり、高密
度・高性能であるものが要求されている。また、さらな
る特性の向上のため、非晶質珪素膜を用いたトランジス
タから多結晶珪素膜を用いたトランジスタへと開発が進
んでいる。
2. Description of the Related Art In recent years, TFT type liquid crystal display devices have been widely used in personal computers, electronic cameras, and the like. . Further, in order to further improve the characteristics, a transistor using an amorphous silicon film has been developed to a transistor using a polycrystalline silicon film.

【0003】以下図面を参照しながら、上記した多結晶
珪素膜を用いた従来のTFT型液晶表示装置の半導体装
置の製造方法の一例について説明する。図2の(a)〜
(c)は、従来の多結晶珪素膜を用いたTFT型液晶表
示装置の製造方法の工程の概略を示す断面図である。T
FT素子の形成は、まずガラス基板1の表面に化学気相
蒸着方法で約200nm厚さの二酸化珪素膜2と約60
nm厚さの非晶質珪素膜3を形成したのち、そのガラス
基板1を真空中で約450℃に加熱して非晶質珪素膜形
成工程中に取り込まれた水素等の脱ガスを行った後、エ
キシマレーザー光照射あるいは急速表面加熱方法等によ
り加熱処理を行い、非晶質珪素膜を多結晶化3′し、そ
の上にフォトレジストパターン4を形成する(図2
(a))。次にそのフォトレジストパターン4をマスク
にして多結晶珪素膜3’をエッチングし、フォトレジス
ト4を除去してから二酸化珪素膜を用いたゲート絶縁膜
5を約100nmの厚さに形成した後、アルミニウム
(Al)配線を形成してゲート電極6とする。つぎにイ
オン注入方法で硼素あるいは燐等の不純物を注入して、
トランジスタのソース・ドレイン10を形成する(図2
(b))。その後、二酸化珪素膜を用いた層間絶縁膜7
を約350nmの厚さに形成し、配線接続のためのコン
タクト穴8と配線電極9を所定のパターンにエッチング
により形成する(図2(c))。
Hereinafter, an example of a method of manufacturing a conventional semiconductor device of a TFT type liquid crystal display device using the above-mentioned polycrystalline silicon film will be described with reference to the drawings. FIG.
(C) is a sectional view showing an outline of a process of a method of manufacturing a TFT type liquid crystal display device using a conventional polycrystalline silicon film. T
The FT element is formed by first forming a silicon dioxide film 2 having a thickness of about 200 nm on a surface of a glass substrate 1 by a chemical vapor deposition method.
After forming an amorphous silicon film 3 having a thickness of nm, the glass substrate 1 was heated to about 450 ° C. in a vacuum to degas hydrogen and the like taken in during the amorphous silicon film forming step. Thereafter, a heat treatment is performed by excimer laser light irradiation or a rapid surface heating method, etc., so that the amorphous silicon film is polycrystallized 3 ', and a photoresist pattern 4 is formed thereon (FIG. 2).
(A)). Next, using the photoresist pattern 4 as a mask, the polycrystalline silicon film 3 ′ is etched to remove the photoresist 4 and form a gate insulating film 5 using a silicon dioxide film to a thickness of about 100 nm. An aluminum (Al) wiring is formed to form a gate electrode 6. Next, impurities such as boron or phosphorus are implanted by an ion implantation method,
The source / drain 10 of the transistor is formed (FIG. 2)
(B)). Then, an interlayer insulating film 7 using a silicon dioxide film is formed.
Is formed to a thickness of about 350 nm, and a contact hole 8 for wiring connection and a wiring electrode 9 are formed in a predetermined pattern by etching (FIG. 2C).

【0004】[0004]

【発明が解決しようとする課題】従来のような構成で
は、非晶質珪素膜3を多結晶化3′するためのエキシマ
レーザー光照射あるいは急速表面加熱時に非晶質珪素膜
中に取り込まれている水素等のガスの突沸を防ぐため
に、あらかじめ真空中で加熱して非晶質珪素膜中に取り
込まれていた水素等を取り除く処理が必要であるので、
移動度μは大きいが、トランジスタのチャンネル部のゲ
ート絶縁膜5と多結晶珪素膜3′との界面が不安定で、
リーク電流が大きく、またトランジスタ特性のばらつき
も大きいという課題を有していた。
In the conventional structure, the amorphous silicon film 3 is taken into the amorphous silicon film at the time of excimer laser beam irradiation or rapid surface heating for polycrystallization 3 '. In order to prevent bumps in the gas such as hydrogen, it is necessary to perform a treatment in advance to remove hydrogen and the like taken in the amorphous silicon film by heating in a vacuum.
Although the mobility μ is large, the interface between the gate insulating film 5 in the channel portion of the transistor and the polycrystalline silicon film 3 ′ is unstable,
There is a problem that the leak current is large and the variation in transistor characteristics is large.

【0005】このような問題点を解決するためには、オ
フセット構造のトランジスタもしくはLDD構造のトラ
ンジスタが有効であるが、それらを形成する工程が複雑
で生産性が低く、また製造上の余裕度も小さい。この発
明は上記課題に鑑み、ゲート絶縁膜と多結晶珪素膜との
界面を安定化し、リーク電流の低下とトランジスタ特性
のばらつきを小さくできるとともに、製造工程が簡単
で、製造上の余裕度も大きい半導体装置およびその製造
方法ならびにTFT型液晶表示装置を提供することを目
的とするものである。
To solve such problems, transistors having an offset structure or transistors having an LDD structure are effective. However, the process of forming them is complicated, the productivity is low, and the manufacturing margin is low. small. In view of the above problems, the present invention can stabilize the interface between a gate insulating film and a polycrystalline silicon film, reduce leakage current and reduce variations in transistor characteristics, simplify the manufacturing process, and provide a large manufacturing margin. It is an object of the present invention to provide a semiconductor device, a method for manufacturing the same, and a TFT liquid crystal display device.

【0006】[0006]

【課題を解決するための手段】請求項1記載の半導体装
置は、基板と、この基板上に多結晶珪素膜および非晶質
珪素膜の順序で積層された二層構造膜と、多結晶珪素膜
に不純物が注入されて形成されたソース・ドレインと、
非晶質珪素膜上に形成されたゲート絶縁膜と、ゲート絶
縁膜上に形成されたゲート電極と、このゲート電極上に
形成された層間絶縁膜と、この層間絶縁膜を通して非晶
質珪素膜に接続されたソース・ドレイン用配線電極とを
備えたものである。
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate; a two-layer structure film laminated on the substrate in the order of a polycrystalline silicon film and an amorphous silicon film; A source / drain formed by injecting impurities into the film;
A gate insulating film formed on the amorphous silicon film, a gate electrode formed on the gate insulating film, an interlayer insulating film formed on the gate electrode, and an amorphous silicon film formed through the interlayer insulating film. And a source / drain wiring electrode connected thereto.

【0007】請求項1記載の半導体装置によれば、多結
晶珪素膜とゲート絶縁膜との間に水素を含む非晶質珪素
膜を形成したため、ゲート絶縁膜と珪素膜との界面が非
晶質珪素膜中に含まれる水素により安定化できるので、
製造方法が簡単で、製造上の余裕度も大きく、またチャ
ネル表面の不安定に起因するリーク電流およびトランジ
スタ特性のばらつきを小さくすることが可能となり、画
質の向上ならびにトランジスタの形成の歩留まりを向上
させることができる。
According to the first aspect of the present invention, since the amorphous silicon film containing hydrogen is formed between the polycrystalline silicon film and the gate insulating film, the interface between the gate insulating film and the silicon film is amorphous. Can be stabilized by hydrogen contained in the porous silicon film,
The manufacturing method is simple, the manufacturing margin is large, and leakage current and variation in transistor characteristics due to instability of the channel surface can be reduced, thereby improving image quality and improving the yield of transistor formation. be able to.

【0008】請求項2記載のTFT型液晶表示装置は、
ソース・ドレインが多結晶珪素膜と非晶質珪素膜の2層
構造からなる第1のトランジスタを有する画素領域と、
ソース・ドレインが多結晶珪素膜からなる第2のトラン
ジスタを有して画素領域の第1のトランジスタを駆動す
る駆動回路とを備えたものである。請求項2記載のTF
T型液晶表示装置によれば、TFT型液晶表示装置の中
に駆動回路を同時に形成する場合には、多結晶珪素膜を
用いたトランジスタにより電子回路として重要な応答速
度の向上が実現できるとともに、画素領域は、格子状に
形成された画素のトランジスタのリーク電流の低減およ
びトランジスタ特性のばらつきが低減でき、画質の向上
ならびにトランジスタ形成歩留まりを向上させることが
できるとともに製造容易であり、請求項1と同様な効果
がある。
According to a second aspect of the present invention, there is provided a TFT type liquid crystal display device.
A pixel region having a first transistor whose source / drain has a two-layer structure of a polycrystalline silicon film and an amorphous silicon film;
A drive circuit having a second transistor whose source and drain are made of a polycrystalline silicon film and driving the first transistor in the pixel region. TF according to claim 2
According to the T-type liquid crystal display device, when a driving circuit is simultaneously formed in the TFT-type liquid crystal display device, a transistor using a polycrystalline silicon film can realize an important improvement in response speed as an electronic circuit, and The pixel region is capable of reducing leakage current and variation in transistor characteristics of a transistor of a pixel formed in a lattice shape, improving image quality and improving a transistor formation yield, and is easy to manufacture. There is a similar effect.

【0009】請求項3記載の半導体装置の製造方法は、
基板に多結晶珪素膜を形成する工程と、その多結晶珪素
膜の表面に非晶質珪素膜を形成する工程と、ゲート絶縁
膜を形成する工程と、そのゲート絶縁膜上にゲート電極
を形成する工程と、前記多結晶珪素膜に不純物を注入し
てソース・ドレインを形成する工程と、前記ゲート電極
上に層間絶縁膜を形成する工程と、層間絶縁膜を通して
ソース・ドレインに配線する配線電極を形成する工程と
を含むものである。
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a polycrystalline silicon film on the substrate, forming an amorphous silicon film on the surface of the polycrystalline silicon film, forming a gate insulating film, and forming a gate electrode on the gate insulating film Forming a source / drain by injecting impurities into the polycrystalline silicon film; forming an interlayer insulating film on the gate electrode; and providing a wiring electrode for wiring to the source / drain through the interlayer insulating film. And a step of forming

【0010】請求項3記載の半導体装置の製造方法によ
れば、請求項1と同様な効果がある。請求項4記載の半
導体装置の製造方法は、請求項3において、多結晶珪素
膜の形成が非晶質珪素膜を熱処理により行なうものであ
る。請求項4記載の半導体装置の製造方法によれば、請
求項3と同様な効果がある。
According to the method of manufacturing a semiconductor device according to the third aspect, the same effect as that of the first aspect is obtained. According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the polycrystalline silicon film is formed by heat-treating the amorphous silicon film. According to the method of manufacturing a semiconductor device according to the fourth aspect, the same effect as that of the third aspect is obtained.

【0011】請求項5記載の半導体装置の製造方法は、
請求項3または請求項4において、ゲート絶縁膜を形成
する工程後に、ゲート絶縁膜と非晶質珪素膜と多結晶珪
素膜を所定のパターンにエッチング形成する工程を含む
ものである。請求項5記載の半導体装置の製造方法によ
れば、請求項3または請求項4と同様な効果のほか、工
程の簡略化が可能となる。
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
The method according to claim 3 or 4, further comprising, after the step of forming the gate insulating film, etching the gate insulating film, the amorphous silicon film, and the polycrystalline silicon film into a predetermined pattern. According to the method of manufacturing a semiconductor device according to the fifth aspect, in addition to the same effect as the third or fourth aspect, the process can be simplified.

【0012】請求項6記載の半導体装置の製造方法は、
請求項3、請求項4または請求項5において、多結晶珪
素膜とゲート絶縁膜との間に形成する非晶質珪素膜の膜
厚が5nmから20nmの間としたものである。請求項
6記載の半導体装置の製造方法によれば、請求項3、請
求項4または請求項5と同様な効果があるほか、膜厚が
5nmから20nmの間であることにより有効性が大き
い。
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
In claim 3, claim 4, or claim 5, the thickness of the amorphous silicon film formed between the polycrystalline silicon film and the gate insulating film is between 5 nm and 20 nm. According to the method of manufacturing a semiconductor device according to the sixth aspect, the same effect as that of the third, fourth, or fifth aspect is obtained, and the effectiveness is large because the film thickness is between 5 nm and 20 nm.

【0013】[0013]

【発明の実施の形態】以下、この発明の一実施の形態の
TFT型液晶表示装置の半導体装置およびその製造方法
について図面1を参照しながら説明する。図1の(a)
〜(c)は、この発明の一実施の形態におけるTFT型
液晶表示装置の製造方法の工程の概略を示す断面図であ
る。TFT素子の形成は、まずガラス基板1の表面に化
学気相蒸着方法で約200nm厚さの二酸化珪素膜2を
形成し、ついでプラズマCVD方法で約50nmの厚さ
の非晶質珪素膜13aを形成したのち、そのガラス基板
1を真空中で約450℃に加熱して非晶質珪素膜形成工
程中に取り込まれた水素等の脱ガスを行った後、エキシ
マレーザー光照射により加熱処理を行い、非晶質珪素膜
を多結晶化する。その後、多結晶化された多結晶珪素膜
13′の表面にプラズマCVD方法で約10nmの厚さ
に非晶質珪素膜13を形成し、フォトレジストパターン
14を形成する(図1(a))。次にそのフォトレジス
トパターン14をマスクにして非晶質珪素膜13と多結
晶珪素膜13′をエッチングし、フォトレジスト14を
除去してから二酸化珪素膜等のゲート絶縁膜15を約1
00nmの厚さに形成した後、アルミニウム(Al)配
線を形成してゲート電極16とする。つぎにイオン注入
方法で硼素あるいは燐等の不純物を注入して、多結晶珪
素膜13′にトランジスタのソース・ドレイン20を形
成する(図1(b))。その後、二酸化珪素膜等を用い
て層間絶縁膜17を約350nmの厚さに形成し、配線
接続のためのコンタクト穴18と配線電極19を所定の
パターンにエッチングにより形成し(図1(c))。ソ
ース・ドレイン電極と配線を形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device of a TFT type liquid crystal display device according to an embodiment of the present invention and a method of manufacturing the same will be described below with reference to FIG. FIG. 1 (a)
FIGS. 1C to 1C are cross-sectional views schematically showing steps of a method of manufacturing a TFT liquid crystal display device according to an embodiment of the present invention. First, a silicon dioxide film 2 having a thickness of about 200 nm is formed on a surface of a glass substrate 1 by a chemical vapor deposition method, and then an amorphous silicon film 13a having a thickness of about 50 nm is formed by a plasma CVD method. After the formation, the glass substrate 1 is heated to about 450 ° C. in vacuum to degas the hydrogen and the like taken in during the amorphous silicon film forming step, and then heat-treated by excimer laser light irradiation. Then, the amorphous silicon film is polycrystallized. Thereafter, an amorphous silicon film 13 having a thickness of about 10 nm is formed on the surface of the polycrystallized polycrystalline silicon film 13 'by a plasma CVD method, and a photoresist pattern 14 is formed (FIG. 1A). . Next, using the photoresist pattern 14 as a mask, the amorphous silicon film 13 and the polycrystalline silicon film 13 'are etched to remove the photoresist 14, and then the gate insulating film 15 such as a silicon dioxide film is
After being formed to a thickness of 00 nm, an aluminum (Al) wiring is formed to form a gate electrode 16. Next, an impurity such as boron or phosphorus is implanted by an ion implantation method to form a source / drain 20 of the transistor in the polycrystalline silicon film 13 '(FIG. 1B). Thereafter, an interlayer insulating film 17 is formed to a thickness of about 350 nm using a silicon dioxide film or the like, and a contact hole 18 for wiring connection and a wiring electrode 19 are formed in a predetermined pattern by etching (FIG. 1C). ). Form source / drain electrodes and wiring.

【0014】図1(c)は、またこの一実施の形態の製
造方法により形成されたTFT型液晶表示装置の概略の
断面を示しており、透光性基板であるガラス基板1と、
この基板1上に多結晶珪素膜13′および非晶質珪素膜
13の順序で積層された二層構造膜と、多結晶珪素膜1
3′に不純物が注入されて形成されたソース・ドレイン
20と、非晶質珪素膜13上に形成されたゲート絶縁膜
15と、ゲート絶縁膜15上に形成されたゲート電極1
6と、このゲート電極16上に形成された層間絶縁膜1
7と、この層間絶縁膜17を通して非晶質珪素膜13に
接続されたソース・ドレイン用配線電極19とを備えて
いる。
FIG. 1C shows a schematic cross section of a TFT type liquid crystal display device formed by the manufacturing method of this embodiment.
A two-layer structure film in which a polycrystalline silicon film 13 'and an amorphous silicon film 13 are laminated in this order on the substrate 1;
3 ′, a source / drain 20 formed by implanting impurities, a gate insulating film 15 formed on the amorphous silicon film 13, and a gate electrode 1 formed on the gate insulating film 15.
6 and the interlayer insulating film 1 formed on the gate electrode 16.
7 and a source / drain wiring electrode 19 connected to the amorphous silicon film 13 through the interlayer insulating film 17.

【0015】このように、上記した構成によって、多結
晶珪素膜13′とゲート絶縁膜15との間に水素を含む
非晶質珪素膜13を形成したため、ゲート絶縁膜15と
多結晶珪素膜13′との界面が非晶質珪素膜13中に含
まれる水素により安定化できるので、製造方法が簡単
で、製造上の余裕度も大きく、またチャネル表面の不安
定に起因するリーク電流およびトランジスタ特性のばら
つきを小さくすることが可能となり、画質の向上ならび
にトランジスタの形成の歩留まりを向上させることがで
きる。
As described above, since the amorphous silicon film 13 containing hydrogen is formed between the polycrystalline silicon film 13 'and the gate insulating film 15 by the above-described structure, the gate insulating film 15 and the polycrystalline silicon film 13 ′ Can be stabilized by hydrogen contained in the amorphous silicon film 13, the manufacturing method is simple, the manufacturing margin is large, and the leakage current and transistor characteristics caused by the instability of the channel surface are increased. Can be reduced, and the image quality can be improved and the yield of transistor formation can be improved.

【0016】また、TFT型液晶表示装置の中に駆動回
路(図示せず)を同時に形成する場合には、ソース・ド
レイン20が多結晶珪素膜13′と非晶質珪素膜13の
2層構造からなる第1のトランジスタを有する画素領域
と、ソース・ドレインが多結晶珪素膜からなる第2のト
ランジスタを有して画素領域の第1のトランジスタを駆
動する駆動回路とを備えた構成とする。
When a driving circuit (not shown) is simultaneously formed in a TFT type liquid crystal display device, the source / drain 20 has a two-layer structure of a polycrystalline silicon film 13 'and an amorphous silicon film 13. And a driving circuit having a second transistor whose source / drain is made of a polycrystalline silicon film and driving the first transistor in the pixel region.

【0017】これにより、多結晶珪素膜を用いたトラン
ジスタにより電子回路として重要な応答速度の向上が実
現できるとともに、画素領域は、格子状に形成された画
素のトランジスタのリーク電流の低減およびトランジス
タ特性のばらつきが低減でき、画質の向上ならびにトラ
ンジスタ形成歩留まりを向上させることができるととも
に製造容易となる。
With this, the transistor using the polycrystalline silicon film can improve the response speed, which is important as an electronic circuit, and the pixel region can reduce the leakage current of the transistor of the pixel formed in a lattice and reduce the transistor characteristics. Can be reduced, the image quality can be improved, and the transistor formation yield can be improved.

【0018】なお、実施の形態において、多結晶化され
る非晶質珪素膜13aの膜厚を50nm、多結晶珪素膜
13′の表面に形成する非晶質珪素膜13の膜厚を10
nmとしたが、これに限定されるものではなく、実験の
結果では、多結晶珪素膜の表面に形成する非晶質珪素膜
の膜厚が5nmから20nmの間が好ましいことがわか
った。すなわち、非晶質珪素膜13の膜厚を小さくする
と移動度μは向上するが、リーク電流およびトランジス
タ特性のばらつきは大きくなり、非晶質珪素膜13の膜
厚を大きくすると移動度μは低下するが、リーク電流お
よびトランジスタ特性のばらつきは小さくなる。また多
結晶珪素膜13′の膜厚を小さくすると移動度μは向上
するため、目標とする特性に応じてそれぞれの膜厚を決
定すればよい。なお、多結晶珪素膜13′の表面に形成
する非晶質珪素膜13の膜厚が5nm未満であると、リ
ーク電流が増大し、トランジスタ特性のばらつきも大き
くなる。また、非晶質珪素膜13の膜厚が20nmを越
えると移動度μが急激に低下するため、多結晶珪素膜1
3′を用いたトランジスタの効果がなくなることが実験
で確認されている。
In the embodiment, the thickness of the amorphous silicon film 13a to be polycrystallized is 50 nm, and the thickness of the amorphous silicon film 13 formed on the surface of the polycrystalline silicon film 13 'is 10 nm.
Although the thickness is set to nm, the present invention is not limited to this, and it has been found from experiments that the thickness of the amorphous silicon film formed on the surface of the polycrystalline silicon film is preferably between 5 nm and 20 nm. That is, when the thickness of the amorphous silicon film 13 is reduced, the mobility μ is improved, but the leakage current and the variation in transistor characteristics are increased, and when the thickness of the amorphous silicon film 13 is increased, the mobility μ is reduced. However, variations in leakage current and transistor characteristics are reduced. In addition, since the mobility μ is improved when the thickness of the polycrystalline silicon film 13 ′ is reduced, the respective thicknesses may be determined according to target characteristics. If the thickness of the amorphous silicon film 13 formed on the surface of the polycrystalline silicon film 13 'is less than 5 nm, the leakage current increases and the variation in transistor characteristics increases. If the thickness of the amorphous silicon film 13 exceeds 20 nm, the mobility μ sharply decreases, so that the polycrystalline silicon film 1
Experiments have confirmed that the effect of the transistor using 3 'is lost.

【0019】さらにまた、前記した実施の形態では、非
晶質珪素膜13と多結晶珪素膜13′を所定のパターン
にエッチング形成してから、ゲート絶縁膜15を形成し
たが、工程を簡略化する目的で、二酸化珪素膜等のゲー
ト絶縁膜15を形成してから、ゲート絶縁膜15と非晶
質珪素膜13と多結晶珪素膜13′を所定のパターンに
エッチング形成することでもよく、この場合も前記した
のと同じ効果があることは明白である。
Furthermore, in the above-described embodiment, the gate insulating film 15 is formed after the amorphous silicon film 13 and the polycrystalline silicon film 13 'are formed by etching in a predetermined pattern. For this purpose, after forming a gate insulating film 15 such as a silicon dioxide film, the gate insulating film 15, the amorphous silicon film 13, and the polycrystalline silicon film 13 'may be etched and formed in a predetermined pattern. It is clear that the same effect is obtained in the case described above.

【0020】[0020]

【発明の効果】請求項1記載の半導体装置によれば、多
結晶珪素膜とゲート絶縁膜との間に水素を含む非晶質珪
素膜を形成したため、ゲート絶縁膜と珪素膜との界面が
非晶質珪素膜中に含まれる水素により安定化できるの
で、製造方法が簡単で、製造上の余裕度も大きく、また
チャネル表面の不安定に起因するリーク電流およびトラ
ンジスタ特性のばらつきを小さくすることが可能とな
り、画質の向上ならびにトランジスタの形成の歩留まり
を向上させることができる。
According to the semiconductor device of the first aspect, since the amorphous silicon film containing hydrogen is formed between the polycrystalline silicon film and the gate insulating film, the interface between the gate insulating film and the silicon film is reduced. Since it can be stabilized by hydrogen contained in the amorphous silicon film, the manufacturing method is simple, the manufacturing margin is large, and variations in leak current and transistor characteristics due to instability of the channel surface are reduced. It is possible to improve image quality and the yield of transistor formation.

【0021】請求項2記載のTFT型液晶表示装置によ
れば、TFT型液晶表示装置の中に駆動回路を同時に形
成する場合には、多結晶珪素膜を用いたトランジスタに
より電子回路として重要な応答速度の向上が実現できる
とともに、画素領域は、格子状に形成された画素のトラ
ンジスタのリーク電流の低減およびトランジスタ特性の
ばらつきが低減でき、画質の向上ならびにトランジスタ
形成歩留まりを向上させることができるとともに製造容
易であり、請求項1と同様な効果がある。
According to the TFT type liquid crystal display device of the present invention, when a driving circuit is formed simultaneously in the TFT type liquid crystal display device, an important response as an electronic circuit is provided by the transistor using the polycrystalline silicon film. In addition to the improvement in speed, the pixel region can reduce the leakage current of the transistors of the pixels formed in a grid and reduce the variation in transistor characteristics, thereby improving the image quality and the transistor formation yield and manufacturing. It is easy and has the same effect as the first aspect.

【0022】請求項3記載の半導体装置の製造方法によ
れば、請求項1と同様な効果がある。請求項4記載の半
導体装置の製造方法によれば、請求項3と同様な効果が
ある。請求項5記載の半導体装置の製造方法によれば、
請求項3または請求項4と同様な効果のほか、工程の簡
略化が可能となる。
According to the method of manufacturing a semiconductor device according to the third aspect, the same effect as that of the first aspect is obtained. According to the method of manufacturing a semiconductor device according to the fourth aspect, the same effect as that of the third aspect is obtained. According to the method of manufacturing a semiconductor device according to claim 5,
In addition to the effects similar to those of the third and fourth aspects, the steps can be simplified.

【0023】請求項6記載のTFT型液晶表示装置の製
造方法によれば、請求項3、請求項4または請求項5と
同様な効果があるほか、膜厚が5nmから20nmの間
であることにより有効性が大きい。
According to the method of manufacturing a TFT type liquid crystal display device of the present invention, the same effect as that of the third, fourth or fifth aspect can be obtained, and the film thickness can be between 5 nm and 20 nm. Greater effectiveness.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施の形態におけるTFT型液晶
表示装置の半導体装置の製造工程および概略を示す断面
図である。
FIG. 1 is a cross-sectional view showing a manufacturing process and outline of a semiconductor device of a TFT type liquid crystal display device according to an embodiment of the present invention.

【図2】従来のTFT型液晶表示装置の半導体装置の製
造工程および概略を示す断面図である。
FIG. 2 is a cross-sectional view showing a manufacturing process and outline of a semiconductor device of a conventional TFT type liquid crystal display device.

【符号の説明】[Explanation of symbols]

1 ガラス基板 2 二酸化珪素膜 13 非晶質珪素膜 13’ 多結晶珪素膜 14 フォトレジスト 15 ゲート絶縁膜 16 ゲート電極 17 層間絶縁膜 18 コンタクト穴 19 配線電極 20 トランジスタのソース・ドレイン DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Silicon dioxide film 13 Amorphous silicon film 13 'Polycrystalline silicon film 14 Photoresist 15 Gate insulating film 16 Gate electrode 17 Interlayer insulating film 18 Contact hole 19 Wiring electrode 20 Source / drain of transistor

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 基板と、この基板上に多結晶珪素膜およ
び非晶質珪素膜の順序で積層された2層構造膜と、前記
多結晶珪素膜に不純物が注入されて形成されたソース・
ドレインと、前記非晶質珪素膜上に形成されたゲート絶
縁膜と、ゲート絶縁膜上に形成されたゲート電極と、こ
のゲート電極上に形成された層間絶縁膜と、この層間絶
縁膜を通して前記非晶質珪素膜に接続されたソース・ド
レイン用配線電極とを備えた半導体装置。
1. A substrate, a two-layer structure film laminated on the substrate in the order of a polycrystalline silicon film and an amorphous silicon film, and a source film formed by injecting impurities into the polycrystalline silicon film.
A drain; a gate insulating film formed on the amorphous silicon film; a gate electrode formed on the gate insulating film; an interlayer insulating film formed on the gate electrode; A semiconductor device comprising: a source / drain wiring electrode connected to an amorphous silicon film.
【請求項2】 ソース・ドレインが多結晶珪素膜と非晶
質珪素膜の2層構造からなる第1のトランジスタを有す
る画素領域と、ソース・ドレインが多結晶珪素膜からな
る第2のトランジスタを有して前記第1のトランジスタ
を駆動する駆動回路とを備えたTFT型液晶表示装置。
2. A pixel region having a first transistor whose source / drain has a two-layer structure of a polycrystalline silicon film and an amorphous silicon film, and a second transistor whose source / drain is made of a polycrystalline silicon film And a driving circuit for driving the first transistor.
【請求項3】 基板に多結晶珪素膜を形成する工程と、
その多結晶珪素膜の表面に非晶質珪素膜を形成する工程
と、ゲート絶縁膜を形成する工程と、そのゲート絶縁膜
上にゲート電極を形成する工程と、前記多結晶珪素膜に
不純物を注入してソース・ドレインを形成する工程と、
前記ゲート電極上に層間絶縁膜を形成する工程と、層間
絶縁膜を通してソース・ドレインに配線する配線電極を
形成する工程とを含む半導体装置の製造方法。
A step of forming a polycrystalline silicon film on the substrate;
Forming an amorphous silicon film on the surface of the polycrystalline silicon film, forming a gate insulating film, forming a gate electrode on the gate insulating film, and adding impurities to the polycrystalline silicon film. Implanting to form a source / drain;
A method of manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film on the gate electrode; and a step of forming a wiring electrode for wiring to a source / drain through the interlayer insulating film.
【請求項4】 多結晶珪素膜の形成は非晶質珪素膜を熱
処理により行なう請求項3記載の半導体装置の製造方
法。
4. The method according to claim 3, wherein the polycrystalline silicon film is formed by heat-treating the amorphous silicon film.
【請求項5】 ゲート絶縁膜を形成する工程後に、ゲー
ト絶縁膜と非晶質珪素膜と多結晶珪素膜を所定のパター
ンにエッチング形成する工程を含む請求項3または請求
項4記載の半導体装置の製造方法。
5. The semiconductor device according to claim 3, further comprising, after the step of forming the gate insulating film, a step of etching and forming the gate insulating film, the amorphous silicon film, and the polycrystalline silicon film in a predetermined pattern. Manufacturing method.
【請求項6】 多結晶珪素膜とゲート絶縁膜との間に形
成する非晶質珪素膜の膜厚が5nmから20nmの間で
ある請求項3、請求項4または請求項5記載の半導体装
置の製造方法。
6. The semiconductor device according to claim 3, wherein the thickness of the amorphous silicon film formed between the polycrystalline silicon film and the gate insulating film is between 5 nm and 20 nm. Manufacturing method.
JP14768797A 1997-06-05 1997-06-05 Semiconductor device and its manufacture, and tft type liquid crystal display device Pending JPH10333185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14768797A JPH10333185A (en) 1997-06-05 1997-06-05 Semiconductor device and its manufacture, and tft type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14768797A JPH10333185A (en) 1997-06-05 1997-06-05 Semiconductor device and its manufacture, and tft type liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH10333185A true JPH10333185A (en) 1998-12-18

Family

ID=15436020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14768797A Pending JPH10333185A (en) 1997-06-05 1997-06-05 Semiconductor device and its manufacture, and tft type liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH10333185A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040013273A (en) * 2002-08-05 2004-02-14 엘지.필립스 엘시디 주식회사 Thin Film Transistor and the same method
KR100946560B1 (en) * 2008-03-28 2010-03-11 하이디스 테크놀로지 주식회사 Method of manufacturing thin film transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040013273A (en) * 2002-08-05 2004-02-14 엘지.필립스 엘시디 주식회사 Thin Film Transistor and the same method
KR100946560B1 (en) * 2008-03-28 2010-03-11 하이디스 테크놀로지 주식회사 Method of manufacturing thin film transistor

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